Storage receiving drive and storage system

Abstract

This invention discloses a storage receiver driver and a storage system, relating to the field of storage technology. The storage receiver driver includes: a data signal input terminal; a drive signal output terminal; a storage receiver pre-drive circuit, whose two signal inputs are respectively used to connect to the data signal input terminal and a mode enable signal. The storage receiver pre-drive circuit generates pull-up control signals and pull-down control signals corresponding to the mode based on the data signal and the mode enable signal; a storage receiver main drive circuit, whose controlled terminal is connected to the output terminal of the storage receiver pre-drive circuit, whose enable terminal is used to connect to the switch enable signal corresponding to the mode, and whose output terminal is connected to the drive signal output terminal; the storage receiver main drive circuit operates in the corresponding drive mode according to the switch enable signal, and drives the memory to operate according to the pull-up control signals and pull-down control signals. This invention is beneficial for improving the compatibility of the storage receiver driver.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a storage receiver driver and a storage system. Background Technology

[0002] With the development of high-performance computing and mobile terminals, different types of DRAM standards coexist in systems, such as DDR5 (Double Data Rate 5) and LPDDR5 (Low-Power Double Data Rate 5). These two types of memory operate at different voltages: DDR5 operates at approximately 1.1V, while LPDDR5 operates at approximately 0.5V. Therefore, their driver structures need to be configured differently. Storage systems typically only use either DDR5 or LPDDR5. Consequently, the receive drivers for DDR5 and LPDDR5 are usually designed specifically for one type of memory. Even in storage systems with both DDR5 and LPDDR5, separate drivers are designed for each type of memory, leading to hardware resource duplication, increased area and power consumption. Furthermore, the existence of multiple voltage domains increases design complexity and the risk of conflicts. Summary of the Invention

[0003] The main objective of this invention is to provide a storage receive driver and storage system, which aims to improve the compatibility of the storage receive driver.

[0004] To achieve the above objectives, the present invention provides a storage receiving driver, comprising: Data signal input terminal, used to receive data signals; The drive signal output terminal is used for connection to the memory; A storage and receiving pre-drive circuit is provided, wherein the first signal input terminal of the storage and receiving pre-drive circuit is connected to the data signal input terminal, the second signal input terminal of the storage and receiving pre-drive circuit is used to receive a mode enable signal, and the storage and receiving pre-drive circuit is used to generate a corresponding pull-up control signal or pull-down control signal according to the data signal and the mode enable signal; or, when the storage and receiving pre-drive circuit is in a disabled state, it generates a high-impedance control signal. The storage receiving main drive circuit has its controlled terminal connected to the output terminal of the storage receiving pre-drive circuit. Its enable terminal is used to receive a corresponding switch enable signal, and its output terminal is connected to the drive signal output terminal. The storage receiving main drive circuit operates in the corresponding drive mode according to the switch enable signal and drives the memory at the corresponding level according to the pull-up or pull-down control signal. Alternatively, when receiving the high-impedance control signal, it outputs a high-impedance signal to the drive signal output terminal to drive the memory to switch to a high-impedance mode.

[0005] In one embodiment, the storage receive pre-drive circuit includes: The mode enable signal includes a first mode enable signal, a second mode enable signal, and a pull-down enable signal; the storage receive pre-drive circuit includes: A first pull-up control circuit, wherein the first signal input terminal of the first pull-up control circuit is connected to the data signal input terminal, and the second signal input terminal of the first pull-up control circuit is used to receive a first mode enable signal; the first pull-up control circuit is used to generate a first pull-up control signal according to the data signal and the first mode enable signal, and the first pull-up control signal is used to control the pull-up of a first type of pull-up drive circuit. A second pull-up control circuit is provided, wherein the first signal input terminal of the second pull-up control circuit is connected to the data signal input terminal, and the second signal input terminal of the second pull-up control circuit is used to receive a second mode enable signal; the second pull-up control circuit is used to generate a second pull-up control signal based on the data signal and the second mode enable signal, and the second pull-up control signal is used to control the pull-up of a second type of pull-up drive circuit; wherein the drive voltages of the first type of pull-up drive circuit and the second type of pull-up drive circuit are different; A pull-down control circuit is provided, wherein a first signal input terminal of the pull-down control circuit is connected to the data signal input terminal, and a second signal input terminal of the pull-down control circuit is used to receive a pull-down enable signal; the pull-down control circuit is used to generate a pull-down control signal based on the data signal and the pull-down enable signal, and the pull-down control signal is used to control the pull-down drive circuit to pull down.

[0006] In one embodiment, the first pull-up control circuit includes: The NOR gate logic circuit has a first signal input terminal connected to the data signal input terminal, and a second signal input terminal used to receive the first mode enable signal; the NOR gate logic circuit is used to generate the first pull-up control signal by performing logic encoding based on the data signal and the first mode enable signal. The first inverter has its input terminal connected to the output terminal of the NOR gate logic circuit. The first inverter is used to invert the first pull-up control signal and then output it.

[0007] In one embodiment, the second pull-up control circuit includes: The first NAND gate logic circuit has a first signal input terminal connected to the data signal input terminal, and a second signal input terminal used to receive a second mode enable signal; the first NAND gate logic circuit is used to generate a second pull-up control signal after performing logical encoding based on the data signal and the second mode enable signal. A delay circuit is provided, the input of which is connected to the output of the first NOT gate logic circuit. The delay circuit is used to delay the second pull-up control signal before outputting it.

[0008] In one embodiment, the pull-down control circuit includes: The second NAND gate logic circuit has its first signal input terminal connected to the data signal input terminal, and its second signal input terminal used to receive a pull-down enable signal; the second NAND gate logic circuit is used to generate a pull-down control signal after logical encoding based on the data signal and the pull-down enable signal. The second inverter has its input connected to the output of the second NAND gate logic circuit. The second inverter is used to invert the pull-down control signal and then output it.

[0009] In one embodiment, the storage receiving main drive circuit includes: The first type of pull-up drive circuit has an input terminal for receiving a first drive voltage, an enable terminal for receiving a first switch enable signal, a controlled terminal for receiving a first pull-up control signal, and an output terminal connected to the drive signal output terminal. The first type of pull-up drive circuit is used to pull up the voltage at the drive signal output terminal to the first drive voltage level according to the first switch enable signal and the first pull-up control signal. The second type of pull-up drive circuit has an input terminal for receiving a first drive voltage, an enable terminal for receiving a second switch enable signal, a controlled terminal for receiving a second pull-up control signal, and an output terminal connected to the drive signal output terminal. This second type of pull-up drive circuit is used to pull up the voltage at the drive signal output terminal to the second drive voltage level according to the second switch enable signal and the second pull-up control signal. The amplitudes of the first drive voltage and the second drive voltage are different. A pull-down driving circuit is provided, wherein the controlled terminal of the pull-down driving circuit is used to receive a pull-down control signal, the input terminal of the pull-down driving circuit is grounded, the output terminal of the pull-down driving circuit is connected to the drive signal output terminal, and the pull-down driving circuit is used to pull down the voltage of the drive signal output terminal to a low level when the pull-down control signal is received.

[0010] In one embodiment, the first type of pull-up drive circuit includes: A first mode switch, wherein the controlled terminal of the first mode switch is the enable terminal of the first type of pull-up drive circuit, and the input terminal of the first mode switch is the input terminal of the first type of pull-up drive circuit. The first pull-up drive switch has a controlled terminal that is the controlled terminal of a first type of pull-up drive circuit. The input terminal of the first pull-up drive switch is connected to the output terminal of the first mode switching switch, and the output terminal of the first pull-up drive switch is the output terminal of the first type of pull-up drive circuit.

[0011] In one embodiment, the second type of pull-up drive circuit includes: The second mode switch has a controlled terminal that is the enable terminal of the second type of pull-up drive circuit, and an input terminal that is the input terminal of the second type of pull-up drive circuit. The second pull-up drive switch has a controlled terminal that is the controlled terminal of the second type of pull-up drive circuit. The input terminal of the second pull-up drive switch is connected to the output terminal of the second mode switching switch, and the output terminal of the second pull-up drive switch is the output terminal of the second type of pull-up drive circuit.

[0012] In one embodiment, the pull-down drive circuit includes: A pull-down drive switch, wherein the controlled terminal of the pull-down drive switch is the controlled terminal of the pull-down drive circuit, the input terminal of the pull-down drive switch is the input terminal of the pull-down drive circuit, and the output terminal of the pull-down drive switch is the output terminal of the pull-down drive circuit.

[0013] The present invention also proposes a storage system, including a memory and a storage receiving driver as described above, wherein the drive signal output terminal of the storage receiving driver is connected to the data terminal of the memory.

[0014] This invention establishes a storage receiver pre-drive circuit that generates corresponding pull-up and pull-down control signals based on the received data signal and mode enable signal. These signals are then output to the storage receiver main drive circuit, controlling it to operate in the corresponding drive mode based on the received switch enable signal. The main drive circuit then applies the pull-up and pull-down control signals to drive the corresponding type of memory at the appropriate voltage level. This invention proposes a single I / O drive structure that, through pull-up path reconstruction, operates in the corresponding drive mode based on the mode selection signal and switch drive signal, enabling switching between different voltage domain drive structures and resolving the incompatibility issue between drive structures of different standard memories. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the functional modules of a storage receiving driver according to an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of the circuit structure of an embodiment of the storage receiver pre-drive circuit; Figure 3 for Figure 1 A schematic diagram of the circuit structure of one embodiment of the storage receiving main drive circuit.

[0017] Explanation of icon numbers: DATA, data signal input terminal; DQ, drive signal output terminal; 10. Storage and reception pre-drive circuit; 11. First pull-up control circuit; 111. NOR gate logic circuit; 112. First inverter; 121. First NAND gate logic circuit; 122. Delay circuit; 12. Second pull-up control circuit; 13. Pull-down control circuit; 131. Second NAND gate logic circuit; 132. Second inverter; 20. Storage and receiving main drive circuit; 21. First type of pull-up drive circuit; 22. Second type of pull-up drive circuit; 23. Pull-down drive circuit; Q11, First mode switch; Q12, First pull-up drive switch; Q21, Second mode switch; Q22, Second pull-up drive switch; Q3, Pull-down drive switch The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0020] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0021] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0022] This invention proposes a storage receiver pre-drive circuit for use in a storage system, which may include DDR5 DRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) and LPDDR DRAM (Low Power Double Data Rate Dynamic Random-Access Memory). With the development of high-performance computing and mobile terminals, different types of DRAM standards coexist in systems, typically DDR5 (Double Data Rate 5) and LPDDR5 (Low-Power Double Data Rate 5). The two types of memory differ in their I / O receiver (RX) main drive structure: the DDR5 receiver main drive structure primarily relies on NMOS pull-down paths and a terminal matching network for signal reception, with an operating voltage of approximately 1.1V. In contrast, the LPDDR5 receiver main drive structure includes voltage detection structures with pull-up and pull-down paths, operating at approximately 0.5V, emphasizing low power consumption and low-voltage signal recognition capabilities. Storage systems typically only use DDR5 or LPDDR5. Therefore, the receive drivers for DDR5 and LPDDR5 are usually designed specifically for one type of memory. In storage systems with both DDR5 and LPDDR5 memory, the drivers for the two types of memory are designed separately, resulting in duplicated hardware resources, increased area and power consumption. At the same time, the existence of multiple voltage domains also increases design complexity and conflict risks.

[0023] To address the aforementioned problems, this invention proposes a storage receive driver, referring to... Figures 1 to 3 In one embodiment of the present invention, the storage receive driver includes: The data signal input terminal DATA is used to receive data signals. The drive signal output terminal DQ is used to connect to the memory. The storage and receiving pre-drive circuit 10 has a first signal input terminal connected to the data signal input terminal DATA, and a second signal input terminal used to receive a mode enable signal. The storage and receiving pre-drive circuit 10 is used to generate corresponding pull-up control signals and pull-down control signals PD according to the data signal and the mode enable signal; or, when the storage and receiving pre-drive circuit 10 is in an disabled state, it generates a high-impedance control signal. The main drive circuit 20 for storage receiving is connected to the output of the storage receiving pre-drive circuit 10. The enable terminal of the main drive circuit 20 is used to receive the switch enable signal of the corresponding mode. The output terminal of the main drive circuit 20 is connected to the drive signal output terminal DQ. The main drive circuit 20 is used to operate in the corresponding drive mode according to the switch enable signal and to drive the memory at the corresponding level according to the pull-up control signal and the pull-down control signal PD. Alternatively, when the main drive circuit 20 receives the high impedance control signal, it outputs a high impedance signal to the drive signal output terminal to drive the memory to switch to the high impedance mode.

[0024] In some embodiments, the storage system may also include a register clock driver, which can communicate with an external storage controller. The register clock driver determines the type of memory the external storage controller needs to access based on the access command output by the external storage controller and outputs the corresponding mode enable signal. For example, when the access command determines that data needs to be written to DDR5 DRAM, it outputs a first mode enable signal PU_D5_EN in DDR5 mode. When the access command determines that data needs to be written to LPDDR5 DRAM, it outputs a second mode enable signal PU_LP5_EN in LPDDR5 mode. The storage receiving pre-drive circuit 10 generates a pull-up control signal corresponding to the received mode enable signal. The number of pull-up control signals generated by the storage receiving pre-drive circuit 10 can be two or more. When set to two, the storage receiving pre-drive circuit 10 can generate two types of drive control signals, or generate a pull-down control signal PD when a pull-down enable signal PD_EN is received. One type of drive control signal can be a first pull-up control signal PU_D5 used to control the main drive circuit to drive the DDR5 DRAM, and the other type can be a second pull-up control signal PU_LP5 used to control the main drive circuit to drive the LPDDR5 DRAM. After completing the data interaction, the register clock driver can also output a de-enabled signal (the opposite logic of the mode enable signal; for example, when the first mode enable signal PU_D5_EN in DDR5 mode is 1, the de-enabled signal is 0; when the second mode enable signal PU_LP5_EN in LPDDR5 mode is 1, the de-enabled signal is 0; when the pull-down enable signal PD_EN is 1, the de-enabled signal is 0). The storage receive pre-drive circuit 10 generates a high-impedance control signal based on the de-enabled signal to control the storage receive main drive circuit 20 to generate a high-impedance signal to the drive signal output terminal DQ, thereby driving the memory to switch to high-impedance mode.

[0025] Referring to Table 1, Table 1 shows the pull-up control signal and pull-down control signal PD generated by the storage receive pre-drive circuit 10 in DDR5 DRAM mode and LPDDR5 DRAM mode as the data signal changes (0, 1, HiZ (high impedance state)).

[0026] Table 1

[0027] The output of the storage receiving main drive circuit 20 is used to connect to the memory. Specifically, it can connect to two different types of memory via a bus. In this embodiment, it can be selected as DDR5 DRAM and LPDDR5 DRAM. It is understood that DDR5 DRAM and LPDDR5 DRAM have different drive voltages. For example, the pull-up drive voltage of DDR5 DRAM is 1.1V, while that of LPDDR5 DRAM is 0.6V. To prevent the 1.1V pull-up drive voltage of DDR5 DRAM from being applied to LPDDR5 DRAM, the register clock driver can also output a switch enable signal to control the connection / disconnection of the two drive voltages. When it is determined according to the access instruction that data needs to be written to DDR5 DRAM, the first switch enable signal D5_EN in DDR5 mode is output. When it is determined according to the access instruction that data needs to be written to LPDDR5 DRAM, the second switch enable signal LP5_EN in LPDDR5 mode is output. The storage receiving main drive circuit 20 connects to the corresponding mode's drive voltage according to the received switch enable signal. The main drive circuit 20 for receiving memory can accept two or more drive voltages. When set to two, it can receive two drive voltages and operate in two drive modes: POD (Pseudo Open Drain, corresponding to DDR5 DRAM) and CMOS (Complementary Metal-Oxide-Semiconductor, corresponding to LPDDR5 DRAM) drive modes. When a switch enable signal is received in DDR5 DRAM mode, the drive voltage for DDR5 DRAM is applied; when a switch enable signal is received in LPDDR5 DRAM mode, the drive voltage for LPDDR5 DRAM is applied. The main drive circuit 20 can apply a corresponding drive voltage based on the applied switch enable signal. When one drive voltage is applied, the other power supply path is turned off, ensuring that only one drive voltage is applied at a time. This achieves safe multiplexing of multiple voltage domains and prevents short circuits across power supplies. Simultaneously, the storage receiving main drive circuit 20 generates a pull-up drive signal for the corresponding mode based on the drive control signal, thereby pulling up the voltage of the output node corresponding to the drive signal output terminal DQ connected to the data receiving terminal of the memory to the level of the corresponding drive voltage, thus realizing high-level drive for different memories. Specifically, when receiving the pull-up control signal and switch enable signal under DDR5 DRAM, the storage receiving main drive circuit 20 generates a pull-up drive signal under DDR5 DRAM, thereby pulling up the voltage of the drive signal output terminal DQ to the level of the drive voltage of DDR5 DRAM.Upon receiving the pull-up control signal and switch enable signal from the LPDDR5 DRAM, the storage receiving main drive circuit 20 generates a pull-up drive signal for the LPDDR5 DRAM, thereby pulling up the voltage at the drive signal output terminal DQ to the level of the LPDDR5 DRAM drive voltage. Mode selection and drive voltage output are achieved by setting the mode enable signal and pull-up control signal. Only when the mode enable signal and pull-up control signal for the corresponding mode are received simultaneously is either the DDR5 DRAM drive path or the LPDDR5 DRAM drive path activated. Thus, at any given time, only one mode's pull-up path is allowed to be active, thereby avoiding conflicts between different voltage domains.

[0028] When a low-level drive signal is required, the register clock driver can also output a pull-down enable signal. The storage and receiving main drive circuit 20 generates a pull-down control signal PD based on this pull-down enable signal to control the storage and receiving main drive circuit 20 to pull down the voltage of the drive signal output terminal DQ to ground level, thereby outputting a low-level drive signal. Simultaneously, the register clock driver can also output a turn-off switch enable signal. At this time, the storage and receiving pre-drive circuit 10 also outputs a turn-off pull-up control signal, ensuring that the pull-up drive path of the storage and receiving main drive circuit 20 is not connected to the drive voltage. When the bus is idle, in a mode switch or in a disabled state, such as after data interaction is completed, when the storage receive pre-drive circuit 10 receives a disabled signal (at the same time the data signal input terminal DATA receives a high-impedance data signal), the storage receive pre-drive circuit 10 generates a pull-up control signal and a pull-down control signal PD to the storage receive main drive circuit 20. The storage receive main drive circuit 20 shuts down both the pull-up drive path and the pull-down drive path. Thus, when both the pull-up and pull-down paths are closed, the output node corresponding to the drive signal output terminal DQ is in a high-impedance state.

[0029] This invention establishes a storage receiving pre-drive circuit 10 that generates pull-up control signals and pull-down control signals (PD) corresponding to the received data signal and mode enable signal, and outputs these signals to the storage receiving main drive circuit 20. This controls the storage receiving main drive circuit 20 to operate in the corresponding drive mode based on the received switch enable signal, and to drive the corresponding type of memory at the corresponding level based on the pull-up control signal and pull-down control signal (PD). This invention proposes a single I / O drive structure that, through pull-up path reconstruction, operates in the corresponding drive mode based on the mode selection signal and switch drive signal, enabling multiple drive modes to coexist and resolving the incompatibility issue between drive structures of different standard memories.

[0030] Reference Figure 1 and Figure 2In one embodiment, the mode enable signal includes a first mode enable signal PU_D5_EN, a second mode enable signal PU_LP5_EN, and a pull-down enable signal PD_EN. The storage receive pre-drive circuit 10 includes: The first pull-up control circuit 11 has its first signal input terminal connected to the data signal input terminal DATA, and its second signal input terminal used to receive the first mode enable signal. The first pull-up control circuit 11 is used to generate a first pull-up control signal PU_D5 based on the data signal and the first mode enable signal PU_D5_EN, so as to control the pull-up of the first type of pull-up drive circuit 21. The second pull-up control circuit 12 has its first signal input terminal connected to the data signal input terminal DATA, and its second signal input terminal used to receive the second mode enable signal PU_LP5_EN. The second pull-up control circuit 12 generates a second pull-up control signal PU_LP5 based on the data signal and the second mode enable signal PU_LP5_EN to control the pull-up of the second type of pull-up drive circuit 22. The drive voltages of the first type of pull-up drive circuit 21 and the second type of pull-up drive circuit 22 are different. The pull-down control circuit 13 has its first signal input terminal connected to the data signal input terminal DATA, and its second signal input terminal used to receive the pull-down enable signal PD_EN. It is used to generate a pull-down control signal PD based on the data signal and the pull-down enable signal PD_EN to control the pull-down drive circuit 23 to pull down.

[0031] In this embodiment, the first type of pull-up driving circuit 21 can be used to drive DDR5 DRAM, and the second type of pull-up driving circuit 22 can be used to drive LPDDR5 DRAM. The common terminal of the first pull-up control circuit 11, the second pull-up control circuit 12, and the pull-down control circuit 13 is used to access data signals. The mode enable signals accessed by the first pull-up control circuit 11 and the second pull-up control circuit 12 are interlocked or mutually exclusive. When the first pull-up control circuit 11 is working, the second pull-up control circuit 12 is not working, and when the second pull-up control circuit 12 is working, the first pull-up control circuit 11 is not working.

[0032] The enable signals connected between the first pull-up control circuit 11 and the pull-down control circuit 13, and between the second pull-up control circuit 12 and the pull-down control circuit 13, are also interlocked. When the first pull-up control circuit 11 is working, the pull-down control circuit 13 is not working, and when the pull-down control circuit 13 is working, the first pull-up control circuit 11 is not working. Similarly, when the second pull-up control circuit 12 is working, the pull-down control circuit 13 is not working, and when the pull-down control circuit 13 is working, the second pull-up control circuit 12 is not working. In the disabled state, the first pull-up control circuit 11, the second pull-up control circuit 12, and the pull-down control circuit 13 are all not working. At this time, the first pull-up control circuit 11 outputs a control signal opposite to the first pull-up control signal PU_D5, the second pull-up control circuit 12 outputs a control signal opposite to the second pull-up control signal PU_LP5, and the pull-down control circuit 13 also outputs a control signal opposite to the pull-down control signal PD.

[0033] Reference Figure 1 and Figure 2 In one embodiment, the first pull-up control circuit 11 includes: The NOR gate logic circuit 111 has its first signal input terminal connected to the data signal input terminal DATA, and its second signal input terminal used to receive the first mode enable signal PU_D5_EN. The NOR gate logic circuit 111 is used to generate a first pull-up control signal PU_D5 for controlling the pull-up of the first type of pull-up drive circuit 21 after logical encoding based on the data signal and the first mode enable signal PU_D5_EN. The first inverter 112 has its input terminal connected to the output terminal of the OR gate logic circuit 111. The first inverter 112 is used to invert the first pull-up control signal PU_D5 and then output it.

[0034] In this embodiment, the two signal input terminals of the NOR gate logic circuit 111 are respectively used to connect the data signal DATA and the mode enable signal PD_EN. When either the data signal DATA or the mode enable signal PD_EN is high, a low-level first pull-up control signal PU_D5 is output; when both the data signal DATA and the mode enable signal PD_EN are low, a high-level first pull-up control signal PU_D5 is output. The first inverter 112 inverts the first pull-up control signal PU_D5 before outputting it. For example, when the NOR gate logic circuit 111 outputs a high-level first pull-up control signal PU_D5, the first pull-up control signal PU_D5 is inverted to a low level by the first inverter 112. Conversely, when the NOR gate logic circuit 111 outputs a low-level first pull-up control signal PU_D5, the first pull-up control signal PU_D5 is inverted to a high level by the first inverter 112. The NOR gate logic circuit 111 is used to generate the pull-up control signal PU_D5 in DDR5 mode. It achieves logic polarity conversion through combinational logic and the first inverter 112, and provides a certain driving capability and delay matching.

[0035] Reference Figure 1 and Figure 2 In one embodiment, the second pull-up control circuit 12 includes: The first NAND gate logic circuit 121 has its first signal input terminal connected to the data signal input terminal DATA, and its second signal input terminal used to receive the second mode enable signal PU_LP5_EN. The first NAND gate logic circuit 121 is used to generate a second pull-up control signal PU_LP5 for controlling the pull-up of the second type of pull-up drive circuit 22 after logical encoding based on the data signal and the second mode enable signal PU_LP5_EN. The delay circuit 122 has its input terminal connected to the output terminal of the first NAND gate logic circuit 121. The delay circuit 122 is used to delay the output of the second pull-up control signal PU_LP5.

[0036] In this embodiment, the two signal input terminals of the first NAND gate logic circuit 121 are respectively connected to the data signal DATA and the mode enable signal PU_LP5_EN. When both the data signal DATA and the mode enable signal PU_LP5_EN are high, the first NAND gate logic circuit 121 outputs a low-level second pull-up control signal PU_LP5. When either the data signal DATA or the second mode enable signal PU_LP5_EN is not high, the first NAND gate logic circuit 121 outputs a high-level second pull-up control signal PU_LP5.

[0037] The delay circuit 122 can be implemented using a normally-on CMOS transmission structure. This CMOS transmission structure includes an NMOS transistor and a PMOS transistor connected in parallel. The gates of the NMOS and PMOS transistors are fixedly connected to the power supply and ground, respectively, ensuring that the NMOS and PMOS transistors are always in the on state. The path formed by the first NAND gate logic circuit 121 and the delay circuit 122 is used to generate the second pull-up control signal PU_LP5 in LPDDR5 mode. Simultaneously, the normally-on CMOS structure introduces an additional propagation delay, ensuring that the path corresponding to the first pull-up control circuit 11 maintains timing consistency with other control paths.

[0038] Reference Figure 1 and Figure 2 In one embodiment, the pull-down control circuit 13 includes: The second NAND gate logic circuit 131 has its first signal input terminal connected to the data signal input terminal DATA, and its second signal input terminal used to receive the pull-down enable signal. The second NAND gate logic circuit 131 is used to generate a pull-down control signal PD for controlling the pull-down of the pull-down drive circuit 23 after performing logical encoding based on the data signal and the pull-down enable signal. The second inverter 132 has its input terminal connected to the output terminal of the second NAND gate logic circuit 131. The second inverter 132 is used to invert the pull-down control signal PD and then output it.

[0039] In this embodiment, the two input terminals of the second NAND gate logic circuit 131 are used to receive the data signal DATA and the pull-down enable signal PD_EN, respectively. When both the data signal DATA and the pull-down enable signal PD_EN are high, the second NAND gate logic circuit 131 outputs a low-level pull-down control signal PD. When either the data signal DATA or the pull-down enable signal PD_EN is not high, the second NAND gate logic circuit 131 outputs a low-level pull-down control signal PD. The second inverter 132 inverts the pull-down control signal PD and outputs it. For example, when the NOR gate logic circuit 111 outputs a high-level pull-down control signal PD, the pull-down control signal PD is inverted to a low level by the first inverter 112. And when the NOR gate logic circuit 111 outputs a low-level pull-down control signal PD, the pull-down control signal PD is inverted to a high level by the first inverter 112. The path formed by the second NAND gate logic circuit 131 and the second inverter 132 is used to generate a pull-down control signal PD, which is used to control the pull-down drive circuit 23 in the main drive circuit to be turned on or off.

[0040] In the above embodiments, it is understood that the storage receive driver of the present invention can be connected to the drivers of at least two types of memory. The storage receive pre-drive circuit 10 needs to output multiple pull-up control signals and pull-down control signals. When the multi-path control signals are switched, the delay is inconsistent, which may lead to misjudgment. To this end, the storage receive pre-drive circuit 10 introduces structural delay units on different drive control paths to achieve timing alignment of the pull-up control signal and the pull-down control signal PD, which is beneficial to improving the stability of drive switching and the integrity of high-speed interface signals.

[0041] Reference Figure 1 and Figure 3 In one embodiment, the storage receiving main drive circuit 20 includes: The first type of pull-up drive circuit 21 has an input terminal for receiving a first drive voltage, an enable terminal for receiving a first switch enable signal D5_EN, a controlled terminal for receiving a first pull-up control signal PU_D5, and an output terminal connected to the drive signal output terminal DQ. The first type of pull-up drive circuit 21 is used to pull up the voltage of the drive signal output terminal DQ to the first drive voltage level according to the first switch enable signal D5_EN and the first pull-up control signal PU_D5. The second type of pull-up drive circuit 22 has an input terminal for receiving a first drive voltage, an enable terminal for receiving a second switch enable signal LP5_EN, a controlled terminal for receiving a second pull-up control signal PU_LP5, and an output terminal connected to the potential drive signal output terminal DQ. The second type of pull-up drive circuit 22 is used to pull up the voltage of the drive signal output terminal DQ to the second drive voltage level according to the second switch enable signal LP5_EN and the second pull-up control signal PU_LP5. The amplitudes of the first drive voltage and the second drive voltage are different. The pull-down drive circuit 23 has a controlled terminal for receiving the pull-down control signal PD, an input terminal for grounding, and an output terminal connected to the drive signal output terminal DQ. The pull-down drive circuit 23 is used to pull down the voltage of the drive signal output terminal DQ to a low level when it receives the pull-down control signal PD.

[0042] In this embodiment, the signals connected to the first type of pull-up drive circuit 21 include control signals: a first pull-up control signal PU_D5, a first switch enable signal D5_EN, and a drive voltage with an amplitude of 1.1V. The first type of pull-up drive circuit 21 serves as the DDR5 pull-up path, pulling the output node to a drive voltage level of 1.1V in DDR5 mode. Upon receiving the first pull-up control signal PU_D5 and the switch enable signal under DDR5 DRAM, the first type of pull-up drive circuit 21 generates a pull-up drive signal under DDR5 DRAM, thereby pulling up the voltage of the drive signal output terminal DQ to the drive voltage level of DDR5 DRAM.

[0043] The second type of pull-up driver circuit 22 receives the following signals: a second pull-up control signal PU_LP5, a second switch enable signal LP5_EN, and a drive voltage with an amplitude of 0.6V. As the pull-up path for LPDDR5, the second type of pull-up driver circuit 22 pulls the output node to a drive voltage level of 0.6V in LPDDR5 mode. Upon receiving the second pull-up control signal PU_LP5 and the switch enable signal from the LPDDR5 DRAM, the second type of pull-up driver circuit 22 generates a pull-up drive signal for the LPDDR5 DRAM, thereby pulling the voltage at the drive signal output terminal DQ to the drive voltage level of the LPDDR5 DRAM.

[0044] Pull-down driver circuit 23 serves as a pull-down path, shared by both DDR5 DRAM and LPDDR5 DRAM. It pulls the output node low to ground when a low output level is required. When both pull-up and pull-down paths are disabled, the output node is in a high-impedance state. For example, in the bus idle state, during mode switching, or in a disabled state, the first type of pull-up driver circuit 21, the second type of pull-up driver circuit 22, and the pull-down driver circuit 23 switch the drive signal output terminal DQ to a high-impedance state based on the disabled signal output by the storage receive pre-drive circuit 10. It can be understood that the pull-down drive paths of DDR5 DRAM and LPDDR5 DRAM are shared uniformly, while the pull-up paths are split according to a standard. This ensures correct functionality while maximizing circuit reuse, optimizing the storage system area, and reducing the overall power consumption of the storage system.

[0045] Reference Figure 1 and Figure 3 In one embodiment, the first type of pull-up drive circuit 21 includes: The first mode switching switch Q11 has its controlled terminal as the enable terminal of the first type of pull-up drive circuit 21, and its input terminal as the input terminal of the first type of pull-up drive circuit 21. The first pull-up drive switch Q12 is the controlled terminal of the first type of pull-up drive circuit 21. The input terminal of the first pull-up drive switch Q12 is connected to the output terminal of the first mode switching switch Q11, and the output terminal of the first pull-up drive switch Q12 is the output terminal of the first type of pull-up drive circuit 21.

[0046] In this embodiment, the first mode switching switch Q11 is turned on / off based on the first switch enable signal D5_EN, and the first pull-up drive switch Q12 is turned on / off based on the first pull-up control signal PU_D5. When both the first mode switching switch Q11 and the first pull-up drive switch Q12 are turned on, a first pull-up drive signal is output to the drive signal output terminal DQ, thereby pulling up the voltage of the drive signal output terminal DQ to the level of the DDR5 DRAM drive voltage. The first mode switching switch Q11 and the first pull-up drive switch Q12 can be implemented using PMOS transistors or other switching transistors with equivalent pull-up structures. In DDR5 mode, when the low-level first pull-up control signal PU_D5 and the first switch enable signal D5_EN are received, both PMOS transistors are turned on, pulling the output node to the 1.1V power supply level.

[0047] Reference Figure 1 and Figure 3 In one embodiment, the second type of pull-up drive circuit 22 includes: The second mode switch Q21 has its controlled terminal as the enable terminal of the second type of pull-up drive circuit 22, and its input terminal as the input terminal of the second type of pull-up drive circuit 22. The second pull-up drive switch Q22 has its controlled terminal being the controlled terminal of the second type of pull-up drive circuit 22. The input terminal of the second pull-up drive switch Q22 is connected to the output terminal of the second mode switching switch Q21, and the output terminal of the second pull-up drive switch Q22 is the output terminal of the second type of pull-up drive circuit 22.

[0048] In this embodiment, the second mode switching switch Q21 is turned on / off based on the second switch enable signal LP5_EN, and the second pull-up drive switch Q22 is turned on / off based on the second pull-up control signal PU_LP5. When both the second mode switching switch Q21 and the second pull-up drive switch Q22 are turned on, a second pull-up drive signal is output to the drive signal output terminal DQ, thereby pulling up the voltage of the drive signal output terminal DQ to the level of the LPDDR5 DRAM drive voltage. The second mode switching switch Q21 can be implemented using a PMOS transistor, and the second pull-up drive switch Q22 can be implemented using an NMOS transistor, or other switching transistors with an equivalent pull-up structure. In LPDDR5 mode, when a high-level second pull-up control signal PU_LP5 and a low-level second switch enable signal LP5_EN are received, the PMOS transistor and the NMOS transistor are turned on respectively, pulling the output node to the 0.5V power supply level.

[0049] Reference Figure 1 and Figure 3 In one embodiment, the pull-down drive circuit 23 includes: The pull-down drive switch Q3 is the controlled terminal of the pull-down drive circuit 23, the input terminal of the pull-down drive switch Q3 is the input terminal of the pull-down drive circuit 23, and the output terminal of the pull-down drive switch Q3 is the output terminal of the pull-down drive circuit 23.

[0050] In this embodiment, the pull-down drive switch Q3 can be implemented using an NMOS transistor. Based on the pull-down control signal PD, the pull-down drive switch Q3 pulls the output node down to ground (GND). This path is shared by DDR5 DRAM and LPDDR5 DRAM, and is used to pull the output node low to ground potential when a low level output is required.

[0051] The present invention also proposes a storage system, including a memory and a storage receiver driver as described above, wherein the drive signal output terminal DQ of the storage receiver driver is connected to the data terminal of the memory.

[0052] The detailed structure of the storage receive driver can be referred to the above embodiments, and will not be repeated here. It is understood that since the above storage receive driver is used in the storage system of the present invention, the embodiments of the storage system of the present invention include all the technical solutions of all the embodiments of the above storage receive driver, and the technical effects achieved are exactly the same, and will not be repeated here.

[0053] In this embodiment, there can be multiple memories, which can share a bus. Chip selection of the corresponding memory is achieved through chip select (CS) and / or output enable (OE) signals. These memories can be used for high-speed interface direction switching. The storage receive driver can connect to two or more types of memories. Depending on the specific memory type to be accessed, the storage receive driver outputs a corresponding drive signal to drive the memory to operate.

[0054] The above description is merely an optional embodiment of the present invention and does not limit the scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of protection of the present invention.

Claims

1. A storage receiving driver, characterized in that, include; Data signal input terminal, used to receive data signals; The drive signal output terminal is used for connection to the memory; A storage and receiving pre-drive circuit is provided, wherein a first signal input terminal of the storage and receiving pre-drive circuit is connected to the data signal input terminal, and a second signal input terminal of the storage and receiving pre-drive circuit is used to receive a mode enable signal and a disable signal. The storage and receiving pre-drive circuit is used to generate a corresponding pull-up control signal or pull-down control signal according to the data signal and the mode enable signal; or, the storage and receiving pre-drive circuit generates a high-impedance control signal when a disable signal is received. The storage receiving main drive circuit has its controlled terminal connected to the output terminal of the storage receiving pre-drive circuit. Its enable terminal is used to receive a corresponding switch enable signal, and its output terminal is connected to the drive signal output terminal. The storage receiving main drive circuit operates in the corresponding drive mode according to the switch enable signal and drives the memory at the corresponding level according to the pull-up control signal or pull-down control signal. Alternatively, when the storage receiving main drive circuit receives the high-impedance control signal, it outputs a high-impedance signal to the drive signal output terminal to drive the memory to switch to a high-impedance mode.

2. The storage receive driver as claimed in claim 1, characterized in that, The mode enable signal includes a first mode enable signal, a second mode enable signal, and a pull-down enable signal; the storage receive pre-drive circuit includes: A first pull-up control circuit, wherein the first signal input terminal of the first pull-up control circuit is connected to the data signal input terminal, and the second signal input terminal of the first pull-up control circuit is used to receive a first mode enable signal; the first pull-up control circuit is used to generate a first pull-up control signal according to the data signal and the first mode enable signal, and the first pull-up control signal is used to control a first type of pull-up drive circuit. A second pull-up control circuit is provided, wherein the first signal input terminal of the second pull-up control circuit is connected to the data signal input terminal, and the second signal input terminal of the second pull-up control circuit is used to receive a second mode enable signal; the second pull-up control circuit is used to generate a second pull-up control signal based on the data signal and the second mode enable signal, and the second pull-up control signal is used to control the pull-up of a second type of pull-up drive circuit; wherein the drive voltages of the first type of pull-up drive circuit and the second type of pull-up drive circuit are different; A pull-down control circuit is provided, wherein a first signal input terminal of the pull-down control circuit is connected to the data signal input terminal, and a second signal input terminal of the pull-down control circuit is used to receive a pull-down enable signal; the pull-down control circuit is used to generate a pull-down control signal based on the data signal and the pull-down enable signal, and the pull-down control signal is used to control the pull-down drive circuit to pull down.

3. The storage receive driver as described in claim 2, characterized in that, The first pull-up control circuit includes: The NOR gate logic circuit has a first signal input terminal connected to the data signal input terminal, and a second signal input terminal used to receive the first mode enable signal; the NOR gate logic circuit is used to generate the first pull-up control signal by performing logic encoding based on the data signal and the first mode enable signal. The first inverter has its input terminal connected to the output terminal of the NOR gate logic circuit. The first inverter is used to invert the first pull-up control signal and then output it.

4. The storage receive driver as described in claim 2, characterized in that, The second pull-up control circuit includes: The first NAND gate logic circuit has a first signal input terminal connected to the data signal input terminal, and a second signal input terminal used to receive the second mode enable signal; the first NAND gate logic circuit is used to generate the second pull-up control signal by performing logic encoding based on the data signal and the second mode enable signal. A delay circuit is provided, the input of which is connected to the output of the first NAND gate logic circuit. The delay circuit is used to delay the second pull-up control signal before outputting it.

5. The storage receive driver as described in any one of claims 2 to 4, characterized in that, The pull-down control circuit includes: The second NAND gate logic circuit has its first signal input terminal connected to the data signal input terminal, and its second signal input terminal used to receive the pull-down enable signal; the second NAND gate logic circuit is used to generate the pull-down control signal by performing logic encoding based on the data signal and the pull-down enable signal. The second inverter has its input connected to the output of the second NAND gate logic circuit. The second inverter is used to invert the pull-down control signal and then output it.

6. The storage receive driver as claimed in claim 1, characterized in that, The storage receiving main driving circuit includes: The first type of pull-up drive circuit has an input terminal for receiving a first drive voltage, an enable terminal for receiving a first switch enable signal, a controlled terminal for receiving a first pull-up control signal, and an output terminal connected to the drive signal output terminal. The first type of pull-up drive circuit is used to pull up the voltage at the drive signal output terminal to the first drive voltage level according to the first switch enable signal and the first pull-up control signal. The second type of pull-up drive circuit has an input terminal for receiving a second drive voltage, an enable terminal for receiving a second switch enable signal, a controlled terminal for receiving a second pull-up control signal, and an output terminal connected to the drive signal output terminal. This second type of pull-up drive circuit is used to pull up the voltage at the drive signal output terminal to the second drive voltage level according to the second switch enable signal and the second pull-up control signal. The amplitudes of the first drive voltage and the second drive voltage are different. A pull-down driving circuit is provided, wherein the controlled terminal of the pull-down driving circuit is used to receive a pull-down control signal, the input terminal of the pull-down driving circuit is grounded, the output terminal of the pull-down driving circuit is connected to the drive signal output terminal, and the pull-down driving circuit is used to pull down the voltage of the drive signal output terminal to a low level when the pull-down control signal is received.

7. The storage receive driver as claimed in claim 6, characterized in that, The first type of pull-up drive circuit includes: A first mode switch, wherein the controlled terminal of the first mode switch is the enable terminal of the first type of pull-up drive circuit, and the input terminal of the first mode switch is the input terminal of the first type of pull-up drive circuit. The first pull-up drive switch has a controlled terminal that is the controlled terminal of a first type of pull-up drive circuit. The input terminal of the first pull-up drive switch is connected to the output terminal of the first mode switching switch, and the output terminal of the first pull-up drive switch is the output terminal of the first type of pull-up drive circuit.

8. The storage receive driver as claimed in claim 6, characterized in that, The second type of pull-up drive circuit includes: The second mode switch has a controlled terminal that is the enable terminal of the second type of pull-up drive circuit, and an input terminal that is the input terminal of the second type of pull-up drive circuit. The second pull-up drive switch has a controlled terminal that is the controlled terminal of the second type of pull-up drive circuit. The input terminal of the second pull-up drive switch is connected to the output terminal of the second mode switching switch, and the output terminal of the second pull-up drive switch is the output terminal of the second type of pull-up drive circuit.

9. The storage receive driver as claimed in any one of claims 6 to 8, characterized in that, The pull-down drive circuit includes: A pull-down drive switch, wherein the controlled terminal of the pull-down drive switch is the controlled terminal of the pull-down drive circuit, the input terminal of the pull-down drive switch is the input terminal of the pull-down drive circuit, and the output terminal of the pull-down drive switch is the output terminal of the pull-down drive circuit.

10. A storage system, characterized in that, It includes a memory and a memory receive driver as described in any one of claims 1 to 9, wherein the drive signal output terminal of the memory receive driver is connected to the data terminal of the memory.

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