Serial word line excitation with linked source voltage supply modulation

Abstract

Embodiments of this disclosure relate to serial word line excitation with linked source voltage supply modulation. SRAM cells are connected column-wise via bit lines and row-wise via first and second word lines coupled to first and second data storage sides of the SRAM cells. The first word lines are first excited in parallel, and then the second word lines are excited in parallel during first and second phases of in-memory computation operations, respectively. The bit line voltages in the first and second phases are processed to generate in-memory computation operation decisions. The low supply node reference voltage of the SRAM cell is selectively modulated between a ground voltage and a negative voltage. During the second phase, the first data storage side receives a negative voltage, and the second data storage side receives a ground voltage. Conversely, during the first phase, the second data storage side receives a negative voltage, while the first data storage side receives a ground voltage.

Description

Case Analysis

[0001] This application is a divisional application of patent application No. 202210805282.7, filed on July 8, 2022, entitled "Serial word line excitation with linked source voltage supply modulation". Technical Field

[0002] The embodiments described herein relate to in-memory computing circuitry utilizing an array of static random access memory (SRAM), and more specifically, to the performance of serial word line activation for simultaneous access of multiple rows of an SRAM array for in-memory computing operations. Furthermore, the serial word line activation can be linked to the modulation of the source supply voltage of the SRAM cell being accessed. Background Technology

[0003] refer to Figure 1 , Figure 1 A schematic diagram of in-memory computation circuitry 10 is shown. Circuitry 10 utilizes a static random access memory (SRAM) array 12, which is formed by standard 6T SRAM memory cells 14 arranged in a matrix format with N rows and M columns. Alternatively, standard 8T memory cells or other bit cells with similar topology and functionality can be used. Each memory cell 14 is programmed to store bits of computational weights for in-memory computational operations. In this context, in-memory computational operations are understood as high-dimensional matrix-vector multiplication (MVM) that supports multi-bit weights stored in multiple bit cells of memory. Bit cell groups (in the case of multi-bit weights) can be thought of as virtual synaptic elements. Each bit of the computational weight has a logic "1" or logic "0" value.

[0004] Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. An 8T-type SRAM cell also includes a read word line RWL and a read bit line RBT. Cells 14 in a common row of the matrix are connected to each other via a common word line WL (and via a common read word line RWL in the 8T-type implementation). Cells 14 in a common column of the matrix are connected to each other via a pair of common complementary bit lines BLT and BLC (and via a common read bit line RBL in the 8T-type implementation). Each word line WL, RWL is driven by a word line driver circuit 16, which may be implemented as a CMOS driver circuit (e.g., a series-connected pair of p-channel and n-channel MOSFET transistors forming a logic inverter circuit). The word line signal applied to the word line and driven by the word line driver circuit 16 is generated from feature data input to the in-memory computing circuitry 10 and controlled by a row controller circuit 18. Column processing circuit 20 senses analog signal voltages on complementary bit line pairs BLT and BLC (and / or read bit line RBL) of M columns and generates decision outputs from these analog signal voltages for in-memory computation operations. Column processing circuit 20 can be implemented to support processing in which the voltages on the columns are first processed individually, followed by recombination of multiple column outputs.

[0005] Although not in Figure 1 As explicitly shown, but should be understood, circuit 10 also includes conventional row decoding, column decoding and read / write circuitry known to those skilled in the art for writing bits of calculated weights into SRAM cells 14 of memory array 12 and reading bits of calculated weights from SRAM cells 14 of memory array 12.

[0006] Now for reference Figure 2 Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series-connected pair of p-channel and n-channel MOSFET transistors. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC that store the complementary logic states of the stored data bits. Cell 14 also includes two transfer gate transistors 26 and 28, whose gate terminals are driven by word line WL. The source-drain path of transistor 26 is connected between the true data storage node QT and the node associated with the true bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., Vdd) at the high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at the low supply node. Although Figure 2This design is specifically for use with 6T-type cells, but those skilled in the art will recognize that 8T-type cells are similarly configured and will further include signal paths coupled to one of the memory nodes, and transmission (transmission gate) transistors coupled to the read word line RWL and the gates driven by signals on the read word line RWL. The word line driver circuit 16 is also typically coupled to receive a high supply voltage (Vdd) at the high supply node and reference a low supply voltage (Gnd) at the low supply node.

[0007] Line controller circuit 18 executes the select word line WL <0> To WL<N-1> The function determines which of the following will be accessed (or activated) simultaneously during in-memory computation operations, and further executes the function of controlling the application of pulse signals to word lines based on characteristic data of the in-memory computation operations. This is merely an example. Figure 1 This illustration demonstrates the simultaneous activation of all N word lines using pulse word line signals. It should be understood that in-memory computation operations can alternatively utilize the simultaneous activation of fewer than all rows of the SRAM array. The analog signal voltage generated on a given complementary bit line pair BLT and BLC (or on the read bit line RBL in the 8T-type embodiment) depends on the logic state of the bits of the computational weights stored in the memory cells 14 of the corresponding columns and the width of the pulse word line signal applied to the characteristic data of those memory cells 14.

[0008] Figure 1 The illustrated implementation shows an example of pulse-width modulation (PWM) in the form of applied word line signals for in-memory computation operations. Using PWM or periodic pulse modulation (PTM) for applied word line signals is a common technique for in-memory computation operations based on the linearity of vectors in multiply-accumulate (MAC) operations. The pulsed word line signal format can be further developed into coded pulse sequences to manage the block sparsity of the feature data for in-memory computation operations. Therefore, it should be appreciated that when multiple word lines are driven simultaneously in response to feature data, any set of encoding schemes for the applied word line signals can be used. Furthermore, in a simpler implementation, it should be understood that all word line signals applied in simultaneous excitation can alternatively have the same pulse width.

[0009] Figure 3This is a timing diagram illustrating the assertion (logic high) of the precharge control signal PCH, which causes the bit line precharge circuit to charge complementary bit line pairs BLT and BLC to the Vdd voltage level. The precharge control signal PCH is then de-asserted (logic low), and subsequently, in response to the characteristic data of a given computation cycle of the in-memory computation operation, pulse-width modulated word line signals are simultaneously applied to multiple rows of memory cells 14 in the SRAM array 12. Analog signal voltages Va,T and Va,C evolve over time on the complementary bit line pairs BLT and BLC, respectively, decreasing from the precharge voltage Vdd in response to the pulse width of those word line signals and the logic state of the bits representing the computation weights stored in memory cells 14. The representation of the analog voltage Va level shown is merely an example. At the end of the computation cycle, the precharge control signal PCH is asserted again to return the bit line voltages to the precharge Vdd level before the next computation cycle. It should be noted that there is a risk that the analog voltage on at least one of the bit lines BLT and BLC may drop from the precharge (Vdd) voltage to a level that causes an unwanted data flip relative to the stored data bit value in one of the column memory cells 14. For example, a logic "1" state stored in column cell 14 can be flipped to a logic "0" state. Such a data flip introduces data errors into the computational weights stored in the memory cell, thereby jeopardizing the accuracy of subsequent in-memory computational operations.

[0010] Undesirable data flips due to excessive bit line voltage drops are primarily caused by simultaneous parallel access of word lines in matrix-vector multiplication mode during in-memory computation operations. This problem differs from normal data flips in SRAM bit cells due to a static noise margin (SNM) issue that occurs during serial bit cell access when the bit lines approach the supply voltage Vdd level. During serial access, normal data flips are instead caused by ground bounce at the data storage node QT or QC.

[0011] A known solution to the Serial Bit Cell Access (SNM) failure problem is to reduce the word line voltage slightly, typically achieved by shorting the word line driver and using a bleeder path. However, parallel access to multiple word lines during in-memory computation operations alternatively requires Radical-WL Lowering / Modulation (RWLM). Another known solution to the aforementioned problem is to apply a fixed word line voltage reduction (e.g., applying a voltage equal to Vdd / 2, VWLUD) at all IC processing corners to ensure the worst-case IC processing corner. However, this word line underdrive (WLUD) solution has a known drawback: the read current on the bit lines is correspondingly reduced, which can negatively impact computational performance. Furthermore, the use of a fixed word line underdrive voltage increases the variability of the read current across the array, leading to a loss of accuracy in in-memory computation operations.

[0012] Another solution is to use a dedicated bit cell circuit design for each memory cell 14, which is less likely to suffer unwanted data flips during simultaneous (parallel) access of multiple rows of in-memory computation operations. The concern with this solution is the increased circuit area occupied by such bit cell circuitry. For some in-memory computation applications, it is preferable to retain the standard 6TSRAM cells used in array 12. Figure 2 The advantages offered by 1000 TRAM cells or 8 TRAM cells.

[0013] Therefore, there is a need in the field for in-memory computing circuitry that supports standard 6T (or 8T) SRAM cells while ensuring that unwanted data flips are prevented during simultaneous row access. Summary of the Invention

[0014] In one embodiment, a circuit includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix of multiple rows and multiple columns, each column including a pair of bit lines connected to the SRAM cells of the column, and each row including: a first word line configured to drive a first transmission gate transistor of the SRAM cell coupled between a first data node of the SRAM cell and a bit line of the bit line pair; and a second word line configured to drive a second transmission gate transistor of the SRAM cell coupled between a second data node of the SRAM cell and another bit line of the bit line pair; a first word line driver circuit for each row having an output connected to drive the first word line of the row; and a second word line driver circuit for each row having an output connected to drive the first word line of the row. The output is connected to drive the second word line of the row; a row controller circuit configured to simultaneously activate only the first word line during a first phase of an in-memory computation operation by applying a pulse to the first word line via the first word line driver circuit, and then simultaneously activate only the second word line during a second phase of the in-memory computation operation by applying a pulse to the second word line via the second word line driver circuit; a column processing circuit connected to the bit line pairs of each column and configured to process analog voltages generated on the bit line pairs in response to the first and second phases of the in-memory computation operation to generate a decision output; and a source supply modulation circuit configured to switch the modulation reference supply voltage for the SRAM cell from ground voltage to a negative voltage during the first and second phases of the in-memory computation operation.

[0015] In one embodiment, a circuit includes: a memory array comprising a plurality of memory cells, each memory cell including a latch circuit, the latch circuit including a first side having a first data node and a first low supply node, and the latch circuit further including a second side having a second data node and a second low supply node; wherein the plurality of memory cells are arranged in a matrix having multiple rows and multiple columns, each column including bit line pairs connected to the memory cells of the column, and each row including a first word line connected to the first side of the latch circuit and a second word line connected to the second side of the latch circuit; and a row controller circuit configured to only send data to the first side of the memory circuit during a first phase of an in-memory computation operation. The first word line is simultaneously pulsed, and then only the second word line is simultaneously pulsed during the second phase of the in-memory computation operation; a column processing circuit connected to the bit line pairs of each column and configured to process the analog voltage generated on the bit line pairs in response to the first and second phases of the in-memory computation operation to generate a decision output; and a source supply modulation circuit configured to switch a first modulation reference supply voltage at the first low supply node from ground voltage to a negative voltage during the second phase, and a second modulation reference supply voltage at the second low supply node from the ground voltage to the negative voltage during the first phase.

[0016] In one embodiment, the circuitry includes SRAM cells connected column-wise by bit lines and row-wise by first word lines and second word lines coupled to a first data storage side and a second data storage side of the SRAM cell. For in-memory computation operations, the first word lines are activated in parallel in a first phase and then the second word lines are activated in parallel in a second phase. The bit line voltages in the first and second phases are processed to generate in-memory computation operation decisions. The low supply node reference voltage of the SRAM cell is selectively modulated between a ground voltage and a negative voltage in a manner linked to serial access using the first and second word lines. During the second phase, when the second word lines are activated simultaneously in parallel, the first data storage side receives a negative voltage and the second data storage side receives a ground voltage. Conversely, during the first phase, when the first word lines are activated simultaneously in parallel, the second data storage side receives a negative voltage while the first data storage side receives a ground voltage. Attached Figure Description

[0017] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0018] Figure 1 This is a schematic diagram of the computing circuitry within the memory;

[0019] Figure 2 Is using Figure 1The circuit diagram shown is of a standard 6T static random access memory (SRAM) cell in a memory array for in-memory computing circuitry.

[0020] Figure 3 This is an explanation Figure 1 Timing diagram of the computational operations within the memory of the circuit;

[0021] Figure 4 This is a circuit diagram of an embodiment of a circuit for providing overdrive voltage and access to time-division multiplexed bit lines;

[0022] Figure 5 Is using Figure 4 The circuit diagram shown is of a 6T SRAM cell in a memory array for in-memory computing circuitry.

[0023] Figure 6 This is an explanation Figure 4 Timing diagram of the computational operations within the memory of the circuit;

[0024] Figure 7 This is a circuit diagram of an embodiment of a circuit for providing overdrive voltage and access to a time-multiplexed bit line connected to a source-supply modulated modulation circuit;

[0025] Figure 8 Is using Figure 7 The circuit diagram shown is of a 6TSRAM cell in a memory array for in-memory computing circuitry.

[0026] Figure 9 This is an explanation Figure 7 Timing diagram of the computational operations within the memory of the circuit;

[0027] Figure 10 This is a circuit diagram of an embodiment of a circuit used to provide a modulated reference supply voltage;

[0028] Figure 11 This is a circuit diagram of an embodiment of a circuit used to provide a modulated reference supply voltage;

[0029] Figure 12 This is a circuit diagram of an embodiment of a circuit used to provide a modulated reference supply voltage;

[0030] Figure 13 This is a circuit diagram of an embodiment of a circuit for providing a modulated reference supply voltage; and

[0031] Figure 14 It's a flowchart. Detailed Implementation

[0032] Now for reference Figure 4 , Figure 4 A schematic diagram of the in-memory computing circuit 110 is shown. Figure 1 and Figure 4 The same reference numerals in the figures indicate the same or similar components, and their descriptions will not be repeated (see the description above). Circuit 110 differs from circuit 10 in that the word line access control for the true and complementary sides of the latch for each SRAM cell has been separated, as shown below. Figure 5 As shown in more detail below. Each cell 14 includes a first transfer (transmission gate) transistor 26 for the true side of the latch, having a gate terminal driven by a first word line WL1. The source-drain of transistor 26 is connected between the true data storage node QT and the node associated with the true bit line BLT. Each cell 14 further includes a second transfer (transmission gate) transistor 28 for the complementary side of the latch, having a gate terminal driven by a second word line WL2. The source-drain of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. With this configuration, word line access to each side of the memory cell 14 can be controlled independently. The circuit also supports the performance of one stage (first stage p1) of an in-memory computation operation that is associated only with the activation of the first word line WL1 in response to accessing / reading feature data on the true side of the latch, and the performance of another stage (second stage p2) of an in-memory computation operation that is associated only with the activation of the second word line WL2 in response to accessing / reading feature data on the complementary side of the latch. The word line signals applied to the first word line and the second word lines WL1 and WL2 are generated in response to the same feature data and will have the same pulse width.

[0033] Figure 6 This is a timing diagram illustrating the circuitry of a computation cycle for an in-memory computation operation, performed in a time-multiplexed manner relative to the true and supplementary sides of the latches of SRAM cells in a given column of the array. Both the true bit line (BLT) and the supplementary bit line (BLC) of the given column are precharged to the desired voltage level (shown here as Vdd voltage level, but other voltage levels are possible) by a bit line precharge circuit. In the first phase p1 of the computation cycle, starting at time ta1, where the true side of the latch circuit is accessed, the bit line precharge terminates, and in response to the characteristic data of the given in-memory computation operation, the row controller circuit 18 simultaneously applies pulse-width modulated word line signals to only the first word lines WL1 of the multiple rows of memory cells 14 in the SRAM array 12. The analog signal voltage Va,T progresses over time on the true bit line BLT, decreasing from the precharge voltage level Vdd in response to the pulse width of those word line signals and the logic state of the bits representing the computational weights stored on the true side of the memory cells 14. The representation of the analog voltage Va,T level shown is merely an example.

[0034] In the second phase p2 of the computation cycle beginning at time ta2, where access is made to the complementary side of the latch circuitry, in response to the characteristic data of a given computational operation within the memory, the row controller circuit 18 simultaneously applies pulse-width modulated word line signals (with the same characteristic data and pulse width as in phase p1) to only the second word line WL2 of the multi-row memory cells 14 in the SRAM array 12. The analog signal voltage Va,C evolves over time on the complementary bit line BLC, decreasing from the precharge voltage level Vdd in response to the pulse width of those word line signals and the logic state of the bits representing the computational weights stored on the complementary true side of the memory cell 14. The representation of the analog voltage Va,C level shown is merely an example.

[0035] Column processing circuit 20 senses analog signal voltages on the complementary bit line pairs BLT and BLC of columns M and generates decision outputs for in-memory computation operations based on these analog signal voltages. It should be noted that the sampling of analog signal voltages Va,T and Va,C is typically performed by column processing circuit 20 at two separate times. The first time is associated with the simultaneous application of pulse-width modulated word line signals to the first word line WL1 during the first phase p1 (at time ts1), where access is made to the true side of the latch circuitry, and the second time is associated with the simultaneous application of pulse-width modulated word line signals to the second word line WL1 during the second phase p2 (at time ts2), where access is made to the complementary side of the latch circuitry. Subsequent sampling (i.e., at or after time ts2) precharges the bit lines back to the precharge voltage level.

[0036] Now for reference Figure 7 , Figure 7 A schematic diagram of the in-memory computing circuit 210 is shown. Figure 1 and Figure 7 The same reference numerals in the figures indicate the same or similar components, and their descriptions will not be repeated (see the description above). Circuit 210 differs from circuit 10 in that the word line access control for the true and complementary sides of the latch for each SRAM cell has been separated, as shown below. Figure 8As shown in more detail below, each cell 14 includes a first transfer (transmission gate) transistor 26 for the true side of the latch circuit, having a gate terminal driven by a first word line WL1. The source-drain of transistor 26 is connected between the true data storage node QT and the node associated with the true bit line BLT. Each cell 14 further includes a second transfer (transmission gate) transistor 28 for the complementary side of the latch circuit, having a gate terminal driven by a second word line WL2. The source-drain of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. With this configuration, word line access to each side of the latch circuit of the memory cell 14 can be controlled independently. The circuit also supports the performance of one stage (first stage p1) of an in-memory computation operation and the performance of another stage (second stage p2) of an in-memory computation operation. One stage of the in-memory computation operation is associated with the true side of the latch circuit, which is activated only on the first word line WL1 in response to feature data to access / read the latch circuit. The other stage of the in-memory computation operation is associated with the complementary side of the latch circuit, which is activated only on the second word line WL2 in response to feature data to access / read the latch circuit. The word line signals on the first and second word lines WL1 and WL2 are generated in response to feature data and will have the same pulse width.

[0037] Circuit 210 differs from circuit 10 in that it provides a source supply modulation circuit 222 to control the reference voltage level at the source terminal of the pull-down transistor in each SRAM cell 14 (i.e., for each side of the latch circuit, there is separate modulation of the voltage at the low supply node). Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24 forming the latch circuit. The source terminals of the p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., a positive voltage Vdd) at the high supply node. However, unlike... Figure 2 and Figure 5In the illustrated embodiment, the source terminal of the (pull-down) n-channel transistor 34 on the true side of the latch circuit associated with the data storage node QT is coupled to receive a (first) modulated reference supply voltage VssT at the true low supply node 224, and the source terminal of the (pull-down) n-channel transistor 36 on the complementary side of the latch circuit associated with the data storage node QC is coupled to receive a (second) modulated reference supply voltage VssC at the complementary low supply node 226. The voltage levels of the modulated reference supply voltage VssT on the true side of the latch circuit and the modulated reference supply voltage VssC on the complementary side of the latch circuit can be controlled independently. In particular, each voltage level is selectively controlled by the source supply modulation circuit 222 to be at a ground reference voltage (Gnd) or a negative reference voltage (Vneg). Even more specifically, as will be explained in detail below, the modulation of the voltages at the true low supply node 224 and the complementary low supply node 226 (e.g., switching between Gnd and Vneg levels) depends on the operating phase of circuitry 210, which is related to the performance of in-memory computation operations, and can be linked to independent control of word line access to each side of the latch circuitry of memory cell 14.

[0038] It should be noted that the negative absolute value of voltage Vneg is preferably defined by the following: a) when the source of pull-down transistor 34 is brought to a negative voltage level and the second word line WL2 is asserted, it remains in a logic 1 state at the QT node, and b) when the source of pull-down transistor 36 is brought to a negative voltage level and the first word line WL1 is asserted, it remains in a logic 1 state at the QC node.

[0039] Whenever stage p1 of an in-memory computation operation is performed, the row controller circuit 18 asserts the stage p1 enable signal p1_En. The source supply modulation circuit 222 responds to the assertion of the stage p1 enable signal p1_En by selectively switching the voltage level of the modulation reference supply voltage VssC at the complementary low supply node 226 on the complementary side of the latch circuit in each SRAM cell 14 to the negative reference voltage Vneg, where access is made to the true side of the latch circuit. It should be noted that this selective switching has no effect on the voltage level of the modulation reference supply voltage VssT at the true low supply node 224 in each SRAM cell 14, which is maintained at the ground reference voltage Gnd. Similarly, whenever stage p2 of an in-memory computation operation is performed, the row controller circuit 18 asserts the stage p2 enable signal p2_En. The source supply modulation circuit 222 responds to the assertion of the stage p2 enable signal p2_En by selectively switching the voltage level of the modulation reference supply voltage VssT at the true low supply node 224 on the true side of the latch circuit in each SRAM cell 14 to the negative reference voltage Vneg, where access is made to the complementary side of the latch circuit. It should be noted that this selective switching has no effect on the voltage level of the modulation reference supply voltage VssC at the complementary low supply node 226 in each SRAM cell 14, which is maintained at the ground reference voltage Gnd.

[0040] Figure 9 This is a timing diagram illustrating the circuitry of a computation cycle for an in-memory computation operation performed in a time-multiplexed manner relative to access / read of the true and complementary sides of latches for SRAM cells 14 in a given column of the array. This operation is associated with modulation of the voltage level at the true low supply node 224 and the voltage level at the complementary low supply node 226 in each SRAM cell 14. Both the true bit line BLT and the complementary bit line BLC of the given column are precharged to the desired voltage level (shown here as Vdd voltage level by example) by a bit line precharge circuit; however, it should be understood that an alternative voltage level can be used for the precharge voltage.

[0041] In the first phase p1 of the computation cycle beginning at time ta1, the pre-charge of the bit lines terminates, and the source supply modulation circuit 222 responds to the assertion of the phase p1 enable signal p1_En associated with the true side of the access latch by switching the voltage level of the modulation reference supply voltage VssC associated with the complementary side of the latch at the complementary low supply node 226 in each SRAM cell 14 from the ground voltage Gnd to the negative reference voltage Vneg (while maintaining the voltage level of the modulation reference supply voltage VssT at the true low supply node 224 in each SRAM cell 14 at the ground reference voltage Gnd). The row controller circuit 18 also responds to the characteristic data of a given in-memory computation operation on the true side (i.e., at the real data storage node QT and bit line BLT) by simultaneously applying pulse width modulated word line signals to the first word line WL1 of the multiple row memory cells 14 in the SRAM array 12. The analog signal voltage Va,T evolves over time on the true bit line BLT, decreasing from the precharge voltage level Vdd in response to the pulse width of those word line signals and the logic state of the bits with calculated weights stored on the true side of memory cell 14. The representation of the analog voltage Va,T level shown is merely an example. The advantageous effect of modulating the voltage level of the modulation reference supply voltage VssC at the complementary low supply node 226 to the negative reference voltage Vneg on the opposite side of the latch circuit to the read access is to enhance the strength of the (pull-up) p-channel transistor 30 in each cell 14 to maintain the logic "1" state stored at the complementary data storage node QC. This provides improved immunity to unwanted data flips from logic "1" to logic "0" due to the decrease in the analog voltage Va,T level on the true side of the latch circuit.

[0042] In the second phase p2 of the computation cycle beginning at time ta2, the source supply modulation circuit 222 responds to the assertion of the phase p2 enable signal p2_En associated with the complementary side of the access latch by switching the voltage level of the modulation reference supply voltage VssT associated with the true side of the latch at the true low supply node 224 in each SRAM cell 14 to the negative reference voltage Vneg (while maintaining the voltage level of the modulation reference supply voltage VssC at the complementary low supply node 226 in each SRAM cell 14 at the ground reference voltage Gnd). The row controller circuit 18 also responds to the characteristic data of a given in-memory computation operation on the complementary side (i.e., at the complementary data storage node QC and bit line BLC) by applying a pulse width modulated word line signal (with the same characteristic data and pulse width as in phase p1) only to the second word line WL2 of the multi-row memory cells 14 in the SRAM array 12. The analog signal voltage Va,C evolves over time on the complementary bit line BLC, decreasing from the precharge voltage level Vdd in response to the pulse width of those word line signals and the logic state of the bits with calculated weights stored on the complementary side of memory cell 14. The representation of the analog voltage Va,C level shown is merely an example. The advantageous effect of modulating the voltage level of the modulated reference supply voltage VssT at the true low supply node 224 to the negative reference voltage Vneg on the opposite side of the latch circuit to the read access is to enhance the strength of the (pull-up) p-channel transistor 32 in each cell 14 to maintain the logic "1" state stored at the true data storage node QT. This provides improved immunity to unwanted data flips from logic "1" to logic "0" due to the decrease in the analog voltage Va,C level on the complementary side of the latch circuit.

[0043] Column processing circuit 20 senses analog signal voltages on the complementary bit line pairs BLT and BLC of columns M and generates decision outputs for in-memory computation operations based on these analog signal voltages. It should be noted that the sampling of analog signal voltages Va,T and Va,C is typically performed by column processing circuit 20 at two separate times: the first time is associated with the simultaneous application of pulse-width modulated word line signals to the first word line WL1 during the first phase p1 (at time ts1), and the second time is associated with the simultaneous application of pulse-width modulated word line signals to the second word line WL1 during the second phase p2 (at time ts2). Subsequent sampling (i.e., at or after time ts2) precharges the bit lines back to the precharge voltage level.

[0044] Now for reference Figure 10The diagram illustrates a circuit diagram of an embodiment of circuitry 300 within a source-supply modulation circuitry 222 for providing modulation reference supply voltages VssT and VssC. Circuitry 300 includes a first n-channel MOSFET device 302 having a source coupled (preferably directly connected) to a ground reference node Gnd and drains coupled (preferably directly connected) to the source terminals of an n-channel transistor 34, the true low supply nodes 224 being located on the true side of a latch circuit (associated with a data storage node QT) coupled to receive the modulation reference supply voltage VssT. The gate of transistor 302 is coupled to receive a stage p2 enable signal p2_En. A first capacitor 304 has a first terminal coupled (preferably directly connected) to the gate of transistor 302 and a second terminal coupled (preferably directly connected) to the true low supply nodes 224. The source of the second n-channel MOSFET device 306 is coupled (preferably directly connected) to a plurality of (if not all) complementary low-supply nodes 226 on the complementary side of the source terminal of the (pull-down) n-channel transistor 36, the latch circuit being coupled to receive a modulated reference supply voltage VssC. The gate of transistor 306 is coupled to receive the stage p1 enable signal p1_En. The second capacitor 308 has a first terminal coupled (preferably directly connected) to the gate of transistor 306 and a second terminal coupled (preferably directly connected) to the complementary low-supply node 226.

[0045] Circuit 300 operates as follows. When the stage p2 enable signal p2_En and the stage p1 enable signal p1_En are deasserted (logic high), transistors 302 and 306 are turned on, and a boost voltage approximately equal to the supply voltage Vdd is stored on the first capacitor and the second capacitors 304 and 308. Furthermore, because transistors 302 and 306 are turned on, the voltage levels at the true low supply node 224 and the complementary low supply node 226 are maintained at the ground reference voltage Gnd. In the first stage p1, the stage p1 enable signal p1_En is asserted (logic low), and the voltage at the complementary low supply node 226 is boosted to the level of the negative reference voltage Vneg by the boost voltage stored on the second capacitor 308 (where the negative voltage level is set by the capacitor ratio and is typically on the order of several hundred millivolts). As described above, when the source of the same-side pull-down transistor is brought to a negative voltage level and the opposite-side word line is asserted, the negative absolute value of voltage Vneg is limited by the maintenance of the logic 1 state on the latch node. Conversely, in the second phase p2, the phase p2 enable signal p2_En is asserted (logic low), and the voltage at the true low supply node 224 is boosted to the level of the negative reference voltage Vneg by the boost voltage stored on the first capacitor 304.

[0046] Now for reference Figure 11 The diagram illustrates a circuit diagram of an embodiment of circuitry 310 within a source-supply modulation circuitry 222 for providing modulation reference supply voltages VssT and VssC. Circuitry 310 includes a first n-channel MOSFET device 312 having a source coupled (preferably directly connected) to a ground Gnd reference node and a source terminal coupled (preferably directly connected) to a plurality of (if not) true low supply nodes 224 for (pull-down) n-channel transistors 34 on the true side of a latching circuit (associated with a data storage node QT), coupled to receive the modulation reference supply voltage VssT. The gate of transistor 312 is coupled to receive a stage p2 enable signal p2_En. A plurality of switched capacitor circuits 314 are coupled between the gate of transistor 312 and the true low supply nodes 224. Each switched capacitor circuit 314 includes a capacitor C connected in series with a switch S (which may be implemented by a transistor device). The second n-channel MOSFET device 316 has a source coupled (preferably directly connected) to a ground Gnd reference node and drains of a plurality of (if not all) complementary low-supply nodes 226 coupled (preferably directly connected) to the source terminal of a (pull-down) n-channel transistor 36 on a complementary side of a latch circuit (associated with a data storage node QC), the complementary low-supply nodes 226 being coupled to receive a modulated reference supply voltage VssC. The gate of transistor 316 is coupled to receive a stage p1 enable signal p1_En. A plurality of switched capacitor circuits 318 are coupled between the gate of transistor 316 and the complementary low-supply nodes 226. Each switched capacitor circuit 318 includes a capacitor C connected in series with a switch S (which may be implemented by a transistor device). A digital control circuit 320 generates a multi-bit digital control signal Csel that selectively activates one or more switches S of switched capacitor circuits 314 and 318 in relation to the level of the generated negative reference voltage Vneg.

[0047] Circuit 310 operates similarly to circuit 300, except that circuit 310 allows modulation of the level of the negative reference voltage Vneg via selective switching S. The more switches S are activated, the more negative the generated negative reference voltage Vneg becomes. The strength of the pull-up transistors in memory cell 14 needs to be modulated to ensure the stability of the stored data. Selective activation of the switches S optimizes pull-up strength modulation without wasting additional energy. This strength modulation can depend on integrated circuit processing and / or temperature information. For example, if process information indicates that the MOSFET devices in memory cell 12 are in a fast-slow processing angle (where NMOS is fast and PMOS is slow), digital control circuit 320 can assert bits of a multi-bit digital control signal Csel to control the selection of switched capacitor circuits 314 and 318, thereby providing a relatively high voltage level (e.g., above the nominal or typical negative voltage level) for the negative reference voltage Vneg. Similarly, if the temperature information indicates a relatively low temperature, the lower absolute value of the negative voltage level can be selected using the multi-digit control signal Csel; conversely, for a relatively high temperature, the selection can be made up of the higher absolute value of the negative voltage level.

[0048] Now for reference Figure 12 The diagram illustrates a circuit diagram of an embodiment of circuitry 330 within a source supply modulation circuitry 222 for providing modulation reference supply voltages VssT and VssC. Circuitry 330 includes a voltage generator circuitry 332 configured to generate a negative reference voltage Vneg. The voltage generator circuitry 332 may, for example, include a voltage regulator circuitry (e.g., a low dropout (LDO) regulator) that generates the negative reference voltage Vneg from the input voltage. Alternatively, the voltage generator circuitry 332 may, for example, include a charge pump circuitry that generates the negative reference voltage Vneg from the supply voltage Vdd.

[0049] The first switching circuit 334 (illustrated herein as an analog multiplexing circuit by way of example only) has a first input configured to receive a negative reference voltage Vneg output from the voltage generator circuit 332 and a second input configured to receive a ground reference voltage Gnd. The output of the first switching circuit 334 is coupled (preferably directly connected) to a plurality (if not all) true low supply nodes 224 of the source terminals of a (pull-down) n-channel transistor 34 on the true side of a latch circuit (associated with the data storage node QT), the latch circuit being coupled to receive a modulated reference supply voltage VssT. The selection operation performed by the first switching circuit 334 is controlled by a stage p2 enable signal p2_En. When the stage p2 enable signal p2_En is deasserted, the first switching circuit 334 applies the ground reference voltage Gnd as the modulated reference supply voltage VssT. Conversely, when the stage p2 enable signal p2_En is asserted, the first switching circuit 334 applies the negative reference voltage Vneg as the modulated reference supply voltage VssT.

[0050] The second switching circuit 336 (illustrated herein as an analog multiplexing circuit by way of example only) has a first input configured to receive a negative reference voltage Vneg output from the voltage generator circuit 332 and a second input configured to receive a ground reference voltage Gnd. The output of the second switching circuit 336 is coupled (preferably directly connected) to a plurality (if not all) of complementary low-supply nodes 226 on the complementary side of a latch circuit (associated with the data storage node QC) of a (pull-down) n-channel transistor 36, which is coupled to receive a modulated reference supply voltage VssC. The selection operation performed by the second switching circuit 336 is controlled by a stage p1 enable signal p1_En. When the stage p1 enable signal p1_En is deasserted, the second switching circuit 336 applies the ground reference voltage Gnd as the modulated reference supply voltage VssC. Conversely, when the stage p1 enable signal p1_En is asserted, the second switching circuit 336 applies the negative reference voltage Vneg as the modulated reference supply voltage VssC.

[0051] Now for reference Figure 13 It shows a circuit diagram of an embodiment of circuit 350 within the source supply modulation circuit 222 for providing modulation reference supply voltages VssT and VssC. Figure 12 and 13 The same reference numerals in the figures indicate the same or similar parts, and their descriptions will not be repeated (see the description above). Circuit 350 differs from circuit 330 in that the level of the negative reference voltage Vneg is modulated according to integrated circuit processing and / or temperature conditions.

[0052] Voltage generator circuit 332 receives a control signal Vsel, which in one embodiment is a digital signal, but may also be an analog control signal. The digital value of the bits in the control signal Vsel selects the level of the negative reference voltage Vneg output by voltage generator circuit 332. The control signal Vsel is generated by control circuit 114 in response to integrated circuit processing and / or temperature information, and therefore modulates the level of negative reference voltage Vneg in a manner dependent on said integrated circuit processing and / or temperature information.

[0053] The integrated circuit processing information is a digital code stored in memory M within control circuitry 114. This digital code represents the center of the processing batch and is generated by a circuit such as a ring oscillator (RO), the output frequency of which varies according to the integrated circuit processing. Therefore, the output frequency of the RO circuit represents the processing center and can be easily converted into a digital code (e.g., using a counter circuit). Process monitoring circuitry 116 within control circuitry 114 can generate a digital value for the control signal Vsel based on the stored digital code for the integrated circuit process. For example, process monitoring circuitry 116 may include a lookup table (LUT) that associates each digital code with a digital value for the control signal Vsel to provide a specific level of the negative reference voltage Vneg, which will generate an optimal boost level for the strength of the (pull-up) p-channel transistors in each cell 14 to maintain a logic "1" state and ensure that unwanted data flips are prevented at a given integrated circuit process angle. Control circuitry 114 outputs the digital value of the control signal Vsel associated with the stored digital code, and voltage generator circuitry 332 responds by generating a corresponding level of the negative reference voltage Vneg.

[0054] Temperature information is generated by temperature sensing circuit 118 and represents the current temperature of the integrated circuit. Temperature sensing circuit 118 can selectively modify or adjust the digital value of the control signal Vsel, which is a function of the detected temperature. For example, temperature sensing circuit 118 may include a lookup table (LUT) that specifies a particular (positive or negative) adjustment of the digital value of the control signal Vsel to provide a corresponding tuning for a specific level of the negative reference voltage Vneg, which will generate optimal performance given the integrated circuit processing angle and current temperature conditions.

[0055] Now for reference Figure 14 It shows Figure 13The flowchart illustrates the operation of the control circuit 114 and process monitoring circuit 116 of the circuit. In step 140, the stored digital code for integrated circuit processing is read from the memory M. In one embodiment, the digital code for integrated circuit processing is loaded into the memory M at the factory, and the digital code is based on the identified integrated circuit processing characteristics (fast / slow corners, etc.) for the integrated circuit manufacturing batch (e.g., source wafer), from which integrated circuits are obtained. Next, in step 142, it is determined whether the read digital code for integrated circuit processing indicates that the MOSFET device of the memory cell 12 is at a certain integrated circuit processing corner (e.g., where NMOS is fast and PMOS is slow – “FS” corner). If so, in step 144, a digital value of the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 332 to generate a negative reference voltage Vneg level higher than the nominal (or default or typical) level. The effect of being higher than the nominal level is to increase the strength of the pull-up transistor and provide better stability and resistance to bit cell flipping. If no in step 142, then in step 146 it is determined whether the read digital code for integrated circuit processing indicates that the MOSFET device of memory cell 12 is in another integrated circuit processing angle (e.g., where NMOS is slow and PMOS is fast – the “SF” angle). If yes, then in step 148 a digital value of the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 332 to generate a negative reference voltage Vneg level below the nominal (or default or typical) level. The effect of being below the nominal level is to ensure bit cell stability with an optimal negative voltage level for power saving. If no in step 146, then in step 150, a digital value of the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 332 to generate a negative reference voltage Vneg level below the nominal level.

[0056] although Figure 14 The process envisions three levels of voltage control (above, below, and equal to nominal), but it should be understood that this is merely exemplary. Additional test steps may be added. Figure 14 During the process, other integrated circuit process angles or process-related conditions are tested, wherein each test has an associated digital code and a digital value of the control signal Vsel to set the corresponding level of the negative reference voltage Vneg generated by the voltage generator circuit 332.

[0057] The foregoing description has provided a complete and informative description of exemplary embodiments of the invention through exemplary and non-limiting examples. However, various modifications and adaptations will become apparent to those skilled in the art when read in conjunction with the accompanying drawings and appended claims, given the foregoing description. Nevertheless, all such modifications and similar alterations taught in this invention will still fall within the scope of the invention as defined by the appended claims.

Claims

1. A method for accessing a memory array during in-memory computation operations, the memory array comprising a plurality of memory cells, each memory cell including latch circuitry, the latch circuitry including a first side having a first data node and a first low supply node coupled to a first modulation reference supply voltage, and further including a second side having a second data node and a second low supply node coupled to a second modulation reference supply voltage, wherein the plurality of memory cells are arranged in a matrix having a plurality of rows and a plurality of columns, each column including a pair of bit lines connected to the memory cells in the column, and each row including a first word line connected to the first side of the latch circuitry and a second word line connected to the second side of the latch circuitry, the method comprising: In the first stage of the computation operation within the memory, pulses are applied simultaneously only to the first word line; During the first phase, the second modulation reference supply voltage at the second low supply node is switched from ground voltage to negative voltage; Then, in the second phase of the computation operation within the memory, pulses are applied simultaneously only to the second word line; During the second phase, the first modulation reference supply voltage at the first low supply node is switched from the ground voltage to the negative voltage; as well as The analog voltage generated on the bit line pair is processed in response to the first and second phases of the in-memory computation operation to generate a decision output for the in-memory computation operation.

2. The method of claim 1, further comprising controlling the level of the negative voltage depending on information regarding integrated circuit processing conditions.

3. The method of claim 1, further comprising controlling the level of the negative voltage depending on information about the temperature conditions of the integrated circuit.

4. The method of claim 1, wherein switching to the negative voltage comprises: A boost is performed to generate the negative voltage, and the level of the negative voltage depends on information about integrated circuit processing and / or temperature conditions.

5. The method of claim 1, wherein switching to the negative voltage comprises: The negative voltage is generated; as well as The level of the negative voltage is controlled in response to a control signal; The control signal is configured to modulate the level of the negative voltage away from the nominal level in response to the applicable integrated circuit processing angle of the transistor device for the memory cell.

6. The method of claim 5, wherein the applicable integrated circuit processing angle is indicated by programming code, and the method further comprises: The programming code is stored in a lookup table (LUT) that associates the programming code with the value of the control signal.

7. The method of claim 5, further comprising sensing temperature, wherein the control signal is configured to cause temperature-dependent adjustment of the level of the negative voltage.

8. The method of claim 7, further comprising storing in a lookup table (LUT) the correlation between temperature and the adjustment level of the value of the control signal.

9. The method of claim 1, wherein switching to the negative voltage comprises: The negative voltage is generated; Sensing temperature; as well as In response to the sensed temperature, the level of the negative voltage is controlled to move away from the nominal level.

10. The method of claim 9, further comprising storing in a lookup table (LUT) the correlation between temperature and the adjustment level of the value of the negative voltage.

11. The method according to claim 1: During the first phase, the first modulation reference supply voltage at the first low supply node remains at the ground voltage; and During the second phase, the second modulation reference supply voltage at the second low supply node remains at the ground voltage.

12. The method of claim 1, further comprising: During the first phase, data is read from the first data node on the first side of the latch; as well as During the second phase, data is read from the second data node on the second side of the latch.

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