Storage device and method of operating the same

Abstract

This disclosure relates to a storage device and a method of operating the same. A method of operating a storage device includes: receiving a first write command; performing a first preselection operation to determine whether a first storage cell is powered on; performing a second preselection operation based on a result of the first preselection operation indicating that the first storage cell is not powered on; and determining the first storage cell as a faulty cell based on a result of the second preselection operation indicating that the first storage cell is not powered on.

Description

[0001] Cross-reference to related applications

[0002] The application claims priority to Korean Patent Application No. 10-2025-0012317, filed with the Korean Intellectual Property Office on January 31, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments relate to integrated circuit technology, and more specifically, to a storage device and a method of operating the same. Background Technology

[0004] In recent years, with the reduction in size, power consumption, performance improvement and diversification of electronic devices, many electronic devices (such as computers and portable communication devices) require memory capable of storing information.

[0005] The memories under investigation also include those capable of storing data by utilizing the property that the memory switches between different resistance states depending on the applied voltage or current. These memories include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuse (E-fuse), and selector-only memory (SOM). Summary of the Invention

[0006] In one embodiment, an operation method of a storage device may include: receiving a first write command; performing a first preselection operation to determine whether a first storage cell has been turned on; performing a second preselection operation based on the result of the first preselection operation to determine that the first storage cell has not been turned on; and determining that the first storage cell is a faulty cell based on the result of the second preselection operation to determine that the first storage cell has not been turned on.

[0007] In one embodiment, a storage device may include: a cell array including at least one storage cell electrically connected between a bit line and a word line, the bit line being electrically connected to a global bit line and the word line being electrically connected to a global word line; control circuitry configured to control at least one of a first preselection operation, a second preselection operation, and a write operation to be performed when a write command is received; a voltage supply circuitry configured to provide a first preselection operation voltage to the global bit line and to provide a second preselection operation voltage to the global word line after the first preselection operation has commenced; and a sense amplifier configured to provide the control circuitry with information indicating whether the storage cell has been turned on due to the first preselection operation and the second preselection operation.

[0008] In one embodiment, a method for operating a non-volatile memory device includes: receiving a write command for a memory cell; performing a first preselection operation on the memory cell; performing a second preselection operation on the memory cell if the memory cell does not exhibit a conductive state in response to the first preselection operation; performing a write operation on the memory cell if the memory cell exhibits a conductive state in response to at least one of the first or second preselection operations; and classifying the memory cell as a faulty cell if the memory cell does not exhibit a conductive state in response to both the first and second preselection operations. Attached Figure Description

[0009] Figure 1 and Figure 2 This is a diagram used to describe a write operation to a storage cell according to an embodiment of the present disclosure.

[0010] Figure 3 and Figure 4 This is a diagram illustrating a write operation of a storage device according to an embodiment of the present disclosure.

[0011] Figure 5 This is a flowchart describing the operation of a storage device according to embodiments of the present disclosure.

[0012] Figures 6 to 8 This is a diagram used to illustrate the operation of a storage device according to embodiments of the present disclosure.

[0013] Figure 9 This is a diagram illustrating components of a storage device according to embodiments of the present disclosure. Detailed Implementation

[0014] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0015] Embodiments of this disclosure relate to techniques for operating non-volatile memory devices that improve write reliability by mitigating the effects of sneak path currents. In one embodiment, the method includes performing a first preselection operation on a memory cell (e.g., by applying a first voltage across the cell) after receiving a write command. If the memory cell is not conductive (e.g., not turned on), a second preselection operation is performed on the memory cell (e.g., by applying a second voltage across the cell). If the memory cell becomes conductive in response to at least one of the first or second preselection operations, a write operation is performed. If the memory cell remains non-conductive after both the first and second preselection operations, the memory cell is classified as a faulty cell.

[0016] A storage device and its operation method are provided that can perform write operations by identifying normal cells and abnormal cells.

[0017] The data storage reliability of storage units can be improved.

[0018] Figure 1 and Figure 2 This is a diagram used to describe a write operation of a storage cell according to an embodiment of the present disclosure.

[0019] Figure 1 This can be a diagram describing a reset (RESET) write operation that stores reset data in the memory cell MC. The threshold voltage of the memory cell MC can change depending on the direction of the current flowing through the memory cell MC. For example, the threshold voltage of the memory cell MC can change to one of a first level and a second level depending on the direction of the current flowing through the memory cell MC. The first level can be higher than the second level. In this case, when the threshold voltage of the memory cell MC is at the first level, the state of the memory cell MC can be a reset state where reset data has been stored in the memory cell MC. Furthermore, when the threshold voltage of the memory cell MC is at the second level, the state of the memory cell MC can be a set state where set data has been stored in the memory cell MC.

[0020] refer to Figure 1 The memory cell MC can be electrically connected to the bit line BL and the word line WL. In this case, a reset write operation can be an operation that changes the state of the memory cell MC to a reset state by storing reset data in the memory cell MC. For example, the reset data can be stored in the memory cell MC by supplying a first voltage to the word line WL and a second voltage to the bit line BL, causing the memory cell MC to be turned on, and causing current to flow from the word line WL through the turned-on memory cell MC to the bit line BL. In this case, the first voltage can be a voltage with a higher level than the second voltage. Furthermore, the first voltage can be a positive voltage (+), and the second voltage can be a negative voltage (-).

[0021] Figure 2 It can be a diagram used to describe a set (SET) write operation that stores set data in the storage unit MC.

[0022] refer to Figure 2The memory cell MC can be electrically coupled between the bit line BL and the word line WL. In this case, a set-write operation can be an operation that changes the state of the memory cell MC to a set state by storing set data in the memory cell MC. For example, set data can be stored in the memory cell MC by providing a first voltage to the bit line BL and a second voltage to the word line WL, causing the memory cell MC to conduct and allowing current to flow from the bit line BL through the conducted memory cell MC to the word line WL. In this case, the first voltage can be a voltage with a higher level than the second voltage. Furthermore, the first voltage can be a positive voltage (+), and the second voltage can be a negative voltage (-).

[0023] In this scenario, when the threshold voltage of the memory cell MC is higher than the first level (higher than the second level), it can be said that the state of the memory cell MC has changed to the state where reset data has been stored in the memory cell MC, i.e., the reset state. Furthermore, when the threshold voltage of the memory cell MC is lower than the second level (lower than the first level), it can be said that the state of the memory cell MC has changed to the state where set data has been stored in the memory cell MC, i.e., the set state.

[0024] In other words, the threshold voltage level of the storage cell MC that has stored reset data can be higher than the threshold voltage level of the storage cell MC that has stored set data.

[0025] Figure 3 and Figure 4 This is a diagram illustrating a write operation of a storage device according to an embodiment of the present disclosure. In this case, Figure 3 and Figure 4 This can be used to describe the determination of having a reference. Figure 1 and Figure 2 The diagram illustrates the write operation of the storage device after a write operation is performed on a storage cell MC that is either a normal cell or an abnormal cell.

[0026] Figure 3 It can show that the memory cell MC has passed Figure 1 The threshold voltage distribution (RST) formed by the reset write operation and the already passed threshold voltage distribution of the memory cell MC. Figure 2 The threshold voltage distribution (SET) formed by the set-write operation.

[0027] Figure 4 It can be a diagram used to describe a pre-selection operation that determines whether the memory cell MC is functioning correctly before performing a reset write or set write operation on the memory cell MC.

[0028] refer to Figure 3 and Figure 4According to embodiments of the present disclosure, the storage device can perform a pre-selection operation and then perform a write operation (e.g., a reset write or a set write operation). In this case, refer to Figure 4 The write operation described can be a SET write operation.

[0029] A preselection operation can be an operation that provides a cell determination signal to a memory cell before a write operation to assess whether it is functioning correctly. The cell determination signal can be a voltage or a current. In one embodiment, the cell determination signal is a cell determination voltage V_cd applied across the memory cell MC (e.g., a first terminal and a second terminal of the memory cell). The preselection operation includes determining whether the memory cell is conducting in response to the cell determination voltage V_cd. In one embodiment, if the memory cell is in a conductive state, then the memory cell is conducting. As used herein, a "conductive state" of a memory cell refers to a state in which the memory cell allows current to flow between its terminals in response to an applied voltage or current, indicating a functional or defect-free memory cell.

[0030] At this time, when memory cell MC is turned on, the storage device can determine that memory cell MC is a normal memory cell. When memory cell MC is not turned on, the storage device can determine that memory cell MC is an abnormal memory cell. Furthermore, the cell determination voltage V_cd can have a level higher than the threshold voltage of memory cell MC in the reset state RST, and can have a level lower than the voltage level between the bit line BL and the word line WL after the start of a write operation. Figure 4 In the preselection operation, the example described is the case where the voltage level of the bit line BL is higher than the voltage level of the word line WL. However, a preselection operation where the voltage level of the bit line BL is lower than the voltage level of the word line is also possible. That is, since the preselection operation is an operation to determine whether the memory cell MC is turned on, the preselection operation can be performed when the difference between the voltage level of the bit line BL and the voltage level of the word line WL is the level of the cell determination voltage V_cd.

[0031] Therefore, when the cell determination voltage V_cd is provided to the memory cell MC, the memory cell MC is normally turned on. The voltage level of the word line WL or bit line BL can change due to the memory cell MC being turned on. For example, current flows from the bit line BL through the turned-on memory cell MC to the word line WL. Therefore, by sensing the voltage level of the word line WL, when the voltage level of the word line WL becomes higher than the reference voltage Vref, the memory cell MC can be determined to be turned on. Furthermore, when the voltage level of the word line WL is lower than the reference voltage Vref, i.e., when the voltage level of the word line WL does not change, the memory cell MC can be determined to be turned off.

[0032] As described above, the storage device according to embodiments of this disclosure can perform a pre-selection operation before performing a write operation to determine whether the storage cell MC (i.e., the target storage cell) to be written to is normal. When the storage cell MC is determined to be an abnormal storage cell based on the result of the pre-selection operation, the write operation may not be able to be performed.

[0033] Figure 5 This is a flowchart describing the operation of a storage device according to embodiments of the present disclosure.

[0034] refer to Figure 5 The operation method of the storage device according to the embodiments of the present disclosure may include a write command receiving process S10, a first pre-selection operation execution process S20, a first continuity check process S30, a write operation execution process S40, a second pre-selection operation execution process S50, a second continuity check process S60, and a fault unit determination process S70.

[0035] The write command receiving process S10 may include a process of receiving a write command from the storage device. In this case, when the storage device receives the write command, it may execute the first pre-selection operation execution process S20.

[0036] The first preselection operation execution process S20 may include a process of providing a cell determination voltage V_cd to both ends of the memory cell MC. In this case, during the first preselection operation execution process S20, when the memory cell MC is turned on, current can flow in a first direction. For example, the first direction may be the direction in which current flows from the bit line BL through the memory cell MC to the word line WL. The first direction may also be the direction in which current flows from the word line WL through the memory cell MC to the bit line BL.

[0037] The first conduction check process S30 is a process for checking the result of the first pre-selection operation, and can be a process for checking whether the memory cell MC has been turned on. For example, the first conduction check process S30 can be a process for detecting a change in the voltage level of the bit line BL or word line WL due to the memory cell MC being turned on. A more specific description is given here by example. The first conduction check process S30 can be a process for determining that the memory cell MC is turned on when the voltage level of the bit line BL or word line WL becomes higher or lower than the level of the reference voltage Vref. The first conduction check process S30 can be a process for determining that the memory cell MC is not turned on when the voltage level of the bit line BL or word line WL is not higher or lower than the level of the reference voltage Vref, that is, when the voltage level of the bit line BL or word line WL does not change. If current flows from the bit line BL to the word line WL due to the memory cell MC being turned on, the voltage level of the word line WL can become higher than the level of the reference voltage Vref. Furthermore, if current flows from the bit line BL to the word line WL due to the memory cell MC being turned on, the voltage level of the bit line BL can become lower than the level of the reference voltage Vref.

[0038] When the memory cell MC is found to be on (yes) during the first conduction check process S30, the write operation execution process S40 can be executed.

[0039] If the storage cell MC is not turned on (no) during the first conduction check process S30, the second pre-selection operation execution process S50 can be executed.

[0040] The write operation execution process S40 may include changing the state of the memory cell MC to a reset state or a set state. In this case, the write operation execution process S40 may include providing the memory cell MC with a voltage level higher than the cell determination voltage V_cd by applying a voltage to both ends of the memory cell MC (i.e., bit line BL and word line WL).

[0041] The second preselection operation execution process S50 may include a process of providing a cell-determined voltage V_cd to both ends of the memory cell MC. In this case, during the second preselection operation execution process S50, when the memory cell MC is turned on, the current can flow in a second direction. For example, the second direction may be the opposite direction to the direction in which the current flows through the turned-on memory cell MC in the first preselection operation execution process S20. For example, if the direction in which the current flows through the turned-on memory cell MC in the first preselection operation execution process S20 is the direction from the bit line BL to the word line WL, then the direction in which the current flows through the turned-on memory cell MC in the second preselection operation execution process S50 may be the direction from the word line WL to the bit line BL. That is, the second preselection operation execution process S50 may be a process of switching the voltages provided to both ends of the memory cell MC (i.e., the bit line BL and the word line WL) respectively in the first preselection operation execution process S20. This will be described in more detail. If a first voltage has been provided to the bit line BL and a second voltage has been provided to the word line WL in the first preselection operation execution process S20, then a second voltage can be provided to the bit line BL and a first voltage can be provided to the word line WL in the second preselection operation execution process S50.

[0042] The second conduction check process S60 is a process for checking the result of the second pre-selection operation, and can be a process for checking whether the memory cell MC has been turned on. For example, the second conduction check process S60 can be a process for detecting the voltage level change of the bit line BL or word line WL due to the memory cell MC being turned on. This is described in more detail as an example. The second conduction check process S60 can be a process for determining that the memory cell MC has been turned on when the voltage level of the bit line BL or word line WL becomes higher or lower than the level of the reference voltage Vref. The second conduction check process S60 can be a process for determining that the memory cell MC has not been turned on when the voltage level of the bit line BL or word line WL is not higher or lower than the level of the reference voltage Vref, that is, when the voltage level of the bit line BL or word line WL has not changed.

[0043] When the memory cell MC is found to be on (yes) during the second conduction check process S60, the write operation execution process S40 can be executed.

[0044] If the memory cell MC is not turned on (no) during the second continuity check process S60, the fault cell determination process S70 can be executed.

[0045] The fault cell determination process S70 is a process of determining or classifying the storage cell MC as a fault cell, and may also include a process of storing the address of the storage cell MC or transmitting the address of the storage cell MC to the controller that controls the storage device.

[0046] In this case, in reference Figure 5 In the described method of operating the storage device, a write operation can be performed on the storage cell MC based on a write command and the result of a first preselection operation. Furthermore, a second preselection operation can be performed based on another read command and the result of the first preselection operation, and a write operation can be performed on the storage cell MC based on the result of the second preselection operation. The second preselection operation can be performed based on yet another read command and the result of the first preselection operation, and the storage cell MC can be identified as a faulty cell based on the result of the second preselection operation.

[0047] Figures 6 to 9 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0048] Figure 6 and Figure 7 It can be a diagram used to describe the operation of preventing a normal memory cell from being identified as a faulty cell due to creeping current after the preselection operation has started. Figure 6 It can be a diagram used to describe the first pre-selection operation. Figure 7 It can be a diagram used to describe the second pre-selection operation.

[0049] In this scenario, the memory cell MC exhibits the following characteristics: Current flows more smoothly through the memory cell MC when it flows in the same direction as the current flow after the write operation begins, compared to the case where the current flows in the opposite direction to the direction of the current flow after the write operation begins. That is, when reading the memory cell MC, an operation can be performed that causes the current to flow in the opposite direction to the direction in the reset write operation (i.e., a read operation), causing the current to flow in the same direction as the direction in the set write operation. In this case, during a read operation where the current flows in the same direction as the direction after the set write operation begins, when the memory cell MC is on, its state can be determined as a low threshold voltage state (set state). When the memory cell MC is not on, its state can be determined as a high threshold voltage state (reset state). If a read operation is performed causing current to flow in the same direction as the reset direction when the memory cell MC is read, the state of the memory cell MC can be determined to be a low threshold voltage state when the memory cell is on, and a high threshold voltage state when the memory cell is not on. In this case, the state of the memory cell MC is checked based on a read operation that causes current to flow in the same direction as after the set write operation begins. After a read operation that causes current to flow in the same direction as in the reset write operation begins, the state of the memory cell MC with a low threshold voltage can be a reset state, while the state of the memory cell MC with a high threshold voltage can be a set state.

[0050] Therefore, the threshold voltage distribution of the memory cell after the start of the first preselection operation when the direction of the current flowing through the memory cell is the first direction, and the threshold voltage distribution of the memory cell after the start of the second preselection operation in the opposite direction (i.e., the second direction) can be as follows: Figure 6 and Figure 7 Switch as shown. Figure 6 The reset state RST in the middle can correspond to Figure 7 The set state in the middle, and Figure 6 The set state SET in the middle can correspond to Figure 7 The reset state RST in the system.

[0051] As described above, the storage device according to embodiments of the present disclosure can provide a cell determination voltage V_cd to the storage cell MC before a write operation, and can perform a pre-selection operation to determine whether the storage cell MC is functioning correctly by detecting the voltage level of a specific node connected to the bit line BL or the word line WL.

[0052] For example, suppose a memory device determines whether a memory cell MC is turned on by detecting the voltage level of the word line WL.

[0053] The storage device can receive write commands.

[0054] The storage device may perform a first preselection operation before a write operation. In this case, the first preselection operation may be an operation that applies a higher voltage to the bit line BL than the voltage applied to the word line WL, so that current flows from the bit line BL through the conducted memory cell MC to the word line WL when the memory cell MC is turned on. In this case, the voltage level difference across the memory cell MC (i.e., the voltage level of the bit line BL and the word line WL) may be the voltage level required to turn on the memory cell MC. That is, after the first preselection operation begins, the voltage level difference between the bit line BL and the word line WL may correspond to the cell-determined voltage V_cd. After the first preselection operation begins, the amount of creeping current increases with the number of memory cells in a low-resistance state (e.g., set state) around the target memory cell to which the write operation is performed (i.e., the memory cell selected after the write operation begins). After the first preselection operation begins, the voltage difference required to turn on the selected memory cell needs to be provided across the selected memory cell. However, if the amount of creeping current increases based on the state of the memory cells surrounding the selected memory cell, a voltage difference may not appear across the selected memory cell to the extent that the selected memory cell can conduct.

[0055] If the memory cell MC is determined to be on in the first pre-selection operation, a write operation can be performed.

[0056] However, if the memory cell MC is determined not to be on during the first pre-selection operation, a second pre-selection operation can be performed.

[0057] The second preselection operation can be an operation that performs a preselection operation such that the direction of current flow through the already-conducting memory cell MC is opposite to the direction of current flow through the memory cell MC after the first preselection operation begins. For example, if the first preselection operation is an operation that creates current flowing from the bit line BL through the already-conducting memory cell MC to the word line WL by applying a voltage higher than that applied to the bit line BL, then the second preselection operation can be an operation that creates current flowing from the word line WL through the already-conducting memory cell MC to the bit line BL by applying a voltage higher than that applied to the word line WL. Therefore, if the memory cell MC is determined to be off due to creeping current in the first preselection operation, the memory cell MC can be determined to be on in the second preselection operation. The reason is that if selecting a memory cell in a low-resistance state around the memory cell MC during a first preselection operation, where a higher voltage is applied to the bit line BL than to the word line WL, increases the amount of creeping current, then selecting a memory cell in a high-resistance state around the memory cell MC during a second preselection operation, where a higher voltage is applied to the word line WL than to the bit line BL, decreases the amount of creeping current. A memory cell has the characteristic that current flows smoothly through the memory cell in the same direction as after the write operation begins (low-resistance state), and the characteristic that current does not flow smoothly through the memory cell in the opposite direction to after the write operation begins (high-resistance state).

[0058] Therefore, whether the memory cell MC is turned on can be determined in the second preselection operation, which is not affected by the creeping current compared to the first preselection operation.

[0059] If it is determined that the storage cell MC is turned on in the second preselection operation, a write operation can be performed.

[0060] Therefore, the storage device according to embodiments of the present disclosure can prevent normal storage cells from being incorrectly identified as abnormal storage cells due to creeping current by performing a second preselection operation based on the result of the first preselection operation.

[0061] Figure 8 It can be a diagram used to describe the operation of checking that the memory cell MC is a faulty cell through the first pre-selection operation and the second pre-selection operation.

[0062] like Figure 8 As shown, assume that the memory cell MC has an anomaly distribution 1. In this case, anomaly distribution 1 can represent the distribution of the threshold voltage of each memory cell having a level higher than the cell's defined voltage V_cd.

[0063] The storage device can receive write commands.

[0064] The storage device may perform a first preselection operation before a write operation. In this case, during the first preselection operation, when the memory cell MC is turned on, current can flow from the bit line BL through the turned-on memory cell MC to the word line WL.

[0065] like Figure 8 As shown, anomaly distribution 1 is a distribution in which each threshold voltage has a level higher than the threshold voltage of the cell-defined voltage V_cd. Therefore, the memory cell MC with anomaly distribution 1 can be determined as having been turned off after the start of the first preselection operation.

[0066] If the storage cell MC is determined to have been turned off in the first preselection operation, the second preselection operation can be performed.

[0067] The second preselection operation is the opposite of the first preselection operation in terms of the voltage applied to the two ends of the memory cell MC (i.e., bit line BL and word line WL). However, the difference in voltage levels across the two ends of the memory cell MC (i.e., bit line BL and word line WL) can be the same in both the first and second preselection operations.

[0068] Memory cells MC with abnormal distribution 1 (including threshold voltages with levels higher than the cell determination voltage V_cd) can even be determined to be off in the second preselection operation.

[0069] Therefore, the storage device according to the embodiments of this disclosure can determine that storage cells with abnormal distribution are faulty cells by performing a second preselection operation based on the result of a first preselection operation.

[0070] The storage device operating as described above according to embodiments of the present disclosure can be configured as follows: Figure 9 As shown.

[0071] Figure 9 This is a diagram illustrating components of a storage device according to embodiments of the present disclosure.

[0072] refer to Figure 9 The storage device according to embodiments of the present disclosure may include a cell array 10, a first voltage supply circuit 20, a second voltage supply circuit 30, a voltage changing circuit 40, a sensing amplifier 50, and a control circuit 60.

[0073] Cell array 10 may include at least one memory cell MC electrically coupled between bit line BL and word line WL. In this case, bit line BL may be electrically coupled to global bit line GBL. Word line WL may be electrically coupled to global word line GWL. For example, bit line BL may be connected to or separated from global bit line GBL based on an address (not shown). Similarly, word line WL may be connected to or separated from global word line GWL based on an address (not shown).

[0074] The first voltage supply circuit 20 can provide a first voltage V_p to the voltage changing circuit 40 via a first voltage line V_sla. In this case, the first voltage V_p may include a first pre-selection operation voltage V_pa and a first write operation voltage V_pb. The first voltage supply circuit 20 can provide one of the first pre-selection operation voltage V_pa and the first write operation voltage V_pb as the first voltage V_p to the voltage changing circuit 40 via the first voltage line V_sla based on a first voltage level control signal C_vsa.

[0075] The second voltage supply circuit 30 can provide a second voltage V_n to the voltage changing circuit 40 via the second voltage line V_slb. In this case, the first voltage V_p can have a higher level than the second voltage V_n. The first voltage V_p can be a positive voltage. The second voltage V_n can be a negative voltage. Furthermore, the second voltage V_n can include a second pre-selection operating voltage V_na and a second write operating voltage V_nb. The second voltage supply circuit 30 can provide one of the second pre-selection operating voltage V_na and the second write operating voltage V_nb as the second voltage V_n via the second voltage line V_slb based on the second voltage level control signal C_vsb.

[0076] The voltage changing circuit 40 can provide a first voltage V_p to one of the global bit line GBL and the global word line GWL based on the voltage switching control signal PSC, and can provide a second voltage V_n to the other of the global bit line GBL and the global word line GWL. For example, when providing the first voltage V_p to the global bit line GBL based on the voltage switching control signal PSC, the voltage changing circuit 40 can provide the second voltage V_n to the global word line GWL. Furthermore, when providing the first voltage V_p to the global word line GWL based on the voltage switching control signal PSC, the voltage changing circuit 40 can provide the second voltage V_n to the global bit line GBL.

[0077] The sensing amplifier 50 can determine whether the memory cell MC is turned on. For example, after the start of the preselection operation, the sensing amplifier 50 can determine whether the memory cell MC is turned on by comparing the level of the second voltage line V_slb with the level of the reference voltage Vref, and can output the determined result as a sensing result SR. This is described more specifically. After the start of the first preselection operation, when the level of the second voltage line V_slb is higher than the level of the reference voltage Vref, the sensing amplifier 50 can output a sensing result SR (e.g., high level) indicating that the memory cell MC is turned on. After the start of the first preselection operation, when the level of the second voltage line V_slb is lower than the level of the reference voltage Vref, the sensing amplifier 50 can output a sensing result SR (e.g., low level) indicating that the memory cell MC is turned off. Furthermore, after the start of the second preselection operation, when the level of the second voltage line V_slb is higher than the level of the reference voltage Vref, the sensing amplifier 50 can output a sensing result SR (e.g., high level) indicating that the memory cell MC is turned off. After the second preselection operation begins, when the level of the second voltage line V_slb is lower than the level of the reference voltage Vref, the sensing amplifier 50 can output a sensing result SR (e.g., low level) indicating that the memory cell MC has been turned on.

[0078] The control circuit 60 can generate a first voltage level control signal C_vsa, a second voltage level control signal C_vsb, and a voltage switching control signal PSC based on the command CMD, the written data WR_d, and the sensing result SR. Furthermore, the control circuit 60 can provide the first voltage level control signal C_vsa and the second voltage level control signal C_vsb to the first voltage supply circuit 20 and the second voltage supply circuit 30, and can provide the voltage switching control signal PSC to the voltage changing circuit 40.

[0079] For example, when the command CMD is a write command, the control circuit 60 can provide a first voltage level control signal C_vsa (which enables the first preselection operation voltage V_pa to be output as the first voltage V_p) and a second voltage level control signal C_vsb (which enables the second preselection operation voltage V_na to be output as the second voltage V_n) to the first voltage supply circuit 20 and the second voltage supply circuit 30, respectively, so that the first preselection operation can be performed. Furthermore, the control circuit 60 can provide a voltage switching control signal PSC to the voltage changing circuit 40, which enables the first preselection operation voltage V_pa to be provided to the global bit line GBL and the second preselection operation voltage V_na to be provided to the global word line GWL. In this case, if the result of the first preselection operation (i.e., the sensing result SR of the sense amplifier 50) contains information indicating that the memory cell MC is turned on, the control circuit 60 can generate the first voltage level control signal C_vsa, the second voltage level control signal C_vsb, and the voltage switching control signal PSC so that a write operation based on the write data WR_d is performed.

[0080] If the result of the first preselection operation (i.e., the sensing result SR of the sensing amplifier 50) includes information indicating that the storage cell MC has been turned off, the control circuit 60 can generate a first voltage level control signal C_vsa, a second voltage level control signal C_vsb, and a voltage switching control signal PSC to execute the second preselection operation. In this case, the control circuit 60 can change the voltage switching control signal PSC after the first preselection operation has started, while the first voltage level control signal C_vsa and the second voltage level control signal C_vsb have been maintained, to execute the second preselection operation. In other words, under the condition that the first voltage supply circuit 20 and the second voltage supply circuit 30 are respectively provided with a first voltage level control signal C_vsa (which enables the first preselection operation voltage V_pa to be output as the first voltage V_p) and a second voltage level control signal C_vsb (which enables the second preselection operation voltage V_na to be output as the second voltage V_n), the control circuit 60 provides the voltage changing circuit 40 with a voltage switching control signal PSC that enables the second preselection operation voltage V_na to be provided to the global bit line GBL and the first preselection operation voltage V_pa to be provided to the global word line GWL. In this case, if the result of the second preselection operation (that is, the sensing result SR of the sense amplifier 50) contains information indicating that the memory cell MC has been turned on, the control circuit 60 can generate the first voltage level control signal C_vsa, the second voltage level control signal C_vsb, and the voltage switching control signal PSC so that the write operation according to the write data WR_d is executed. If the result of the second preselection operation (i.e., the sensing result SR of the sensing amplifier 50) contains information indicating that the memory cell MC has been turned off, the control circuit 60 can determine that the memory cell MC is a faulty cell.

[0081] The control circuit 60 that performs the write operation can generate a first voltage level control signal C_vsa and a second voltage level control signal C_vsb that enable the first write operation voltage V_pb and the second write operation voltage V_nb to be provided to the voltage changing circuit 40. It can provide the first write operation voltage V_pb to one of the global bit line GBL and the global word line GWL based on the write data WR_d, and can generate a voltage switching control signal PSC that enables the second write operation voltage V_nb to be provided to the other of the global bit line GBL and the global word line GWL.

[0082] Therefore, upon receiving a write command, the first voltage supply circuit 20, the second voltage supply circuit 30, and the voltage changing circuit 40 can, under the control of the control circuit 60, execute at least one of the first preselection operation, the second preselection operation, and the write operation. In this case, after the first preselection operation begins, the first voltage supply circuit 20, the second voltage supply circuit 30, and the voltage changing circuit 40 can, under the control of the control circuit 60, provide the first preselection operation voltage V_pa to the global bit line GBL and the second preselection operation voltage V_na to the global word line WL. Furthermore, after the second preselection operation begins, the first voltage supply circuit 20, the second voltage supply circuit 30, and the voltage changing circuit 40 can, under the control of the control circuit 60, provide the first preselection operation voltage V_pa to the global word line GWL and the second preselection operation voltage V_na to the global bit line GBL. Furthermore, after the write operation begins, the first voltage supply circuit 20, the second voltage supply circuit 30, and the voltage changing circuit 40, under the control of the control circuit 60, can provide a first write operation voltage V_pb to one of the global bit line GBL and the global word line GWL, and provide a second write operation voltage V_nb to the other of the global bit line GBL and the global word line GWL. For example, in a write operation where the state of the memory cell MC changes to the set state SET, the first write operation voltage V_pb can be provided to the global bit line GBL, and the second write operation voltage V_nb can be provided to the global word line GWL. Similarly, in a write operation where the state of the memory cell MC changes to the reset state RST, the second write operation voltage V_nb can be provided to the global bit line GBL, and the first write operation voltage V_pb can be provided to the global word line GWL.

[0083] Therefore, the first voltage supply circuit 20, the second voltage supply circuit 30, and the voltage changing circuit 40 can be referred to as the voltage supply circuit 70, because under the control of the control circuit 60, the first voltage supply circuit 20, the second voltage supply circuit 30, and the voltage changing circuit 40 provide the first preselection operation voltage V_pa and the second preselection operation voltage V_na to the global bit line GBL and the global word line GWL, respectively, or provide the first write operation voltage V_pb and the second write operation voltage V_nb to the global bit line GBL and the global word line GWL, respectively.

[0084] Although embodiments according to the spirit of this disclosure have been described above with reference to the accompanying drawings, these embodiments are provided only to illustrate embodiments based on the concept of this disclosure, and this disclosure is not limited to these embodiments. Those skilled in the art to which this disclosure pertains can substitute, modify, and change these embodiments in various ways without departing from the spirit of this disclosure as set forth in the claims. Such substitutions, modifications, and changes can be considered to fall within the scope of this disclosure.

Claims

1. A method for operating a storage device, the method comprising: Receive the first write command; Perform a first pre-selection operation to determine whether the first memory cell can be turned on; If the first preselection operation fails to turn on the first storage cell, then a second preselection operation is performed to determine whether the first storage cell can be turned on. and If the second pre-selection operation fails to turn on the first storage cell, then the first storage cell is determined to be a faulty cell.

2. The method according to claim 1, further comprising: If the second preselection operation turns on the first storage cell, then a write operation is performed on the first storage cell in response to the first write command. Wherein, if the first storage cell is turned on through the first preselection operation, the first current of the first storage cell flows along the first direction, and if the first storage cell is turned on through the second preselection operation, the second current of the first storage cell flows along the second direction, wherein the first direction and the second direction are different directions.

3. The method according to claim 2, wherein: The first current flowing along the first direction is from the bit line through the first memory cell to the word line, and The second current flow along the second direction is from the word line through the first memory cell to the bit line.

4. The method according to claim 3, wherein, In each of the first preselection operation and the second preselection operation, the difference in voltage levels applied to the first and second terminals of the first memory cell is less than the difference in voltage levels applied to the first and second terminals of the first memory cell after the write operation begins.

5. The method according to claim 1, further comprising: Receive the second write command; Perform a third pre-selection operation to determine whether the second memory cell can be turned on; as well as If the second storage cell is determined to be on, a write operation is performed on the second storage cell in response to the second write command.

6. The method according to claim 1, further comprising: Receive the third write command; Perform a fourth preselection operation to determine whether the third memory cell can be turned on; If the fourth preselection operation fails to turn on the third storage cell, then the fifth preselection operation is performed; and If the third storage unit is activated through the fifth preselection operation, a write operation is performed on the third storage unit.

7. The method according to claim 6, wherein: The fourth preselection operation is an operation used to allow current to flow from the bit line through the third memory cell to the word line, and The fifth preselection operation is an operation used to allow current to flow from the word line through the third memory cell to the bit line.

8. A storage device, comprising: A cell array comprising at least one memory cell, wherein the memory cell is electrically coupled between a bit line and a word line, the bit line is electrically coupled to a global bit line, and the word line is electrically coupled to a global word line; A control circuit that controls one or more of a first preselection operation, a second preselection operation, and a write operation in response to a received write command; Voltage supply circuit, Specifically: providing a first preselection operation voltage to the global bit line, and providing a second preselection operation voltage to the global word line after the first preselection operation begins; as well as A sensing amplifier that provides the control circuit with information indicating whether the memory cell has been turned on in response to at least one of the first preselection operation or the second preselection operation.

9. The storage device according to claim 8, wherein, When the memory cell is turned on, the first preselection operation involves current flowing in a first direction, while the second preselection operation involves current flowing in a second direction.

10. The storage device according to claim 9, wherein The first preselection operation causes current to flow from the bit line through the turned-on memory cell to the word line, and The second preselection operation causes current to flow from the word line through the turned-on memory cell to the bit line.

11. The storage device according to claim 10, wherein, In each of the first preselection operation and the second preselection operation, the difference in voltage levels applied across the memory cell is less than the difference in voltage levels applied across the memory cell during the write operation.

12. The storage device according to claim 9, wherein, When the write command is received, if the storage unit has been turned on in response to the first preselection operation, the control circuit controls the execution of the write operation.

13. The storage device according to claim 9, wherein, When the write command is received, if the storage unit has not yet been turned on in response to the first preselection operation, the control circuit controls the execution of the second preselection operation.

14. The storage device according to claim 13, wherein, The control circuit: if the storage cell is turned on in response to the second preselection operation, then controls the execution of the write operation; And if the storage unit has not been turned on in response to the second preselection operation, the storage unit is classified as a faulty unit.

15. The storage device according to claim 9, wherein, The voltage supply circuit provides the first preselection operation voltage to the global word line and the second preselection operation voltage to the global bit line after the second preselection operation begins.

16. The storage device according to claim 15, wherein, The voltage supply circuit provides the first preselection operation voltage and the second preselection operation voltage to the global bit line and the global word line respectively, such that after the first preselection operation and the second preselection operation begin, the voltage level difference between the global bit line and the global word line is less than the voltage level difference between the global bit line and the global word line after the write operation begins.

17. The storage device according to claim 16, wherein, The voltage supply circuit includes: A first voltage supply circuit, wherein: after the first preselection operation and the second preselection operation begin; and after the write operation begins; a first write operation voltage is output; A second voltage supply circuit, wherein: after the first preselection operation and the second preselection operation begin; and after the write operation begins; and a second write operation voltage is output; and A voltage changing circuit that: after the first preselection operation begins, provides the output of the first voltage supply circuit to the global bit line and provides the output of the second voltage supply circuit to the global word line; and after the second preselection operation begins, provides the output of the first voltage supply circuit to the global word line and provides the output of the second voltage supply circuit to the global bit line.

18. A method for operating a non-volatile memory device, the method comprising: Receive write commands for the storage unit; Perform a first pre-selection operation on the storage unit; If the memory cell does not exhibit a conductive state in response to the first preselection operation, then a second preselection operation is performed on the memory cell; If the memory cell becomes conductive in response to at least one of the first preselection operation or the second preselection operation, a write operation is performed on the memory cell. and If the memory cell does not exhibit a conductive state in response to the first preselection operation and the second preselection operation, the memory cell is classified as a faulty cell.

19. The method according to claim 18, wherein, The first preselection operation involves applying a first voltage across the memory cell to allow current to flow from the bit line through the memory cell to the word line, while the second preselection operation involves applying a second voltage across the memory cell to allow current to flow from the word line through the memory cell to the bit line.

20. The method according to claim 19, wherein, During each of the first preselection operation and the second preselection operation, the voltage difference applied across the memory cell is less than the voltage difference applied across the memory cell during the write operation.

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