Data storage device and method for read threshold calibration in fractional bits-per-cell memory

Abstract

This disclosure relates to data storage devices and methods for read threshold calibration in fractional-per-cell bit-of-bit memory. One data storage device includes a memory capable of storing a fractional (i.e., non-integer) number of bits per memory cell. For example, word lines in the memory may have different groups of memory cells, in which stored bits can be inferred by reading a pair of memory cells stored across the different groups. To balance the bit error rate, different program-verification levels can be used in each group. These different program-verification levels can be provided by using different control gate voltage (VCGR) offsets or by modifying the integration time of the sense amplifier capacitor. A method for calibrated read thresholds for entangled pages is also described.

Description

Background Technology

[0001] Bits per cell (BPC) refers to the number of bits that can be stored in a non-volatile memory (NVM) cell. Typically, BPC is an integer, such as four bits per cell. While using four bits per cell can save costs, it may reduce performance. Attached Figure Description

[0002] Figure 1A This is a block diagram of the data storage device in the implementation scheme.

[0003] Figure 1B This is a block diagram illustrating the storage module of an example implementation.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system for an example implementation.

[0005] Figure 2A This is an example based on the implementation plan. Figure 1A The block diagram of the controller components of the data storage device is illustrated in the figure.

[0006] Figure 2B This is an example based on the implementation plan. Figure 1A The block diagram of the components of the data storage device is shown in the figure.

[0007] Figure 3 This is a block diagram of the host and data storage devices in the implementation scheme.

[0008] Figure 4A and Figure 4B These are examples of independent memory cells and entangled memory cells in the implementation scheme.

[0009] Figure 5 This is a flowchart of a method for writing to a memory having an integer number of bits per unit.

[0010] Figure 6 This is a flowchart of a method for writing to a memory having a non-integer number of bits per unit.

[0011] Figure 7 This is a graph showing the relationship between per-page BER and average BER in an implementation scheme that does not use bit error rate (BER) balancing.

[0012] Figure 8 This is a graph showing the relationship between per-page BER and average BER in an implementation using BER balancing.

[0013] Figure 9 This is a graph showing the relationship between the charging voltage distribution (CVD) and the DAC in an implementation scheme that does not use balancing.

[0014] Figure 10This is a graph showing the relationship between CVD and DAC using a balanced implementation scheme.

[0015] Figure 11 This is a diagram showing the relationship between the BER of the implementation plan and the actual BER.

[0016] Figure 12 This is a flowchart of a method for implementing BER balancing in fractional per-unit bit-of-bit memory.

[0017] Figure 13 This is a flowchart of a method for implementing the extraction of the reading threshold.

[0018] Figure 14 This is a flowchart of a method for performing a read threshold calibration implementation.

[0019] Figure 15 This is a flowchart of a method for implementing read threshold calibration in fractional-per-unit bit memory. Detailed Implementation

[0020] The following embodiments generally relate to data storage devices and methods for bit error rate balancing in fractional-per-unit bit-of-bit memory. In one embodiment, a data storage device is provided, comprising a memory and one or more processors. The memory includes word lines having a first set of memory cells and a second set of memory cells. The one or more processors are individually or in combination configured to: program memory cells in the first set of memory cells and the second set of memory cells to store a non-integer number of bits in each of the programmed memory cells; and to perform bit error rate (BER) balancing by using different program-verification levels in the first set of memory cells and the second set of memory cells.

[0021] In another embodiment, a method is provided to be performed in a data storage device including memory, the memory including word lines, wherein the word lines include a first set of memory cells and a second set of memory cells. The method includes: programming a fractional number of bits per memory cell in the memory cells of the first set of memory cells and the second set of memory cells; and using different program-verify levels in the first set of memory cells and the second set of memory cells to balance the bit error rate between the first set of memory cells and the second set of memory cells.

[0022] In yet another embodiment, a data storage device is provided, comprising: a memory including a first set of memory cells and a second set of memory cells; and means for verifying the memory cells being programmed in the first set of memory cells and the second set of memory cells to perform bit error rate (BER) balancing by using different programming-verification levels when storing a non-integer number of bits in each of the programmed memory cells.

[0023] In one embodiment, a data storage device is provided, comprising a memory and one or more processors. The memory includes word lines, wherein the word lines include a first set of memory cells and a second set of memory cells. The one or more processors are individually or in combination configured to: program a plurality of entangled data pages in the first set of memory cells and the second set of memory cells, wherein at least some of the entangled pages share a read threshold; and calibrate a read threshold for one of the entangled pages.

[0024] In another embodiment, a method is provided performed in a data storage device including memory, wherein a data page is stored between a first set of fractional bits per unit (BPC) memory cells and a second set of fractional bits per unit (BPC) memory cells. The method includes: fixing some read thresholds of the data page while scanning other read thresholds of the data page; performing a bit error rate estimation scan on the data page to generate optimized scanned read thresholds; fixing the optimized scanned read thresholds and scanning the previously fixed read thresholds; calibrating the previously fixed read thresholds; and outputting a set of calibrated read thresholds of the data page.

[0025] In yet another embodiment, a data storage device is provided, comprising: a memory including a first set of memory cells and a second set of memory cells configured to store a plurality of entangled pages; and a component for calibrating a read threshold for one of the plurality of entangled pages.

[0026] Other embodiments are possible, and each embodiment can be used alone or in combination. Therefore, various embodiments will now be described with reference to the accompanying drawings.

[0027] Implementation Plan

[0028] The implementation schemes described below relate to data storage devices (DSDs). As used herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Detailed information about example DSDs is provided below.

[0029] Figures 1A to 1C Examples of data storage devices suitable for implementing these embodiments are shown below. It should be noted that these are merely examples and other specific implementations may be used. Figure 1A This is a block diagram illustrating a data storage device 100 according to an implementation scheme. (See reference) Figure 1A In this example, the data storage device 100 includes a controller 102 coupled to non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term "die" refers to a non-volatile memory cell formed on a single semiconductor substrate and the associated circuitry for managing the physical operation of those non-volatile memory cells. The controller 102 interfaces with a host system and sends a sequence of commands for read, program, and erase operations to the non-volatile memory die 104. Furthermore, as used herein, the phrase "communicating with" or "coupled with" can mean directly communicating / coupling with or indirectly communicating / coupling with through one or more components, which may or may not be shown or described herein. The communication / coupling can be wired or wireless.

[0030] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller) may include one or more components configured individually or in combination to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, such as Figure 2A As shown, controller 102 may include one or more processors 138, which are individually or in combination configured to perform these functions, such as, but not limited to, those described herein and illustrated in the flowcharts, by executing computer-readable program code stored within and / or outside controller 102 (e.g., stored in random access memory (RAM) 116 or read-only memory (ROM) 118). Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0031] In one example implementation, a nonvolatile memory controller 102 is a device that manages data stored on nonvolatile memory and communicates with a host (such as a computer or electronic device) having any suitable operating system. The nonvolatile memory controller 102 may have various functionalities beyond those specifically described herein. For example, the nonvolatile memory controller may format the nonvolatile memory to ensure proper operation, map out faulty nonvolatile memory cells, and allocate spare cells to replace future failed cells. A portion of the spare cells may be used to maintain firmware (and / or other metadata for housekeeping and tracking) to operate the nonvolatile memory controller and implement other features. In operation, the host may communicate with the nonvolatile memory controller when it needs to read data from or write data to the nonvolatile memory. If the host provides a logical address where data will be read / written, the nonvolatile memory controller may translate the logical address received from the host into a physical address in the nonvolatile memory. The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wear on specific blocks of memory that would otherwise be repeatedly written) and garbage collection (moving only valid data pages to a new block after a block is full, so that the full block can be erased and reused).

[0032] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash memory) memory cells and may be programmable once, less-programmable, or more-programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC), etc.) or may use other memory cell-level technologies now known or developed hereafter. Furthermore, the memory cells may be fabricated in two or three dimensions.

[0033] The interface between controller 102 and non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, data storage device 100 can be a card-based system, such as a Secure Digital (SD) card or a micro-Secure Digital (micro-SD) card. In another embodiment, data storage device 100 can be part of an embedded data storage device.

[0034] Despite Figure 1AIn the illustrated example, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as...) Figure 1B and Figure 1C In the architecture shown, depending on the controller's capabilities, there may be two, four, eight, or more memory channels between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and the memory die.

[0035] Figure 1B An example is illustrated of a storage module 200 comprising multiple non-volatile data storage devices 100. Thus, the storage module 200 may include a storage controller 202 that interfaces with a host and with data storage devices 204, which include multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Connected Small Scale Compute Interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptops and tablets.

[0036] Figure 1C This is a block diagram illustrating a tiered storage system. The tiered storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) interface or an Ethernet Fibre Channel (FCoE) interface. In one embodiment, Figure 1C The illustrated system may be a rack-mounted mass storage system that can be accessed by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0037] Refer again Figure 2AThe controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls the internal bus arbitration of controller 102. Modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. Although in Figure 2A The RAM 116 is illustrated as being located separately from the controller 102, but in other embodiments, one or both of the RAM 116 and ROM 118 may be located within the controller 102. In yet another embodiment, portions of the RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0038] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide electrical interfacing with a host or next-level storage controller. The type of host interface 120 may be chosen depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial ATA Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0039] Backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. Command sequencer 126 generates command sequences (such as programming and erasing command sequences) to be sent to the non-volatile memory die 104. RAID (Redundant Array of Independent Disks) module 128 manages the generation of RAID parity and the recovery of faulty data. RAID parity can be used as an additional level of integrity protection for data being written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0040] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not necessary in the controller 102.

[0041] Figure 2B This is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 and address decoders 148, 150 for caching data. In this example, the peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102. The peripheral circuitry 141 may also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to those described herein and illustrated in the flowchart. For example, as... Figure 2B As shown, the memory die 104 may include one or more processors 168, which are individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, in the memory array 142, or external to the memory die 104. Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0042] As a complement or alternative to one or more processors 138 (or more generally, components) in controller 102 and one or more processors 168 (or more generally, components) in memory die 104, data storage device 100 may include another set of one or more processors (or more generally, components). Generally, regardless of the location and number of the one or more processors (or more generally, components) in data storage device 100, these processors may be configured individually or in combination to perform various functions, including but not limited to those described herein and illustrated in the flowcharts. For example, the one or more processors (or components) may be located in controller 102, memory device 104, and / or other locations within data storage device 100. Furthermore, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Additionally, a controller comprising one or more components (e.g., processors or other components described above) may be used to implement components for performing functions.

[0043] Return again Figure 2A The flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal operations of memory management and translates writes from the host into writes destined for memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only be written in multi-page format, and / or may not be written to at all (unless it is erased as a block). The FTL understands these potential limitations of memory 104, which may be invisible to the host. Therefore, the FTL attempts to translate writes from the host into writes destined for memory 104.

[0044] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table structure or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBA”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (enabling the recovery of the FTL’s data structure in the event of a sudden power outage) and wear leveling (ensuring uniform wear across memory blocks to prevent some blocks from becoming excessively worn, which would lead to a greater likelihood of failure).

[0045] Turn to the attached image again. Figure 3This is a block diagram of a host 300 and a data storage device 100 according to an embodiment. The host 300 may take any suitable form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 (hereinafter referred to as a computing device) in this embodiment includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to transfer data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0046] As mentioned above, bits per cell (BPC) refers to the number of bits that can be stored in a non-volatile memory (NVM) cell. Typically, BPC is an integer, such as four bits per cell (“X4”). While using four bits per cell (or 16 distinct states per cell) can save costs, it can reduce performance. To provide a trade-off between performance / reliability and cost savings, “fractional BPC” memory with non-integer bits per cell (e.g., 3.5 bits per cell (“X3.5”)) can be used. In X3.5 memory, 56 kilobytes (KB) of data are written to 16 KB of memory cells in the word line. In contrast, 48 KB of data is written to three bits per cell (X3) memory, and 64 KB of data is written to four bits per cell (X4) memory. Unlike X3 or X4 memory, in X3.5 memory, the mapping between user data and the various memory cell states is not straightforward, and different mappings can be associated with different drawbacks.

[0047] Turn to the attached image again. Figure 4A and Figure 4B An example of a bit-line pairing scheme for mapping data to various memory cell states is illustrated. In this scheme, a pair of memory cells exists within a page. This pair of memory cells can be independent or entangled, such as... Figure 4A and Figure 4BExamples are shown below. As these figures illustrate, there are two sets of memory cells on the same word line: an 8KB set on the left side of the word line and an 8KB set on the right side. There are four independent logical pages, including 32KB (4*8KB) consisting only of cells from the left or right side; and three entangled logical pages (3*8KB) consisting of cells from both sides. Therefore, seven bits are stored on each of the two memory cells. Pairing is performed within the same page (different column addresses but the same block address). Independent pages have a mapping that depends on only one cell, similar to X3 or X4 memory. Entangled pages combine the read thresholds from two cells on the same word line. Entangled bit decoding can be performed within the read amplifier or in the data path.

[0048] Two cells are read to read the page and infer the bit. To read the entangled logic page, a logic function is applied to the read results from the two cells. In this example, the first cell is read in state eight (S8), and the second cell is read in state four (S4). Then, a logic operation is applied to the two pages to derive the read bit.

[0049] Host data is written directly to logical pages. Ideally, different logical pages should not differ significantly in throughput and read latency when reading data. To achieve this, bit error rate (BER) balancing can be used between logical pages. BER balancing can be achieved by shifting states to be unevenly spaced, as done in x3 and x4 memory. In x3 and x4 memory, all memory cells within a word line receive the same read and write / verification threshold offsets because there are no inherent differences between them. More specifically, the flash memory programming process may involve performing multiple programming pulses. After each programming pulse, a set of verification operations is performed to check which cells have reached their target state and can be disabled. Verification operations are performed by sensing at each verification level corresponding to the target state. Normally, the same verification level is applied to all cells in the word line.

[0050] However, in X3.5 memory, due to the presence of entangled pages, BER balancing cannot be achieved using simple verification level optimization as in X3 and X4 memory. The following implementations provide new methods for achieving BER balancing in X3.5 memory. These implementations improve BER balancing and reduce the maximum BER while minimizing the impact on write latency. In general, these implementations provide several methods for optimizing BER balancing in non-volatile memory with entangled pages. These methods may rely on utilizing entangled pages and different aspects of the memory system.

[0051] In one embodiment, a novel verification method is provided for achieving BER balancing of entangled pages in a memory with a fractional BPC. While X3.5 memory will be used as an example to illustrate these embodiments, it should be understood that these embodiments can be used with any suitable memory with a fractional BPC, and X3.5 should not be construed as included in the claims unless explicitly stated herein. In one example embodiment, two different verification levels are used for a pair of entangled cells within the same word line for joint memory bits. Here, a different Control Gate Voltage (VCGR) offset is used for the verification level of each pair of entangled cells. This may involve doubling the number of verification levels, resulting in a reduction in write speed. For example, assume that cell 1 is entangled with cell 2, cell 3 with cell 4, and so on. Furthermore, it is assumed that for all states, the verification level for odd-numbered cells is lower than the verification level for even-numbered cells. According to this process, a set of verification operations is applied with increasing verification levels, where odd-numbered cells are verified using odd VCGR levels, followed by even-numbered cells verified using higher even VCGR verification levels. The operation can be performed on all states (e.g., 11 states for X3.5) in ascending order using 22 verification levels (i.e., 11 verification levels for odd-numbered units and 11 different levels for even-numbered units).

[0052] While the system proposed in this implementation improves the balance, the increased number of write / verification pulses may lead to increased write latency. Since the write thresholds differ, the read thresholds for entangled cells also vary. Therefore, it may be necessary to calibrate each read threshold individually, employing calibration schemes for the left and right cells. However, when calibrating entangled pages, there are read thresholds shared between different logical pages.

[0053] In another implementation, a modification to the integration time of the sense amplifier (SA) capacitor can be used instead of a modification to the VCGR to reduce write latency while maintaining double the number of verification levels for optimal BER balance. Modulating the capacitor integration time produces results similar to VCGR modulation, but without requiring actual modification to the VCGR, thus avoiding higher latency. Using the same VCGR with multiple capacitor integration times speeds up verification time, thereby increasing programming speed.

[0054] The proposed method can be combined with a Quick Pass Write (QPW) approach, in which memory cells are presented with high programming pulses (faster programming speed) until they reach the first verification level below their target state. Once a cell passes this lower verification level, the bit line voltage of that cell is adjusted so that the threshold voltage (Vt) increment caused by subsequent programming pulses is smaller (slower programming speed), thereby improving accuracy and tightening the charge voltage distribution (CVD). The QPW scheme can be summarized as using four verification levels per state: slow odd cells, fast odd cells, slow even cells, and fast even cells. These verification levels can be adjusted directly via VCGR or indirectly via SA capacitor integral time modulation.

[0055] Now will describe Figure 5 and Figure 6 To compare with writes used for non-fractional BPCs ( Figure 5 ) and writing for fractional BPC ( Figure 6 ).like Figure 5 As shown in flowchart 700, when writing the next state to a memory with a non-fractional BPC, the controller 102 of the data storage device 100 modifies the VCGR (710) and performs a fast QPW step to modify the capacitor integration time (720). Next, the controller 102 applies a write pulse (730) and performs a slow QPW step to modify the capacitor integration time (740). After several pulses, the controller 102 checks the verification level to determine whether the programming was successful (750).

[0056] like Figure 6 As shown in flowchart 800, when writing the next state to a memory with a fractional BPC, the controller 102 of the data storage device 100 modifies the VCGR (805) and performs a fast QPW step to modify the capacitor integration time of the left cell (810). Next, the controller 102 applies a write pulse (815) and performs a fast QPW step to modify the capacitor integration time of the right cell (820). Then, the controller 102 applies a write pulse (825) and performs a slow QPW step to modify the capacitor integration time of the left cell (830). The controller 102 then applies a write pulse (835), performs a slow QPW step to modify the capacitor integration time of the right cell (840), and applies an additional write pulse (845). After multiple pulses, the controller 102 checks the verification level to determine whether the programming was successful (855).

[0057] Balancing BER by moving memory states can increase the average BER but decrease the maximum BER. Figure 7 and Figure 8The effects of using different BER balancing methods are shown. More specifically, Figure 7 This is a graph showing the relationship between per-page BER and average BER in an implementation scheme that does not use bit error rate (BER) balancing. Figure 8 This is a graph showing the relationship between BER per page and average BER in an implementation using BER balancing. In these graphs, the X-axis represents the average BER, and the Y-axis represents the BER per page. Figure 7 The data is not balanced. It is clear that the contribution of each page is different, and the independent pages (non-entangled) with higher read thresholds (pages 0 to 3) contribute more BER. Figure 8 The diagram shows the balanced BER for a given average BER point.

[0058] This balance can also be seen when observing the CVD of the X3.5 line. Figure 9 This is a graph showing the relationship between the charging voltage distribution (CVD) and the DAC in an implementation scheme that does not use balancing. Figure 10 These are graphs showing the relationship between CVD and DAC using a balanced implementation. As these graphs show, balancing effectively shifts the state center (and read threshold). It should be noted that the shorter higher voltage states in both cases are due to X3.5, not balancing.

[0059] These figures show that balancing can be achieved for a given average BER point. However, when the BER is low and (more importantly) high, it is no longer possible to balance the BER across pages; however, entangled pages possess other advantageous properties that can be utilized. Due to the definition of page 5, sensing the soft bit (SB) is not as simple as with independent pages. To obtain an accurate SB, more logical operations can be performed, which may require more time and higher computational complexity.

[0060] To mitigate this problem, inaccurate bit reads (SBs) can be used to detect entangled pages. For example, for page 2, if a separate soft bit read (SBR) must be performed on the NAND, some cells may be unnecessarily marked as SBs. Decoding with inaccurate SBs will reduce error correction capability to some extent. Figure 11 The error correction capability for entangled page Page5 using inaccurate SB is shown, where the X-axis is the actual BER measured at the input to the decoder.

[0061] When designing this system, the BER balance can be calibrated so that pages corresponding to inaccurate SBs are less likely to have higher BERs. This manipulation of the BER balance can be customized for the logical mapping to maximize the use of BER imbalance. In other words, the BER balance can account for differences in decoding quality between pages (e.g., Page 5 has lower decoding capabilities due to suboptimal SB sensing). Specifically, in the example above, the balance reduces the BER on Page 5 (because its error correction capability is reduced) at the expense of slightly higher BERs on other pages.

[0062] In another implementation, when the BER is not fully balanced among logical pages, more important data can be written to a "more secure" logical page. This data may include, for example, firmware headers, important metadata, security keys, computation results, and other objects that are more important than regular data.

[0063] Several advantages exist associated with these implementations. For example, these implementations can be used to improve BER balancing in X3.5 memory and other fractional BPC memories. This avoids performance degradation, reduced error correction capability, and increased power consumption that can occur if BER cannot be balanced across pages. In one example implementation, these advantages can be used... Figure 12 This is implemented using the method described in flowchart 1500. Figure 12 As shown, the method includes: causing a BER balancing system (e.g., implemented in controller 102) to consider logical page attributes (such as SB efficiency) at some input BERs (1510). Next, the BER balancing system sets the verification levels of the left and right cells to account for some imbalances that favor lower SB efficiency (1520). Then, the BER balancing system uses the obtained verification levels in its operation (1530).

[0064] Another implementation involves read threshold calibration. While read thresholds for individual pages can be calibrated without any modifications, calibrating read thresholds for certain entangled logical pages presents some challenges because some pages share read thresholds across different logical pages.

[0065] The following implementation scheme can be used to address the read threshold calibration challenge of entangled pages, which improves the quality of the obtained read threshold, thereby reducing the BER. This increases throughput while reducing power consumption and read latency. Furthermore, directly minimizing the BER (e.g., by using a BER estimation scan (BES)) offers advantages over other calibration methods, such as valley-based search (VS) methods.

[0066] Generally, these implementations can be used to calibrate the read threshold for several entangled pages. Different trade-offs may be made between these options when implementing calibration using different options. The following paragraphs describe the options for handling read threshold calibration based on entanglement.

[0067] Read threshold calibration for entangled cells with the same read threshold

[0068] In one implementation, the read thresholds are equal between the left and right cells. This is the easiest configuration to manage because there is no need to distinguish between left-side and right-side read threshold calibration. In this design, when the logic mapping involves the same threshold from both left and right cells, calibration can be performed using a BER estimation scan (BES) as if there were only one read threshold. More specifically, a scan can be performed by applying multiple read operations around a single read threshold.

[0069] For each such read operation, entangled bits are generated by applying logical operations within memory 104, and the read page is passed to controller 102 for BER estimation. BER estimation is performed by calculating the parity weights corresponding to the read pages (i.e., by counting the number of pages that do not meet the parity equation). In single read threshold mode, this BER estimation can also be performed using the existing BES engine without hardware changes.

[0070] Read threshold calibration for entangled cells with different read thresholds

[0071] In another implementation, a read threshold calibrated based on other pages shared with the entangled page of the topic will be used to read the entangled page.

[0072] Figure 13 The flowchart 1600 in the document summarizes this aspect. For example... Figure 13 As shown, in this implementation, Page 5 read threshold calibration is required (1610). Controller 102 calibrates the read threshold of Page 4 (1620), and then calibrates the read threshold of Page 6 (1630). Then, controller 102 extracts the read threshold associated with Page 5 (1640).

[0073] Full scan

[0074] For the full scan method, to calibrate entangled pages involving N read thresholds, controller 102 can perform M^N reads, where M is the desired scan resolution around each of the read thresholds. For each of the M^N reads, controller 102 can compute the entangled pages in memory die 104 and perform BER estimation on them. The combination of read thresholds with the minimum checksum weights can be selected as optimal. Taking Page 5 as an example, this page involves N = 2 read thresholds, and it is assumed that a scan resolution of M = 7 is required. Controller 102 can perform 7^2 regular read operations (where entanglement is completed in memory die 104) and perform BER estimation for each of 49 options. This can be disabled due to the large number of sensing operations and the corresponding latency.

[0075] Simulated Scan

[0076] Using a simulated scanning method, memory 104 performs only M regular read operations (each involving sensing at N read thresholds), while the remaining processing is executed in controller 102. As in regular BES operation, the voltage range of each cell can be obtained by analyzing M read pages (i.e., its voltage range can be derived from the M read bits of each cell). Once the voltage range of each cell is determined, the read results for that cell under each of the M^N read level combinations can be simulated. Entangled bits are calculated based on the simulated read results of each of the two entangled cells to determine the entangled pages. Finally, BER estimation is performed on the simulated entangled pages. The read threshold combination corresponding to the minimum BER estimate among the M^N combinations is determined to be optimal.

[0077] In this method, only M read operations are performed to simulate M^N possible entangled pages, thus resulting in a significant reduction in sensing latency (compared to actual scanning). In some specific implementations, the simulated scan may require a dedicated ASIC (i.e., dedicated BES logic) adapted for X3.5 memory mapping to perform entangled page calculations.

[0078] In entangled pages with several thresholds, some read thresholds can be fixed while BES is performed on the remaining read thresholds. Read threshold calibration is independent; however, the checksum weight calculation used in BES depends on the position of all read thresholds in the logical page. If the fixed read thresholds are significantly off-target, it will hinder subsequent BES processes performed in this manner. However, if the fixed read thresholds are close enough to the optimal read threshold, performing BES on the remaining thresholds will find the optimal read threshold, and the process can then continue with BES on the previously fixed read thresholds.

[0079] In one implementation, one of the thresholds for entangled pages is fixed, and a BES is performed on another read threshold. The process can then be reversed so that the previously fixed read threshold is also optimized using BES. This option allows the use of existing ASICs with conventional memory (having a conventional BES engine). Taking Page 5 as an example, R3 can be fixed, and a single threshold scan can be performed around R7 and the corresponding single threshold BES. R7 can then be fixed based on the BES result, and a single threshold scan can be performed around R3, followed by a single threshold BES operation.

[0080] In another implementation, the BER indication can be read after Page 4 calibration to determine whether Page 5 can now be successfully read or whether Page 6 needs to be calibrated before rereading Page 5. It should be noted that calibrating all read thresholds for the failed-to-read subject pages is beneficial but does not necessarily need to occur "online" while the host 300 is waiting for the requested data. Furthermore, in one implementation, data for Page 5 can be read after Page 4 calibration, while calibration of the remaining read thresholds depending on Page 6 can be completed later during background operations.

[0081] Figure 14 Flowcharts illustrating these processes are provided in 1700. For example... Figure 14 As shown, an emergency Page 5 read threshold calibration is required (1710). After calibrating the read threshold of Page 4 (1720), controller 102 determines whether there is an indication that partial read threshold correction is sufficient (1730) (e.g., whether partial read threshold calibration calibrates the read threshold shared with Page 5). If partial read threshold correction is insufficient, the read threshold of Page 6 is also calibrated (these read thresholds relate to other uncalibrated read thresholds of the remaining Page 5) (1740), and the read thresholds associated with Page 5 are extracted (1750). However, if partial read threshold correction is sufficient, the read thresholds associated with Page 5 are extracted without additional calibration (1760), and the calibration of the remaining Page 5 read thresholds is scheduled for background operation time (1770). In a general setup, it may be necessary to configure a scheme based on the selected logical mapping for all states so that an appropriate read threshold calibration scheme is available.

[0082] As mentioned above, the BER balance between pages is not optimal when the left and right cells use the same read threshold. Also as mentioned above, to achieve optimal BER balance, the left and right cells of an entangled page can use different verification levels, and therefore require different read thresholds when reading the entangled page. In this case, even when an entangled page involves a single threshold, it will effectively involve two read thresholds because some cells have different thresholds. Therefore, if this type of BER balance is used, a single-threshold entangled page effectively becomes a page with multiple read thresholds, making the above method applicable to this situation as well.

[0083] Several advantages exist associated with these implementations. For example, these implementations can improve various aspects of read threshold calibration for X3.5 memory or other fractional-bit memory because a well-calibrated read threshold can improve performance and reduce power consumption. Furthermore, the read threshold calibration process itself may be length-limited, and these implementations can be used to reduce latency. In one example implementation, these advantages can be used... Figure 15 This is implemented using the method described in flowchart 1800. Figure 15 As shown, after initiating read threshold calibration (1810) for the entanglement threshold, memory 104 fixes some read thresholds (while scanning other read thresholds) and passes the read pages to controller 102 (1820). Controller 102 performs standard BES operations on the read pages to optimize the scanned read thresholds (1830). Memory 104 fixes the optimized read thresholds and scans the previously fixed read thresholds (1840). Then, controller 102 calibrates the previously fixed read thresholds and outputs a complete set of calibrated read thresholds (1850).

[0084] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0085] Memory devices can be formed from passive and / or active components in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as antifuses, phase-change materials, and optionally manipulation elements such as diodes. As yet another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0086] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0087] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0088] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in the xz plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element is formed. As a non-limiting example, the substrate may include a semiconductor (such as silicon).

[0089] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0090] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the y direction is generally perpendicular to the main surface of the substrate, and the x and z directions are generally parallel to the main surface of the substrate).

[0091] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xz plane) to produce a three-dimensional arrangement of memory elements having multiple vertically stacked elements on memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0092] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0093] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers that are at least partially located within the single substrate. As a non-limiting example, the substrate may include a semiconductor (such as silicon). In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the lower memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or there may be intermediate layers between memory device classes.

[0094] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0095] The operation and communication with memory elements typically require associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0096] Those skilled in the art will recognize that the present invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures as described herein and as understood by those skilled in the art.

[0097] The above detailed description is intended to be understood as an illustration of selected forms of the invention, and not a definition of the invention. Only the following claims (including all equivalents) are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A data storage device, the data storage device comprising: The memory includes word lines, wherein the word lines include a first set of memory cells and a second set of memory cells; and One or more processors, wherein the one or more processors are configured individually or in combination to: Programming multiple entangled data pages in the first group of memory cells and the second group of memory cells, wherein at least some of the multiple entangled pages share a read threshold; as well as Calibrate the read threshold of one of the multiple entangled pages.

2. The data storage device of claim 1, wherein the first set of memory cells and the second set of memory cells have the same read threshold, and wherein a bit error rate (BER) estimation scan (BES) is used to calibrate the read threshold of the one of the plurality of entangled pages, the BER estimation scan (BES) applying multiple read operations around a single read threshold.

3. The data storage device of claim 1, wherein the first group of memory cells and the second group of memory cells have different read thresholds, and wherein the read threshold of the one entangled page among the plurality of entangled pages is calibrated based on the read threshold of other entangled pages that share the read threshold with the one entangled page among the plurality of entangled pages.

4. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to perform a full scan of the plurality of read thresholds to achieve the desired scan resolution.

5. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to perform analog scans.

6. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to calibrate the read threshold of one of the plurality of entangled pages by: Perform partial read threshold calibration on another entangled page among the plurality of entangled pages; Determine whether the partial read threshold calibration provides sufficiently good calibration for the read threshold shared with one of the plurality of entangled pages; as well as In response to determining whether the partial read threshold calibration provides sufficiently good calibration for the read threshold shared with the one of the plurality of entangled pages, the calibrated read threshold of the other of the plurality of entangled pages is used as the calibrated read threshold of the one of the plurality of entangled pages.

7. The data storage device of claim 6, wherein the one or more processors are further configured individually or in combination to: The reading threshold calibration for another entangled page among the multiple entangled pages is performed as a background operation.

8. The data storage device of claim 6, wherein the one or more processors are further configured individually or in combination to: In response to the determination that the partial read threshold calibration did not provide sufficiently good calibration for the read threshold shared with one of the plurality of entangled pages: Calibrate the read threshold of yet another entangled page among the plurality of entangled pages; and The calibrated read threshold of the yet another entangled page among the plurality of entangled pages is used as the calibrated read threshold of the one entangled page among the plurality of entangled pages.

9. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

10. In a data storage device including memory, wherein data pages are stored between a first set of fractional bits per unit (BPC) memory cells and a second set of fractional bits per unit (BPC) memory cells: Fix some read thresholds for the data page, while scanning other read thresholds for the data page; Perform a bit error rate estimation scan on the data page to generate an optimized scanned read threshold; Fix the optimized scanned read threshold, and scan the previously fixed read threshold; Calibrate the previously fixed read threshold; as well as Output a set of calibrated read thresholds for the data page.

11. The method of claim 10, wherein the data page comprises an entangled data page.

12. The method of claim 10, further comprising: Perform a full scan of the data page at the required scan resolution to reach the read threshold.

13. The method of claim 10, further comprising: Perform a simulated scan of the read threshold of the data page.

14. The method according to claim 10, further comprising: Perform partial read threshold calibration on another data page; Determine whether the partial read threshold calibration provides sufficiently good calibration for the read threshold shared with the data page; as well as In response to determining whether the partial read threshold calibration calibrates a read threshold shared with the data page, the calibrated read threshold of the other data page is used as the calibrated read threshold of the data page.

15. The method according to claim 14, further comprising: The read threshold calibration for the other data page is performed as a background operation.

16. The method of claim 14, further comprising: In response to the determination that the partial read threshold calibration did not provide sufficiently good calibration for the read threshold shared with the data page: Calibrate the read threshold for another data page; as well as The calibrated read threshold of the other data page is used as the calibrated read threshold of the data page.

17. The method of claim 10, wherein the scan is performed by the memory.

18. The method of claim 10, wherein the bit error rate estimation scan is performed by a controller in the data storage device.

19. The method of claim 10, further comprising: The data page is read using the set of calibrated read thresholds.

20. A data storage device, the data storage device comprising: The memory includes a first set of memory cells and a second set of memory cells configured to store a plurality of entangled pages; and A component for calibrating the read threshold of one of the plurality of entangled pages.

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