Delay line circuit, DDR delay adjustment system and DDR memory chip
By designing cascaded delay units and adjustment units, the problems of glitches and timing losses in DDR transmission are solved, achieving glitches-free and timing loss-free delay adjustment, simplifying the control logic and reducing the chip area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- VIA ALLIANCE SEMICON CO LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-31
AI Technical Summary
During DDR transmission, phase switching of delay line circuits is prone to generating glitches, which affect the stability of the DDR PHY system. Furthermore, existing technologies require the addition of glitch elimination circuits, which can lead to timing losses.
The design employs multiple cascaded delay units and adjustment units. By selectively accessing the delay path with control signals, it ensures that the signals are superimposed in phase, avoiding glitches. Furthermore, it achieves delay adjustment without timing loss through an inverter.
It achieves glitch-free and timing-free phase switching, simplifies control logic, reduces chip area of delay lines and delay compensation modules, and improves system stability and anti-interference performance.
Smart Images
Figure CN122493916A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor integrated circuit technology, and in particular to a delay line circuit, a DDR delay adjustment system, and a DDR memory chip. Background Technology
[0002] During Double Data Rate (DDR) transmission, the timing accuracy requirements of the data path are extremely stringent. Since each timing stage may face strict constraints, and timing deviations are inevitably introduced during actual transmission, the DDR physical layer (DDR PHY) needs to deploy a large number of delay line units to achieve timing calibration through precise delay adjustment.
[0003] During delay adjustment, the phase of the delay line cells needs to be frequently switched to traverse and lock the optimal delay value. However, phase switching operations are prone to inducing glitch, which in turn affects the stability of the DDR PHY system.
[0004] To eliminate the effects of glitches, delay line circuits typically require the integration of dedicated de-glitch circuits. However, regardless of the glitch elimination technique employed, some degree of timing loss is unavoidable during phase switching. Summary of the Invention
[0005] In view of this, this disclosure proposes a delay line circuit, a DDR delay adjustment system, and a DDR memory chip, so that no glitches are generated and no timing loss occurs when switching phases.
[0006] According to a first aspect of this disclosure, a delay line circuit is provided for delaying an input clock signal to obtain a delayed clock signal. The delay line circuit includes: a plurality of cascaded delay units, each including a first delay element, a second delay element, and a selection element; a second input terminal of the first delay element is connected to a first input terminal of the second delay element via the selection element; the selection element selects whether to connect the second delay element to the delay path of the clock signal according to a control signal related to the amount of delay required to delay the clock signal to the delayed clock signal; and an adjustment unit that receives a signal output by the first delay element of the last delay unit, inverts the signal, and inputs the inverted signal to the second input terminal of the second delay element of the last delay unit, wherein the input clock signal is input to the second input terminal of the first delay element of the first delay unit, the delayed clock signal is output from the output terminal of the second delay element of the first delay unit, and the input signals of the first and second input terminals of the selected second delay element are in phase.
[0007] In one possible implementation, for any two adjacent delay units among the plurality of delay units, the output terminal of the first delay element of one delay unit is connected to the second input terminal of the first delay element of the other delay unit, and the output terminal of the second delay element of the other delay unit is connected to the second input terminal of the second delay element of the first delay unit.
[0008] In one possible implementation, the first input terminal of the first delay element of any odd-numbered delay unit in the plurality of delay units is out of phase with the input signal of the first input terminal of the first delay element of any even-numbered delay unit.
[0009] In one possible implementation, the first input terminal of the first delay element of any odd-numbered delay unit is input with a low level, and the first input terminal of the first delay element of any even-numbered delay unit is input with a high level.
[0010] In one possible implementation, the first delay element, the second delay element, and the selection element of each delay unit respectively include a first multiplexer, a second multiplexer, and a switching device. Whether the switching device of each delay unit is turned on or off is controlled by the control signal. Each time the delay line circuit is used to delay the input clock signal, the switching device of only one delay unit among the plurality of delay units is turned on.
[0011] In one possible implementation, the adjustment unit includes an inverter, the input of which is connected to the output of the first delay element of the last delay unit, and the output of which is connected to the second input of the second delay element of the last delay unit.
[0012] In one possible implementation, when the delay line circuit is used to delay the positive phase clock signal to obtain a first delayed clock signal, the positive phase clock signal is input to the second input terminal of the first delay element of the first delay unit, and the first delayed clock signal is the clock signal output by the output terminal of the second delay element of the first delay unit.
[0013] In one possible implementation, when the delay line circuit is used to delay the inverted clock signal to obtain a second delayed clock signal, the inverted clock signal is inverted and then input to the second input terminal of the first delay element of the first delay unit, and the second delayed clock signal is the inverted signal of the clock signal output by the output terminal of the second delay element of the first delay unit.
[0014] According to a second aspect of this disclosure, a DDR delay adjustment system is provided, comprising: the delay line circuit described above; and a controller for generating the control signal based on the phase difference between the input clock signal and the delayed clock signal.
[0015] According to a third aspect of this disclosure, a DDR memory chip is provided, comprising: a memory cell array for storing data; the aforementioned delay line circuit; and a controller for generating the control signal based on the phase difference between the input clock signal and the delayed clock signal.
[0016] This disclosure eliminates glitches and timing losses during phase switching, and eliminates the need for glitches suppression circuitry in the delay lines, thereby reducing the area of the BDL and DLYCOMP. Furthermore, the control logic is simplified, thus reducing the design complexity of the controller.
[0017] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0018] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0019] Figure 1 A block diagram of a delay line circuit 100 according to an embodiment of the present disclosure is shown.
[0020] Figure 2 A schematic diagram illustrating the principle of a delay unit 110 according to an embodiment of the present disclosure is shown.
[0021] Figure 3 An exemplary block diagram of a delay line circuit 100 according to an embodiment of the present disclosure is shown.
[0022] Figure 4 This diagram illustrates the delay path of connecting the second delay element of the first delay unit to the clock signal.
[0023] Figure 5 This diagram illustrates the delay path of the second delay element of the second delay unit connected to the clock signal.
[0024] Figure 6 This diagram illustrates the delay path in which the second delay element of the penultimate delay unit is connected to the clock signal.
[0025] Figure 7 The timing diagram corresponding to the delay adjustment in the prior art is shown.
[0026] Figure 8A timing diagram is shown corresponding to delay adjustment of a delay line circuit according to an embodiment of the present disclosure.
[0027] Figure 9 A block diagram of a DDR latency adjustment system 900 according to an embodiment of the present disclosure is shown.
[0028] Figure 10 A block diagram of a DDR memory chip 1000 according to an embodiment of the present disclosure is shown. Detailed Implementation
[0029] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0030] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0031] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0032] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0033] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0034] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0035] Figure 1A block diagram of a delay line circuit 100 according to an embodiment of the present disclosure is shown. The delay line circuit 100 can be used to delay an input clock signal CLKI to obtain a phase-controllable delayed clock signal CLKO, thereby meeting the stringent timing alignment requirements of the DDR interface.
[0036] like Figure 1 As shown, the delay line circuit 100 may include a plurality of cascaded delay units 110, each delay unit 110 including a first delay element 111, a second delay element 112, and a selection element 113. Within each delay unit 110, the second input terminal, such as terminal B, of the first delay element 111 is connected to the first input terminal, such as terminal A, of the second delay element 112 via the selection element 113. The selection element 113 selects whether to connect the second delay element 112 to the delay path of the clock signal CLKI based on a control signal, such as the BIN value described below, related to the amount of delay required to adjust the clock signal CLKI to the delayed clock signal CLKO.
[0037] like Figure 1 As shown, the delay line circuit 100 may further include an adjustment unit 120, which is used to receive the signal output by the first delay element 111 of the last delay unit, invert the signal, and input the inverted signal to the second input terminal of the second delay element 112 of the last delay unit.
[0038] The clock signal CLKI is input to the second input terminal of the first delay element 111 of the first delay unit, and the delayed clock signal CLKO is output from the output terminal of the second delay element 112 of the first delay unit. The input signals of the first and second input terminals of the selected second delay element 112 are in phase.
[0039] In some embodiments, the cascading of multiple delay units 110 in the delay line circuit 100 refers to the multiple delay units 110 forming a cross-coupled chain structure through bidirectional signal paths, forming two complementary transmission paths in the forward and reverse directions.
[0040] It should be understood that a bidirectional signal path may include a forward signal path from the preceding delay unit to the following delay unit and a reverse signal path from the following delay unit to the preceding delay unit.
[0041] like Figure 1As shown, the first delay element 111 of multiple delay units 110 is connected in series with the output terminal through the second input terminal. That is, the output terminal of the first delay element 111 of the i-th delay unit is connected to the second input terminal of the first delay element 111 of the (i+1)-th delay unit, thereby forming a forward signal path from the clock signal CLKI to the last delay unit.
[0042] The second delay elements 112 of the multiple delay units 110 are connected in series with the second input terminal through the output terminal. That is, the output terminal of the second delay element 112 of the (i+1)th delay unit is connected to the second input terminal of the second delay element 112 of the ith delay unit, thereby forming an inverted signal path from the inverted signal output from the adjustment unit 120 to the first delay unit.
[0043] Where i is an integer greater than or equal to 1. It can be understood that for the i-th delay unit and the (i+1)-th delay unit, the i-th delay unit is the preceding delay unit, and the (i+1)-th delay unit is the following delay unit.
[0044] Taking the clock signal CLKI as a positive-phase clock signal (P clock) as an example, the forward signal path and the reverse signal path carry the in-phase signal and the reverse signal respectively. The in-phase signal is transmitted along the first delay element in the forward signal path, and the reverse signal is transmitted back along the second delay element in the reverse signal path.
[0045] It should be understood that the P clock is a positive clock, which is the direct output of the reference clock, with a phase of 0 degrees and the rising edge aligned with the reference clock. The N clock is an inverted clock, which is the inverted output of the reference clock, with a phase of 180 degrees and the inversion of the P clock.
[0046] When the selection element 113 of the i-th delay unit selects to connect the second delay element 112 of the i-th delay unit to the delay path of the clock signal CLKI according to the control signal, the signal on the second input terminal of the i-th delay unit is input to the first input terminal of the second delay element 112 of the i-th delay unit.
[0047] For example, such as Figure 4 As shown, when the selection element 113 of the first delay unit selects to connect the second delay element 112 of the first delay unit to the delay path of the clock signal CLKI according to the control signal, the signal on the second input terminal of the first delay element 111 of the first delay unit is input to the first input terminal of the second delay element 112 of the first delay unit, and the signals on the second input terminals of the first delay elements of all other delay units are input to the second input terminal.
[0048] Taking the clock signal CLKI as the P clock as an example, the clock signal CLKI is initially at a low level, such as 0. This low level is output from the first delay element of the last delay unit to the adjustment unit 120 through the forward signal path. The adjustment unit 120 inverts the low level to a high level, such as 1. This high level is output as a low level from the second delay element of the second delay unit through the reverse signal path to the second input terminal of the second delay element 112 of the first delay unit. At the same time, the low level of the clock signal CLKI is input to the first input terminal of the second delay element 112 of the first delay unit. Therefore, the signals at the first and second input terminals of the second delay element 112 of the first delay unit are both low level. The signals at these two input terminals are in phase and no glitches will be generated.
[0049] For example, such as Figure 5 As shown, when the selection element 113 of the second delay unit selects to connect the second delay element 112 of the second delay unit to the delay path of the clock signal CLKI according to the control signal, the signal on the second input terminal of the first delay element 111 of the second delay unit is input to the first input terminal of the second delay element 112 of the second delay unit, and the signals on the second input terminals of the first delay elements of all other delay units are input to the second input terminal.
[0050] Compared to adopting Figure 4 The delay adjustment adopts Figure 5 The delay adjustment is achieved by adding a first delay component 111 of the first delay unit 110 and a second delay component 112 of the second delay unit 110 to the delay path of the clock signal CLKI.
[0051] Continuing with the example of clock signal CLKI as P clock, the low level of clock signal CLKI is output to adjustment unit 120 through the first delay element of the last delay unit via the forward signal path. Adjustment unit 120 inverts the low level to a high level, such as 1. This high level is output to the second input terminal of the second delay element 112 of the second delay unit via the reverse signal path. At the same time, the low level of clock signal CLKI is converted to a high level through the first delay unit and input to the first input terminal of the second delay element 112 of the second delay unit. Therefore, the signals at the first and second input terminals of the second delay element 112 of the second delay unit are both high level. The signals at these two input terminals are in phase and no glitches are generated.
[0052] like Figure 6As shown, when the selection element 113 of the second-to-last delay unit selects to connect the second delay element 112 of the second-to-last delay unit to the delay path of the clock signal CLKI according to the control signal, the signal on the second input terminal of the first delay element 111 of the second-to-last delay unit is input to the first input terminal of the second delay element 112 of the second-to-last delay unit, and the signals on the second input terminals of the first delay elements of all other delay units are input to the second input terminal.
[0053] Continuing with the example of clock signal CLKI as P clock, the low level of clock signal CLKI is output from the first delay element of the last delay unit to the adjustment unit 120 through the forward signal path. The adjustment unit 120 inverts the low level to a high level, such as 1. This high level is then output as a low level through the second delay element of the last delay unit to the second input terminal of the second delay element 112 of the second-to-last delay unit through the reverse signal path. At the same time, the low level of clock signal CLKI is converted to a low level through the third-to-last delay unit through the forward signal path and input to the first input terminal of the second delay element 112 of the second-to-last delay unit. Therefore, the signals at the first and second input terminals of the second delay element 112 of the second-to-last delay unit are both high level. The signals at these two input terminals are in phase and will not produce glitches.
[0054] Therefore, in each delay adjustment, through the control signal, only one delay unit, under the selection of its selection element, has its signal on the second input terminal of the first delay element of that delay unit inputted to the first input terminal of the second delay element of that delay unit, so as to connect the second delay element to the delay path of the clock signal CLKI.
[0055] Furthermore, the first input terminal of the second delay element of the delay unit receives the signal from the first delay element of the delay unit, and the second input terminal of the second delay element of the delay unit receives the feedback signal from the adjacent delay unit. Due to the symmetry of the delay unit and the phase flipping characteristic of the adjustment unit 120, the two input terminals are logically in phase in steady state, such as being both high or both low. Therefore, the signals on the two input terminals of the second delay element of the delay unit are in phase, and thus no glitches are generated.
[0056] The control signal can be used to select which delay unit's second delay element to connect to the delay path of the clock signal CLKI. Compared to connecting the second delay element of the i-th delay unit to the delay path, connecting the second delay element of the (i+1)-th delay unit to the delay path allows the clock signal CLKI to flow further through the first delay component 111 of the i-th delay unit 110 and the second delay component 112 of the (i+1)-th delay unit 110, thereby increasing the delay of the clock signal CLKI.
[0057] Therefore, the delay path of the delay line circuit 100 is selectable. The clock signal CLKI can be selected by the control signal to flow through the corresponding delay elements of the delay unit to delay the clock signal CLKI by the above-mentioned delay amount, thereby outputting the above-mentioned delayed clock signal. The further the delay unit to which the second delay element connected to the delay path belongs is from the first delay unit, the greater the delay amount of the clock signal CLKI.
[0058] It should be understood that this embodiment does not impose specific limitations on the specific topology, process type, or delay implementation method of the first and second delay elements. Any device that possesses controllable delay characteristics and is equipped with a first input terminal, a second input terminal, and an output terminal can be used as the first and second delay elements in this embodiment. For example, such as... Figure 2 As shown, the first delay element and the second delay element can be multiplexers composed of inverters.
[0059] Furthermore, it should be understood that this embodiment does not impose specific limitations on the specific topology and implementation of the selection element. Any device capable of responding to a control signal to select whether the second delay element of its respective delay unit is connected to the delay path of the clock signal CLKI, that is, any device capable of responding to a control signal to control the on / off state between the second delay element of its respective delay unit and the delay path of the clock signal CLKI, can be used as the selection element in this embodiment. For example, the selection element may include, but is not limited to, any device with controllable on / off functions such as a transmission gate, a tri-state gate, a multiplexer, or an analog switch.
[0060] The following will combine Figure 7 and Figure 8 The technical effects of this embodiment will be explained below. It should be understood that CLKI represents the input clock signal, CLKO represents the delayed clock signal, DLY_UPDATE represents the delayed update signal, BIN represents the binary configuration signal, which is the control signal mentioned above, and DEG_MODE represents the degraded mode control signal, which is a high-level active signal that remains high during the T2 stage, indicating that the DDR PHY has entered the degraded working mode.
[0061] like Figure 7As shown, in the prior art delay line circuit, the clock signal CLKI needs to be turned off when switching phases during delay adjustment, resulting in... Figure 7 The timing parameters T1, T2, T3, and T4 are forcibly interrupted and lost. Furthermore, the signal transitions during phase switching are prone to glitches. To suppress these glitches, additional circuitry (i.e., de-glitch circuitry) needs to be added to the delay lines, increasing chip area overhead.
[0062] In contrast, according to this embodiment, the input of the second delay element 112 continuously receives drive signals from either the forward or reverse signal path. Therefore, the second delay element 112 is always in an active drive state. Furthermore, during phase switching, the two signals from the forward and reverse signal paths are superimposed in phase, allowing the output signal to maintain continuous transmission without the need for a wait period or a shielding window. Adjusting the delay of the clock signal CLKI only requires controlling the selection element 113 at different positions to connect the second delay element 112 at the corresponding position to the delay path via a control signal. The signal propagation of the entire delay line is uninterrupted, fundamentally avoiding timing loss.
[0063] Therefore, as Figure 8 As shown, the delay line circuit in this embodiment does not need to shut down the clock signal CLKI when switching phases during delay adjustment, thus avoiding timing loss and achieving zero timing loss. At the same time, since no glitches are generated during phase switching, there is no need to add an additional de-glitch circuit to the delay line. This not only simplifies the circuit design but also effectively reduces the chip area of the bit delay line (BDL) and delay compensation (DLYCOMP) modules, thus achieving dual optimization of area and performance.
[0064] In this context, BDL (Block Delay Line) typically refers to delay line units configured for specific time widths (such as DQ / DQS), while DLYCOMP (Due Time Compression Line) typically refers to auxiliary circuitry used to dynamically track and compensate for process / voltage / temperature variations, working in conjunction with BDL to ensure delay accuracy. Since this embodiment eliminates the need for de-glitch circuitry, the structural design of BDL can be simplified, reducing its area. Because signal propagation in this embodiment is uninterrupted and delay adjustment is more stable, the compensation burden on DLYCOMP can be reduced, further simplifying its structure and consequently reducing its area.
[0065] Therefore, the delay line circuit according to this embodiment can not only achieve no glitches and no timing loss when switching phases, but also eliminate the need to add circuitry for glitches elimination in the delay line, thereby reducing the area of BDL and DLYCOMP.
[0066] In one possible implementation, such as Figure 1 As shown, for any two adjacent delay units among the plurality of delay units 110, the output terminal of the first delay element 111 of one delay unit is connected to the second input terminal of the first delay element 111 of the other delay unit, and the output terminal of the second delay element 112 of the other delay unit is connected to the second input terminal of the second delay element 112 of the first delay unit.
[0067] For example, the output terminal of the first delay element 111 of the first delay unit is connected to the second input terminal of the first delay element 111 of the second delay unit, and the output terminal of the second delay element 112 of the second delay unit is connected to the second input terminal of the second delay element 112 of the first delay unit.
[0068] Thus, two adjacent delay units are bidirectionally interconnected, forming a bidirectional path for the forward signal path and the reverse signal path in the delay line. When the phase is switched, the signals of the forward signal path and the reverse signal path are superimposed in phase at the switching node (i.e., the second delay element of the selected delay unit), so that no glitches are generated and timing loss can be avoided.
[0069] In one possible implementation, the first input terminal of the first delay element of any odd-numbered delay unit in the plurality of delay units is out of phase with the input signal of the first input terminal of the first delay element of any even-numbered delay unit.
[0070] For example, the first input terminal of the first delay element 111 of the first delay unit is input with a low level, and the first input terminal of the first delay element 111 of the second delay unit is input with a high level. Therefore, the signal at the first input terminal of the first delay element 111 of the first delay unit is out of phase with the signal at the first input terminal of the first delay element 111 of the second delay unit.
[0071] Therefore, the delay unit remains actively pre-driven in both selected and unselected states. This allows the signals in the forward and reverse signal paths to be superimposed in phase during phase switching, ensuring continuous output signal transmission and achieving zero timing loss. Simultaneously, the signal processing of the inverting input is similar to a differential signal mechanism, effectively suppressing common-mode interference and improving the system's anti-interference performance. Furthermore, the smooth signal switching process avoids glitches at the source, eliminating the need for additional glitches-eliminating circuitry and enabling glitch-free delay adjustment.
[0072] In one possible implementation, such as Figures 3-6As shown, each delay unit 110 includes a first delay element 111, a second delay element 112, and a selection element 113, which respectively include a first multiplexer, a second multiplexer, and a switching device S1. The conduction of the switching device S1 of each delay unit 110 is controlled by the control signal. Each time the delay line circuit 100 is used to adjust the delay of the clock signal CLKI, the switching device S1 of only one delay unit 110 among the plurality of delay units 110 is turned on.
[0073] Therefore, the conduction state of the switching device S1 in each delay unit 110 is controlled by the control signal, and each time the delay line circuit 100 operates, only one delay unit 110 has its switching device S1 turned on, while the switching devices S1 of the remaining delay units are turned off. This avoids signal conflicts caused by simultaneous conduction of multiple paths, simplifies the control logic, and thus reduces the design complexity of the controller.
[0074] In one possible implementation, the adjustment unit 120 includes an inverter, the input of which is connected to the output of the first delay element of the last delay unit, and the output of which is connected to the second input of the second delay element of the last delay unit.
[0075] Therefore, the inverter receives the output signal of the first delay element 111 of the last delay unit 110, flips its phase by 180°, and feeds it back to the second input terminal of the second delay element 112 of the last delay unit 110.
[0076] In one possible implementation, when the delay line circuit 100 is used to delay the positive phase clock signal to obtain a first delayed clock signal, the positive phase clock signal is input to the second input terminal of the first delay element of the first delay unit, and the first delayed clock signal is the clock signal output by the output terminal of the second delay element of the first delay unit.
[0077] Therefore, when the delay line circuit 100 is used to delay the P clock to obtain the first delayed clock signal, the P clock is directly input to the second input terminal of the first delay element 111 of the first delay unit 100. The signal is transmitted step by step, and after being processed by the second delay element 112 of the selected delay unit, the first delayed clock signal is output from the output terminal of the second delay element 112 of the first delay unit.
[0078] In one possible implementation, when the delay line circuit 100 is used to delay the inverted clock signal to obtain the second delayed clock signal, the inverted clock signal is inverted and then input to the second input terminal of the first delay element 111 of the first delay unit 110, and the second delayed clock signal is the inverted signal of the clock signal output by the output terminal of the second delay element 112 of the first delay unit 110.
[0079] Therefore, when the delay line circuit 100 is used to delay the N clock to obtain the second delayed clock signal, the inverted clock signal is first inverted by an external inverter, restored to the in-phase state, and then input to the second input terminal of the first delay element 111 of the first delay unit 110. The signal is transmitted step by step, and after being processed by the second delay element 112 of the selected delay unit, the signal output from the output terminal of the second delay element 112 of the first delay unit is inverted by an external inverter to obtain the second delayed clock signal.
[0080] Figure 9 A block diagram of a DDR latency adjustment system 900 according to an embodiment of the present disclosure is shown. Figure 9 As shown, the DDR delay adjustment system 900 may include a delay line circuit 100 and a controller 920. The controller 920 is used to generate the control signal based on the phase difference between the input clock signal and the delayed clock signal. For the delay line circuit 100, please refer to the previous section on... Figures 1-6 The specific details will not be repeated here.
[0081] In some embodiments, the controller 920 can calculate the number of delay units required to be connected in the delay path based on the total delay time required to adjust the clock signal CLKI to the delayed clock signal CLKO and the delay parameters of a single delay unit, and generate control signals, such as BIN values, for connecting that number of delay units to the delay path. Then, corresponding to the generated control signals, the selection element 113 of each delay unit 110 selects whether to connect the second delay element 112 to the delay path, thereby achieving phase switching. It should be understood that... Figure 2 The sel and selb signals in the code are control signals.
[0082] Taking the BIN value as a control signal as an example, the controller 920 can flexibly adjust the number of bits in the BIN value according to the calculated number of delay units. For example, if 4 delay units are required, the controller 920 can generate a 2-bit BIN value; if 8 delay units are required, the controller 920 can generate a 3-bit BIN value; and if 16 delay units are required, the controller 920 can generate a 4-bit BIN value.
[0083] Therefore, the controller 920 can generate a BIN value with the corresponding bit width according to the actual delay unit requirements, so as to achieve precise selection and control of the delay units accessed in the delay path.
[0084] Therefore, the DDR delay adjustment system according to this embodiment can not only achieve no glitches and no timing loss when switching phases, but also eliminate the need to add circuitry for glitches elimination in the delay lines, thereby reducing the area of BDL and DLYCOMP.
[0085] Figure 10 A block diagram of a DDR memory chip 1000 according to an embodiment of the present disclosure is shown. Figure 10 As shown, the DDR memory chip 1000 may include a memory cell array 1010, a delay line circuit 100, and a controller 920. The controller 920 is used to generate the control signal based on the phase difference between the input clock signal and the delayed clock signal. For the delay line circuit 100, please refer to the previous section on... Figures 1-6 Detailed descriptions are omitted here. For the controller 920, please refer to the previous section on... Figure 9 The specific details will not be repeated here.
[0086] In some embodiments, the memory cell array 1010 is used to store data. The memory cell array 1010 can adopt any memory architecture known in the art (e.g., DRAM array), and its specific circuit structure and working principle are within the scope of prior art, so they will not be described in detail here.
[0087] Therefore, the DDR memory chip according to this embodiment can not only achieve no glitches and no timing loss when switching phases, but also eliminates the need to add circuitry for glitches elimination in the delay lines, thereby reducing the area of BDL and DLYCOMP, and thus reducing the area of the DDR memory chip.
[0088] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A delay line circuit for delaying an input clock signal to obtain a delayed clock signal, characterized in that, include: Multiple cascaded delay units, each including a first delay element, a second delay element, and a selection element, wherein the second input terminal of the first delay element is connected to the first input terminal of the second delay element via the selection element, and the selection element selects whether to connect the second delay element to the delay path of the clock signal according to a control signal related to the amount of delay required to adjust the clock signal to the delay amount required for the delayed clock signal; as well as The adjustment unit receives the signal output from the first delay element of the last delay unit, inverts the signal, and inputs the inverted signal to the second input terminal of the second delay element of the last delay unit. The clock signal is input to the second input terminal of the first delay element of the first delay unit, and the delayed clock signal is output from the output terminal of the second delay element of the first delay unit. The input signals of the first input terminal and the second input terminal of the selected second delay element are in phase.
2. The delay line circuit according to claim 1, characterized in that, For any two adjacent delay units among the plurality of delay units, the output terminal of the first delay element of one delay unit is connected to the second input terminal of the first delay element of the other delay unit, and the output terminal of the second delay element of the other delay unit is connected to the second input terminal of the second delay element of the first delay unit.
3. The delay line circuit according to claim 1, characterized in that, The first input terminal of the first delay element of any odd-numbered delay unit in the plurality of delay units is out of phase with the first input terminal of the first delay element of any even-numbered delay unit.
4. The delay line circuit according to claim 3, characterized in that, The first input terminal of the first delay element of any odd-numbered delay unit is input with a low level, and the first input terminal of the first delay element of any even-numbered delay unit is input with a high level.
5. The delay line circuit according to claim 1, characterized in that, Each delay unit's first delay element, second delay element, and selection element respectively include a first multiplexer, a second multiplexer, and a switching device. Whether the switching device of each delay unit is turned on or off is controlled by the control signal. Each time the delay line circuit is used to adjust the delay of the clock signal, the switching device of only one of the multiple delay units is turned on.
6. The delay line circuit according to any one of claims 1 to 5, characterized in that, The adjustment unit includes an inverter, the input of which is connected to the output of the first delay element of the last delay unit, and the output of which is connected to the second input of the second delay element of the last delay unit.
7. The delay line circuit according to any one of claims 1 to 5, characterized in that, When the delay line circuit is used to delay the positive phase clock signal to obtain the first delayed clock signal, the positive phase clock signal is input to the second input terminal of the first delay element of the first delay unit, and the first delayed clock signal is the clock signal output by the output terminal of the second delay element of the first delay unit.
8. The delay line circuit according to any one of claims 1 to 5, characterized in that, When the delay line circuit is used to delay the inverted clock signal to obtain the second delayed clock signal, the inverted clock signal is inverted and then input to the second input terminal of the first delay element of the first delay unit. The second delayed clock signal is the inverted signal of the clock signal output by the output terminal of the second delay element of the first delay unit.
9. A DDR latency adjustment system, characterized in that, include: The delay line circuit according to any one of claims 1 to 8; A controller is configured to generate the control signal based on the phase difference between the clock signal and the delayed clock signal.
10. A DDR memory chip, characterized in that, include: An array of storage units for storing data; The delay line circuit according to any one of claims 1 to 8; A controller is configured to generate the control signal based on the phase difference between the clock signal and the delayed clock signal.