Multiplexed data buffer, test method thereof and electronic device

Abstract

This invention proposes a multiplexed data buffer, its testing method, and an electronic device. Upon entering the testing phase, the control module controls the m-th inverting logic device to switch its startup state, causing the m-th delay unit to switch to oscillation mode. The control module distributes target control words to each delay unit. The counting module counts the number of oscillation cycles of each delay unit within a preset time under the control of the target control word and uploads this number of oscillation cycles to the testing machine. The testing machine then determines whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit. By obtaining the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, the testing machine can determine whether the multiplexed data buffer is a defective chip with manufacturing defects in the DCDL (Distributed Data Buffer).

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a multiplexed data buffer, its testing method, and an electronic device. Background Technology

[0002] The Multiplexed Rank Data Buffer (MDB) protocol of the Double Data Rate 5 (DDR5) memory interface specifies various adjustable internal latency parameters. A common method for adjusting latency is through delay chains. In schemes employing Digital Control Delay Lines (DCDLs), this delay chain multiplexes multiple data bits, such as within MDQ0~MDQ7 of the MDB. The protocol specifies that the unit of adjustment for this latency in the registers is 1 / 64 of the duty cycle. In a common scheme, determining how many control words need to be adjusted in the delay chain to correspond to 1 / 64 of the duty cycle requires an additional Digital Delay Locked Loop (DLL) for locking.

[0003] To save power and area, a single DLL is used to obtain a unified control word (CODE) for all DCDLs, which is then decoded to control all corresponding DCDLs. This method requires that the differences between all DCDLs cannot exceed a certain value. If the difference exceeds this value, the sampling position may not be centered during eye diagram training, leading to performance degradation and indicating manufacturing defects in the DCDLs. It is necessary to screen out defective chips with such defects. Summary of the Invention

[0004] The purpose of this invention is to provide a multiplexed data buffer, its testing method, and an electronic device to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a multiplexed data buffer, the multiplexed data buffer comprising: a control module, M delay units, M inverting logic devices, and a counting module; The input of the m-th inverting logic device is connected to the output of the m-th delay unit, and the output of the m-th inverting logic device is connected to the input of the m-th delay unit, 1≤m≤M; The control module is connected to each delay unit and the counting module, and the counting module is connected to the output terminal of each delay unit; After entering the testing phase, the control module is used to control the m-th inverting logic device to switch the start-up state so that the m-th delay unit switches to oscillation mode; The control module is used to distribute target control words to each delay unit. The initial target control word is the control word corresponding to the basic detection frequency of the target delay unit, and the target delay unit is the delay unit with the shortest connection trace distance to the control module. The counting module is used to count the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and upload the number of oscillation cycles of each delay unit to the test machine, so that the test machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit.

[0006] By obtaining the number of oscillation cycles of each delay unit within a preset duration under the control of the target control word, the test machine can determine whether the multiplexed data buffer is a defective chip with manufacturing error in DCDL.

[0007] Optionally, the test machine is used to obtain the oscillation period deviation between the oscillation period number of each first type of delay unit and the oscillation period number of the target delay unit, and when any oscillation period deviation exceeds the threshold range, the multiplexed data buffer is determined to be a defective chip, wherein the first type of delay unit is the delay unit in the multiplexed data buffer other than the target delay unit.

[0008] Determining whether a multiplexed data buffer is a defective chip solely based on the oscillation period deviation does not rely on external equipment, thus reducing testing costs and ensuring the accuracy of test results.

[0009] Optionally, after the test of the current target control word is completed, if no defective product indication is received from the test machine, the control module is used to determine a new target control word, wherein the new target control word is a control word obtained by scaling or enlarging the previous target control word or the initial target control word. After determining the new target control word, the control module is used to distribute the target control word to each delay unit; The counting module is used to count the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and upload the number of oscillation cycles of each delay unit to the test machine, so that the test machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit.

[0010] By scaling or enlarging the previous target control word or the initial target control word to obtain a new target control word, and then retesting based on the new target control word, the accuracy of the final test results can be ensured.

[0011] Optionally, the counting module uses a counter, the control module is connected to the counter, and the counter is connected to the output of each delay unit; The control module is used to control the counter to count the number of oscillation cycles of the h-th delay unit, and when the single counting time reaches the preset time, control the counter to stop counting. After the counter uploads or caches the number of oscillation cycles of the h-th delay unit, control the counter to clear to zero, let h = h + 1, and repeatedly control the counter to count the number of oscillation cycles of the h-th delay unit until h > M.

[0012] Only one counter needs to be set up to count the number of oscillation cycles of each delay unit within a preset duration under the control of the target control word through time-division multiplexing, thereby reducing costs.

[0013] Secondly, embodiments of the present invention provide a method for testing multiplexed data buffers applied to a test machine, the test machine being used to test the aforementioned multiplexed data buffers, the method comprising: Obtain the number of oscillation cycles of each delay unit within a preset duration under the control of the target control word; The multiplexed data buffer is determined as a faulty chip based on the number of oscillation cycles of each delay unit.

[0014] Optionally, determining whether the multiplexed data buffer is a faulty chip based on the number of oscillation cycles of each delay unit includes: The oscillation cycle deviation between the oscillation cycle number of each first-type delay unit and the oscillation cycle number of the target delay unit is obtained. When any oscillation cycle deviation exceeds the threshold range, the multiplexed data buffer is determined to be a defective chip. The first-type delay unit is the delay unit in the multiplexed data buffer other than the target delay unit.

[0015] Thirdly, embodiments of the present invention provide an electronic device including the aforementioned multiplexed data buffer.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the architecture of a multiplexed data buffer provided in an embodiment of the present invention.

[0019] Figure 2 This is a partial connection diagram of a multiplexed data buffer provided in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the architecture of the delay unit provided in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of oscillation period counting provided in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the architecture of a multiplexed data buffer provided in an embodiment of the present invention. Figure 2 This is a partial connection diagram of a multiplexed data buffer provided in an embodiment of the present invention.

[0027] The multiplexed data buffer includes: a control module, M delay units, M inverting logic devices, and a counting module, where M is greater than or equal to 2. The inverting logic devices can be, but are not limited to, inverters.

[0028] The input of the m-th inverting logic device is connected to the output of the m-th delay unit, and the output of the m-th inverting logic device is connected to the input of the m-th delay unit, where 1 ≤ m ≤ M.

[0029] The control module is connected to each delay unit and the counting module, and the counting module is connected to the output of each delay unit.

[0030] Upon entering the testing phase, the control module controls the m-th inverting logic device to switch its startup state, and shorts the input and output terminals of the m-th delay unit to switch the m-th delay unit into oscillation mode. It should be understood that during non-testing phases, the inverting logic device is in an off state.

[0031] The control module is used to distribute target control words to each delay unit. The initial target control word is the control word corresponding to the basic detection frequency of the target delay unit. The target delay unit is the delay unit with the shortest connection trace distance to the control module (specifically, to the digital delay phase-locked loop in it).

[0032] The basic detection frequency can be, but is not limited to, the frequency corresponding to 1 / 64 of the working cycle. 1 / 64 of the working cycle is 1 / 64 tBck, where tBck is the reference clock cycle.

[0033] The counting module is used to count the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and upload the number of oscillation cycles of each delay unit to the test machine so that the test machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit.

[0034] The counting module can count the rising or falling edges of the output signal of the delay unit to determine the number of oscillation cycles corresponding to the delay unit. Alternatively, the counting module can be connected to the test machine, directly uploading the number of oscillation cycles of each delay unit to the test machine; or the test machine can be connected to the control module, with the counting module uploading the number of oscillation cycles of each delay unit to the test machine through the control module.

[0035] In the multiplexed data buffer provided in this embodiment of the invention, the number of oscillation cycles of each delay unit within a preset time under the control of the target control word is obtained so that the test machine can determine whether the multiplexed data buffer is a defective chip with manufacturing error defects in DCDL.

[0036] Please refer to Figure 3 , Figure 3This is a schematic diagram of the architecture of the delay unit provided in an embodiment of the present invention. The delay unit includes 2N logic gate arrays. The input terminal of the first logic gate array serves as the input terminal of the delay unit. The first output terminal of the i-th logic gate array is connected to the input terminal of the (i+1)-th logic gate array. The second output terminal of the i-th logic gate array is connected to the first input terminal of the (2N-i+1)-th logic gate array. The output terminal of the j-th logic gate array is connected to the second input terminal of the (j+1)-th logic gate array. 1≤i≤N-1, N≤j≤2N-1.

[0037] Optionally, the i-th logic gate array includes two NAND gates, namely a first NAND gate and a second NAND gate. The first input terminals of the first NAND gate and the second NAND gate are connected together as the input terminals of the i-th logic gate array. The second input terminals of the first NAND gate and the second NAND gate are used to receive the target control word sent by the control module. The output terminal of the first NAND gate serves as the first output terminal of the i-th logic gate array, and the output terminal of the second NAND gate serves as the second output terminal of the i-th logic gate array.

[0038] The j-th logic gate array includes a NAND gate, specifically a third NAND gate. The first terminal of the third NAND gate serves as the first input terminal of the j-th logic gate array, the second terminal of the third NAND gate serves as the second input terminal of the j-th logic gate array, and the output terminal of the third NAND gate serves as the output terminal of the j-th logic gate array.

[0039] In one optional implementation, the tester is used to obtain the number of oscillation cycles between the number of oscillation cycles of each first-type delay unit and the number of oscillation cycles of the target delay unit, and when any oscillation cycle deviation exceeds a threshold range, the multiplexed data buffer is determined to be a defective chip, wherein the first-type delay unit is the delay unit in the multiplexed data buffer other than the target delay unit.

[0040] Optionally, Nx-N0 represents the oscillation period deviation between the oscillation period number of the xth first-type delay unit and the oscillation period number of the target delay unit, where Nx represents the oscillation period number of the xth first-type delay unit and N0 represents the oscillation period number of the target delay unit.

[0041] If all oscillation cycle deviations are within the threshold range under the current target control word, it indicates that the multiplexed data buffer is qualified under the control of the target control word. It is necessary to determine whether the multiplexed data buffer is qualified under other control words.

[0042] Optionally, after the test of the current target control word is completed, if no defective product indication is received from the test machine (i.e., all oscillation cycle deviations are within the threshold range), the control module is used to determine a new target control word, wherein the new target control word is a control word obtained by scaling or enlarging the previous target control word or the initial target control word.

[0043] Optionally, by combining the scaling ratio between the target detection frequency and the basic detection frequency, the initial target control word can be scaled or enlarged to obtain a new target control word.

[0044] After determining the new target control word, the control module distributes the target control word to each delay unit.

[0045] The counting module is used to count the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and upload the number of oscillation cycles of each delay unit to the test machine so that the test machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit.

[0046] If, under the control of the target control word corresponding to all detection frequencies, all oscillation cycle deviations are within the threshold range, it indicates that the multiplexed data buffer is a good chip.

[0047] It should be noted that the different delay times achieved by the delay unit are obtained by using different logic gate paths from input to output. For example, for higher frequencies, the first path of the delay might be: 1st logic gate array → 2nd logic gate array → 3rd logic gate array → 2N-2nd logic gate array → 2N-1th logic gate array → 2Nth logic gate array. For lower frequencies, the second path of the delay might be: 1st logic gate array → 2nd logic gate array → 3rd logic gate array → 4th logic gate array → 5th logic gate array → 6th logic gate array → 2N-5th logic gate array → 2N-4th logic gate array → 2N-3th logic gate array → 2N-2nd logic gate array → 2N-1th logic gate array → 2Nth logic gate array.

[0048] Therefore, if only a specific frequency point is detected, such as a relatively low frequency, the possible scenario is that the delay of the second path of the x-th type-1 delay unit is the same as or similar to the delay of the second path of the target delay unit, and Nx-N0 (the deviation of oscillation periods between the x-th type-1 delay unit and the target delay unit) is within the threshold range. However, in reality, the delay of the first path of the x-th type-1 delay unit may deviate significantly from the delay of the first path of the target delay unit, but this deviation is filled by the remaining path in the second path. Therefore, if only a single frequency point is detected, the detection result is not accurate.

[0049] By scaling or enlarging the previous target control word or the initial target control word to obtain a new target control word, and then retesting based on the new target control word, the accuracy of the final test results can be ensured.

[0050] In one alternative implementation, the counting module employs a counter that is adjacent to the control module, i.e., the wiring distance between the two is less than a preset distance. The control module is connected to the counter, and the counter is connected to the output of each delay unit.

[0051] The control module simultaneously distributes the target control word to each delay unit. The control module controls the counter to count the number of oscillation cycles of the h-th delay unit (the initial value of h is 1). When the single counting duration reaches the preset duration, the control module stops counting. After the counter uploads or caches the number of oscillation cycles of the h-th delay unit, the control module clears the counter and sets h = h + 1. The control module repeats the counting of the number of oscillation cycles of the h-th delay unit until h > M, indicating that the number of oscillation cycles of all delay units within the preset duration under the control of the target control word has been counted.

[0052] Only one counter needs to be set up to count the number of oscillation cycles of each delay unit within a preset duration under the control of the target control word through time-division multiplexing, thereby reducing costs.

[0053] The counter can be directly uploaded to the test machine each time the oscillation cycle count of any delay unit is obtained, or it can be cached first and then uploaded to the test machine at the same time when the oscillation cycle counts of multiple delay units are obtained. There is no limitation here.

[0054] In one optional implementation, the counting module includes M counters, the m-th counter is disposed on one side of the m-th delay unit, the m-th counter is connected to the output terminal of the m-th delay unit, and all M counters are connected to the control module. The control module is used to control the m-th counter to count the number of oscillation cycles of the m-th delay unit after sending the target control word to the m-th delay unit, and to control the m-th counter to stop counting when the counting time reaches the preset time.

[0055] Alternatively, please continue to refer to Figure 1 and Figure 2 The control module includes a digital delay-locked loop (DLL), control logic circuitry, and timers. The DLL and timers are connected to the control logic circuitry, which in turn is connected to each delay unit and counter.

[0056] Digital delay phase-locked loops are used to distribute target control words to each delay unit through control logic circuits.

[0057] After the counter counts the number of oscillation cycles of the h-th delay unit, the timer is used to start timing and control the counter to count the number of oscillation cycles of the h-th delay unit; when the timing reaches the preset duration, the counter is controlled to stop counting.

[0058] The timer can directly control the counter to stop counting, or the timer can send a timing end signal to the control logic circuit to make the control logic circuit control the counter to stop counting.

[0059] Please continue to refer to this. Figure 2 Assuming the set delay of the m-th delay unit is T0 = 312.5 ps and the set delay of the m-th inverting logic device is T1 = 10 ps, ​​the ideal oscillation period corresponding to them is Tosc = 2 × (T0 + T1).

[0060] In this embodiment of the invention, the preset duration is the effective counting time of the counter, and the counting time Tc = K × tBck.

[0061] Theoretically, the number of oscillation periods N of the m-th delay unit is N = K × tBck ÷ [2 × (T0 + T1)], specifically as follows: Figure 4 As shown, Figure 4 This is a schematic diagram of an oscillation period counting method provided in an embodiment of the present invention. It should be understood that when the counter receives a high-level enable (EN), it begins counting the m-th delay unit and acquires the counting pulse.

[0062] The table below calculates the theoretical values ​​of the calculator for T0 errors of 1%, 2%, and 3%. It can be seen that a 1% error in T0 can be determined using an error threshold of 9; a 2% error can be determined using a difference threshold of 20. This method can detect manufacturing errors with a precision of 1% based on these thresholds. Although T1 time is short, manufacturing errors still exist. Considering the fluctuation of T1, it can be seen that a 5% T1 error does not affect the T0 threshold limiting the error precision to 1%.

[0063]

[0064] In one alternative implementation, the threshold range of the oscillation period deviation can be determined based on the accuracy requirement. When the accuracy requirement is 1%, the threshold range is (-18, 9), and when the accuracy requirement is 2%, the threshold range is (-38, 19).

[0065] This invention also provides a multiplexed data buffer testing method applied to a test machine. The test machine is used to test the aforementioned multiplexed data buffer. The multiplexed data buffer testing method includes: S10, obtain the number of oscillation cycles of each delay unit within a preset duration under the control of the target control word; S20 determines whether the multiplexed data buffer is a faulty chip based on the number of oscillation cycles of each delay unit.

[0066] Optionally, S20, determining whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit includes: obtaining the number of oscillation cycles between the number of oscillation cycles of each first-type delay unit and the number of oscillation cycles of the target delay unit, and determining that the multiplexed data buffer is a defective chip when any oscillation cycle deviation exceeds a threshold range, wherein the first-type delay unit is the delay unit in the multiplexed data buffer excluding the target delay unit.

[0067] This invention also provides an electronic device including the aforementioned multiplexed data buffer.

[0068] In summary, the multiplexed data buffer, its testing method, and electronic device provided by this invention, after entering the testing phase, involve a control module controlling the m-th inverting logic device to switch its startup state, thereby switching the m-th delay unit to oscillation mode; the control module distributing target control words to each delay unit; and a counting module counting the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and uploading the number of oscillation cycles of each delay unit to the testing machine, so that the testing machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit. By obtaining the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, the testing machine can determine whether the multiplexed data buffer is a defective chip with manufacturing error defects in the DCDL (Digital Channel Buffer).

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0070] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A multiplexed data buffer, characterized in that, The multiplexed data buffer includes: a control module, M delay units, M inverting logic devices, and a counting module; The input of the m-th inverting logic device is connected to the output of the m-th delay unit, and the output of the m-th inverting logic device is connected to the input of the m-th delay unit, 1≤m≤M; The control module is connected to each delay unit and the counting module, and the counting module is connected to the output terminal of each delay unit; After entering the testing phase, the control module is used to control the m-th inverting logic device to switch the start-up state so that the m-th delay unit switches to oscillation mode; The control module is used to distribute target control words to each delay unit. The initial target control word is the control word corresponding to the basic detection frequency of the target delay unit, and the target delay unit is the delay unit with the shortest connection trace distance to the control module. The counting module is used to count the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and upload the number of oscillation cycles of each delay unit to the test machine, so that the test machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit.

2. The multiplexed data buffer as described in claim 1, characterized in that, The delay unit comprises 2N logic gate arrays. The input terminal of the first logic gate array serves as the input terminal of the delay unit. The first output terminal of the i-th logic gate array is connected to the input terminal of the (i+1)-th logic gate array. The second output terminal of the i-th logic gate array is connected to the first input terminal of the (2N-i+1)-th logic gate array. The output terminal of the j-th logic gate array is connected to the second input terminal of the (j+1)-th logic gate array. 1≤i≤N-1, N≤j≤2N-1.

3. The multiplexed data buffer as described in claim 1, characterized in that, The i-th logic gate array includes two NAND gates, namely a first NAND gate and a second NAND gate. The first input terminals of the first NAND gate and the first input terminals of the second NAND gate are connected together as the input terminals of the i-th logic gate array. The second input terminals of the first NAND gate and the second NAND gate are used to receive the target control word sent by the control module. The output terminal of the first NAND gate serves as the first output terminal of the i-th logic gate array, and the output terminal of the second NAND gate serves as the second output terminal of the i-th logic gate array. The j-th logic gate array includes a NAND gate, specifically a third NAND gate. The first terminal of the third NAND gate serves as the first input terminal of the j-th logic gate array, the second terminal of the third NAND gate serves as the second input terminal of the j-th logic gate array, and the output terminal of the third NAND gate serves as the output terminal of the j-th logic gate array.

4. The multiplexed data buffer as described in claim 1, characterized in that, The test machine is used to obtain the oscillation cycle deviation between the oscillation cycle number of each first-type delay unit and the oscillation cycle number of the target delay unit, and to determine that the multiplexed data buffer is a defective chip when any oscillation cycle deviation exceeds the threshold range. The first-type delay unit is the delay unit in the multiplexed data buffer other than the target delay unit.

5. The multiplexed data buffer as described in claim 1, characterized in that, After the test of the current target control word is completed, if no defective product indication is received from the test machine, the control module is used to determine a new target control word, wherein the new target control word is a control word obtained by scaling or enlarging the previous target control word or the initial target control word. After determining the new target control word, the control module is used to distribute the target control word to each delay unit; The counting module is used to count the number of oscillation cycles of each delay unit within a preset time under the control of the target control word, and upload the number of oscillation cycles of each delay unit to the test machine, so that the test machine can determine whether the multiplexed data buffer is a defective chip based on the number of oscillation cycles of each delay unit.

6. The multiplexed data buffer as described in claim 1, characterized in that, The counting module uses a counter, the control module is connected to the counter, and the counter is connected to the output of each delay unit; The control module is used to control the counter to count the number of oscillation cycles of the h-th delay unit, and when the single counting time reaches the preset time, control the counter to stop counting. After the counter uploads or caches the number of oscillation cycles of the h-th delay unit, control the counter to clear to zero, let h = h + 1, and repeatedly control the counter to count the number of oscillation cycles of the h-th delay unit until h > M.

7. The multiplexed data buffer as described in claim 6, characterized in that, The control module includes a digital delay phase-locked loop, control logic circuitry, and a timer; The digital delay phase-locked loop is used to distribute target control words to each delay unit through the control logic circuit; After the counter counts the number of oscillation cycles of the h-th delay unit, the timer is used to start timing and control the counter to count the number of oscillation cycles of the h-th delay unit; when the timing reaches the preset duration, the counter is controlled to stop counting.

8. A test method for a multiplexed data buffer, characterized in that, Applied to a test machine, the test machine is used to test the multiplexed data buffer according to any one of claims 1-7, the method comprising: Obtain the number of oscillation cycles of each delay unit within a preset duration under the control of the target control word; The multiplexed data buffer is determined as a faulty chip based on the number of oscillation cycles of each delay unit.

9. The multiplexed data buffer test method as described in claim 8, characterized in that, The step of determining whether the multiplexed data buffer is a faulty chip based on the oscillation cycle number of each delay unit includes: The oscillation cycle deviation between the oscillation cycle number of each first-type delay unit and the oscillation cycle number of the target delay unit is obtained. When any oscillation cycle deviation exceeds the threshold range, the multiplexed data buffer is determined to be a defective chip. The first-type delay unit is the delay unit in the multiplexed data buffer other than the target delay unit.

10. An electronic device, characterized in that, Includes the multiplexed data buffer as described in any one of claims 1-7.

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