A data detection system and method

Abstract

This invention discloses a data detection system and method, belonging to the field of data storage technology. The data detection system includes: a first checksum generator, which acquires the checksum of write data sent by the front-end address buffer or the checksum of read data received as a first checksum; a second checksum generator, which acquires the checksum of write data received by the cache or the checksum of read data sent as a second checksum; a checksum comparator, with two input terminals electrically connected to the output terminals of the first and second checksum generators, which compares the first and second checksums in real time; and an error handling module, with its input terminal electrically connected to the output terminal of the checksum comparator, which executes a hardware-level error response when the first and second checksums are different. The storage device testing method disclosed in this invention allows for real-time detection of data transmission within the storage device.

Description

Technical Field

[0001] This invention belongs to the field of data storage technology, and specifically relates to a data detection system and detection method. Background Technology

[0002] In storage devices such as embedded multimedia cards, when the host writes data to the storage device, the data is first transmitted through the external input / output interface to the front-side address buffer inside the storage device controller, then transmitted through the storage device's internal high-performance bus to the high-speed cache, and finally written to the non-volatile storage medium through the internal transmission interface. When the host reads data, the data flow path is executed in reverse. Because the overall data transmission path is relatively long and involves multiple hardware modules and complex bus interactions, there is a risk of data errors during transmission due to bus contention, timing discrepancies, hardware aging, etc.

[0003] When the controller reads data from the cache and compares it with the original data to check for data consistency, this check consumes hardware resources and is a post-error check. It cannot perform real-time detection of data transmission within the storage device. Damaged data will be directly written to the storage medium, resulting in serious data pollution and system failure. Summary of the Invention

[0004] The purpose of this invention is to provide a data detection system and method that can solve the problems of not being able to detect the transmission of data inside storage devices in real time and the detection consuming hardware resources.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a data detection system, which is installed in a storage device to realize data detection between a front-end address cache and a high-speed cache. The data detection system includes: A first check value generator is set in the front-end address buffer. When data is transmitted between the front-end address buffer and the cache, it obtains the check value of the write data sent by the front-end address buffer or the check value of the read data received as the first check value. A second check value generator is set in the cache. When data is transmitted between the cache and the front-end address cache, it obtains the check value of the write data received by the cache or the check value of the read data sent by the cache as the second check value. A checksum comparator, with two input terminals electrically connected to the output terminals of the first checksum generator and the second checksum generator, compares the first checksum and the second checksum in real time; and The error handling module has its input terminal electrically connected to the output terminal of the check value comparator. When the first check value and the second check value are different, it executes a hardware-level error response.

[0006] In one embodiment of the present invention, the data detection system further includes an error message recording register, which is electrically connected to the output terminal of the error handling module. When the first check value and the second check value are different, the error handling module writes error information to the error message recording register to alarm the firmware.

[0007] In one embodiment of the present invention, the data detection system further includes a direct memory access engine retransmission register, which is electrically connected to the output of the error handling module. When the first check value and the second check value are different, the error handling module writes a control value to the direct memory access engine retransmission register to drive the direct memory access engine to perform hardware retransmission.

[0008] In one embodiment of the present invention, after the direct memory access engine performs hardware retransmission and the retransmission is successful, the error handling module clears the error information in the error message recording register.

[0009] In one embodiment of the present invention, the first check value generator and the second check value generator are cyclic redundancy check generators.

[0010] In one embodiment of the present invention, the first check value generator and the second check value generator are CRC-32 generators.

[0011] In one embodiment of the present invention, the first check value generator and the second check value generator obtain the first check value and the second check value in units of 512-byte data blocks.

[0012] In one embodiment of the present invention, the front-end address cache and the cache are connected via an advanced high-performance bus.

[0013] The present invention also provides a data detection method, which realizes data detection between the front-end address cache and the cache in a storage device, and the data detection method includes at least the following steps: When data is transmitted between the front-end address buffer and the cache, a first check value generator set in the front-end address buffer is used to obtain the check value of the write data sent by the front-end address buffer or the check value of the read data received by the front-end address buffer as the first check value. When data is transmitted between the cache and the front-end address cache, a second check value generator set in the cache is used to obtain the check value of the write data received by the cache or the read data sent by the cache as the second check value. A checksum comparator electrically connected to the outputs of the first checksum generator and the second checksum generator is used to compare the first checksum and the second checksum; and When the first check value and the second check value are different, an error handling module electrically connected to the output of the check value comparator is used to perform a hardware-level error response.

[0014] In one embodiment of the present invention, when the first check value is the same as the first check value, it is determined that the data transmission is error-free, and the write data is allowed to be transmitted to the cache or the read data is allowed to be transmitted to the front-end address cache.

[0015] In summary, the data detection system and method provided by this invention firstly, by setting a first checksum generator and a second checksum generator in the front-end address buffer and the cache, and using a checksum comparator for real-time comparison, real-time, automatic, hardware-level data consistency detection of the internal transmission path from the front-end address buffer to the cache is achieved without occupying controller resources or interrupting normal data transmission. This dual checksum verification can independently monitor the transmission process of the high-performance bus. The detection process is completely completed automatically by the hardware circuit without the need for controller intervention, fundamentally improving the shortcomings of traditional solutions such as high power consumption, poor timeliness, and lack of internal bus monitoring, and greatly reducing the probability of erroneous data being written to the cache and contaminating non-volatile storage media. Secondly, by introducing a dedicated error message recording register and a direct memory access engine retransmission register, the retransmission control logic is completely hardware-based. When data inconsistency is detected, the error handling module directly drives the direct memory access engine to retransmit, without real-time firmware intervention. This purely hardware-level direct-drive mechanism eliminates the scheduling latency, interrupt response, and context switching overhead of the software protocol stack, thereby achieving microsecond-level ultra-fast data recovery and ensuring the continuity of data transmission and the efficient operation of the system. Furthermore, after the direct memory access engine successfully retransmits and the data verification is consistent, the error handling module automatically clears the error message record register, achieving hardware-level closed-loop control. This effectively avoids redundant alarms and unnecessary exception handling overhead in the firmware, greatly improving the robustness of the system and the efficiency of software operation.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a structural block diagram of a data detection system according to an embodiment of the present invention.

[0019] Figure 2 This is a flowchart of a data detection method in one embodiment of the present invention.

[0020] Figure 3 This is a flowchart of a data detection method in one embodiment of the present invention.

[0021] Label Explanation: 100. Storage device; 110. Controller; 111. Front-end address buffer; 112. Cache; 113. First checksum generator; 114. Second checksum generator; 115. Checksum comparator; 116. Error handling module; 117. Error message logging register; 118. Direct memory access engine retransmission register; 120. Non-volatile storage medium. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0025] With the rapid development of solid-state storage technology, embedded multimedia memory cards (eMMC) and other storage devices are widely used in smartphones, tablets, automotive electronic systems, and various IoT terminal devices due to their high integration, low power consumption, and excellent read / write performance. Storage devices interact with external hosts at high speed through external input / output (IO) interfaces. In practical applications, such as in in-vehicle infotainment terminals, intelligent driving domain controllers, or high-end smartphones, storage devices serve as the medium for system booting and carrying core data; the absolute accuracy of their data transmission directly affects the security and stability of the entire system.

[0026] Please see Figure 1 As shown, the storage device 100 includes a controller 110 and a non-volatile storage medium 120, such as NAND flash memory. The controller 110 also includes a front-side address (Internet Protocol, IP) buffer 111 and a cache 112. The front-side address buffer 111 directly interfaces with the physical layer of the external input / output interface protocol and is a hardware buffer storage unit used to temporarily store write data received from an external host or read data to be sent to an external host. The front-side address buffer 111 is, for example, a static random-access memory (SRAM) or a first-in-first-out (FIFO) hardware queue. The cache 112 is located between the system bus and the interface of the non-volatile storage medium 120 and is a hardware storage unit used for sector-level or block-level caching of large amounts of data. The cache 112 is, for example, a dual-port or multi-port random access memory (RAM) array.

[0027] Please see Figure 1As shown, during the writing process to storage device 100, the external host sends the write data to storage device 100 through the input / output interface. The physical layer and protocol layer logic inside storage device 100 receive the write data and temporarily stores it in the front-side address buffer 111. Subsequently, the Direct Memory Access (DMA) engine inside storage device 100 is activated, reads the write data from the front-side address buffer 111, and transfers it to the cache 112 through the Advanced High-performance Bus (AHB) inside storage device 100. Finally, the write data in cache 112 is written to the non-volatile storage medium 120 through the NAND Flash IO interface. When reading data from storage device 100, the read data flow path is executed in reverse.

[0028] Please see Figure 1 As shown, in storage device 100, due to the long physical traces of the Advanced High Performance Bus (AHS-B) and the presence of a large amount of electromagnetic radiation, transient voltage fluctuations, and high-frequency clock jitter inside storage device 100, data is prone to bit flips or data loss during the critical intermediate link of data transmission via the AHS-B. Once a transient data error occurs during internal bus transmission, storage device 100 cannot detect and intercept it in real time, which can easily lead to dirty data being written to cache 112 or even contaminating non-volatile storage medium 120.

[0029] Please see Figure 1 As shown, this application provides a data detection system, which is installed in the storage device 100 to realize data detection between the front-end address buffer 111 and the high-speed buffer 112. Specifically, this application sets a first checksum generator 113 in the front-end address buffer 111 and a second checksum generator 114 in the high-speed buffer 112 to obtain the checksum in each buffer when data is transmitted between the front-end address buffer 111 and the high-speed buffer 112. Then, a checksum comparator 115 is used to compare the checksums in the two buffers. Without occupying the controller 110 or interrupting normal data transmission, real-time, automatic, and hardware-level detection of data consistency along the internal transmission path from the front-end address buffer 111 to the high-speed buffer 112 is achieved. At the same time, an error handling module 116 is set up to perform hardware-level error response, providing a hardware-level automatic retransmission recovery mechanism, overcoming the defects of high power consumption, poor timeliness, lack of internal bus monitoring, and high retransmission delay.

[0030] Please see Figure 1As shown, in one embodiment of the present invention, the front-end address buffer 111 in the storage device 100 can receive and temporarily store write data written from an external host or read data read from a non-volatile storage medium 120. A first checksum generator 113 is disposed in the front-end address buffer 111. When data is transmitted between the front-end address buffer 111 and the cache 112, it acquires the checksum of the write data sent by the front-end address buffer 111 or the checksum of the read data received as the first checksum. That is, when the front-end address buffer 111 outputs write data to the cache 112, or when the front-end address buffer 111 receives read data output by the cache 112, the first checksum generator 113 acquires the checksum of the write data or the checksum of the read data in real time as the first checksum. The first checksum generator 113 is electrically connected between the front-end address buffer 111 and the sideband signal channel of the high-performance bus. At this time, the first checksum generated by the first checksum generator 113 can be transmitted to the cache 112 through the sideband signal channel of the high-performance bus.

[0031] Please see Figure 1 As shown, in one embodiment of the present invention, a cache 112 in the storage device 100 is used to receive and store write data input via an Advanced High Performance Bus (AHS-B) or read data input via a NAND Flash I / O interface. A second checksum generator 114 is disposed in the cache 112. When data is transmitted between the cache 112 and the front-end address cache 111, the checksum of the write data received by the cache 112 or the checksum of the read data sent by the cache 112 is obtained as the second checksum. That is, when the cache 112 receives write data output from the front-end address cache 111, or when the cache 112 outputs read data to the front-end address cache 111, the second checksum generator 114 obtains the checksum of the write data or the checksum of the read data in real time as the second checksum. The second checksum generator 114 is electrically connected between the sideband signal channel of the AHS-B and the cache 112. At this time, the second checksum generated by the second checksum generator 114 can be transmitted to the front-end address cache 111 through the sideband signal channel of the AHS-B.

[0032] Please see Figure 1As shown, in one embodiment of the present invention, an Advanced High-Performance Bus (AHS-B) is connected between the front-end address buffer 111 and the cache 112, and between the first checksum generator 113 and the second checksum generator 114. The AHS-B includes a standard data channel and parallel sideband signal channels. The data channel is used to transmit write data output from the front-end address buffer 111 or read data output from the cache 112, and the sideband signal channels are used to transmit a first checksum obtained in real time by the first checksum generator 113 or a second checksum obtained in real time by the second checksum generator 114. This physically parallel bus architecture achieves strong synchronous transmission of data and checksums in the time domain.

[0033] Please see Figure 1 As shown, in one embodiment of the present invention, the checksum comparator 115 can be a purely hardware comparison circuit. The two input terminals of the checksum comparator 115 are electrically connected to the output terminals of the first checksum generator 113 and the second checksum generator 114. The checksum comparator 115 compares the first checksum and the second checksum in real time and outputs the comparison result as a level signal. When the first checksum and the second checksum are the same, the checksum comparator 115 outputs a low-level signal, for example. When the first checksum and the second checksum are different, the checksum comparator 115 outputs a high-level signal, for example.

[0034] Please see Figure 1 As shown, in one embodiment of the present invention, the input terminal of the error handling module 116 is electrically connected to the output terminal of the check value comparator 115. When the first check value and the second check value are different, a hardware-level error response is executed. The error handling module 116 can be composed of a purely hardware state mechanism. The error handling module 116 can respond within a very short time when it detects a high-level signal output by the check value comparator 115, thereby avoiding delays caused by software interruptions.

[0035] Please see Figure 1 As shown, in one embodiment of the present invention, an error message recording register 117 and a direct memory access engine retransmission register 118 are electrically connected to the output of the error handling module 116, which can improve the timeliness of error response and realize fast recovery without firmware intervention.

[0036] Please see Figure 1As shown, in one embodiment of the present invention, the error message recording register 117 is electrically connected to the output terminal of the error handling module 116. When the first checksum and the second checksum are different, the error handling module 116 writes error information to the error message recording register 117 to alarm the firmware. The output terminal of the error message recording register 117 is electrically connected to the interrupt control line of the controller 110 in the storage device 100, and is used to provide asynchronous alarms to the firmware so that the firmware records bus transmission error logs in the background without requiring real-time intervention in the current error correction process.

[0037] Please see Figure 1 As shown, in one embodiment of the present invention, the Direct Memory Access Engine (DME) retransmission register 118 is electrically connected to the output of the error handling module 116. When the first checksum and the second checksum are different, the error handling module 116 writes a control value to the DME retransmission register 118 to drive the DME engine to perform hardware retransmission. The control value written by the error handling module 116 to the DME retransmission register 118 is, for example, 1, which is the retransmission enable bit of the DME retransmission register 118. The output of the DME retransmission register 118 is directly electrically connected to the hardware trigger input of the DME engine inside the controller 110 in the storage device 100. When the DME retransmission register 118 is set, it outputs a high-level signal to directly drive the DME engine to perform a hardware-level retransmission operation, rereading the corresponding data block from the front-end address buffer 111 and re-initiating the high-performance bus transmission.

[0038] Please see Figure 1 As shown, in one embodiment of the present invention, after the direct memory access engine performs a hardware retransmission and the retransmission is successful, the error handling module 116 clears the error information in the error message recording register 117. That is, after the direct memory access engine performs a hardware retransmission and the retransmission is successful, the error handling module 116 automatically sends a clear signal to the error message recording register 117, automatically clearing the error message recording register 117 to restore its initial state. Since the error message recording register 117 is automatically cleared after a successful retransmission, the firmware will not detect any residual error states when subsequently reading the error message recording register 117, thereby effectively avoiding redundant alarms and unnecessary exception handling overhead, greatly improving the robustness of the system and the efficiency of software operation.

[0039] Please see Figure 1As shown, in one embodiment of the present invention, the first check value generator 113 and the second check value generator 114 are cyclic redundancy check (CRC) generators. Compared with parity check and error correcting code (ECC) checks, using CRC to generate the first and second check values ​​simplifies the hardware. In other embodiments, the first check value generator 113 and the second check value generator 114 can also be selected from check value generators such as parity check generators or error correcting code check generators.

[0040] Please see Figure 1 As shown, in one embodiment of the present invention, the first check value generator 113 and the second check value generator 114 are CRC-32 generators, which can fully match the 32-bit or 64-bit data width of the high-performance bus, so that the first check value generator 113 and the second check value generator 114 can complete the calculation of the cyclic redundancy check value of the input / output data block in a single clock cycle without introducing additional transmission delay.

[0041] Please see Figure 1 As shown, in one embodiment of the present invention, the first checksum generator 113 and the second checksum generator 114 obtain the first checksum and the second checksum in units of 512-byte data blocks. In the storage device 100, after the first checksum generator 113 calculates the first checksum in a single clock cycle, the first checksum is used as a sideband signal and transmitted synchronously with the corresponding 512-byte data in the same high-performance bus cycle. At this time, the absolute alignment of the checksum data and the business data in the time domain can be ensured, avoiding timing deviations caused by bus multiplexing or asynchronous transmission, thereby preventing misjudgments caused by timing misalignment and achieving strong synchronization between data and checksum under high-bandwidth transmission. At the same time, by introducing a 512-byte block fine-grained detection mechanism, any bus transmission error can be accurately locked onto a specific 512-byte data block, which not only greatly improves the timeliness and accuracy of error location, but also significantly reduces the amount of data retransmitted by hardware, avoiding unnecessary waste of bus bandwidth.

[0042] Please see Figure 1As shown, in one embodiment of the present invention, the Direct Memory Access Engine (DME) within the storage device 100 is used as the direct hardware execution entity for data transfer. When the error handling module 116 detects data inconsistency and writes a specific control value to the DME retransmission register 118, the output signal of the DME retransmission register 118 is directly connected to the start control terminal of the DME as a hardware trigger source. After detecting the hardware trigger signal, the DME is directly woken up at the hardware level without going through the interrupt handler of the controller 110 or any real-time intervention from the firmware, and automatically resets its read / write pointers. It then rereads the currently erroneous 512-byte data block from the front-end address buffer 111 and re-initiates the high-performance bus transmission. This pure hardware-level direct drive mechanism eliminates the scheduling delay of the software protocol stack and enables microsecond-level ultra-fast data recovery.

[0043] Please see Figure 2 As shown, the present invention also provides a data detection method, which realizes data detection between the front-end address cache 111 and the cache 112 in the storage device 100, and the data detection method includes the following steps S101 to S105.

[0044] Step S101: When data is transmitted between the front-end address buffer and the cache, the first check value generator set in the front-end address buffer is used to obtain the check value of the write data sent by the front-end address buffer or the check value of the read data received as the first check value.

[0045] Step S102: When data is transmitted between the cache and the front-end address cache, the second check value generator set in the cache is used to obtain the check value of the write data received by the cache or the read data sent by the cache as the second check value.

[0046] Step S103: Use a check value comparator electrically connected to the output of the first check value generator and the output of the second check value generator to compare the first check value and the second check value.

[0047] Step S104: When the first check value and the second check value are different, use the error handling module electrically connected to the output of the check value comparator to execute a hardware-level error response.

[0048] Step S105: If the first check value and the second check value are the same, the data transmission is determined to be error-free, and write data is allowed to be transmitted to the cache or read data is allowed to be transmitted to the front-end address cache.

[0049] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, when the first check value and the second check value are different, the data detection method includes: using the error handling module 116 to write the error message into a specific error message recording register 117 to send an asynchronous alarm signal to the firmware, so that the system background can record the bus transmission error log.

[0050] Please see Figure 2 As shown, in one embodiment of the present invention, when the first check value and the second check value are different, the data detection method includes: the error handling module 116 controls the direct memory access engine of the storage device 100 to reread the data block from the front-end address cache 111 and retransmit it through the high-performance bus by writing a control value to the direct memory access engine retransmission register 118. Furthermore, when the retransmitted data is incorrect, the retransmission process is repeatedly executed until the correct data is transmitted to the cache 112.

[0051] Please see Figure 2 As shown, in one embodiment of the present invention, when the first check value and the second check value are different, the data detection method includes: after the data retransmission is successful, the error handling module 116 automatically sends a clear signal to the error message recording register 117 to automatically clear the error message in the error message recording register 117, so that the storage device 100 is restored to normal working state.

[0052] Please see Figure 2 As shown, the data detection method provided in this application has a complete closed-loop control process of alarm, retransmission, and reset. The entire retransmission and recovery process is completely controlled and executed autonomously by the hardware state machine without any intervention from the software protocol stack, thus ensuring ultra-high timeliness of error response at the method level and minimizing the impact of bus transient interference on the overall system throughput.

[0053] Please see Figure 3 As shown, in one embodiment of the present invention, the detection of write data is described by taking the writing of write data to flash memory as an example. At this time, the data detection method includes steps S201 to S208.

[0054] Step S201: The storage device receives write data sent by the external host and stores the write data in the front-end address cache.

[0055] Please see Figure 1 and Figure 3 As shown, in one embodiment of the present invention, the storage device 100 receives write data sent by an external host through an input / output interface protocol and stores the write data in the front-end address buffer 111. The front-end address buffer 111 serves as the first station for data flowing into the device and can temporarily buffer high-speed input data.

[0056] Step S202: Output the write data in the front-end address buffer through the direct memory access engine, and use the first check value generator set in the front-end address buffer to obtain the check value of the write data sent by the front-end address buffer as the first check value.

[0057] Step S203: The write data and the first check value are transmitted to the cache via the high-performance bus through the direct memory access engine, and the second check value generator set in the cache is used to obtain the check value of the write data received by the cache as the second check value.

[0058] In this process, the written data and the first check value can be transmitted synchronously and at the same frequency on the advanced high-performance bus.

[0059] Step S204: Use a check value comparator electrically connected to the output of the first check value generator and the output of the second check value generator to compare the first check value and the second check value.

[0060] Step S205: When the first check value and the second check value are different, use the error handling module electrically connected to the output of the check value comparator to execute a hardware-level error response.

[0061] Step S206: When the first check value and the second check value are the same, it is determined that the data transmission is error-free and the write data is allowed to be transmitted to the cache.

[0062] Please see Figure 1 As shown, in another embodiment of the present invention, the detection of write data is explained using the example of reading read data from flash memory. First, the storage device 100 reads read data from flash memory and temporarily stores it in cache 112. Next, when read data is output from cache 112 via the Direct Memory Access Engine, a second checksum generator 114 provided in cache 112 is used to obtain the checksum of the read data sent by cache 112 as the second checksum. When the read data and the second checksum are transmitted to front-end address cache 111 via the High-Performance Bus via the Direct Memory Access Engine, a first checksum generator 113 provided in front-end address cache 111 is used to obtain the checksum of the read data received by front-end address cache 111 as the first checksum. Finally, a checksum comparator 115 electrically connected to the output of the first checksum generator 113 and the output of the second checksum generator 114 is used to compare the first checksum and the second checksum. When the first checksum and the second checksum are different, the error handling module 116, which is electrically connected to the output of the checksum comparator 115, performs a hardware-level error response. When the first checksum and the second checksum are the same, the data transmission is determined to be error-free, and the read data is allowed to be passed to the front-end address buffer 111.

[0063] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A data detection system, characterized in that, The data detection system is installed in the storage device to realize data detection between the front-end address cache and the high-speed cache. The data detection system includes: A first check value generator is set in the front-end address buffer. When data is transmitted between the front-end address buffer and the cache, it obtains the check value of the write data sent by the front-end address buffer or the check value of the read data received as the first check value. A second check value generator is set in the cache. When data is transmitted between the cache and the front-end address cache, it obtains the check value of the write data received by the cache or the check value of the read data sent by the cache as the second check value. A checksum comparator, with two input terminals electrically connected to the output terminals of the first checksum generator and the second checksum generator, compares the first checksum and the second checksum in real time; and The error handling module has its input terminal electrically connected to the output terminal of the check value comparator. When the first check value and the second check value are different, it executes a hardware-level error response.

2. The data detection system according to claim 1, characterized in that, The data detection system also includes an error message recording register, which is electrically connected to the output of the error handling module. When the first check value and the second check value are different, the error handling module writes error information to the error message recording register to alarm the firmware.

3. The data detection system according to claim 2, characterized in that, The data detection system also includes a direct memory access engine retransmission register, which is electrically connected to the output of the error handling module. When the first check value and the second check value are different, the error handling module writes a control value to the direct memory access engine retransmission register to drive the direct memory access engine to perform hardware retransmission.

4. The data detection system according to claim 3, characterized in that, After the direct memory access engine performs a hardware retransmission and the retransmission is successful, the error handling module clears the error information in the error message recording register.

5. The data detection system according to claim 1, characterized in that, The first check value generator and the second check value generator are cyclic redundancy check generators.

6. The data detection system according to claim 1, characterized in that, The first check value generator and the second check value generator are CRC-32 generators.

7. The data detection system according to claim 1, characterized in that, The first check value generator and the second check value generator obtain the first check value and the second check value in 512-byte data blocks.

8. The data detection system according to claim 1, characterized in that, The front-end address cache and the cache are connected via an advanced high-performance bus.

9. A data detection method, characterized in that, The data detection method enables data detection between the front-end address cache and the cache in the storage device, and the data detection method includes at least the following steps: When data is transmitted between the front-end address buffer and the cache, a first check value generator set in the front-end address buffer is used to obtain the check value of the write data sent by the front-end address buffer or the check value of the read data received by the front-end address buffer as the first check value. When data is transmitted between the cache and the front-end address cache, a second check value generator set in the cache is used to obtain the check value of the write data received by the cache or the read data sent by the cache as the second check value. A checksum comparator electrically connected to the outputs of the first checksum generator and the second checksum generator is used to compare the first checksum and the second checksum; and When the first check value and the second check value are different, an error handling module electrically connected to the output of the check value comparator is used to perform a hardware-level error response.

10. The data detection method according to claim 9, characterized in that, If the first check value is the same as the first check value, the data transmission is determined to be error-free, and the write data is allowed to be transmitted to the cache or the read data is allowed to be transmitted to the front-end address cache.

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