Duty cycle measurement circuit, duty cycle measurement method, processor and electronic device

Abstract

This disclosure relates to the field of integrated circuits, and proposes a duty cycle measurement circuit, a duty cycle measurement method, a processor, and an electronic device. The circuit's signal generation module generates first and second adjustment signals based on a first input signal. When the first input signal is a burst data signal, the starting points of the i-th effective time period of the first and second adjustment signals are the same, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal. A voltage detection module detects the duty cycle of the first and second adjustment signals, converting the duty cycle into two voltage signals, which are then input to a comparison module. The comparison module compares the two voltage signals, and the comparison result indicates whether the duty cycle of the first input signal exceeds a threshold. This circuit can be used to measure the duty cycle of burst data signals, and can promptly correct errors in the duty cycle of burst data signals, improving the data transmission performance of DDR.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a duty cycle measurement circuit, a duty cycle measurement method, a processor, and an electronic device. Background Technology

[0002] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) / Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM) refers to the memory in electronic devices (mobile phones, tablets, computers, etc.). These devices typically also include a memory controller to support DDR data transfer protocols (such as DDR5 / LPDDR5).

[0003] The memory controller includes two transmission paths: one for transmitting the clock signal and the other for transmitting the data strobe signal (DQS). DDR data transmission is highly sensitive to the clock signal's duty cycle; the quality of the clock signal's duty cycle significantly impacts DDR data transmission performance. Therefore, most memory controllers incorporate a duty cycle corrector (DCC) on the clock signal's transmission path to correct the clock signal's duty cycle. However, errors in the DQS duty cycle can also affect DDR data transmission performance. Current DCCs are typically designed specifically for correcting the clock signal's duty cycle. Since DQS is a burst data signal, and the waveforms of the clock signal and the burst data signal differ, current DCCs cannot measure the duty cycle of the burst data signal and thus cannot correct it in a timely manner, leading to reduced DDR data transmission performance. Summary of the Invention

[0004] In view of this, this disclosure proposes a duty cycle measurement circuit, a duty cycle measurement method, a processor, and an electronic device. The duty cycle measurement circuit of this disclosure can be used to measure the duty cycle of burst data signals, and can correct errors in the duty cycle of burst data signals in a timely manner, thereby improving the data transmission performance of DDR.

[0005] According to one aspect of this disclosure, a duty cycle measurement circuit is provided. The circuit includes a signal generation module, a voltage detection module, and a comparison module. The signal generation module is used to generate a first adjustment signal and a second adjustment signal based on a first input signal. When the first input signal is a burst data signal, the waveform of the i-th effective time period of the first adjustment signal is opposite to the waveform of the i-th effective time period of the second adjustment signal. The starting point of the i-th effective time period of the first adjustment signal and the starting point of the i-th effective time period of the second adjustment signal are the same, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal, where i is a positive integer. The voltage detection module is used to detect the duty cycle of the first adjustment signal and the second adjustment signal, and convert the duty cycle into two voltage signals which are input to the comparison module. The comparison module is used to compare the two voltage signals from the voltage detection module and output a comparison result, the comparison result indicating whether the duty cycle of the first input signal exceeds a preset threshold.

[0006] In one possible implementation, the circuit is located in a memory controller that supports the DDR protocol; the memory controller includes a first path, a second path, and a third path, the endpoint of the first path being the starting point of the second path and the third path; the first path transmits a clock signal and the burst data signal, the second path transmits the clock signal, and the third path transmits the burst data signal; the circuit is located on the first path, and the first input signal is either the clock signal or the burst data signal.

[0007] In one possible implementation, the signal generation module includes a first inverter, a signal generation submodule, a first switching submodule, and a second switching submodule. The first inverter is used to obtain a second input signal based on the first input signal, wherein the second input signal has a waveform opposite to the first input signal. The signal generation submodule is used to, when the first input signal is a burst data signal, remove the data carried by the first input signal in the first clock cycle of each valid time period to obtain a first output signal; and remove the data carried by the second input signal in the first clock cycle of each valid time period to obtain a second output signal. The first switching submodule is used to, when the first input signal is a clock signal, use the first input signal as the first adjustment signal; and when the first input signal is the burst data signal, use the first output signal as the first adjustment signal. The second switching submodule is used to, when the first input signal is a clock signal, use the second input signal as the second adjustment signal; and when the first input signal is the burst data signal, use the second output signal as the second adjustment signal.

[0008] In one possible implementation, the signal generation submodule includes a reset signal generation unit, a first AND gate, and a second AND gate. The reset signal generation unit is used to generate a first reset signal and a second reset signal that are active high based on the first input signal. The start point of the i-th effective time period of the first reset signal is one clock cycle later than the start point of the i-th effective time period of the first input signal, and the end point of the i-th effective time period of the first reset signal is the same as the end point of the i-th effective time period of the first input signal. The start point of the i-th effective time period of the second reset signal is the same as the start point of the i-th effective time period of the first input signal, and the end point of the i-th effective time period of the second reset signal is one clock cycle later than the end point of the i-th effective time period of the first input signal. The first AND gate is used to perform an AND operation on the first reset signal and the first input signal to output the first output signal. The second AND gate is used to perform an AND operation on the second reset signal and the second input signal to output the second output signal.

[0009] In one possible implementation, the reset signal generating unit includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, an XOR gate, a NAND gate, and a second inverter. The reset terminal of the first flip-flop receives the first reset signal, the control terminal of the first flip-flop receives the first input signal, the data input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, and the non-inverted output terminal of the first flip-flop is connected to the first input terminal of the XOR gate and the first input terminal of the NAND gate. The reset terminal of the second flip-flop receives the first reset signal, the control terminal of the second flip-flop receives the first input signal, the data input terminal of the second flip-flop is connected to the output terminal of the XOR gate, and the non-inverted output terminal of the second flip-flop is connected to the second input terminal of the XOR gate, the second input terminal of the NAND gate, and the input terminal of the second inverter. The control terminal of the third flip-flop receives the second input signal, the data input terminal of the third flip-flop is connected to the output terminal of the NAND gate, and the non-inverted output terminal of the third flip-flop outputs the first reset signal. The control terminal of the fourth flip-flop receives the first input signal, the data input terminal of the fourth flip-flop is connected to the output terminal of the second inverter, and the non-inverted output terminal of the fourth flip-flop outputs the second reset signal.

[0010] According to another aspect of this disclosure, a duty cycle measurement method is provided, the method comprising: a signal generation module generating a first adjustment signal and a second adjustment signal based on a first input signal; wherein, when the first input signal is a burst data signal, the waveform of the i-th effective time period of the first adjustment signal is opposite to the waveform of the i-th effective time period of the second adjustment signal; the starting point of the i-th effective time period of the first adjustment signal and the starting point of the i-th effective time period of the second adjustment signal are the same, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal, where i is a positive integer; a voltage detection module detecting the duty cycle of the first adjustment signal and the second adjustment signal, converting the duty cycle into two voltage signals and inputting them to a comparison module; the comparison module comparing the two voltage signals from the voltage detection module and outputting a comparison result, the comparison result indicating whether the duty cycle of the first input signal exceeds a preset threshold.

[0011] In one possible implementation, the circuit is located in a memory controller that supports the DDR protocol; the memory controller includes a first path, a second path, and a third path, the endpoint of the first path being the starting point of the second path and the third path; the first path transmits a clock signal and the burst data signal, the second path transmits the clock signal, and the third path transmits the burst data signal; the circuit is located on the first path, and the first input signal is either the clock signal or the burst data signal.

[0012] In one possible implementation, the signal generation module includes a first inverter, a signal generation submodule, a first switching submodule, and a second switching submodule. The step of generating a first adjustment signal and a second adjustment signal based on a first input signal includes: the first inverter obtaining a second input signal based on the first input signal, the second input signal having a waveform opposite to the first input signal; the signal generation submodule, when the first input signal is a burst data signal, removing the data carried by the first input signal in the first clock cycle of each valid time period to obtain a first output signal; and removing the data carried by the second input signal in the first clock cycle of each valid time period to obtain a second output signal; the first switching submodule, when the first input signal is a clock signal, using the first input signal as the first adjustment signal; and when the first input signal is the burst data signal, using the first output signal as the first adjustment signal; the second switching submodule, when the first input signal is a clock signal, using the second input signal as the second adjustment signal; and when the first input signal is the burst data signal, using the second output signal as the second adjustment signal.

[0013] In one possible implementation, the signal generation submodule includes a reset signal generation unit, a first AND gate, and a second AND gate. The step of removing data carried by the first input signal in the first clock cycle of each valid time period to obtain a first output signal includes: the reset signal generation unit generating a first reset signal based on the first input signal, wherein the start point of the i-th valid time period of the first reset signal is one clock cycle later than the start point of the i-th valid time period of the first input signal, and the end point of the i-th valid time period of the first reset signal is the same as the end point of the i-th valid time period of the first input signal; the first AND gate performing an AND operation on the first reset signal and the first input signal to output the first output signal. The step of removing data carried by the second input signal in the first clock cycle of each valid time period to obtain a second output signal includes: the reset signal generation unit generating a second reset signal based on the first input signal, wherein the start point of the i-th valid time period of the second reset signal is the same as the start point of the i-th valid time period of the first input signal, and the end point of the i-th valid time period of the first reset signal is one clock cycle later than the end point of the i-th valid time period of the first input signal; the second AND gate performing an AND operation on the second reset signal and the second input signal to output the second output signal.

[0014] In one possible implementation, the reset signal generating unit includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, an XOR gate, a NAND gate, and a second inverter. The reset terminal of the first flip-flop receives the first reset signal, the control terminal of the first flip-flop receives the first input signal, the data input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, and the non-inverted output terminal of the first flip-flop is connected to the first input terminal of the XOR gate and the first input terminal of the NAND gate. The reset terminal of the second flip-flop receives the first reset signal, the control terminal of the second flip-flop receives the first input signal, the data input terminal of the second flip-flop is connected to the output terminal of the XOR gate, and the non-inverted output terminal of the second flip-flop is connected to the second input terminal of the XOR gate, the second input terminal of the NAND gate, and the input terminal of the second inverter. The control terminal of the third flip-flop receives the second input signal, the data input terminal of the third flip-flop is connected to the output terminal of the NAND gate, and the non-inverted output terminal of the third flip-flop outputs the first reset signal. The control terminal of the fourth flip-flop receives the first input signal, the data input terminal of the fourth flip-flop is connected to the output terminal of the second inverter, and the non-inverted output terminal of the fourth flip-flop outputs the second reset signal.

[0015] According to another aspect of this disclosure, a processor is provided, including the duty cycle measurement circuit described in any of the above claims.

[0016] According to another aspect of this disclosure, an electronic device is provided, including the processor described above.

[0017] The duty cycle measurement circuit according to an embodiment of this disclosure includes a signal generation module, a voltage detection module, and a comparison module. The signal generation module is used to generate a first adjustment signal and a second adjustment signal based on a first input signal. When the first input signal is a burst data signal, the waveform of the i-th effective time period of the first adjustment signal is opposite to the waveform of the i-th effective time period of the second adjustment signal. The starting point of the i-th effective time period of the first adjustment signal and the starting point of the i-th effective time period of the second adjustment signal are the same, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal, where i is a positive integer. The voltage detection module is used to detect the duty cycle of the first adjustment signal and the second adjustment signal, and convert the duty cycle into two voltage signals which are input to the comparison module. The comparison module is used to compare the two voltage signals from the voltage detection module and output a comparison result, the comparison result indicating whether the duty cycle of the first input signal exceeds a preset threshold. Since the starting point of the i-th effective time period of the first adjustment signal and the starting point of the i-th effective time period of the second adjustment signal are the same when the first input signal is a burst data signal, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal, this ensures that when the first input signal is in an invalid time period, the first adjustment signal and the second adjustment signal are also in invalid time periods, and the voltage of the input comparison module remains unchanged without charging / discharging. When the effective time period of the first input signal arrives, the effective time periods of the first adjustment signal and the second adjustment signal also arrive after one clock cycle, ensuring that the voltage of the input comparison module can charge / discharge normally. Therefore, the duty cycle measurement circuit can support the duty cycle measurement of burst data signals. The duty cycle measurement circuit of this embodiment can be used to measure the duty cycle of burst data signals, and can correct errors in the duty cycle of burst data signals in a timely manner, improving the data transmission performance of DDR.

[0018] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0020] Figure 1 An exemplary application scenario of a duty cycle measurement circuit according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic diagram showing the waveforms of a clock signal and a burst data signal according to an embodiment of the present disclosure is provided.

[0022] Figure 3 A schematic diagram showing the structure of a duty cycle measurement circuit according to an embodiment of the present disclosure is provided.

[0023] Figure 4 A schematic diagram showing the waveforms of a first adjustment signal, a second adjustment signal, and a first input signal according to an embodiment of the present disclosure is provided.

[0024] Figure 5 A schematic diagram showing the structure of a voltage detection module and a comparison module according to an embodiment of the present disclosure is provided.

[0025] Figure 6 A schematic diagram showing the location of the duty cycle measurement circuit in the memory controller according to an embodiment of the present disclosure.

[0026] Figure 7 A schematic diagram showing the structure of a signal generation module according to an embodiment of the present disclosure is provided.

[0027] Figure 8 A schematic diagram showing the waveforms of a first output signal, a second output signal, a first input signal, and a second input signal according to an embodiment of the present disclosure.

[0028] Figure 9 A schematic diagram showing the structure of a signal generation submodule according to an embodiment of the present disclosure is provided.

[0029] Figure 10 A schematic diagram showing the waveforms of the first reset signal and the second reset signal according to an embodiment of the present disclosure is provided.

[0030] Figure 11 A schematic diagram showing the structure of a reset signal generation unit according to an embodiment of the present disclosure is provided.

[0031] Figure 12 A schematic diagram illustrating the flow of a duty cycle measurement method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0032] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0033] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0034] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0035] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0036] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0037] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0038] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0039] Figure 1 An exemplary application scenario of a duty cycle measurement circuit according to an embodiment of the present disclosure is shown.

[0040] like Figure 1 As shown, the electronic device may include a processor, wherein the processor further includes memory and a memory controller. Duty cycle measurement circuitry may be disposed on the memory controller.

[0041] The duty cycle measurement circuit can be used to measure whether the duty cycle of the first input signal exceeds a preset threshold. Based on the measurement result, the duty cycle of the first input signal can be corrected. The memory controller can then control the memory read / write process based on the corrected first input signal.

[0042] The first input signal can be either a clock signal or a burst data signal. The clock signal pulses are continuous, while the burst data signal pulses are intermittent. Figure 2 A schematic diagram showing the waveforms of a clock signal and a burst data signal according to an embodiment of the present disclosure is provided.

[0043] like Figure 2 As shown, a clock signal is a signal that includes only one valid time period and excludes invalid time periods. Within the valid time period, the clock signal consists of continuous pulses. A burst data signal is a signal that includes multiple valid time periods and multiple invalid time periods, with an invalid time period between every two valid time periods. Within the valid time period, the burst data signal carries data, therefore it consists of continuous pulses; within the invalid time period, the burst data signal does not carry data, therefore it has no pulses and remains at a low level.

[0044] Figure 3 A schematic diagram showing the structure of a duty cycle measurement circuit according to an embodiment of the present disclosure is provided.

[0045] like Figure 3 As shown, in one possible implementation, the duty cycle measurement circuit includes a signal generation module, a voltage detection module, and a comparison module.

[0046] The signal generation module is used to generate a first adjustment signal UP and a second adjustment signal DN based on the first input signal IN. When the first input signal IN is a burst data signal, the waveform of the i-th effective time period of the first adjustment signal UP is opposite to the waveform of the i-th effective time period of the second adjustment signal DN. The starting point of the i-th effective time period of the first adjustment signal UP is the same as the starting point of the i-th effective time period of the second adjustment signal DN, and is one clock cycle later than the starting point of the i-th effective time period of the first input signal IN, where i is a positive integer.

[0047] The voltage detection module is used to detect the duty cycle of the first adjustment signal UP and the second adjustment signal DN, and convert them into two voltage signals VCN1 and VCN2 based on the duty cycle, which are then input into the comparison module.

[0048] The comparison module is used to compare two voltage signals VCN1 and VCN2 from the voltage detection module and output the comparison result DCM_OUT. The comparison result DCM_OUT indicates whether the duty cycle of the first input signal IN exceeds a preset threshold.

[0049] For example, the signal generation module receives a first input signal IN, which can be a burst data signal.

[0050] The signal generation module shapes the first input signal IN to obtain a first adjustment signal UP and a second adjustment signal DN. When the first input signal IN is a burst data signal, the number of effective time periods for the first adjustment signal UP and the second adjustment signal DN are equal, and also equal to the number of effective time periods for the first input signal IN. The i-th effective time period of the first input signal IN, the i-th effective time period of the second adjustment signal DN, and the i-th effective time period of the first adjustment signal UP correspond to each other.

[0051] Figure 4 A schematic diagram showing the waveforms of a first adjustment signal, a second adjustment signal, and a first input signal according to an embodiment of the present disclosure is provided.

[0052] exist Figure 4 In the example, the first input signal IN is a burst data signal. The first input signal IN, the first adjustment signal UP, and the second adjustment signal DN each include three valid time periods. The starting point of the i-th (i=1,2,3) valid time period of the first adjustment signal UP is the same as the starting point of the i-th valid time period of the second adjustment signal DN, and is one clock cycle later than the starting point of the i-th valid time period of the first input signal IN. The waveform of the i-th valid time period of the first adjustment signal UP is opposite to the waveform of the i-th valid time period of the second adjustment signal DN.

[0053] The waveform of the second adjustment signal during the i-th effective time period is consistent with the waveform of the first input signal during the i-th effective time period after removing the first clock cycle. In this case, the measured duty cycles of the first and second adjustment signals are consistent with the duty cycle of the first input signal during the effective time period.

[0054] This disclosure does not limit the specific structure of the signal generation module, as long as the signal generation module can generate the first adjustment signal and the second adjustment signal as described above based on the burst data signal. Exemplary structures of the signal generation module can be found below. Figure 7 Related descriptions.

[0055] The first and second adjustment signals are input to the voltage detection module. The voltage detection module detects the duty cycle of the first and second adjustment signals, converting the measured duty cycle into two voltage signals through charging / discharging, which are then input to the comparison module. The comparison module compares the voltages from the voltage detection module and outputs a comparison result indicating whether the duty cycle of the first input signal exceeds a preset threshold. This preset threshold can be 50%.

[0056] Since the first input signal is a burst data signal, the start point of the i-th effective time period of the first adjustment signal and the start point of the i-th effective time period of the second adjustment signal are the same, and are one clock cycle later than the start point of the i-th effective time period of the first input signal. This ensures that when the first input signal is in an invalid time period, both the first and second adjustment signals are also in invalid time periods, and the voltage of the input comparison module remains unchanged. When the effective time period of the first input signal arrives, the effective time periods of the first and second adjustment signals also arrive after one clock cycle, ensuring that the voltage signal of the input comparison module charges / discharges normally. Therefore, the duty cycle measurement circuit can support the duty cycle measurement of burst data signals.

[0057] The voltage detection module and the comparison module can be implemented based on existing technologies. The specific structure of the voltage detection module and the comparison module is not limited in the embodiments disclosed herein. Figure 5 A schematic diagram showing the structure of a voltage detection module and a comparison module according to an embodiment of the present disclosure is provided.

[0058] like Figure 5 As shown, the voltage detection module may include a first charge pump CP1 and a second charge pump CP2. The comparison module may include a comparator COMP. The non-inverting input of the comparator is connected to the first charge pump, and the inverting input is connected to the second charge pump.

[0059] The first charge pump and the second charge pump have the same structure. The first charge pump receives a first adjustment signal UP through a first input terminal A and a second adjustment signal DN through a second input terminal B. The second charge pump receives the second adjustment signal DN through a first input terminal A and the first adjustment signal UP through a second input terminal B.

[0060] The first charge pump charges and outputs a high-level voltage signal VCN1 to the comparator when the first adjustment signal level is higher than the second adjustment signal level; and discharges and outputs a low-level voltage signal VCN1 to the comparator when the first adjustment signal level is lower than or equal to the second adjustment signal level. The second charge pump discharges and outputs a low-level voltage signal VCN2 to the comparator when the first adjustment signal level is higher than the second adjustment signal level; and charges and outputs a high-level voltage signal VCN2 to the comparator when the first adjustment signal level is lower than or equal to the second adjustment signal level. In this case, a COMP output of 1 indicates that the duty cycle of the first input signal is greater than 50%, and a COMP output of 0 indicates that the duty cycle of the first input signal is less than 50%.

[0061] The first charge pump, the second charge pump, and the comparator are all commonly used circuit structures in the prior art. The details of how the first charge pump, the second charge pump, and the comparator achieve the above functions will not be elaborated here.

[0062] The duty cycle measurement circuit according to an embodiment of this disclosure includes a signal generation module, a voltage detection module, and a comparison module. The signal generation module is used to generate a first adjustment signal and a second adjustment signal based on a first input signal. When the first input signal is a burst data signal, the waveform of the i-th effective time period of the first adjustment signal is opposite to the waveform of the i-th effective time period of the second adjustment signal. The starting point of the i-th effective time period of the first adjustment signal and the starting point of the i-th effective time period of the second adjustment signal are the same, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal, where i is a positive integer. The voltage detection module is used to detect the duty cycle of the first adjustment signal and the second adjustment signal, and convert the duty cycle into two voltage signals which are input to the comparison module. The comparison module is used to compare the two voltage signals from the voltage detection module and output a comparison result, the comparison result indicating whether the duty cycle of the first input signal exceeds a preset threshold. Since the starting point of the i-th effective time period of the first adjustment signal and the starting point of the i-th effective time period of the second adjustment signal are the same when the first input signal is a burst data signal, and are one clock cycle later than the starting point of the i-th effective time period of the first input signal, this ensures that when the first input signal is in an invalid time period, the first adjustment signal and the second adjustment signal are also in invalid time periods, and the voltage of the input comparison module remains unchanged without charging / discharging. When the effective time period of the first input signal arrives, the effective time periods of the first adjustment signal and the second adjustment signal also arrive after one clock cycle, ensuring that the voltage of the input comparison module can charge / discharge normally. Therefore, the duty cycle measurement circuit can support the duty cycle measurement of burst data signals. The duty cycle measurement circuit of this embodiment can be used to measure the duty cycle of burst data signals, and can correct errors in the duty cycle of burst data signals in a timely manner, improving the data transmission performance of DDR.

[0063] Figure 6 A schematic diagram showing the location of the duty cycle measurement circuit in the memory controller according to an embodiment of the present disclosure.

[0064] In one possible implementation, the circuit is located in the memory controller, which supports the DDR protocol;

[0065] like Figure 6 As shown, the memory controller includes a first path, a second path, and a third path, with the endpoint of the first path being the starting point of the second and third paths.

[0066] The first path transmits clock signals and burst data signals, the second path transmits clock signals, and the third path transmits burst data signals.

[0067] The duty cycle measurement circuit is located on the first path, and the first input signal is a clock signal or a burst data signal.

[0068] For example, a memory controller may include a first path, a second path, and a third path, with the first path ending at the beginning of the second and third paths. The first path may transmit clock signals and burst data signals, the second path may transmit clock signals, and the third path may transmit burst data signals.

[0069] In existing technologies, the duty cycle correction circuit is placed on the second path, thus preventing the correction of burst data signals. This embodiment places the duty cycle measurement circuit on the first path. The first input signal can be a clock signal or a burst data signal; that is, the clock signal and burst data signal can be multiplexed using the duty cycle measurement circuit to complete the duty cycle measurement. In this way, a single duty cycle measurement circuit can be used to measure both the duty cycle of burst data signals and the duty cycle of clock signals, saving hardware costs for the memory controller and improving its performance.

[0070] Those skilled in the art will understand that the duty cycle measurement circuit can also be located on the third path, and a prior art duty cycle correction circuit can be located on the second path. In this case, the memory controller can also measure the duty cycle of the burst data signal and the duty cycle of the clock signal, thereby improving the performance of the memory controller.

[0071] Figure 7 A schematic diagram showing the structure of a signal generation module according to an embodiment of the present disclosure is provided.

[0072] like Figure 7 As shown, in one possible implementation, the signal generation module includes a first inverter, a signal generation submodule, a first switching submodule, and a second switching submodule.

[0073] The first inverter is used to obtain a second input signal INB based on the first input signal IN, wherein the level of the second input signal INB is opposite to that of the first input signal IN.

[0074] The signal generation submodule is used to, when the first input signal IN is a burst data signal, remove the data carried by the first input signal IN in the first clock cycle of each valid time period to obtain the first output signal CKOB; and remove the data carried by the second input signal INB in ​​the first clock cycle of each valid time period to obtain the second output signal CKOD.

[0075] The first switching submodule is used to, when the first input signal IN is a clock signal, use the first input signal IN as the first adjustment signal; and when the first input signal IN is a burst data signal, use the first output signal CKOB as the first adjustment signal UP.

[0076] The second switching submodule is used to use the second input signal INB as the second adjustment signal DN when the first input signal IN is a clock signal; and to use the second output signal CKOD as the second adjustment signal DN when the first input signal IN is a burst data signal.

[0077] For example, since the first input signal IN can be either a clock signal or a burst data signal, and the waveform characteristics of clock signals and burst data signals are different, the way to obtain the first adjustment signal UP and the second adjustment signal DN based on the clock signal is not exactly the same as the way to obtain the first adjustment signal UP and the second adjustment signal DN based on the burst data signal.

[0078] First, since the waveform of the first adjustment signal UP during the i-th effective time period is opposite to the waveform of the second adjustment signal DN during the i-th effective time period, the first input signal IN can be inverted regardless of its type. The signal generation module may include a first inverter for obtaining a second input signal INB from the first input signal IN, wherein the waveform of the second input signal INB is opposite to that of the first input signal IN.

[0079] If the first input signal IN is a clock signal, the simplest method is to directly use the first input signal IN as the first adjustment signal UP and the second input signal INB as the second adjustment signal DN. If the first input signal IN is a burst data signal, then the first adjustment signal UP and the second adjustment signal DN need to be obtained by processing the first input signal IN and the second input signal INB. Therefore, the signal generation module may also include a signal generation submodule, a first switching submodule, and a second switching submodule.

[0080] The signal generation submodule is used to process the first input signal IN and the second input signal INB to obtain the first output signal CKOB and the second output signal CKOD when the first input signal IN is a burst data signal. The first switching submodule is used to select whether to output the first input signal as the first adjustment signal or the first output signal as the first adjustment signal. The second switching submodule is used to select whether to output the second input signal as the second adjustment signal or the second output signal as the second adjustment signal.

[0081] Figure 8 A schematic diagram showing the waveforms of a first output signal, a second output signal, a first input signal, and a second input signal according to an embodiment of the present disclosure is provided. Figure 8As shown, removing the data carried by the first input signal IN in the first clock cycle of each valid time period yields the first output signal CKOB; removing the data carried by the second input signal INB in ​​the first clock cycle of each valid time period yields the second output signal CKOD.

[0082] This disclosure does not limit the structure of the signal generation submodule or the specific way in which it implements the above functions. Examples of the structure of the signal generation submodule and its implementation of the above functions can be found in the following text. Figure 9 Related descriptions.

[0083] In one example, the first switching submodule and the second switching submodule can be multiplexers. This disclosure does not limit the specific implementation of the first switching submodule and the second switching submodule.

[0084] In this way, the signal generation submodule is only needed when the first input signal is a burst data signal, and is not needed when the first input signal is a clock signal. This ensures the accuracy of the first and second adjustment signals, and also enables the duty cycle measurement circuit to measure the duty cycle of burst data signals and clock signals when it is set on the first path.

[0085] The first and second output signals are obtained by removing the data carried by the first and second input signals in the first clock cycle of each valid time period. This ensures that when the first clock cycle of the valid time period of the first input signal is reached, the first and second output signals are in the invalid time period, and the voltage of the input comparison module remains unchanged without being charged / discharged. When the valid time period of the first input signal arrives, the valid time periods of the first and second adjustment signals also arrive after one clock cycle, ensuring that the voltage of the input comparison module can be charged / discharged normally.

[0086] Figure 9 A schematic diagram showing the structure of a signal generation submodule according to an embodiment of the present disclosure is provided.

[0087] like Figure 9 As shown, in one possible implementation, the signal generation submodule includes a reset signal generation unit, a first AND gate, and a second AND gate.

[0088] The reset signal generation unit is used to generate a first reset signal CNT_RST and a second reset signal CNT_RST1 that are active high based on the first input signal. The start point of the i-th effective time period of the first reset signal CNT_RST is one clock cycle later than the start point of the i-th effective time period of the first input signal IN, and the end point of the i-th effective time period of the first reset signal CNT_RST is the same as the end point of the i-th effective time period of the first input signal IN. The start point of the i-th effective time period of the second reset signal CNT_RST1 is the same as the start point of the i-th effective time period of the first input signal IN, and the end point of the i-th effective time period of the second reset signal CNT_RST1 is one clock cycle later than the end point of the i-th effective time period of the first input signal IN.

[0089] The first AND gate is used to perform an AND operation on the first reset signal CNT_RST and the first input signal IN, and output the first output signal CKOB.

[0090] The second AND gate is used to perform an AND operation on the second reset signal CNT_RST1 and the second input signal INB, and output the second output signal CKOD.

[0091] It should be understood that logical operations can be performed between a signal with a specific waveform and the target signal to control the level of the target signal to meet the requirements.

[0092] Therefore, the signal generation submodule may include a reset signal generation unit for generating a first reset signal CNT_RST and a second reset signal CNT_RST1. The signal waveform obtained by performing a logical operation (e.g., AND operation) on the first reset signal CNT_RST and the first input signal IN is consistent with the waveform of the first input signal IN after removing the data carried in the first clock cycle of each valid time period. The signal waveform obtained by performing a logical operation (e.g., AND operation) on the second reset signal CNT_RST1 and the second input signal INB is consistent with the waveform of the second input signal INB after removing the data carried in the first clock cycle of each valid time period.

[0093] Figure 10 A schematic diagram showing the waveforms of the first reset signal and the second reset signal according to an embodiment of the present disclosure is provided.

[0094] like Figure 10 As shown, both the first reset signal CNT_RST and the second reset signal CNT_RST1 are active high, meaning that the high-level part is the active time period and the low-level part is the inactive time period.

[0095] The start of the i-th valid time period of the first reset signal CNT_RST is one clock cycle later than the start of the i-th valid time period of the first input signal IN, and the end of the i-th valid time period of the first reset signal CNT_RST is the same as the end of the i-th valid time period of the first input signal IN; the start of the i-th valid time period of the second reset signal CNT_RST1 is the same as the start of the i-th valid time period of the first input signal IN, and the end of the i-th valid time period of the second reset signal CNT_RST1 is one clock cycle later than the end of the i-th valid time period of the first input signal IN.

[0096] Accordingly, the signal generation submodule may include a first AND gate for performing an AND operation on the first reset signal and the first input signal, resulting in a first output signal. The signal generation submodule may also include a second AND gate for performing an AND operation on the second reset signal and the second input signal, resulting in a second output signal.

[0097] This disclosure does not limit the specific structure of the reset signal generation unit. As long as the first reset signal and the first input signal are ANDed to obtain a first output signal with the desired waveform, and the second reset signal and the second input signal are ANDed to obtain a second output signal with the desired waveform, then the reset signal can be used as the reference. Exemplary structures and functions of the reset signal generation unit can be found below. Figure 11 Related descriptions.

[0098] Those skilled in the art will understand that, in addition to using the first reset signal and the second reset signal for AND operation, other waveforms can also be used to perform other types of logical operations to obtain the first output signal and the second output signal that meet the requirements. This disclosure does not limit the type of logical operation used by the signal generation submodule.

[0099] Figure 11 A schematic diagram showing the structure of a reset signal generation unit according to an embodiment of the present disclosure is provided.

[0100] like Figure 11 As shown, in one possible implementation, the reset signal generation unit includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, an XOR gate, a NAND gate, and a second inverter.

[0101] The reset terminal of the first flip-flop receives a first reset signal, the control terminal of the first flip-flop receives a first input signal, the data input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, and the non-inverted output terminal of the first flip-flop is connected to the first input terminal of the XOR gate and the first input terminal of the NAND gate.

[0102] The reset terminal of the second flip-flop receives the first reset signal, the control terminal of the second flip-flop receives the first input signal, the data input terminal of the second flip-flop is connected to the output terminal of the XOR gate, and the non-inverting output terminal of the second flip-flop is connected to the second input terminal of the XOR gate, the second input terminal of the NAND gate, and the input terminal of the second inverter.

[0103] The control terminal of the third flip-flop receives the second input signal, the data input terminal of the third flip-flop is connected to the output terminal of the NAND gate, and the non-inverting output terminal of the third flip-flop outputs the first reset signal.

[0104] The control terminal of the fourth flip-flop receives the first input signal, the data input terminal of the fourth flip-flop is connected to the output terminal of the second inverter, and the non-inverting output terminal of the fourth flip-flop outputs the second reset signal.

[0105] For example, the reset signal generation unit uses its internal four flip-flops (FF1-FF4), one XOR gate, one NAND gate, and one inverter (INV2) to accurately generate the first reset signal CNT_RST and the second reset signal CNT_RST1. This disclosure does not limit the type of flip-flops; for example, it can be a D flip-flop. R represents the reset terminal of the flip-flop, CK represents the control terminal of the flip-flop, D represents the data input terminal of the flip-flop, Q represents the non-inverting output terminal of the flip-flop, and QB represents the inverting output terminal of the flip-flop.

[0106] The reset terminal of the first flip-flop FF1 receives the first reset signal CNT_RST. When CNT_RST is valid (usually low or high, depending on the specific type of flip-flop), FF1 is reset, and the signal Q0 output from the non-inverting output terminal is low. When CNT_RST is invalid, FF1 is triggered in response to the rising edge of the first input signal IN received at the control terminal, and the level of the signal Q0 output from the non-inverting output terminal depends on the level of the data input terminal.

[0107] The data input terminal of FF1 is connected to its own inverting output terminal to flip the level of the signal Q0 output terminal. For example, when the rising edge of the first input signal IN received by the control terminal arrives, FF1 will latch the signal at the data input terminal (i.e., the output of the inverting output terminal), and when it is triggered again, it will output the latched level to the non-inverting output terminal, causing the level output by the non-inverting output terminal to flip.

[0108] The reset terminal of the second flip-flop FF2 receives the first reset signal CNT_RST. When CNT_RST is valid (usually low or high, depending on the specific type of flip-flop), FF2 is reset, and the signal Q1 output from the non-inverting output terminal is low. When CNT_RST is invalid, FF2 is triggered in response to the rising edge of the first input signal IN received at the control terminal, and the level of the signal Q1 output from the non-inverting output terminal depends on the level of the data input terminal.

[0109] The data input of FF2 is connected to the output of the XOR gate, while its non-inverting output is connected to one input of the XOR gate. The other input of the XOR gate is connected to the non-inverting output of FF1. In other words, when the rising edge of the first input signal IN received by the control terminal arrives, FF2 latches the result of the XOR operation between signal Q0 and signal Q1, and outputs the latched level to the non-inverting output the next time it is triggered.

[0110] The third flip-flop FF3 is triggered in response to the rising edge of the second input signal INB received at the control terminal. The level of the first reset signal CNT_RST output from the non-inverting output terminal depends on the level of the data input terminal. The data input terminal of FF3 is connected to the output terminal of the NAND gate, receiving the result of the NAND operation between signal Q0 and signal Q1.

[0111] The fourth flip-flop FF4 is triggered in response to the rising edge of the first input signal IN received at the control terminal. The level of the second reset signal CNT_RST1 output from the non-inverting output terminal depends on the level of the data input terminal. The data input terminal of FF4 is connected to the output terminal of the second inverter INV2, receiving the result of the NOT operation of signal Q1.

[0112] By using the aforementioned flip-flops and logic gates in combination, a first reset signal and a second reset signal that meet the requirements can be generated. Flip-flops, inverters, NAND gates, and XOR gates are all commonly used circuit structures in existing technology, and the details of how flip-flops, inverters, NAND gates, and XOR gates implement the above functions will not be elaborated here.

[0113] This disclosure also proposes a method for measuring duty cycle. Figure 12 A schematic diagram illustrating the flow of a duty cycle measurement method according to an embodiment of the present disclosure is shown.

[0114] like Figure 12 As shown, in one possible implementation, the method includes:

[0115] Step S11: The signal generation module generates a first adjustment signal and a second adjustment signal based on the first input signal. When the first input signal is a burst data signal, the waveform of the first adjustment signal during the i-th effective time period is opposite to that of the second adjustment signal during the i-th effective time period. The starting point of the first adjustment signal during the i-th effective time period is the same as that of the second adjustment signal during the i-th effective time period, and is one clock cycle later than the starting point of the first input signal during the i-th effective time period, where i is a positive integer.

[0116] In step S12, the voltage detection module detects the duty cycle of the first adjustment signal and the second adjustment signal, and converts the duty cycle into two voltage signals which are then input to the comparison module.

[0117] Step S13: The comparison module compares the two voltage signals from the voltage detection module and outputs the comparison result. The comparison result indicates whether the duty cycle of the first input signal exceeds a preset threshold.

[0118] In one possible implementation, the circuit is located in a memory controller that supports the DDR protocol; the memory controller includes a first path, a second path, and a third path, the endpoint of the first path being the starting point of the second path and the third path; the first path transmits a clock signal and the burst data signal, the second path transmits the clock signal, and the third path transmits the burst data signal; the circuit is located on the first path, and the first input signal is either the clock signal or the burst data signal.

[0119] In one possible implementation, the signal generation module includes a first inverter, a signal generation submodule, a first switching submodule, and a second switching submodule. The step of generating a first adjustment signal and a second adjustment signal based on a first input signal includes: the first inverter obtaining a second input signal based on the first input signal, the second input signal having a waveform opposite to the first input signal; the signal generation submodule, when the first input signal is a burst data signal, removing the data carried by the first input signal in the first clock cycle of each valid time period to obtain a first output signal; and removing the data carried by the second input signal in the first clock cycle of each valid time period to obtain a second output signal; the first switching submodule, when the first input signal is a clock signal, using the first input signal as the first adjustment signal; and when the first input signal is the burst data signal, using the first output signal as the first adjustment signal; the second switching submodule, when the first input signal is a clock signal, using the second input signal as the second adjustment signal; and when the first input signal is the burst data signal, using the second output signal as the second adjustment signal.

[0120] In one possible implementation, the signal generation submodule includes a reset signal generation unit, a first AND gate, and a second AND gate. The step of removing data carried by the first input signal in the first clock cycle of each valid time period to obtain a first output signal includes: the reset signal generation unit generating a first reset signal based on the first input signal, wherein the start point of the i-th valid time period of the first reset signal is one clock cycle later than the start point of the i-th valid time period of the first input signal, and the end point of the i-th valid time period of the first reset signal is the same as the end point of the i-th valid time period of the first input signal; the first AND gate performing an AND operation on the first reset signal and the first input signal to output the first output signal. The step of removing data carried by the second input signal in the first clock cycle of each valid time period to obtain a second output signal includes: the reset signal generation unit generating a second reset signal based on the first input signal, wherein the start point of the i-th valid time period of the second reset signal is the same as the start point of the i-th valid time period of the first input signal, and the end point of the i-th valid time period of the first reset signal is one clock cycle later than the end point of the i-th valid time period of the first input signal; the second AND gate performing an AND operation on the second reset signal and the second input signal to output the second output signal.

[0121] In one possible implementation, the reset signal generating unit includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, an XOR gate, a NAND gate, and a second inverter. The reset terminal of the first flip-flop receives the first reset signal, the control terminal of the first flip-flop receives the first input signal, the data input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, and the non-inverted output terminal of the first flip-flop is connected to the first input terminal of the XOR gate and the first input terminal of the NAND gate. The reset terminal of the second flip-flop receives the first reset signal, the control terminal of the second flip-flop receives the first input signal, the data input terminal of the second flip-flop is connected to the output terminal of the XOR gate, and the non-inverted output terminal of the second flip-flop is connected to the second input terminal of the XOR gate, the second input terminal of the NAND gate, and the input terminal of the second inverter. The control terminal of the third flip-flop receives the second input signal, the data input terminal of the third flip-flop is connected to the output terminal of the NAND gate, and the non-inverted output terminal of the third flip-flop outputs the first reset signal. The control terminal of the fourth flip-flop receives the first input signal, the data input terminal of the fourth flip-flop is connected to the output terminal of the second inverter, and the non-inverted output terminal of the fourth flip-flop outputs the second reset signal.

[0122] This disclosure also proposes a processor, including the duty cycle measurement circuit described above. The processor may be a central processing unit, a graphics processing unit, etc., and this disclosure does not limit the specific type of processor.

[0123] This disclosure also proposes an electronic device including the processor described above. The electronic device may be a terminal device or a server; this disclosure does not limit the specific type of electronic device.

[0124] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0125] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A duty cycle measurement circuit, characterized in that, The circuit includes a signal generation module, a voltage detection module, and a comparison module. The signal generation module is used to generate a first adjustment signal and a second adjustment signal based on a first input signal. When the first input signal is a burst data signal, the waveform of the first adjustment signal during the i-th effective time period is opposite to the waveform of the second adjustment signal during the i-th effective time period. The starting point of the i-th effective time period of the first adjustment signal is the same as the starting point of the i-th effective time period of the second adjustment signal, and is one clock cycle later than the starting point of the i-th effective time period of the first input signal, where i is a positive integer; The voltage detection module is used to detect the duty cycle of the first adjustment signal and the second adjustment signal, and convert the duty cycle into two voltage signals which are then input to the comparison module. The comparison module is used to compare two voltage signals from the voltage detection module and output a comparison result. The comparison result indicates whether the duty cycle of the first input signal exceeds a preset threshold.

2. The circuit according to claim 1, characterized in that, The circuit is located in the memory controller, which supports the DDR protocol; The memory controller includes a first path, a second path, and a third path, wherein the endpoint of the first path is the starting point of the second path and the third path; The first path transmits the clock signal and the burst data signal, the second path transmits the clock signal, and the third path transmits the burst data signal; The circuit is located on the first path, and the first input signal is the clock signal or the burst data signal.

3. The circuit according to claim 1 or 2, characterized in that, The signal generation module includes a first inverter, a signal generation submodule, a first switching submodule, and a second switching submodule. The first inverter is used to obtain a second input signal based on the first input signal, wherein the second input signal has a waveform opposite to that of the first input signal; The signal generation submodule is used to, when the first input signal is a burst data signal, remove the data carried by the first input signal in the first clock cycle of each effective time period to obtain a first output signal; and remove the data carried by the second input signal in the first clock cycle of each effective time period to obtain a second output signal. The first switching submodule is configured to: use the first input signal as the first adjustment signal when the first input signal is a clock signal; and use the first output signal as the first adjustment signal when the first input signal is the burst data signal. The second switching submodule is used to use the second input signal as the second adjustment signal when the first input signal is a clock signal, and to use the second output signal as the second adjustment signal when the first input signal is the burst data signal.

4. The circuit according to claim 3, characterized in that, The signal generation submodule includes a reset signal generation unit, a first AND gate, and a second AND gate. The reset signal generation unit is used to generate a first reset signal and a second reset signal that are active at a high level according to the first input signal. The start point of the i-th effective time period of the first reset signal is one clock cycle later than the start point of the i-th effective time period of the first input signal, and the end point of the i-th effective time period of the first reset signal is the same as the end point of the i-th effective time period of the first input signal. The start point of the i-th valid time period of the second reset signal is the same as the start point of the i-th valid time period of the first input signal, and the end point of the i-th valid time period of the second reset signal is one clock cycle later than the end point of the i-th valid time period of the first input signal. The first AND gate is used to perform an AND operation on the first reset signal and the first input signal, and output the first output signal; The second AND gate is used to perform an AND operation on the second reset signal and the second input signal, and output the second output signal.

5. The circuit according to claim 4, characterized in that, The reset signal generation unit includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, an XOR gate, a NAND gate, and a second inverter. The reset terminal of the first flip-flop receives the first reset signal, the control terminal of the first flip-flop receives the first input signal, the data input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, and the non-inverted output terminal of the first flip-flop is connected to the first input terminal of the XOR gate and the first input terminal of the NAND gate. The reset terminal of the second flip-flop receives the first reset signal, the control terminal of the second flip-flop receives the first input signal, the data input terminal of the second flip-flop is connected to the output terminal of the XOR gate, and the non-inverting output terminal of the second flip-flop is connected to the second input terminal of the XOR gate, the second input terminal of the NAND gate, and the input terminal of the second inverter. The control terminal of the third flip-flop receives the second input signal, the data input terminal of the third flip-flop is connected to the output terminal of the NAND gate, and the non-inverting output terminal of the third flip-flop outputs the first reset signal. The control terminal of the fourth flip-flop receives the first input signal, the data input terminal of the fourth flip-flop is connected to the output terminal of the second inverter, and the non-inverting output terminal of the fourth flip-flop outputs the second reset signal.

6. A method for measuring duty cycle, characterized in that, The method includes: The signal generation module generates a first adjustment signal and a second adjustment signal based on the first input signal. When the first input signal is a burst data signal, the waveform of the first adjustment signal during the i-th effective time period is opposite to the waveform of the second adjustment signal during the i-th effective time period. The starting point of the first adjustment signal during the i-th effective time period is the same as the starting point of the second adjustment signal during the i-th effective time period, and is one clock cycle later than the starting point of the first input signal during the i-th effective time period, where i is a positive integer. The voltage detection module detects the duty cycle of the first adjustment signal and the second adjustment signal, and converts the duty cycle into two voltage signals which are then input to the comparison module. The comparison module compares two voltage signals from the voltage detection module and outputs a comparison result, which indicates whether the duty cycle of the first input signal exceeds a preset threshold.

7. The method according to claim 6, characterized in that, The signal generation module includes a first inverter, a signal generation submodule, a first switching submodule, and a second switching submodule. The step of generating the first adjustment signal and the second adjustment signal based on the first input signal includes: The first inverter obtains a second input signal based on the first input signal, and the second input signal has a waveform opposite to that of the first input signal; When the first input signal is a burst data signal, the signal generation submodule removes the data carried by the first input signal in the first clock cycle of each valid time period to obtain a first output signal; and removes the data carried by the second input signal in the first clock cycle of each valid time period to obtain a second output signal. When the first input signal is a clock signal, the first switching submodule uses the first input signal as the first adjustment signal; when the first input signal is the burst data signal, it uses the first output signal as the first adjustment signal. When the first input signal is a clock signal, the second switching submodule uses the second input signal as the second adjustment signal; when the first input signal is the burst data signal, it uses the second output signal as the second adjustment signal.

8. The method according to claim 7, characterized in that, The signal generation submodule includes a reset signal generation unit, a first AND gate, and a second AND gate. The step of removing the data carried by the first input signal in the first clock cycle of each valid time period to obtain the first output signal includes: the reset signal generation unit generating a first reset signal according to the first input signal, wherein the start of the i-th valid time period of the first reset signal is one clock cycle later than the start of the i-th valid time period of the first input signal, and the end of the i-th valid time period of the first reset signal is the same as the end of the i-th valid time period of the first input signal; and the first AND gate performing an AND operation on the first reset signal and the first input signal to output the first output signal. The step of removing the data carried by the second input signal in the first clock cycle of each valid time period to obtain the second output signal includes: the reset signal generation unit generating a second reset signal according to the first input signal, wherein the start point of the i-th valid time period of the second reset signal is the same as the start point of the i-th valid time period of the first input signal, and the end point of the i-th valid time period of the first reset signal is one clock cycle later than the end point of the i-th valid time period of the first input signal; and the second AND gate performing an AND operation on the second reset signal and the second input signal to output the second output signal.

9. A processor, characterized in that, The duty cycle measurement circuit includes any one of claims 1-5.

10. An electronic device, characterized in that, Includes the processor as described in claim 9.

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