Chip serial number processing method, device and electronic equipment

Abstract

This application provides a chip serial number processing method, apparatus, and electronic device. The method includes: generating a first serial number for the chip based on the chip's test time information and test station information; determining the mapping relationship between each logical bit of the first serial number and a physical storage unit bit in multiple memory addresses within the chip based on a predefined mapping table; generating a corresponding programming operation command based on the mapping relationship and each logical bit of the first serial number, and performing a programming operation corresponding to the programming operation command on the physical storage unit bit; after the programming operation is completed, reading data from the physical storage unit bit, and recombining the read data according to the mapping relationship to obtain a second serial number; comparing the second serial number with the first serial number to verify whether the chip's serial number is correct, which can improve storage space utilization and reduce additional storage resource consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip serial number processing method, apparatus and electronic device. Background Technology

[0002] In recent years, with the development of semiconductor integrated circuit testing technology, a unique serial number is written for each chip before mass production and shipment. Because it can realize product life cycle tracking, quality control, anti-counterfeiting traceability and failure analysis, it has been widely used in the chip mass production testing process.

[0003] However, traditional serial number programming schemes, such as those executed by automated test equipment or external main controllers, typically rely on pre-generating consecutive serial numbers and writing them into a reserved contiguous storage area within the chip using a contiguous addressing method. This approach suffers from drawbacks such as requiring additional contiguous storage space, low storage resource utilization, strong dependence on the chip's physical address layout, and insufficient subsequent expansion capabilities. Especially in applications with small-capacity one-time programmable memories where available physical storage units are scattered, the above scheme struggles to simultaneously meet the mass production testing requirements of low cost, high storage utilization, and flexible expansion. Summary of the Invention

[0004] The chip serial number processing method, apparatus, and electronic device provided in this application are intended to solve at least some of the defects existing in the current chip serial number processing methods.

[0005] In a first aspect, embodiments of this application provide a chip serial number processing method. The chip serial number processing method includes: generating a first serial number for the chip based on test time information and test station information; determining a mapping relationship between each logical bit of the first serial number and a physical storage unit bit in a plurality of memory addresses within the chip based on a predefined mapping table; generating a corresponding programming operation command based on the mapping relationship and each logical bit of the first serial number, and performing a programming operation corresponding to the programming operation command on the physical storage unit bit; after the programming operation is completed, reading data from the physical storage unit bit, and recombining the read data according to the mapping relationship to obtain a second serial number; comparing the second serial number with the first serial number to verify whether the chip's serial number is correct.

[0006] In some embodiments, generating a first serial number for the chip based on the chip's test time information and test station information includes: acquiring the chip's test time information and test station information; encoding the test time information and test station information respectively to obtain a test time code and a test station code; and combining the test time code and the test station code in a preset order to obtain the first serial number.

[0007] In some embodiments, the test time information includes multiple time fields; encoding the test time information and test station information to obtain test time code and test station code respectively includes: encoding the multiple time fields according to their respective preset bit widths and then concatenating them to obtain the test time code; encoding the test station information according to the preset bit width to obtain the test station code.

[0008] In some embodiments, generating a corresponding programming operation command based on the mapping relationship and each logical bit of the first sequence number includes: determining the physical storage unit bit corresponding to each logical bit according to the value of each logical bit of the first sequence number and the mapping relationship; generating a first command corresponding to the physical storage unit bit when the value of the logical bit indicates that programming is required; and generating a second command corresponding to the physical storage unit bit when the value of the logical bit indicates that programming is not required.

[0009] In some embodiments, performing a programming operation on the physical storage cell bit corresponding to the programming operation command includes: sequentially accessing the physical storage cell bits determined in the mapping table according to a preset programming timing sequence; and performing a programming operation on the physical storage cell bit based on the programming operation instruction; wherein the preset programming timing sequence includes voltage, pulse width, and pulse interval.

[0010] In some embodiments, reading data from the physical storage unit bit and recombining the read data according to the mapping relationship to obtain a second sequence number includes: reading data from the physical storage unit bit; and recombining the data according to the logical bit order of the first sequence number according to the mapping relationship to obtain the second sequence number.

[0011] In some embodiments, comparing the second serial number with the first serial number to verify whether the serial number of the chip is correct includes: comparing the second serial number with the first serial number; if the comparison result indicates that the second serial number is consistent with the first serial number, outputting that the serial number of the chip is correct; if the comparison result indicates that the second serial number is inconsistent with the first serial number, outputting that the serial number of the chip is incorrect, and marking the chip as unqualified.

[0012] In some embodiments, the mapping table includes redundant physical storage unit bits, which are used to expand the information capacity of the first serial number, store verification information, or replace damaged physical storage unit bits.

[0013] Secondly, embodiments of this application provide a chip serial number processing apparatus. The chip serial number processing apparatus includes: a generation module, used to generate a first serial number for the chip based on the chip's test time information and test station information; a determination module, used to determine the mapping relationship between each logical bit of the first serial number and a physical storage unit bit in a plurality of storage addresses within the chip based on a predefined mapping table; a programming module, used to generate a corresponding programming operation command based on the mapping relationship and each logical bit of the first serial number, and to perform a programming operation corresponding to the programming operation command on the physical storage unit bit; a combination module, used to read data from the physical storage unit bit after the programming operation is completed, and to recombine the read data according to the mapping relationship to obtain a second serial number; and a comparison module, used to compare the second serial number with the first serial number to verify whether the chip's serial number is correct.

[0014] Thirdly, embodiments of this application provide an electronic device. The electronic device includes a memory and a processor, the processor being communicatively connected to the memory. The memory stores computer program instructions, which, when invoked by the processor, cause the processor to execute the chip serial number processing method described above.

[0015] The beneficial effects of the chip serial number processing method provided in this application are as follows: By generating a chip serial number based on the chip's test time information and test station information, a highly unique identification information is formed during the chip testing process. This eliminates the need for complex continuous serial number management methods or additional serial number allocation procedures, thereby simplifying the testing process and reducing implementation costs. Simultaneously, by pre-establishing a mapping relationship between the serial number's logical bits and the physical storage unit bits in multiple memory addresses within the chip, the serial number can be written into the physical storage unit bits of multiple memory addresses within the chip without reserving consecutive physical storage unit bits, thus improving storage space utilization and reducing additional storage resource consumption. Furthermore, since the mapping relationship can be predefined, this method can adapt to different serial number requirements and different chip storage layouts, thus exhibiting high flexibility and applicability. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 A schematic diagram illustrating a chip serial number processing method provided in an embodiment of this application; Figure 2 A schematic diagram of a sub-process of step S110 of the chip serial number processing method provided in the embodiments of this application; Figure 3 A schematic diagram of a sub-process of step S112 of the chip serial number processing method provided in the embodiments of this application; Figure 4 A schematic diagram of a sub-process of step S130 of the chip serial number processing method provided in the embodiments of this application; Figure 5 A schematic diagram of a sub-process of step S130 of the chip serial number processing method provided in the embodiments of this application; Figure 6 A schematic diagram of a sub-process of step S140 of the chip serial number processing method provided in the embodiments of this application; Figure 7 A schematic diagram of a sub-process of step S150 of the chip serial number processing method provided in the embodiments of this application; Figure 8 A schematic diagram illustrating another chip serial number processing method provided in an embodiment of this application; Figure 9 A schematic diagram of OTP discrete free bit distribution provided in an embodiment of this application; Figure 10This is a schematic diagram of the chip serial number processing device provided in the embodiments of this application; Figure 11 This is a schematic diagram of the architecture of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] To facilitate understanding of this application, a more detailed description of this application will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0019] It should be noted that when a component is said to be "set on" another component, it can be directly on the other component or there may be an intervening component. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intervening component, or it can refer to the two components being interconnected via signals. When a component is considered to be "coupled" to another component, it can be directly coupled to the other component or there may be an intervening component, or it can refer to the two components interacting via signals.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] In chip mass production testing scenarios, it is typically necessary to write a unique serial number to each chip before it leaves the factory to enable functions such as product tracking, quality control, anti-counterfeiting traceability, and failure analysis. Typical methods for writing chip serial numbers include: First, the serial number of the chip to be written is obtained through an automated testing device or an external controller; then, according to the pre-planned consecutive memory addresses inside the chip, a consecutive addressing write operation is performed on the serial number.

[0023] However, during the actual research and implementation process, the applicant noted that the serial number programming schemes in related technologies typically employ a contiguous address storage architecture, requiring a contiguous physical storage area within the chip specifically for storing the serial number. While this approach enables serial number writing, the limited capacity and scattered bit distribution of one-time programmable storage resources often result in significant additional storage resource consumption due to the continuous reservation of dedicated storage areas. This, in turn, increases chip manufacturing costs and reduces storage utilization.

[0024] In addition, in order to balance serial number uniqueness, storage resource utilization and subsequent expansion needs, related technologies may also be improved by adding additional storage areas, introducing external serial number management modules, or redesigning the internal storage layout of the chip. However, such methods usually further increase the complexity of the test system and development costs, and it is difficult to achieve a unified balance of low cost, high utilization and flexible expansion in application scenarios with small-capacity one-time programmable memory and scattered available physical storage units.

[0025] To overcome the aforementioned shortcomings, the applicant discovered that by introducing a serial number generation mechanism based on test environment parameters during chip testing, and combining it with a pre-configured discrete address mapping relationship, each logical bit of the serial number can be assigned to a corresponding physical storage unit bit in multiple memory addresses within the chip. This eliminates the need for the serial number to be written to contiguous dedicated storage areas. Furthermore, by restoring and verifying the readback results of discrete physical storage unit bits according to the mapping relationship, effective confirmation of the serial number writing results can be achieved, thus achieving a better balance between low cost, high storage utilization, and flexible expansion.

[0026] Based on the above-described inventive concept, the chip serial number processing method provided in this application can be generally applied to various chip mass production testing scenarios using small-capacity one-time programmable memory, solving problems such as wasted storage resources, insufficient scalability, and poor portability inherent in contiguous address storage methods in related technologies. For ease of understanding, the specific implementation of the chip serial number processing method provided in this application will be described below with reference to specific embodiments.

[0027] Figure 1 This is a schematic diagram illustrating a chip serial number processing method provided in an embodiment of this application. Figure 1 As shown, the chip serial number processing method includes: S110. Based on the chip's test time information and test station information, generate the chip's first serial number; Here, "chip" refers to an integrated circuit device that needs to be written with a unique serial number before entering the mass production testing process. The chip can be a power management chip, control chip, sensor chip, driver chip, or other types of chip; this embodiment does not limit the type of chip.

[0028] "Test time information" refers to the time data acquired at the start of chip testing, used to characterize the moment when the chip enters the test phase. Test time information typically includes multiple time units, such as year, month, day, hour, minute, and second.

[0029] "Test station information" refers to the identification information of the test position of the chip in a multi-station test system.

[0030] "First serial number" refers to the serial number used to identify the chip.

[0031] In some embodiments, after the chip enters the mass production testing process, the testing equipment first obtains the test time information and test station information corresponding to the current chip, and then generates a first serial number based on the test time information and test station information.

[0032] For example, when the testing equipment performs online testing on a chip, it obtains the test time information as 2026-01-29 14:25:30 and the test station information as Site0. Then, it encodes the test time information according to the preset encoding rules to obtain the test time code as 0x187AE65E, and encodes the test station information to obtain the test station code as 0x0. Then, it combines the test station code and the test time code to obtain the first serial number of the chip as 0x0187AE65E.

[0033] S120. Based on a predefined mapping table, determine the mapping relationship between each logical bit of the first serial number and the physical memory cell bit in the multiple memory addresses within the chip; The "mapping table" refers to a pre-configured and stored correspondence table used to represent the correspondence between the logical bits of the serial number and the physical memory cell bits in multiple memory addresses within the chip.

[0034] "Logical bits" refer to the individual binary bits in the first serial number. The first serial number consists of multiple binary bits, and each binary bit can be considered a logical bit. For example, a 34-bit serial number can include 34 logical bits, and each logical bit corresponds to a value to be written.

[0035] "Physical memory bits in multiple memory addresses" refers to multiple actual programmable memory bits distributed across multiple memory addresses within the chip. These physical memory bits can be distributed contiguously or non-contiguously.

[0036] "Mapping relationship" refers to the correspondence established between logical bits and physical storage unit bits, used to determine which actual storage location inside the chip each bit of the first sequence number should be written to.

[0037] In some embodiments, after generating the first serial number, a pre-configured mapping table is invoked to determine the correspondence between each logical bit in the first serial number and the physical memory cell bits in multiple memory addresses within the chip, thereby providing a mapping basis for subsequent programming operations.

[0038] For example, during the chip test program development phase, a mapping table is pre-configured and stored. When the first serial number is 0x0187AE65E, the mapping table can be used to determine that the first logical bit in the first serial number corresponds to the first physical memory cell bit of the first memory address within the chip, the second logical bit corresponds to the second physical memory cell bit of the first memory address within the chip, the third logical bit corresponds to the third physical memory cell bit of the first memory address within the chip, and so on. Each physical memory cell bit is distributed across multiple memory addresses within the chip.

[0039] S130. Based on the mapping relationship and each logical bit of the first sequence number, generate a corresponding programming operation command, and perform a programming operation corresponding to the programming operation command on the physical storage unit bit. "Programming operation commands" refer to control instructions generated based on logical bit values ​​and mapping relationships, used to control the corresponding physical memory unit bits to perform write operations. Programming operation commands can include control commands that trigger programming, or control commands that maintain the status quo or skip processing.

[0040] "Programming operation" refers to the process of writing to physical storage units according to programming operation commands.

[0041] In some embodiments, after determining the mapping relationship, corresponding programming operation commands are generated based on the values ​​of each logical bit in the first sequence number and the corresponding mapping relationship, and the test device is controlled to perform the corresponding programming operation only on the physical storage unit bits specified in the mapping table.

[0042] For example, when a logical bit in the first sequence number is a value indicating that programming is required, the test device can generate a programming pulse command for the physical storage unit bit corresponding to that logical bit and perform a programming operation on that physical storage unit bit; when another logical bit is a value indicating that programming is not required, the test device can generate a keep-as-it-is instruction or a skip instruction, without performing a programming operation on the corresponding physical storage unit bit. Furthermore, the test device can access each physical storage unit bit sequentially according to a preset programming timing sequence and complete the discrete programming operation.

[0043] S140. After the programming operation is completed, data is read from the physical storage unit bit, and the read data is recombined according to the mapping relationship to obtain the second serial number; "Reading data" refers to the data read from multiple physical storage units after the programming operation is completed.

[0044] "Reassembly" refers to the process of restoring data read from multiple physical storage units to their corresponding logical positions based on the mapping relationship, and then reassembling them into a complete sequence number. Since the sequence number is scattered across multiple physical storage units, it needs to be restored according to the mapping relationship after reading back.

[0045] The "second serial number" refers to the serial number obtained by recombining the read data, which is used to characterize the serial number actually read back from inside the chip.

[0046] Understandably, the first serial number is the original serial number to be written to the chip, and the second serial number is the serial number obtained by reading it from the chip and restoring it after it has been written to the chip.

[0047] In some embodiments, after the programming operation is completed, the test device accesses multiple physical storage cell bits again according to the mapping table to read the data in each physical storage cell bit; then, according to the mapping relationship, the read data is restored to the corresponding logical bit position and recombined into the second serial number.

[0048] For example, after programming the first serial number 0x0187AE65E, the test device reads data from multiple physical storage unit bits specified in the mapping table; the read data is restored and concatenated according to the mapping relationship to form the second serial number.

[0049] S150. Compare the second serial number with the first serial number to verify whether the serial number of the chip is correct.

[0050] The term "comparison" refers to the process of comparing the second serial number with the first serial number to determine whether the serial number obtained after writing and reading back is consistent with the originally generated serial number. The comparison can be performed bit by bit or as an overall consistency judgment method; this application does not specify a particular method.

[0051] In some embodiments, after obtaining the second serial number, the second serial number is compared with the first serial number to verify whether the chip's serial number is correct.

[0052] For example, if the second serial number is 0x0187AE65E and the first serial number is also 0x0187AE65E, the chip serial number can be determined to be correct, and the programming success result can be output; if the second serial number is 0x0187AE65F and the first serial number is 0x0187AE65E, the two can be determined to be inconsistent, and the chip serial number can be output as incorrect.

[0053] In this embodiment, a chip serial number is generated based on the chip's test time and test station information, thus forming highly unique identification information during chip testing. This eliminates the need for complex continuous serial number management methods or additional serial number allocation processes, simplifying the testing process and reducing implementation costs. Simultaneously, by pre-establishing a mapping relationship between the serial number's logical bits and physical storage unit bits in multiple memory addresses within the chip, the serial number can be written into physical storage unit bits across multiple memory addresses without reserving consecutive physical storage unit bits, thereby improving storage space utilization and reducing additional storage resource consumption. Furthermore, since the mapping relationship can be predefined, this method can adapt to different serial number requirements and different chip storage layouts, thus exhibiting high flexibility and applicability.

[0054] In some embodiments, such as Figure 2 As shown, S110 specifically includes: S111. Obtain the test time information and the test station information of the chip; In some embodiments, after the test equipment starts the test program, it obtains the test time information and test station information corresponding to the current chip. For example, the test equipment can obtain the test time information as 2026-01-29 14:25:30 and the test station information as Site0.

[0055] S112. Encode the test time information and test station information respectively to obtain the test time code and test station code; Among them, "test time encoding" refers to the encoding result obtained by converting each time field in the test time information according to preset rules.

[0056] "Test station code" refers to the encoding result obtained after converting test station information according to preset encoding rules.

[0057] In some embodiments, after obtaining test time information and test station information, the test time information and test station information are encoded respectively to obtain test time code and test station code, so as to combine them to generate the first serial number.

[0058] For example, the test time information 2026-01-29 14:25:30 is compressed and encoded according to a preset encoding rule, resulting in a test time code of 0x187AE65E; simultaneously, the test station information Site0 is converted according to a preset encoding rule, resulting in a test station code of 0x0. As another example, when the test station information is Site1, it is encoded as 0x1.

[0059] S113. Combine the test time code and the test station code in a preset order to obtain the first sequence number.

[0060] The "preset order" refers to a pre-defined coding sequence used to determine the order of the test time code and the test station code within the first sequence number. The preset order can be set according to actual design requirements, such as placing the test station code in the higher digits and the test time code in the lower digits, or using other orders; this application does not impose specific limitations on this.

[0061] In some embodiments, after obtaining the test time code and the test station code, the test time code and the test station code are combined in a preset order to obtain the first serial number corresponding to the chip.

[0062] For example, taking the test station code 0x0 and the test time code 0x187AE65E as an example, they are combined in the order of high byte first and low byte last to obtain the first serial number 0x0187AE65E.

[0063] In this embodiment, the test time information and test station information are encoded separately and combined in a preset order to generate the first serial number, thereby realizing the on-site generation and regular expression of the chip serial number.

[0064] In some embodiments, the test time information includes multiple time fields; such as Figure 3 As shown, S112 specifically includes: S1121. Encode the multiple time fields according to their respective preset bit widths and then concatenate them to obtain the test time code; "Multiple time fields" refers to multiple data fields in the test time information used to represent different time units, such as year field, month field, date field, hour field, minute field, and second field.

[0065] "Preset bit width" refers to the number of bits pre-set for different time fields, which is used to limit the length of data bits occupied by each time field in the encoding result.

[0066] Different time fields have different value ranges, so different preset bit widths can be configured for each field to reduce storage usage while maintaining expressive power. For example, a field representing the last digit of the year can use a smaller bit width, while a field representing the second segment can use a larger bit width.

[0067] "Encoding" refers to the process of converting a time field into its corresponding binary or other data representation. The encoded result is used in subsequent concatenation to form a standardized test time code.

[0068] "Sponging" refers to the process of connecting the encoded results of multiple time fields in a predetermined order to form a complete piece of time data.

[0069] In some embodiments, after obtaining the test time information, the multiple time fields contained in the test time information are encoded respectively, and the encoding results corresponding to each time field are concatenated to obtain the test time code.

[0070] For example, the test equipment obtains the current time as 16:31:52 on January 20, 2026 at the start of chip testing. Then, it extracts multiple time fields from this time information and compresses and encodes them respectively. The year field takes the last digit "6" and encodes it as 0x06, the month field "1" is encoded as 0x01, the date field "20" is encoded as 0x14, the hour field "16" is encoded as 0x10, the minute field "31" is encoded as 0x1F, and the second field "52" is encoded as 0x34. Then, the encoding results of the time fields are concatenated in order from high digit to low digit to obtain a 30-bit binary test time code.

[0071] It should be noted that when the test time information changes, the values ​​of each time field will also change, which in turn will change the encoding results of each time field, thus changing the final generated test time encoding accordingly.

[0072] S1122. Encode the test station information according to the preset bit width to obtain the test station code.

[0073] In some embodiments, after obtaining the test station information, the test station information is encoded according to a preset bit width to obtain the test station code.

[0074] For example, in an 8-station testing system, when the current chip is located at Site0, the current station number is encoded as 0x0; when the current chip is located at Site1, the current station number is encoded as 0x1.

[0075] In this embodiment, by splitting the test time information into multiple time fields and encoding them separately, and simultaneously encoding the test station information, key information in the time and station dimensions can be retained with fewer bits of encoding, thereby generating a chip serial number with high uniqueness.

[0076] In some embodiments, such as Figure 4 As shown, the step S130, "generating corresponding programming operation commands based on the mapping relationship and each logical bit of the first sequence number," specifically includes: S131. Determine the physical storage unit bit corresponding to each logical bit based on the value of each logical bit of the first sequence number and the mapping relationship; In some embodiments, after generating a first sequence number and determining the mapping relationship between logical bits and physical storage unit bits, the physical storage unit bit corresponding to each logical bit is determined according to the value of each logical bit in the first sequence number and the mapping relationship.

[0077] For example, when the first serial number is 0x0186907F4, the mapping table determines that each logical bit in the first serial number corresponds to multiple physical memory cell bits inside the chip. The physical memory cell bits are not contiguous in address and are scattered in different areas of the one-time programmable memory.

[0078] S132. If the value of the logical bit indicates that programming is required, generate a first command corresponding to the bit of the physical storage unit. In this context, "a value indicating programming is required" means that the value of the logical bit corresponds to a write operation that needs to be performed on the physical storage unit bit. For example, a logical bit value of 1 can indicate that programming is required.

[0079] The "first command" refers to the control command generated when the logical bit value indicates that programming is required. It is used to perform programming actions on the bits of the physical memory unit. The first command can be a control command to apply a programming pulse, or it can be any other write command that can change the state of the bits of the physical memory unit.

[0080] In some embodiments, after determining the physical storage unit bit corresponding to each logical bit, the processing method corresponding to the current value of each logical bit is determined; when the value of a certain logical bit indicates that a write operation needs to be performed, a first command matching the physical storage unit bit corresponding to that logical bit is generated.

[0081] For example, when a certain logical bit in the first serial number is 1, the logical bit is determined to be a logical bit that needs to be programmed; at this time, the test device can generate a first command for the physical storage unit bit corresponding to the logical bit, such as generating a programming pulse command for the corresponding mapped address, so that the physical storage unit bit will change its state in subsequent operations.

[0082] S133. If the value of the logical bit indicates that programming is not required, generate a second command corresponding to the bit of the physical storage unit.

[0083] Here, "a value indicating no programming is required" means that the value of the logical bit corresponds to a situation where no write operation to the physical storage unit is needed. For example, a logical bit value of 0 can indicate that no programming is required.

[0084] A "second command" refers to a control command generated when the logical bit value indicates that programming is not required. It is used to avoid performing programming actions on the physical memory unit bits. A second command can be a "keep as is" instruction or a "skip" instruction.

[0085] In some embodiments, after determining the physical storage unit bit corresponding to each logical bit, for logical bits whose values ​​indicate that no write operation needs to be performed, a second command matching the corresponding physical storage unit bit is generated to avoid performing unnecessary programming processing on the physical storage unit bit.

[0086] For example, when a certain logical bit in the first serial number is 0, the logical bit is determined to be a logical bit that does not need to be programmed. At this time, the test device can generate a second command for the physical storage unit bit corresponding to the logical bit, such as generating a keep-as-is instruction or a skip instruction, so that no write operation is performed on the physical storage unit bit in subsequent operations.

[0087] In this embodiment, by generating control commands corresponding to the physical storage unit bits according to the value of each logical bit in the sequence number and the mapping relationship, programming processing can be performed only on the physical storage unit bits that need to be written, while the physical storage unit bits that do not need to be written can be kept in their original state or skipped, thereby improving programming efficiency and reducing invalid operations.

[0088] In some embodiments, such as Figure 5 As shown, the "performing a programming operation corresponding to the programming operation command on the physical storage unit bit" in S130 specifically includes: S134. According to the preset programming timing, access the physical storage unit bits determined in the mapping table in sequence; "Preset programming timing" refers to the timing control rules that are set in advance when programming the internal memory bits of the chip. The preset programming timing is used to limit the application method and sequence of various control parameters during the programming process, so as to ensure that the physical memory cell bits can be written in accordance with the method specified in the chip datasheet.

[0089] Specifically, the preset programming timing includes voltage, pulse width, and pulse interval.

[0090] Here, "voltage" refers to the driving voltage applied to the physical memory cell bit or related programming path during the programming process, which is used to change the state of the physical memory cell bit.

[0091] "Pulse width" refers to the duration of a single programming pulse, used to characterize the duration of a programming stimulus.

[0092] "Pulse interval" refers to the time interval between two adjacent programming pulses, which is used to control the time distribution between continuous programming operations.

[0093] In some embodiments, after generating programming operation commands, the physical memory cell bits determined in the mapping table are accessed sequentially according to a preset programming timing sequence so as to perform subsequent programming processing on each physical memory cell bit in accordance with chip programming rules.

[0094] For example, when programming a physical memory cell bit, a predetermined voltage can be applied first and the corresponding pulse width can be maintained; after the pulse ends, after a predetermined pulse interval, the voltage is applied to the next physical memory cell bit and the corresponding pulse width is maintained, thereby realizing programming timing control based on voltage, pulse width and pulse interval.

[0095] S135. Based on the programming operation instructions, perform programming operations on the physical storage unit bits.

[0096] In some embodiments, after accessing the physical storage cell bit, corresponding programming operations are performed on each physical storage cell bit according to the corresponding programming operation instructions, thereby writing the data corresponding to the first serial number into the chip's internal storage location.

[0097] For example, when the programming operation instruction corresponding to a certain physical storage cell bit is a programming pulse command, the test device performs a write operation on the physical storage cell bit, changing the corresponding storage bit from the initial state to the target state; when the programming operation instruction corresponding to another physical storage cell bit is a keep-as-you-go instruction or a skip instruction, the test device does not perform a write operation on the physical storage cell bit.

[0098] In this embodiment, by sequentially accessing and writing multiple physical memory cell bits according to a programming timing sequence including voltage, pulse width, and pulse interval, the discrete address programming process can meet the chip programming timing requirements, thereby improving the stability and accuracy of the programming operation.

[0099] In some embodiments, such as Figure 6 As shown, S140 specifically includes: S141. Read the data from the physical storage unit bit; Here, "data" refers to the actual stored data read from multiple physical storage units.

[0100] In some embodiments, after determining the physical storage cell bit, the data in the physical storage cell bit is read.

[0101] For example, the test device reads first data from a first physical storage unit bit, reads second data from a second physical storage unit bit, reads third data from a third physical storage unit bit, and so on, thereby obtaining a set of data read out bit by bit.

[0102] S142. According to the mapping relationship, the data is recombined according to the logical bit order of the first sequence number to obtain the second sequence number.

[0103] In some embodiments, after reading the data corresponding to the bits of multiple physical storage units, the data is restored to the positions corresponding to each logical bit according to the mapping relationship, and then recombined according to the logical bit order of the first sequence number to generate the second sequence number.

[0104] For example, if a set of data read from multiple physical storage units is reversed through mapping and corresponds to the first logical bit, the second logical bit, the third logical bit, and so on up to the last logical bit, the test device can concatenate these data in the logical bit order to finally obtain the second serial number; for example, the result after recombination can be 0x0186907F4, thereby completing the readback and restoration of the original serial number.

[0105] In this embodiment, by locating and reading back multiple physical storage unit bits according to the mapping table, and restoring and reassembling the read-back data according to the logical bit order corresponding to the first sequence number, data scattered in different physical locations can be restored to a complete sequence number, thereby achieving accurate read-back of discrete programming results.

[0106] In some embodiments, such as Figure 7 As shown, S150 specifically includes: S151. Compare the second serial number with the first serial number; In some embodiments, after completing the readback and obtaining the second serial number, the test device compares the second serial number with the first serial number to verify whether the chip's serial number is correct.

[0107] Specifically, the testing equipment compares the second serial number obtained from the readback with the first serial number generated before programming, bit by bit, to determine whether the two are consistent.

[0108] S152. If the comparison result indicates that the second serial number is consistent with the first serial number, output that the serial number of the chip is correct; "The chip's serial number is correct" refers to the output information when the second serial number matches the first serial number, which indicates that the current chip's serial number programming process has been completed correctly.

[0109] In some embodiments, after the test device compares the second serial number with the first serial number, if the second serial number is found to be completely consistent with the first serial number, it is determined that the programming result of the current chip is correct, and the chip's serial number is output as correct.

[0110] Specifically, if the first serial number is 0x0187AE65E, and the second serial number obtained by reading back and recombining is also 0x0187AE65E, then it can be determined that the second serial number is consistent with the first serial number, and the serial number of the output chip is correct.

[0111] S153. If the comparison result indicates that the second serial number is inconsistent with the first serial number, output that the serial number of the chip is incorrect and mark the chip as unqualified.

[0112] Among them, "chip serial number error" refers to the output information when the second serial number is inconsistent with the first serial number, which is used to indicate that there is an anomaly in the current chip serial number programming process.

[0113] In some embodiments, after the testing device compares the second serial number with the first serial number, if it finds that the second serial number and the first serial number are inconsistent by at least one bit, it determines that the current chip programming result is incorrect, outputs that the chip serial number is incorrect, and marks the chip as unqualified.

[0114] Specifically, if the first serial number is 0x0187AE65E, and the second serial number obtained by reading back and recombining is 0x0187AE65F, then it can be determined that the second serial number is inconsistent with the first serial number, the serial number of the output chip is incorrect, and the current chip is marked as unqualified.

[0115] In this embodiment, by verifying the consistency between the serial number obtained from the readback recovery and the serial number generated before programming, and outputting whether the chip's serial number is correct or incorrect based on the verification result, it is possible to determine in a timely manner whether the current chip's serial number has been written correctly, thereby achieving effective verification of the programming result.

[0116] In some embodiments, the mapping table includes redundant physical storage unit bits, which are used to expand the information capacity of the first serial number, store verification information, or replace damaged physical storage unit bits.

[0117] In addition to containing the mapping relationship between serial numbers and physical storage unit bits, the mapping table can also contain additional reserved storage locations to support expansion, verification, or replacement functions.

[0118] "Redundant physical storage bits" refer to additional physical storage locations that are pre-reserved in the mapping table and are not occupied by serial numbers. Redundant physical storage bits can be distributed in different areas of the one-time programmable memory inside the chip to improve the flexibility and reliability of the serial number storage scheme.

[0119] "Information capacity of the first serial number" refers to the range or quantity of data content in the first serial number. For example, when new identification information needs to be added to the first serial number later, such as batch information, production line information, test version information, or other additional information, the information capacity of the first serial number can be expanded by adding logical bits.

[0120] "Verification information" refers to information used to check whether a serial number is correct. For example, verification information may include error correction information, parity check information, or other information used to verify the integrity and correctness of the data.

[0121] "Damaged physical storage cell bit" refers to a physical storage cell bit that cannot perform write, hold, or read functions normally due to manufacturing defects, programming anomalies, or storage failures.

[0122] In this embodiment, by reserving redundant physical storage unit bits in the mapping relationship and using these redundant physical storage unit bits for information expansion, storage verification, or replacement of abnormal storage bits, the expansion capability of the serial number can be improved without changing the original storage layout, thereby taking into account both the flexible configuration requirements and programming reliability under the discrete storage structure.

[0123] Figure 8 A schematic diagram of another chip serial number processing method provided in this application embodiment is shown below. Figure 8 As shown, the chip serial number processing method includes: S201. Load the chip into the mass production testing process; S202. Start the test equipment and test program; S203. The testing equipment collects the chip's test time information and test station information in real time. S204. Encode the test time information and test station information respectively to obtain the test time code and test station code; S205. Concatenate the test time code and the test station code to obtain the first SN code (i.e. the first serial number mentioned above). S206. Call the predefined mapping table to map each bit of the first SN code to an OTP programming command (i.e., the first command or the second command mentioned above). S207. The test equipment writes the OTP programming command into the corresponding discrete OTP bit (i.e., the physical storage unit bit mentioned above) according to the OTP programming timing sequence. S208. The test equipment reads data from the discrete OTP bits according to the mapping table and reassembles them to obtain the second SN code (i.e., the second sequence number mentioned above). S209. Determine whether the verification is successful based on the second SN code and the first SN code; if yes, the verification is successful and proceed to S210; otherwise, the verification is unsuccessful and proceed to S211. S210, The serial number of the output chip is correct; S211, The serial number of the output chip is incorrect, and the chip is marked as unqualified.

[0124]

[0125] Table 1 Discrete Address Mapping Table As shown in Table 1, the zeroth bit of the serial number (e.g., SN[0]) is mapped to the sixth bit (e.g., bit6) of address 56 (e.g., 0x56), the first bit of the serial number (e.g., SN[1]) is mapped to the seventh bit (e.g., bit7) of address 56 (e.g., 0x56), the second bit of the serial number (e.g., SN[2]) is mapped to the sixth bit (e.g., bit6) of address 57 (e.g., 0x57), and the third bit of the serial number (e.g., SN[3]) is mapped to the seventh bit (e.g., bit6) of address 57 (e.g., 0x57). 7) The fourth bit of the serial number (e.g., SN[4]) is mapped to the sixth bit (e.g., bit6) of address 58 (e.g., 0x58), and the fifth bit of the serial number (e.g., SN[5]) is mapped to the seventh bit (e.g., bit7) of address 58 (e.g., 0x58). Subsequent serial numbers are sequentially mapped to the corresponding positions in addresses 59, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, and 106. It can be seen that this application does not write the serial number into a contiguous memory space, but instead uses a preset mapping table to write each logical bit of the serial number into multiple programmable read-only memory cells that are scattered and physically discontinuous, thereby effectively utilizing the scattered and idle memory resources inside the chip.

[0126] Meanwhile, the 34th (e.g., SN

[34] ), 35th (e.g., SN

[35] ), 36th (e.g., SN

[36] ), and 37th (e.g., SN

[37] ) bits of the serial number in Table 1 correspond to the relevant bits in addresses 105 and 106, respectively. These bits are reserved as redundant bits and can be used to expand the serial number information, store verification information, or replace abnormal storage bits, thereby improving the utilization rate of storage resources, the flexibility of the scheme, and the reliability of the system.

[0127] Figure 9 This application provides a schematic diagram of the OTP discrete idle bit distribution, as shown in the embodiment. Figure 9 As shown, Figure 9The top center represents the first storage address (e.g., OTP ADDRESS1) and the second storage address (e.g., OTP ADDRESS2). Figure 9 Below are the corresponding first register address (e.g., REG ADDRESS1) and second register address (e.g., REG ADDRESS2); solid arrows indicate that the corresponding physical memory cell bit has been mapped to the register function bit, and therefore this part of the physical memory cell bit has been occupied by the original function of the chip and cannot be used for serial number burning; dashed arrows indicate that the corresponding physical memory cell bit has not been mapped to the register function bit, and therefore belongs to the available free bit. Figure 10 This is a schematic diagram of the chip serial number processing device provided in an embodiment of this application. Figure 10 As shown, the chip serial number processing device 300 includes: a generation module 310, a determination module 320, a programming module 330, a combination module 340, and a comparison module 350, wherein: The generation module 310 is used to generate the first serial number of the chip based on the chip's test time information and test station information; The determining module 320 is used to determine the mapping relationship between each logical bit of the first serial number and the physical memory cell bit in a plurality of memory addresses in the chip, based on a predefined mapping table. The programming module 330 is used to generate a corresponding programming operation command based on the mapping relationship and each logical bit of the first sequence number, and to perform a programming operation corresponding to the programming operation command on the physical storage unit bit. The combination module 340 is used to read data from the physical storage unit bit after the programming operation is completed, and to recombine the read data according to the mapping relationship to obtain the second serial number; The comparison module 350 is used to compare the second serial number with the first serial number to verify whether the serial number of the chip is correct.

[0128] In some embodiments, the generation module 310 includes: an acquisition unit, an encoding unit, and a combination unit, wherein: the acquisition unit is used to acquire the test time information and the test station information of the chip; the encoding unit is used to encode the test time information and the test station information respectively to obtain a test time code and a test station code; and the combination unit is used to combine the test time code and the test station code in a preset order to obtain the first sequence number.

[0129] In some embodiments, the test time information includes multiple time fields; the encoding unit is specifically used to: encode the multiple time fields according to their respective preset bit widths and then concatenate them to obtain the test time code; and encode the test station information according to the preset bit width to obtain the test station code.

[0130] In some embodiments, the programming module 330 is specifically configured to: determine the physical storage unit bit corresponding to each logical bit according to the value of each logical bit of the first sequence number and the mapping relationship; generate a first command corresponding to the physical storage unit bit when the value of the logical bit indicates that programming is required; and generate a second command corresponding to the physical storage unit bit when the value of the logical bit indicates that programming is not required.

[0131] In some embodiments, the programming module 330 is specifically used to: sequentially access the physical storage unit bits determined in the mapping table according to a preset programming timing sequence; and perform a programming operation on the physical storage unit bits based on the programming operation instructions; wherein the preset programming timing sequence includes voltage, pulse width, and pulse interval.

[0132] In some embodiments, the combination module 340 is specifically used to: read data from the physical storage unit bit; and recombine the data according to the logical bit order of the first sequence number to obtain the second sequence number based on the mapping relationship.

[0133] In some embodiments, the comparison module 350 is specifically configured to: compare the second serial number with the first serial number; if the comparison result indicates that the second serial number is consistent with the first serial number, output that the serial number of the chip is correct; if the comparison result indicates that the second serial number is inconsistent with the first serial number, output that the serial number of the chip is incorrect and mark the chip as unqualified.

[0134] In some embodiments, the mapping table includes redundant physical storage unit bits, which are used to expand the information capacity of the first serial number, store verification information, or replace damaged physical storage unit bits.

[0135] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the functional modules described above can be referred to the corresponding method steps in the foregoing embodiments, and will not be repeated here. Those skilled in the art can use different methods to implement the described functions for each specific application. For example, a computer software program containing the steps of the above method embodiments can be stored in a computer-readable storage medium so that, when executed, the program can implement one or more steps of the above method embodiments.

[0136] Figure 11 The diagram shows the structure of an electronic device according to an embodiment of this application. This embodiment does not limit the specific implementation of the electronic device.

[0137] like Figure 11 As shown, the electronic device 400 may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440.

[0138] The processor 410, communication interface 420, and memory 430 communicate with each other via communication bus 440. Communication interface 420 is used for communication connections with other external devices. The processor 410 executes program 450 to implement the chip serial number processing method in one or more of the above embodiments.

[0139] Specifically, program 450 may include program code that includes computer operation instructions. When program 450 is invoked, processor 410 executes the computer operation instructions to implement the steps in the chip serial number processing method of one or more embodiments.

[0140] Depending on the actual application scenario, the processor 410 can be of the appropriate type, including but not limited to mainstream embedded processors such as microcontrollers (MCUs) and ARM architecture processors, as well as other types of processors such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs), as long as they can provide the computing and control capabilities required by the actual application scenario.

[0141] The memory 430 is used to store the program 450. It includes a program storage area and a data storage area. The program storage area is used to store firmware programs, embedded applications, and various functional modules; the data storage area is used to store data and calculation results during program execution. For example, the memory 430 may include: on-chip RAM (for temporary data storage during program execution); on-chip Flash memory (for storing program code and configuration data); and EEPROM or other types of non-volatile memory (for storing parameters that need to be retained when power is off).

[0142] This application also provides a computer-readable storage medium. This computer-readable storage medium can be a non-volatile computer-readable storage medium. This computer-readable storage medium stores a computer program.

[0143] When executed by a processor, the computer program implements one or more steps of the chip serial number processing method disclosed in the embodiments of this application. The complete computer program product is embodied on one or more computer-readable storage media containing the computer program disclosed in the embodiments of this application.

[0144] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip serial number processing method, characterized by, The method includes: Based on the chip's test time information and test station information, a first serial number for the chip is generated; Based on a predefined mapping table, the mapping relationship between each logical bit of the first serial number and the physical memory cell bit in multiple memory addresses within the chip is determined; Based on the mapping relationship and each logical bit of the first sequence number, a corresponding programming operation command is generated, and a programming operation corresponding to the programming operation command is executed on the physical storage unit bit. After the programming operation is completed, data is read from the physical storage unit bit, and the read data is recombined according to the mapping relationship to obtain the second serial number; The second serial number is compared with the first serial number to verify whether the serial number of the chip is correct.

2. The chip serial number processing method according to claim 1, characterized in that, The step of generating the first serial number of the chip based on the chip's test time information and test station information includes: Obtain the test time information and the test station information of the chip; The test time information and test station information are encoded respectively to obtain the test time code and the test station code; The test time code and the test station code are combined in a preset order to obtain the first sequence number.

3. The chip serial number processing method according to claim 2, characterized in that, The test time information includes multiple time fields; The step of encoding the test time information and test station information respectively to obtain test time code and test station code includes: The test time code is obtained by encoding the multiple time fields according to their respective preset bit widths and then concatenating them. The test station information is encoded according to the preset bit width to obtain the test station code.

4. The chip serial number processing method according to claim 1, characterized in that, The step of generating corresponding programming operation commands based on the mapping relationship and each logical bit of the first sequence number includes: Based on the value of each logical bit of the first sequence number and the mapping relationship, determine the physical storage unit bit corresponding to each logical bit; When the value of the logical bit indicates that programming is required, a first command corresponding to the bit of the physical storage unit is generated; The value of the logical bit indicates that no programming is required, and a second command corresponding to the physical storage unit bit is generated.

5. The chip serial number processing method according to claim 4, characterized in that, The step of performing the programming operation corresponding to the programming operation command on the physical storage unit bit includes: According to the preset programming timing, the physical storage unit bits determined in the mapping table are accessed sequentially; Based on the programming operation instructions, a programming operation is performed on the physical storage unit bit; The preset programming timing includes voltage, pulse width, and pulse interval.

6. The chip serial number processing method according to claim 1, characterized in that, The step of reading data from the physical storage unit bit and recombining the read data according to the mapping relationship to obtain the second sequence number includes: Read the data from the physical storage unit. According to the mapping relationship, the data is recombined according to the logical bit order of the first sequence number to obtain the second sequence number.

7. The chip serial number processing method according to claim 1, characterized in that, The step of comparing the second serial number with the first serial number to verify whether the serial number of the chip is correct includes: Compare the second serial number with the first serial number; If the comparison result indicates that the second serial number is consistent with the first serial number, the chip's serial number is output as correct; If the comparison result indicates that the second serial number is inconsistent with the first serial number, the serial number of the chip is incorrect, and the chip is marked as unqualified.

8. The chip serial number processing method according to any one of claims 1 to 7, characterized in that, The mapping table includes redundant physical storage unit bits, which are used to expand the information capacity of the first serial number, store verification information, or replace damaged physical storage unit bits.

9. A chip serial number processing device, characterized in that, The device includes: The generation module is used to generate the first serial number of the chip based on the chip's test time information and test station information; The determination module is used to determine the mapping relationship between each logical bit of the first serial number and the physical memory cell bit in multiple memory addresses within the chip, based on a predefined mapping table; The programming module is used to generate corresponding programming operation commands based on the mapping relationship and each logical bit of the first sequence number, and to perform programming operations corresponding to the programming operation commands on the physical storage unit bits. The combination module is used to read data from the physical storage unit bit after the programming operation is completed, and to recombine the read data according to the mapping relationship to obtain the second serial number; The comparison module is used to compare the second serial number with the first serial number to verify whether the serial number of the chip is correct.

10. An electronic device, characterized in that, include: The system includes a memory and a processor, wherein the processor is communicatively connected to the memory, the memory stores computer program instructions, and when the computer program instructions are invoked by the processor, the processor executes the chip serial number processing method as described in any one of claims 1-8.

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