Any programmable multi-channel semiconductor array parallel testing system and testing method
By using the parallel excitation of the core controller and multi-channel source measurement unit module and the flexible addressing and switching of the matrix switch module, the problems of low efficiency, large interference, insufficient protocol and poor scalability of existing semiconductor test systems are solved, and efficient and accurate semiconductor array electrical testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA NORMAL UNIV
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-31
AI Technical Summary
Existing semiconductor testing systems suffer from low testing efficiency, are unable to achieve hardware-level multi-channel parallel stimulation and measurement, have creep path interference issues, lack flexibility in testing protocols, have poor scalability, and cannot meet the high-throughput testing requirements of new semiconductor arrays.
The parallel test system employs an arbitrary programmable multi-channel semiconductor array. The core controller generates a global synchronization clock signal, the multi-channel source measurement unit module realizes parallel excitation and acquisition, the matrix switch module performs flexible addressing and switching, supports arbitrary programmable test protocols, and has automated yield verification functions.
It achieves hardware-level parallel testing, significantly improves testing efficiency, solves creep path interference, adapts to complex testing requirements, improves the testing accuracy and flexibility of the system, supports fully automated processes, and enhances the electrical testing performance of semiconductor device arrays.
Smart Images
Figure CN122493923A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor testing technology, and in particular to a parallel testing system and method for arbitrary programmable multi-channel semiconductor arrays. Background Technology
[0002] As semiconductor technology rapidly advances towards new structures and principles, novel non-volatile memory devices such as ferroelectric capacitors, ferroelectric tunnel junctions, and memristors, with their advantages of low power consumption, high-speed read / write, and high integration, have become core components for building next-generation in-memory computing chips and neuromorphic computing chips. These chips typically employ a large-scale cross-array architecture. Their research, verification, and mass production require comprehensive electrical characteristic characterization of the vast number of device cells in the array, including IV characteristics, pulse read / write characteristics, retention characteristics, and fatigue characteristics. The accuracy, efficiency, and flexibility of the test data directly determine the speed of chip development iteration and mass production yield.
[0003] Currently, electrical testing of semiconductor device arrays primarily relies on traditional single-channel or few-channel semiconductor parameter analyzers (SPAs), coupled with relay switch matrices to achieve cell-by-cell testing of the array. To improve the channel utilization of a single SPA, existing technologies have designed improved schemes based on relay arrays to multiplex the channels of a single SPA, reducing the hardware cost of the testing system to some extent. However, such schemes are essentially still an extension of "single-channel serial testing," and their test throughput is limited by the signal generation and measurement rate of a single SPA, failing to achieve true hardware-level multi-channel parallel excitation and measurement, and thus struggling to meet the testing requirements of large-scale new semiconductor arrays.
[0004] Specifically, existing technologies suffer from the following insurmountable drawbacks: First, the testing efficiency is extremely low, making it unsuitable for the high-throughput testing requirements of large-scale arrays. Traditional testing systems employ a serial, cell-by-cell testing mode, with testing time increasing linearly with array size. The time required to complete a single basic electrical characteristic test of the entire array is lengthy, severely restricting the speed of chip R&D iteration and mass production capacity.
[0005] Secondly, the creeping path interference problem in passive cross-array testing cannot be solved at the physical level, resulting in poor test data accuracy. Because passive cross-arrays lack selective isolation, when a test voltage is applied to the target cell, the current will form multiple creeping paths through unselected devices, causing the measured current to contain a large amount of crosstalk components, failing to accurately reflect the electrical characteristics of the target cell. Traditional single-channel test systems, limited by their hardware architecture, cannot simultaneously apply synchronous compensating bias voltages to all unselected row and column ports in the array. They can only use algorithms to correct the test data later, failing to fundamentally solve the influence of creeping current, resulting in large test errors or even the inability to complete the test.
[0006] Furthermore, the test protocols lack sufficient flexibility and cannot adapt to the complex testing requirements of new principle devices. The signal generation capabilities of traditional test systems are limited to a single semiconductor parameter analyzer, making it difficult to simultaneously apply complex signals of different types and timings to different cells in the array. For complex testing scenarios such as diverse parallel pulse sequences, asynchronous read / write operations, and pulse timing-dependent plasticity required for neuromorphic chip training, traditional fixed-protocol test systems cannot achieve the desired results, necessitating customized dedicated test hardware, which significantly increases R&D costs and timelines.
[0007] Furthermore, the system suffers from poor channel scalability and low hardware resource utilization. Traditional channel-multiplexing-based test systems introduce significant signal crosstalk and attenuation when expanding channels, and there is a hardware limit to the number of channels. Simultaneously, the system cannot flexibly allocate hardware resources according to test requirements, making it difficult to achieve concurrent operations for writing, reading, and online crosstalk monitoring, thus limiting the depth and reliability of the test.
[0008] Therefore, developing a semiconductor array electrical testing system and method that can achieve true hardware-level parallel testing, solve creep path interference at the physical level, has flexible channel expansion, supports arbitrary programmable testing protocols, and has automated yield verification functions is a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0009] The problem to be solved by the present invention is to provide a parallel test system and test method for arbitrary programmable multi-channel semiconductor arrays, so as to overcome the shortcomings of the prior art, such as extremely low test efficiency, inability to solve the problem of creep path interference, insufficient test protocol flexibility and poor scalability.
[0010] The technical solution adopted by this invention to solve its technical problem is: an arbitrary programmable multi-channel semiconductor array parallel testing system, comprising: The core controller is used to generate a global synchronization clock signal and test control commands, and to process and store test data. The multi-channel source measurement unit module includes multiple independent and programmable source measurement channels. Some of these source measurement channels are electrically connected to all row ports of the semiconductor device under test array, and are used to output independently programmable electrical signal excitations in parallel to designated row ports / all row ports of the semiconductor device under test array under the scheduling of the global synchronization clock signal, and synchronously acquire the electrical response signals of the semiconductor device under test. The matrix switch module has its input terminal electrically connected to some other source measurement channels of the multi-channel source measurement unit module, and its output terminal electrically connected to each column port of the semiconductor device under test array, respectively. It is used to switch the source measurement channel to any specified column port of the semiconductor device under test array according to the test control command of the core controller. The core controller, the multi-channel source measurement unit module, and the matrix switch module are communicatively connected. The core controller, based on the global synchronization clock signal, uniformly schedules and synchronizes the electrical signal output of the multi-channel source measurement unit with the switching action of the matrix switch module.
[0011] As a further improvement of the present invention, the multi-channel source measurement unit module is composed of multiple source measurement unit boards spliced together, and each source measurement unit board has several independent programmable source measurement channels.
[0012] As a further improvement of the present invention, the matrix switch module is a multiplexer or a cross-point switch array, and the number of its switching channels is greater than or equal to the maximum number of columns of the semiconductor device array under test.
[0013] As a further improvement of the present invention, the matrix switch module is configured with at least two sets of independent switch sub-units. The output terminal of each set of switch sub-units is connected to the column port of the semiconductor device under test array, and the input terminal of each set of switch sub-units is connected to different source measurement channels. The core controller can select and enable any set of switch sub-units according to different test bias modes to apply different bias voltages to the column port of the semiconductor device under test array.
[0014] As a further improvement of the present invention, the core controller is equipped with test control software, which supports graphical or script-based programming and can customize test sequences. The test sequence includes setting the voltage / current output waveform, amplitude, pulse width, range, and sampling rate of the specified source measurement channel, as well as controlling the switching timing of the matrix switch module.
[0015] As a further improvement of the present invention, the arbitrary programmable multi-channel semiconductor array parallel test system also includes a signal conversion interface module. The semiconductor device array under test is mounted on a test board or probe card. The signal conversion interface module is used to adapt and connect the ports of the multi-channel source measurement unit module and the matrix switch module to the test board or probe card carrying the semiconductor device array under test.
[0016] As a further improvement of the present invention, the core controller, the multi-channel source measurement unit module and the matrix switch module are integrated in the same chassis via a standard system bus.
[0017] This invention also provides a parallel testing method for arbitrary programmable multi-channel semiconductor arrays, which uses the arbitrary programmable multi-channel semiconductor array parallel testing system described above for testing, and includes the following steps: S1. Mount the array of semiconductor devices under test on the test board or probe card, and electrically connect it to the multi-channel source measurement unit module and the matrix switch module respectively through the signal conversion interface module; S2. Configure global test parameters through the core controller. The global test parameters include the range of the device under test (DUT) cells in the DUT array, the test type, the electrical signal excitation parameters, and the electrical signal excitation output timing of the multi-channel source measurement unit and the switching timing parameters of the matrix switch module. S3. Control the matrix switch module through the core controller to electrically connect the specified source measurement channel with the target column port of the semiconductor device array under test; S4. Control the designated source measurement channel through the core controller to output the programmed electrical signal excitation in parallel to the designated row port / all row ports of the semiconductor device array under test, and simultaneously collect the electrical response data of the device unit under test corresponding to the current target column; S5. Repeat steps S3 to S4 until all specified device cells in the semiconductor device array under test are tested; S6. All collected electrical response data are sent back to the core controller for processing and storage.
[0018] As a further improvement of the present invention, when performing a write test, the electrical signal excitation in step S4 is a write pulse signal; after the write is completed, the multi-channel source measurement unit module is automatically switched to read mode, and read voltage is applied to all row ports simultaneously to synchronously collect the electrical response data of the device under test unit corresponding to the current target column.
[0019] As a further improvement of the present invention, the test items include IV scan test, voltage-driven It test, pulse read / write test, retention characteristic test, and fatigue characteristic test; the array of semiconductor devices under test is any one of the following arrays: ferroelectric capacitor cross array, ferroelectric tunnel junction cross array, memristor cross array, 1T1R array, and 2T array.
[0020] The beneficial effects of this invention are as follows: This invention provides an arbitrary programmable multi-channel semiconductor array parallel testing system and testing method. Through a core controller generating a global synchronous clock and unified scheduling control, multi-channel source measurement unit modules achieve independent parallel excitation and acquisition of the row ports of the semiconductor device array under test, and a matrix switch module flexibly addresses and switches the column ports. Simultaneously, it strictly achieves timing synchronization between the electrical signal output of the source measurement units and the switching actions of the matrix switch module, enabling true hardware-level parallel electrical testing. This significantly improves overall testing efficiency compared to traditional serial multiplexing testing schemes. The hardware architecture with multi-channel synchronous independent output effectively solves the inherent creeping path interference problem of passive cross-arrays, ensuring accurate and reliable test data from a hardware principle perspective. Furthermore, this testing system has arbitrary programmable test protocol configuration capabilities, fully adapting to the complex and diverse electrical testing needs of various new principle semiconductor devices. Simultaneously, relying on the integrated scheduling control of the core controller, it achieves fully automated test process operation, significantly improving the comprehensive performance of semiconductor device array electrical testing. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a schematic diagram of the overall hardware architecture of the arbitrary programmable multi-channel semiconductor array parallel test system of the present invention; Figure 2 This is a flowchart illustrating the steps of the parallel testing method for arbitrary programmable multichannel semiconductor arrays of the present invention. Figure 3 This is a schematic diagram of different weighted read / write operation modes of the semiconductor device array under test according to the present invention, where a is the bidirectional polarization full bias method, b is the full bias method, c is the half bias method, and d is the one-third bias method. Figure 4a ~f is a schematic diagram of the parallel writing operation of the semiconductor device array under test using the bidirectional polarization full bias method of the present invention. Detailed Implementation
[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0024] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0026] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.
[0027] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.
[0028] Example 1
[0029] See Figure 1This invention provides an arbitrary programmable multi-channel semiconductor array parallel test system, comprising: a core controller, a multi-channel source measurement unit module, and a matrix switch module. The core controller generates a global synchronization clock signal and test control commands, and processes and stores test data. The multi-channel source measurement unit module includes multiple independent programmable source measurement channels. Some of these source measurement channels are configured to be electrically connected to all row ports of the semiconductor device under test (SDD) array, respectively, and to output independently programmable electrical signal excitations in parallel to designated row ports / all row ports of the SDD array under the scheduling of the global synchronization clock signal, while simultaneously acquiring the electrical response signals of the SDD semiconductor device. The input terminal of the matrix switch module is electrically connected to other source measurement channels (excluding those electrically connected to row ports) of the multi-channel source measurement unit module, and its output terminal is electrically connected to each column port of the SDD semiconductor device array, respectively, to switch the source measurement channel (referring to the aforementioned "other source measurement channels") to any designated column port of the SDD semiconductor device array according to the test control commands of the core controller.
[0030] The core controller, multi-channel source measurement unit module, and matrix switch module are connected in communication. The core controller, based on a global synchronization clock signal, uniformly schedules the synchronization of the electrical signal output of the multi-channel source measurement unit and the switching action of the matrix switch module.
[0031] This invention provides an arbitrary programmable multi-channel semiconductor array parallel testing system. Through a core controller generating a global synchronous clock and unified scheduling control, multi-channel source measurement unit modules independently and parallelly excite and acquire data at the row ports of the semiconductor device under test array, and a matrix switch module flexibly addresses and switches column ports. Simultaneously, it strictly synchronizes the timing of the source measurement unit's electrical signal output with the matrix switch module's switching actions, enabling truly hardware-level parallel electrical testing. This significantly improves overall testing efficiency compared to traditional serial multiplexing testing schemes. The hardware architecture with multi-channel synchronous independent output effectively solves the inherent creeping path interference problem of passive cross-arrays, ensuring accurate and reliable test data from a hardware principle perspective. Furthermore, the system possesses arbitrary programmable test protocol configuration capabilities, fully adapting to the complex and diverse electrical testing needs of various new principle semiconductor devices. With integrated scheduling control from the core controller, it achieves fully automated testing processes, significantly improving the overall performance of semiconductor device array electrical testing.
[0032] In this invention, the core controller can be implemented using various mature control devices in the field without special limitations. To ensure the accuracy of global synchronization control, data processing efficiency, and operational stability of the system, an embedded controller, such as the PXIe-8880 embedded controller, is preferred. This type of embedded controller possesses powerful computing capabilities, a high-speed real-time communication interface, and stable timing control performance. It can efficiently generate a global synchronization clock signal and various test control commands, accurately schedule the collaborative work of the multi-channel source measurement unit module and the matrix switch module, and ensure that the electrical signal output of the multi-channel source measurement unit and the switching action of the matrix switch module are strictly synchronized. At the same time, it has sufficient storage capacity and high-speed data processing capabilities, and can quickly complete the reception, processing, and storage of test data, meeting the data processing requirements of high-throughput testing scenarios. Furthermore, the embedded controller has excellent scalability and compatibility, and can be flexibly adapted to source measurement unit boards and matrix switch modules of different specifications, which facilitates subsequent system upgrades and functional expansion. At the same time, its miniaturization and integration characteristics also make it easier to integrate with other hardware modules of the system in the same chassis through a standard system bus, further improving the overall system integration, operational reliability and anti-interference capability, and meeting the high-precision and high-stability requirements of semiconductor array testing.
[0033] Of course, in addition to computers, programmable logic controllers (PLCs) and other devices can be selected according to the needs of actual application scenarios. Regardless of which implementation method is adopted, the core controller must have a high-speed communication interface with the multi-channel source measurement unit module and the matrix switch module. It can realize data interaction and instruction transmission through the standard system bus, and at the same time, it can run test control software, support graphical or scripted programming, complete global test parameter configuration, test sequence customization and automated scheduling of the entire test process, and ensure the coordinated and stable operation of all hardware modules of the test system.
[0034] The core controller of this invention has built-in test control software, which is developed using LabVIEW software and supports both graphical programming and script-based programming. Users can customize test sequences according to test requirements. The test sequence includes parameter settings for the voltage / current output waveform, amplitude, pulse width, range, and sampling rate of the specified source measurement channel, as well as the switching timing control of the matrix switch module.
[0035] Specifically, the test control software includes a hardware driver and initialization module, a test sequence graphical editing module, a matrix switch addressing control module, a real-time data acquisition and display module, and a data storage and analysis module. All of the above software functional modules are existing mature technologies in the field, and this invention does not improve the underlying architecture, basic drivers, or general data processing logic of the software modules. Specifically, the hardware driver and initialization module is used to complete the power-on drive and system initialization configuration of each hardware module; the test sequence graphical editing module provides a graphical drag-and-drop editing interface and script editing interface, supporting user-defined test sequences, including test steps, excitation parameters of each source measurement channel, switching timing of the matrix switch module, and test logic; the matrix switch addressing control module is used to implement channel on / off control and column port addressing control of the matrix switch module; the real-time data acquisition and display module is used to synchronously acquire electrical response signals and visualize them in real time; and the data storage and analysis module is used to complete test data saving, device status determination, and array yield statistical analysis. The improvement of this invention lies in utilizing existing mature software modules to achieve integrated programmable collaborative control of the multi-channel parallel excitation hardware, multiple sets of switchable matrix switch sub-units, multiple bias modes, and read / write traversal yield verification process unique to this invention.
[0036] In this invention, the multi-channel source measurement unit module is composed of multiple source measurement unit boards (SMU boards) spliced together. The SMU boards are such as NI PXIe-4163 or similar models. Each SMU board has several independent programmable source measurement channels, which enables the system test channels to have modular expansion capabilities. The number of SMU boards can be flexibly increased or decreased according to the number of rows of the semiconductor device array under test. At the same time, the modular structure facilitates hardware maintenance, fault diagnosis and partial upgrades, effectively improving system adaptability and service life.
[0037] In this invention, the matrix switch module is a multiplexer or cross-point switch array, and its number of switches (referring to the number of output ports that a single matrix switch module can independently control) is greater than or equal to the maximum number of columns of the semiconductor device array under test, which can realize complete and omission-free addressing and switching of all column ports of the array under test.
[0038] Optionally, the matrix switch module can be an NI PXIe-2533 or similar model, which supports path switching in the microsecond to millisecond range, with stable signal conduction performance, meeting the path switching requirements of high-precision electrical testing and ensuring the feasibility of full-column array testing.
[0039] It is worth mentioning that the matrix switch module of this invention is configured with at least two sets of independent switch sub-units. The output terminals of each set of switch sub-units are connected one-to-one to the column ports of the semiconductor device under test array, and the input terminals of each set of switch sub-units are connected to different source measurement channels. The core controller can select and enable any set of switch sub-units according to different test bias modes to apply different bias voltages to the column ports of the semiconductor device under test array. This allows the same hardware system to be compatible with various creeping interference suppression bias test modes such as bidirectional polarization full bias method, full bias method, half bias method, and one-third bias method without rewiring. It can solve the creeping path crosstalk of passive cross arrays from the physical level, significantly improve the test accuracy of complex arrays, and greatly improve the compatibility and flexibility of the system test modes.
[0040] The arbitrary programmable multi-channel semiconductor array parallel test system of the present invention also includes a chassis, such as an NI PXIe chassis, in which the core controller, multi-channel source measurement unit module and matrix switch module are integrated in the same chassis via a standard system bus (PXIe / PCIe).
[0041] Furthermore, the arbitrary programmable multi-channel semiconductor array parallel test system of the present invention also includes a signal conversion interface module. The semiconductor device array under test is mounted on a test board or probe card. The signal conversion interface module is used to adapt and connect the ports of the multi-channel source measurement unit module and the matrix switch module to the test board or probe card carrying the semiconductor device array under test. This enables impedance matching, electrical isolation and signal conversion between the high-precision electrical ports of the system and the chip test carrier, reduces signal transmission loss and external crosstalk, and facilitates quick disassembly and replacement of the chip under test, thereby improving the system's universal adaptability and ease of use in the field.
[0042] The signal conversion interface module can be any interface structure known to those skilled in the art capable of achieving electrical port adaptation, signal conversion, and impedance matching, such as a high-frequency probe interface, a PCB adapter board, an RF adapter, a customized interface adapter, or a standard test interface module. Specifically, when the semiconductor device under test (DUT) array is mounted on a probe card, the signal conversion interface module can use a high-frequency probe adapter matching the probe card specifications to achieve high-precision signal transmission between the matrix switch module, the multi-channel source measurement unit module, and the probe card. When the DUT array is mounted on a test board, the signal conversion interface module can use a PCB adapter board, electrically connected to the corresponding interface of the test board via standardized pads, while integrating impedance matching circuitry and electromagnetic shielding structure to reduce attenuation and crosstalk during signal transmission. Furthermore, the signal conversion interface module can also be customized according to the specific specifications of the test board, probe card, and the test requirements of the DUT, flexibly adapting to different types of test carriers to ensure the reliability of electrical connections and signal transmission stability between the system ports and the DUT array, further improving the universality and test accuracy of the test system.
[0043] Example 2
[0044] See Figure 2 The present invention also provides a parallel testing method for arbitrary programmable multi-channel semiconductor arrays, which uses the arbitrary programmable multi-channel semiconductor array parallel testing system as described in Embodiment 1, and includes the following steps: S1. Mount the array of semiconductor devices under test on the test board or probe card, and electrically connect it to the multi-channel source measurement unit module and the matrix switch module respectively through the signal conversion interface module; S2. Configure global test parameters through the core controller. Global test parameters include the range of the device under test (DUT) cells in the array of semiconductor devices under test, the test type, the electrical signal excitation parameters, and the electrical signal excitation output timing of the multi-channel source measurement unit and the switching timing parameters of the matrix switch module. S3. Control the matrix switch module through the core controller to electrically connect the specified source measurement channel to the target column port of the semiconductor device array under test; S4. Control the designated source measurement channel through the core controller to output the programmed electrical signal excitation in parallel to the designated row port / all row ports of the semiconductor device array under test, and simultaneously collect the electrical response data of the device unit under test corresponding to the current target column; S5. Repeat steps S3 to S4 until all specified device cells in the semiconductor device array under test are tested; S6. All collected electrical response data is sent back to the core controller for processing and storage.
[0045] When the test type is write and yield verification test, the electrical signal excitation in step S4 is a write pulse signal; after the write operation is completed, the corresponding source measurement channel is automatically switched to read mode, and the same column traversal method as the write test is used to apply a read voltage or small current read excitation much lower than the write voltage to the specified row port, and the read response data of each device under test is collected synchronously; the read response data is compared with the preset theoretical threshold to determine the good or bad status of the corresponding device unit, and the good or bad status of all device units under test is counted to generate array yield data.
[0046] In this invention, the test items include IV scan test, voltage-driven It test, pulse read / write test, hold characteristic test, and fatigue characteristic test; the semiconductor device array under test is any one of the following arrays: ferroelectric capacitor cross array, ferroelectric tunnel junction cross array, memristor cross array, 1T1R array (one transistor + one memristor array), and 2T array (two transistor arrays).
[0047] Figure 3 This diagram illustrates different weighted read / write operation methods for the semiconductor device array under test according to the present invention. In the diagram, a represents the bidirectional polarization full bias method, b represents the full bias method, c represents the half-bias method, and d represents the one-third bias method. The following section specifically uses the testing of passive cross-connected arrays as an example. On a PXIe platform-based system, the bidirectional polarization full bias method is used to test passive cross-connected arrays (such as ferroelectric capacitor cross-connected arrays, ferroelectric tunnel junction cross-connected arrays, and memristor passive cross-connected arrays). The specific process is as follows: The core controller completes system power-on and hardware self-test, loads test control software and initializes the multi-channel source measurement unit module and matrix switch module, configures the global synchronization clock signal, establishes a stable communication link between the core controller and each hardware module, and ensures that the electrical signal output of the multi-channel source measurement unit and the switching action of the matrix switch module maintain strict timing synchronization.
[0048] The voltage-driven It test item is selected through the graphical interface of the test control software, and the test bias mode is set to bidirectional polarization full bias method. Then, the parameter configuration interface is entered to configure global test parameters such as the size of the passive cross array under test, the programmable pulse voltage amplitude (such as 0V, ±5V), pulse width, sampling rate, and scan rate. The test control software parses the above configuration parameters into corresponding test control commands and sends them to the multi-channel source measurement unit module and the matrix switch module.
[0049] According to the biasing rules of the bidirectional polarization full bias method, one set of switch sub-units of the matrix switch module is enabled. The input of this set of switch sub-units is connected to the designated source measurement channel to apply a -5V bias voltage. The other set of switch sub-units is kept off to meet the biasing requirements of the bidirectional polarization full bias method for the column ports.
[0050] like Figure 4a As shown, the core controller controls the multi-channel source measurement unit module to output a +5V pulse voltage excitation to all row ports of the passive cross array under test, and at the same time controls the matrix switch module to output a -5V pulse voltage excitation to all column ports of the passive cross array under test, so that the polarization direction of the passive cross array under test is consistent.
[0051] like Figures 4b to 4f As shown, the core controller performs unified scheduling based on a global synchronization clock signal, controlling the multi-channel source measurement unit module to output programmed pulse voltage excitation in parallel to all row ports of the passive cross array under test. At the same time, it controls the matrix switch module to perform column scanning addressing operation, sequentially turning on the target column port and the corresponding source measurement channel according to the preset timing sequence, while keeping the other unselected column ports off. This achieves synchronous acquisition of parallel electrical excitation and electrical response signals of all device units in the current column, completing the voltage drive It curve test of that column.
[0052] After the current column test is completed, the core controller controls the matrix switch module to quickly switch to the next target port, repeating the parallel excitation output and electrical response acquisition operations, and sequentially traversing all specified columns in the passive cross array under test according to the column scanning method until all test units of the device under test are completed.
[0053] During the test, the multi-channel source measurement unit module transmits the collected current, voltage and other electrical response data back to the core controller in real time. The core controller processes the data in real time, displays the waveforms and stores them locally, and finally completes the parallel writing and electrical characteristic characterization of the passive cross array based on the bidirectional polarization full bias method.
[0054] It should be noted that the testing system described in this invention is not limited to the bidirectional polarization full polarization method described above. It can also be flexibly adapted to the type, size, and accuracy requirements of the passive cross-array under test. Figure 3 Other bias test modes include the full bias method shown in b, the half bias method shown in c, and the one-third bias method shown in d. The test procedures for each of these bias methods are basically the same as those for the bidirectional polarization full bias method described in this embodiment, and the specific test procedures for each bias method will not be repeated. Users can directly select the corresponding bias mode and configure the relevant parameters through the graphical interface of the test control software according to their actual test needs, thereby completing the passive cross-array parallel electrical test under the corresponding bias mode, fully demonstrating the flexibility and versatility of the test system of this invention.
[0055] The same or similar parts between the various embodiments in this specification can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments.
[0056] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An arbitrary programmable multi-channel semiconductor array parallel test system, characterized by, include: The core controller is used to generate a global synchronization clock signal and test control commands, and to process and store test data. The multi-channel source measurement unit module includes multiple independent and programmable source measurement channels. Some of these source measurement channels are electrically connected to all row ports of the semiconductor device under test array, and are used to output independently programmable electrical signal excitations in parallel to designated row ports / all row ports of the semiconductor device under test array under the scheduling of the global synchronization clock signal, and synchronously acquire the electrical response signals of the semiconductor device under test. The matrix switch module has its input terminal electrically connected to some other source measurement channels of the multi-channel source measurement unit module, and its output terminal electrically connected to each column port of the semiconductor device under test array, respectively. It is used to switch the source measurement channel to any specified column port of the semiconductor device under test array according to the test control command of the core controller. The core controller, the multi-channel source measurement unit module, and the matrix switch module are communicatively connected. The core controller, based on the global synchronization clock signal, uniformly schedules and synchronizes the electrical signal output of the multi-channel source measurement unit with the switching action of the matrix switch module.
2. The arbitrarily programmable multi-channel semiconductor array parallel test system of claim 1, wherein, The multi-channel source measurement unit module is composed of multiple source measurement unit boards spliced together, and each source measurement unit board has several independent programmable source measurement channels.
3. The arbitrarily programmable multi-channel semiconductor array parallel test system of claim 1, wherein, The matrix switch module is a multiplexer or cross-point switch array, and its number of switches is greater than or equal to the maximum number of columns of the semiconductor device array under test.
4. The arbitrarily programmable multi-channel semiconductor array parallel test system of claim 1, wherein, The matrix switch module is configured with at least two sets of independent switch sub-units. The output of each set of switch sub-units is connected to the column port of the semiconductor device array under test, and the input of each set of switch sub-units is connected to different source measurement channels. The core controller can select and enable any group of switch sub-units according to different test bias modes to apply different bias voltages to the column ports of the array of semiconductor devices under test.
5. The arbitrarily programmable multi-channel semiconductor array parallel test system of claim 1, wherein, The core controller is equipped with test control software, which supports graphical or script-based programming and allows for the customization of test sequences. The test sequences include setting the voltage / current output waveform, amplitude, pulse width, range, and sampling rate of the specified source measurement channel, as well as controlling the switching timing of the matrix switch module.
6. The arbitrary programmable multi-channel semiconductor array parallel test system according to claim 1, characterized in that, It also includes a signal conversion interface module. The semiconductor device under test array is mounted on a test board or probe card. The signal conversion interface module is used to adapt and connect the ports of the multi-channel source measurement unit module and the matrix switch module to the test board or probe card that carries the semiconductor device under test array.
7. The arbitrary programmable multi-channel semiconductor array parallel test system according to claim 1, characterized in that, The core controller, the multi-channel source measurement unit module, and the matrix switch module are integrated in the same chassis via a standard system bus.
8. A method for parallel testing of arbitrary programmable multi-channel semiconductor arrays, wherein the testing is performed using the arbitrary programmable multi-channel semiconductor array parallel testing system as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1. Mount the array of semiconductor devices under test on the test board or probe card, and electrically connect it to the multi-channel source measurement unit module and the matrix switch module respectively through the signal conversion interface module; S2. Configure global test parameters through the core controller. The global test parameters include the range of the device under test (DUT) cells in the DUT array, the test type, the electrical signal excitation parameters, and the electrical signal excitation output timing of the multi-channel source measurement unit and the switching timing parameters of the matrix switch module. S3. Control the matrix switch module through the core controller to electrically connect the specified source measurement channel with the target column port of the semiconductor device array under test; S4. Control the designated source measurement channel through the core controller to output the programmed electrical signal excitation in parallel to the designated row port / all row ports of the semiconductor device array under test, and simultaneously collect the electrical response data of the device unit under test corresponding to the current target column; S5. Repeat steps S3 to S4 until all specified device cells in the semiconductor device array under test are tested; S6. All collected electrical response data are sent back to the core controller for processing and storage.
9. The parallel testing method for arbitrary programmable multi-channel semiconductor arrays according to claim 8, characterized in that, When performing a write test, the electrical signal excitation in step S4 is a write pulse signal; After writing is complete, the multi-channel source measurement unit module is automatically switched to read mode, and read voltage is applied to all row ports simultaneously to synchronously collect the electrical response data of the device under test unit corresponding to the current target column.
10. The parallel testing method for arbitrary programmable multi-channel semiconductor arrays according to claim 8, characterized in that, The test items include IV scan test, voltage-driven It test, pulse read / write test, retention characteristic test, and fatigue characteristic test; the semiconductor device array under test is any one of the following arrays: ferroelectric capacitor cross array, ferroelectric tunnel junction cross array, memristor cross array, 1T1R array, and 2T array.