Controlled RF power for in-process improvement on wafers

Abstract

According to one embodiment, a system for adjusting the RF power delivered to a plasma chamber is disclosed. One or more memory devices store associated data. First associated data is based on film thickness values ​​and a corresponding matching network value for each film thickness value. Second associated data is based on film thickness values ​​and a corresponding RF power setting for each film thickness value. For the current wafer operation, control circuitry determines the current matching network value. Using this value and the first associated data, the current film thickness of the semiconductor wafer is determined. Using the current film thickness and the second associated data, a corresponding RF power setting is determined. The RF power is adjusted based on the corresponding RF power setting to achieve a new film thickness within a desired film thickness range.

Description

Technical Field

[0001] This disclosure relates to systems and methods for regulating radio frequency (RF) power delivered to a plasma chamber. Background Technology

[0002] The semiconductor device manufacturing process uses plasma processing at different stages to create semiconductor devices such as microprocessors, memory chips, and other integrated circuits or devices. Plasma processing involves energizing a gas mixture by introducing radio frequency (RF) energy into the gas molecules. This gas mixture is typically contained within a vacuum chamber, also known as a plasma chamber. The semiconductor wafer is located within the plasma chamber. RF energy is introduced through electrodes or other devices within the chamber. In a typical plasma process, an RF source generates power at the desired RF frequency and power, and this power is transferred to the plasma chamber. To provide efficient power transfer from the RF source to the plasma chamber, a matching network is located between the RF source and the plasma chamber.

[0003] Different conditions within the plasma chamber (such as gas type, gas pressure, gas flow rate, wafer temperature, etc.) result in varying impedances at the RF input of the plasma chamber. An RF source generates RF power, which is transmitted to an RF matching network via a suitable RF connection (e.g., an RF coaxial cable). The matching network adjusts its internal component settings to deliver the maximum amount of RF power generated by the RF generator to the plasma chamber. The gaseous plasma generated by the RF power fed into the chamber then reacts with the wafer surface, etching or depositing material onto the wafer.

[0004] In deposition systems, the conditions within the plasma chamber vary slightly each time a process is run on a semiconductor wafer. This may be due to variations in the conditions of the plasma chamber walls, as byproducts of the process gases coat the walls. These variations in plasma chamber conditions, in turn, affect the process, leading to inter-wafer variations in the thickness of the deposited film. To overcome these variations, the plasma chamber undergoes regular maintenance to keep the deposited film thickness within acceptable limits. However, frequent preventative maintenance cycles can reduce the uptime of the processing equipment and impact the system's operating costs. Summary of the Invention

[0005] In one aspect, the present invention relates to a system for regulating radio frequency (RF) power delivered to a plasma chamber, the system comprising: a matching network configured to be coupled between an RF source and a plasma chamber; one or more memory devices configured to: store first association data based on film thickness values ​​and corresponding matching network values ​​for each film thickness value, wherein each matching network value is a value, position, or setting for parameters associated with the matching network; and store second association data based on film thickness values ​​and corresponding RF power settings for the RF source for each film thickness value; and control circuitry operatively coupled to the one or more memory devices, the control circuitry configured to: for current wafer operation of a semiconductor wafer, determine current matching network values ​​for parameters associated with the matching network; use the current matching network values ​​and the first association data to determine a current film thickness of the semiconductor wafer for the current wafer operation; use the current film thickness and the second association data to determine a corresponding RF power setting for the RF source; and send a control signal to the RF source to regulate the RF power output by the RF source based on the corresponding RF power setting, thereby achieving a new film thickness for the semiconductor wafer for the current wafer operation within a desired film thickness range.

[0006] In another aspect, a method for adjusting the RF power delivered to a plasma chamber is disclosed, the method comprising: storing or accessing first correlation data based on film thickness values ​​and corresponding matching network values ​​for each film thickness value, wherein each matching network value is a value for parameters associated with a matching network connected between an RF source and a plasma chamber; storing or accessing second correlation data based on film thickness values ​​and corresponding RF power settings for the RF source for each film thickness value; determining, for a current wafer operation of a semiconductor wafer, current matching network values ​​for parameters associated with the matching network; using the current matching network values ​​and the first correlation data, determining a current film thickness for the semiconductor wafer in the current wafer operation; using the current film thickness and the second correlation data, determining a corresponding RF power setting for the RF source; and adjusting the RF power output from the RF source based on the corresponding RF power setting to achieve a new film thickness for the semiconductor wafer in the current wafer operation within a desired film thickness range.

[0007] In another aspect, a system for adjusting RF power delivered to a plasma chamber is disclosed, the system comprising: a matching network configured to be coupled between an RF source and a plasma chamber; one or more memory devices configured to store associated data based on: film thickness values ​​and corresponding matching network values ​​for each film thickness value, wherein each matching network value is a value for parameters associated with the matching network; and a corresponding RF power setting for the RF source for each film thickness value; and control circuitry operatively coupled to the one or more memory devices, the control circuitry being configured to: for a current wafer operation of a semiconductor wafer, determine a current matching network value for parameters associated with the matching network; determine a corresponding RF power setting using the current matching network value and the associated data; and send a control signal to adjust the RF power delivered to the plasma chamber based on the corresponding RF power setting, thereby achieving a new film thickness for the semiconductor wafer in the current wafer operation within a desired film thickness range. Attached Figure Description

[0008] This disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0009] Figure 1 This is a block diagram of an embodiment of a semiconductor processing system, including a system for controlling a matching network for the semiconductor processing system;

[0010] Figure 2 This is a block diagram of an embodiment of a semiconductor processing system with an L-configuration matching network;

[0011] Figure 3 This is a block diagram of an embodiment of a semiconductor processing system with a π-configuration matching network;

[0012] Figure 4 This is a block diagram of an embodiment of an electronic circuit for providing variable capacitance using an electronically variable capacitor having two capacitor arrays;

[0013] Figure 5 This is a block diagram of an embodiment of a variable capacitor system for switching on and off an electronic variable capacitor using discrete capacitors.

[0014] Figure 6 This is a flowchart illustrating an embodiment of a process for matching impedance by changing a variable capacitor;

[0015] Figure 7 This is a graph showing the correlation between the film thickness and the capacitor position of the first variable capacitor in a matching circuit according to one embodiment.

[0016] Figure 8 This is a graph showing the correlation between the film thickness and the capacitor position of the second variable capacitor in a matching circuit according to one embodiment.

[0017] Figure 9 This is a flowchart of a method for adjusting the RF power delivered to a plasma chamber according to one embodiment. Detailed Implementation

[0018] The following description of preferred embodiments is merely exemplary in nature and is in no way intended to limit one or more inventions. The description of illustrative embodiments is intended to be read in conjunction with the accompanying drawings, which are considered an integral part of the entire written description. Any references to directions or orientations in the description of the exemplary embodiments disclosed herein are merely for convenience of description and are not intended to limit the scope of the invention in any way. The discussion herein describes and illustrates some possible non-limiting combinations of features that may exist alone or in other combinations of features. Furthermore, as used herein, the term “or” will be interpreted as a logical operator that produces a true result whenever one or more of its operands are true. Additionally, as used herein, the phrase “based on” will be interpreted as meaning “at least partially based on” and is therefore not limited to the interpretation of “fully based on”.

[0019] The features of this invention can be implemented in software, hardware, firmware, or a combination thereof. The computer program described herein is not limited to any particular embodiment and can be implemented in an operating system, application, foreground or background process, driver, or any combination thereof. The computer program can execute on a single computer or server processor or multiple computers or server processors.

[0020] The processor described herein can be any central processing unit (CPU), microprocessor, microcontroller, computing or programmable device or circuit configured to execute computer program instructions (e.g., code). Various processors can be embodied in any suitable type of computer and / or server hardware (e.g., desktop computers, laptops, tablets, cellular phones, etc.) and can include all common auxiliary components required to form a functional data processing device, including but not limited to buses, software and data memory (e.g., volatile and non-volatile memory), input / output devices, graphical user interfaces (GUIs), removable data storage, and wired and / or wireless communication interface devices (including Wi-Fi, Bluetooth, LAN, etc.).

[0021] The computer-executable instructions or programs (e.g., software or code) and data described herein may be programmed into and tangibly embodied in a non-transitory computer-readable medium accessible and retrieved by the corresponding processor described herein, wherein the processor is configured and instructed to perform desired functions and processes by executing the instructions encoded in the medium. A device embodying a programmable processor configured as such non-transitory computer-executable instructions or programs may be referred to as a “programmable device” or “device,” and multiple programmable devices communicating with each other may be referred to as a “programmable system.” It should be noted that the non-transitory “computer-readable medium” described herein may include, but is not limited to, any suitable volatile or non-volatile memory, including random access memory (RAM) and its various types, read-only memory (ROM) and its various types, USB flash memory, and magnetic or optical data storage devices (e.g., internal / external hard disks, floppy disks, magnetic tape CD-ROMs, DVD-ROMs, optical discs, ZIP™ drives, Blu-ray discs, etc.), which may be written to and / or read by a processor operatively connected to the medium.

[0022] In some embodiments, the invention may be embodied in the form of computer-implemented processes and apparatus, such as processor-based data processing and communication systems or computer systems for performing those processes. The invention may also be embodied in the form of software or computer program code in a non-transitory computer-readable storage medium, which, when loaded into and executed by the data processing and communication system or computer system, configures the processor to create specific logic circuitry configured to implement the processes.

[0023] The term "range" is used throughout as a concise expression to describe each value within that range. Any value within the range may be chosen as the endpoint of the range. Furthermore, all references cited herein are incorporated herein by reference in their entirety. In the event of any conflict between definitions in this disclosure and those in the cited references, this disclosure shall prevail.

[0024] In the following description, where circuits are shown and described, those skilled in the art will recognize that, for clarity, not all peripheral circuits or components are shown in the drawings or described in the specification. Furthermore, the terms "connection" and "operably connected" can refer to a direct or indirect connection between two components of the circuit.

[0025] The following description of preferred embodiments is merely exemplary in nature and is in no way intended to limit one or more inventions. The description of illustrative embodiments is intended to be read in conjunction with the accompanying drawings, which are considered an integral part of the entire written description. Any references to directions or orientations in the description of the exemplary embodiments disclosed herein are merely for convenience of description and are not intended to limit the scope of the invention in any way. Relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “upward,” “downward,” “left,” “right,” “top,” “bottom,” “front,” and “rear,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the orientation as described subsequently or as shown in the discussed drawings. These relative terms are for convenience of description only and do not require the device to be constructed or operated in a particular orientation unless expressly indicated otherwise. Terms such as “attach,” “attach,” “connect,” “link,” “interconnect,” “fixed,” and other similar terms refer to a relationship in which structures are directly or indirectly fixed or attached to each other through intermediate structures, and to movable or rigid attachments or relationships, unless expressly stated otherwise. The discussion herein describes and illustrates some possible non-limiting combinations of features that may exist alone or in other combinations of features. Furthermore, as used herein, the term "or" will be interpreted as a logical operator that produces a true result whenever one or more of its operands are true. Additionally, as used herein, the phrase "based on" will be interpreted as meaning "at least partially based on," and is therefore not limited to the interpretation of "fully based on."

[0026] The term "range" is used throughout as a concise expression to describe each value within that range. Any value within the range may be chosen as the endpoint of the range. Furthermore, all references cited herein are incorporated herein by reference in their entirety. In the event of any conflict between definitions in this disclosure and those in the cited references, this disclosure shall prevail.

[0027] Semiconductor processing system

[0028] refer to Figure 1 This document illustrates a semiconductor device processing system 85 utilizing an RF source 15. System 85 includes an RF source 15 and a semiconductor processing tool 86. The semiconductor processing tool 86 includes a matching network 11 and a plasma chamber 19. In other embodiments, the RF source 15 or other power source may be formed part of the semiconductor processing tool. For the semiconductor processing systems and components thereof discussed herein (e.g., matching networks, EVC, and EVRE), the applicant incorporates in its entirety from U.S. Publication No. 2024 / 0177970.

[0029] The semiconductor device can be a microprocessor, a memory chip, or other type of integrated circuit or device. A silicon wafer 27 can be placed in a plasma chamber 19, which is configured to deposit or etch material layers onto or from the wafer 27. Plasma processing involves exciting a gas mixture by imparting energy to the gas molecules through the introduction of RF energy. This gas mixture is typically contained within a vacuum chamber (plasma chamber 19), and the RF energy is typically introduced into the plasma chamber 19 via electrodes. Therefore, the plasma can be excited by coupling RF power from an RF source 15 into the plasma chamber 19 to perform deposition or etching.

[0030] Matching Network

[0031] In a typical plasma process, RF source 15 generates radio frequency power—typically in the range of 3 kHz to 300 GHz—and this power is transmitted to plasma chamber 19 via RF cables and networks. To provide efficient power transmission from RF source 15 to plasma chamber 19, an intermediate circuit is used to match the fixed impedance of RF source 15 to the variable impedance of plasma chamber 19. This intermediate circuit is commonly referred to as an RF impedance matching network, or more simply as a matching network or matching circuit. The purpose of matching network 11 is to transform the variable plasma impedance to a value that more closely matches the fixed impedance of RF source 15. An example of this matching network is provided in commonly owned U.S. Patent Application No. 14 / 669568 (the disclosure of which is incorporated herein by reference in its entirety).

[0032] Figure 2 This is a block diagram of an embodiment of a semiconductor processing system 85 having a semiconductor processing tool 86 including an L-configuration matching network 11. The matching network 11 has an RF input 13 connected to an RF source 15 and an RF output 17 connected to a plasma chamber 19. An RF input sensor 21 may be connected between the matching network 11 and the RF source 15. An RF output sensor 49 may be connected between the matching network 11 and the plasma chamber 19, enabling monitoring of the RF output from the impedance matching network and the plasma impedance presented by the plasma chamber 19. Some embodiments may include only one of the input sensor 21 and the output sensor 49. The function of these sensors 21 and 49 is described in more detail below.

[0033] As described above, the matching network 11 helps maximize the amount of RF power transmitted from the RF source 15 to the plasma chamber 19 by matching the impedance at the RF input 13 to the fixed impedance of the RF source 15. The matching network 11 may consist of a single module within a single housing designed for electrical connection to the RF source 15 and the plasma chamber 19. In other embodiments, components of the matching network 11 may be located in different housings, some components may be external to the housing, and / or some components may share the housing with external components of the matching network.

[0034] The plasma within plasma chamber 19 typically experiences some fluctuations beyond operational control, resulting in a variable impedance presented by plasma chamber 19. Since the variable impedance of plasma chamber 19 cannot be fully controlled, an impedance matching network can be used to create impedance matching between plasma chamber 19 and RF source 15. Furthermore, the impedance of RF source 15 can be fixed at a set value through the specific design of RF source 15. Although the fixed impedance of RF source 15 may experience minor fluctuations during use due to factors such as temperature or other environmental changes, it is still considered a fixed impedance for impedance matching purposes because the fluctuations do not cause a significant change in the fixed impedance from the initially set impedance value. Other types of RF source 15 can be designed such that the impedance of RF source 15 can be set during or after use. The impedance of this type of RF source 15 is still considered fixed because it can be controlled by the user (or at least by a programmable controller), and the impedance set value can be known at any time during operation, thus effectively making the set value a fixed impedance.

[0035] RF source 15 may include an RF generator configured to generate RF signals at an appropriate frequency and power for use in processes performed within plasma chamber 19. RF source 15 may be electrically connected to the RF input 13 of matching network 11 using a coaxial cable, which will have the same fixed impedance as RF source 15 for impedance matching purposes.

[0036] The plasma chamber 19 includes a first electrode 23 and a second electrode 25, and in a process known in the art, the first electrode 23 and the second electrode 25, in combination with a suitable control system (not shown) and plasma in the plasma chamber 19, are capable of one or both of the following: depositing material onto the wafer 27 and etching material from the wafer 27.

[0037] In an exemplary embodiment, the matching network 11 includes a series variable capacitor 31, a shunt variable capacitor 33, and a series inductor 35 to form an "L"-shaped matching network. The parallel variable capacitor 33 is shown as shunt to a reference potential, which in this embodiment is ground 40.

[0038] Alternatively, matching network 11 can be configured with other matching network configurations, such as a "T" type configuration or a "π" or "π" type configuration, as follows: Figure 3 As shown. In some embodiments, the variable capacitor and switching circuitry described below can be included in any configuration suitable for the matching network.

[0039] In an exemplary embodiment, and with reference to Figure 2 Each of the series variable capacitor 31 and the shunt variable capacitor 33 can be an electronic variable capacitor (EVC), as described in U.S. Patent No. 7,251,121, whereby the EVC is effectively formed as a capacitor array consisting of a plurality of discrete capacitors. The series variable capacitor 31 is connected in series between RF input 13 and RF output 17 (and also in parallel between RF source 15 and plasma chamber 19). The shunt variable capacitor 33 is connected between RF input 13 and ground 40. In other configurations, the shunt variable capacitor 33 can be connected in parallel between RF output 19 and ground 40. Other configurations can also be implemented without departing from the functionality of the matching network. In other configurations, the shunt variable capacitor 33 can be connected in parallel between a reference potential and one of RF input 13 and RF output 19.

[0040] A series variable capacitor 31 is connected to a series RF choke and filter circuit 37 and to a series driver circuit 39. Similarly, a shunt variable capacitor 33 is connected to a shunt RF choke and filter circuit 41 and a shunt driver circuit 43. Each of the series driver circuit 39 and the shunt driver circuit 43 is connected to a control circuit 45, which is configured with a suitable processor and / or signal generation circuitry to provide input signals for controlling the series driver circuit 39 and the shunt driver circuit 43. A power supply 47 is connected to each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45 to provide operating power to each of these components at the designed current and voltage. The voltage level provided by the power supply 47, and therefore the voltage level adopted by each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45 to perform a corresponding specified task, is a matter of design selection. In other embodiments, various electronic components may be used to enable the control circuit 45 to send commands to the variable capacitor. Furthermore, although the driver circuits 39, 43 and the RF chokes and filters 37, 41 are shown as separate from the control circuit 45, these components can also be considered as part of the control circuit 45. The control circuit 45 may include or be coupled to a memory 46. The memory 46 may store instructions for the control circuit 45 and other data that the control circuit 45 can utilize.

[0041] In an exemplary embodiment, control circuitry 45 includes a processor. The processor can be any type of suitably programmed processing device configured to execute computer program instructions (e.g., code), such as a computer or microprocessor. The processor can be embodied in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, cellular phone, etc.) and can include all common auxiliary components required to form a functional data processing device, including but not limited to buses, software and data storage (e.g., volatile and non-volatile memory), input / output devices, graphical user interfaces (GUIs), removable data storage, and wired and / or wireless communication interface devices, including Wi-Fi, Bluetooth, LAN, etc. The processor in the exemplary embodiment is configured with specific algorithms to enable the matching network 11 to perform the functions described herein.

[0042] By using the combination of series variable capacitor 31 and shunt variable capacitor 33, the combined impedance of matching network 11 and plasma chamber 19 can be controlled by control circuit 45, series driver circuit 39 and shunt driver circuit 43 to match or at least substantially match the fixed impedance of RF source 15.

[0043] Control circuit 45 operates matching network 11 by receiving multiple inputs from sources such as RF input sensor 21 and series and shunt variable capacitors 31, 33, performing necessary calculations to determine the variations in series and parallel variable capacitors 31, 33, and issuing commands to series and parallel variable capacitors 31, 33 to create impedance matching. Control circuit 45 is a type of control circuit commonly used in semiconductor manufacturing processes and is therefore known to those skilled in the art. Any differences in control circuit 45 compared to prior art control circuits arise in programming differences to account for the speed at which matching network 11 can perform switching and impedance matching of variable capacitors 31, 33.

[0044] Each of the series and shunt RF choke and filter circuits 37, 41 is configured such that a DC signal can pass between the series and shunt driver circuits 39, 43 and the corresponding series and shunt variable capacitors 31, 33, while the RF signal from the RF source 15 is blocked to prevent RF signal leakage to the outputs of the series and shunt driver circuits 39, 43 and the output of the control circuit 45. The series and parallel RF choke and filter circuits 37, 41 are of a type known to those skilled in the art.

[0045] Figure 3 This is a block diagram of an embodiment of the semiconductor processing system 85A, which has the same... Figure 2 The L-configuration matching network is relative to the π-configuration matching network 11A. For ease of understanding, this diagram omits [details missing]. Figure 2RF chokes and filters, driver circuits, and power supplies. Figure 3 Use and Figure 2 In the case of identical reference numerals in the accompanying drawings, it should be understood that the relevant parts may have the same reference numerals as those concerning... Figure 2 The features discussed are similar to those discussed.

[0046] The most significant difference between the L-configuration and the π-configuration is that the L-configuration utilizes a series capacitor 31 and a shunt capacitor 33, while the π-configuration utilizes two shunt capacitors 31A and 33A. However, the control circuit 45 can change the capacitance of these shunt variable capacitors 31A and 33A to induce impedance matching. As mentioned above, each of these shunt variable capacitors 31A and 33A can be an EVC. They can be controlled by a choke, filter, and driver, similar to the above description. Figure 2 The methods of discussion.

[0047] EVC capacitor array

[0048] Figure 4 An electronic circuit 650 for providing variable capacitance according to one embodiment is shown. Circuit 650 utilizes an EVC 651 comprising two capacitor arrays 651a and 651b. The first capacitor array 651a may include a plurality of first discrete capacitors, each having a first capacitance value. The second capacitor array 651b may include a plurality of second discrete capacitors, each having a second capacitance value. The first capacitance value differs from the second capacitance value, allowing EVC 651 to provide both coarse and fine control over the capacitance generated by EVC 651. The first capacitor array 651a and the second capacitor array 651b are connected in parallel between a signal input 613 and a signal output 630.

[0049] The first and second capacitance values ​​can be any values ​​sufficient to provide the desired total capacitance for the EVC651. In one embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0050] Electronic circuit 650 also includes control circuit 645, which may have features similar to control circuit 45 discussed above. Control circuit 645 is operatively coupled to a first capacitor array 651a and a second capacitor array 651b via command input 629. In an exemplary embodiment, command input 629 has a direct electrical connection to capacitor arrays 651a and 651b, but in other embodiments, this connection may be indirect. The coupling of control circuit 645 to capacitor arrays 651a and 651b will be discussed in further detail below.

[0051] The control circuit 645 is configured to change the variable capacitance of EVC651 by controlling the on and off states of (a) each of the first plurality of discrete capacitors 651a and (b) each of the second plurality of discrete capacitors 651b. As described above, the control circuit 645 may have [specific characteristics related to...]. Figure 2 and Figure 3 The control circuit 45 has similar features to those described. For example, the control circuit 645 can receive inputs from capacitor arrays 651a and 651b, perform calculations to determine changes to capacitor arrays 651a and 651b, and send commands to capacitor arrays 651a and 651b to change the capacitance of EVC651. Figure 4 The EVC651 can include multiple electronic switches. Each electronic switch can be configured to activate and deactivate one or more discrete capacitors.

[0052] and Figure 2 and Figure 3 Similar to control circuit 45, control circuit 645 can also be connected to driver circuit 639 and RF choke and filter circuit 637. Control circuit 645, driver circuit 639, and RF choke and filter circuit 637 can have the same characteristics as... Figure 2 and Figure 3The capabilities discussed are similar. In an exemplary embodiment, a driver circuit 639 is operatively coupled between a control circuit 645 and a first capacitor array 651a and a second capacitor array 651b. The driver circuit 639 is configured to change the variable capacitance based on a control signal received from the control circuit 645. An RF filter 637 is operatively coupled between the driver circuit 639 and the first and second capacitor arrays 651a, 651b. In response to a control signal sent by the control unit 645, the driver circuit 639 and the RF filter 637 are configured to send a command signal to a command input 629. The command signal is configured to change the variable capacitance by instructing at least one electronic switch to activate or deactivate (a) at least one of a first plurality of discrete capacitors or (b) at least one of a second plurality of discrete capacitors.

[0053] In an exemplary embodiment, the driver circuit 639 is configured to turn a high-voltage source on or off in less than 15 microseconds, the high-voltage source controlling an electronic switch of each of the first and second capacitor arrays to change the variable capacitance. However, the EVC651 can be switched by any means or speed discussed in this application.

[0054] Control circuit 645 can be configured to calculate coarse and fine capacitance values ​​to be provided by the respective capacitor arrays 651a, 651b. In an exemplary embodiment, control circuit 645 is configured to calculate the coarse capacitance value to be provided by controlling the on and off states of the first capacitor array 651a. Furthermore, control circuitry is configured to calculate the fine capacitance value to be provided by controlling the on and off states of the second capacitor array 651b. In other embodiments, capacitor arrays 651a, 651b can provide alternative capacitance levels. In other embodiments, EVC can utilize additional capacitor arrays.

[0055] Figure 4 The EVC651 can be used in most systems that require variable capacitance. For example, the EVC651 can be used as... Figure 2 The series EVC and / or branch EVC in the matching network 11, or used as Figure 3 One or two of the branch EVCs in the matching network 11A. It is generally desirable that the difference between the capacitance values ​​allows for both a sufficiently fine resolution of the total capacitance of the circuit and a wide range of capacitance values ​​to achieve better impedance matching at the input of the matching network, and the EVC651 allows this.

[0056] The EVC651 can also be used in systems or methods for manufacturing semiconductors, methods for controlling variable capacitors, and / or methods for controlling matching networks. Such methods may include changing at least one of a series variable capacitor and a shunt variable capacitor to determined series and shunt capacitor values, respectively. This change can be achieved by controlling the on / off state of each of a plurality of discrete capacitors for each of the series and shunt EVCs. In other embodiments, the EVC651 and circuit 650 can be used in other methods and systems to provide variable capacitors.

[0057] Connecting and disconnecting discrete capacitors to change the EVC capacitance

[0058] As described above, an EVC is a variable capacitor that can use multiple switches, each switch creating an open or short circuit, with a separate series capacitor to change the capacitance of the variable capacitor. The switches can be mechanical (such as relays) or solid-state (such as PIN diodes, transistors, or other switching devices). The following is a discussion of methods for configuring an EVC or other variable capacitor to provide varying capacitance.

[0059] In the case of what is sometimes referred to as an "accumulated setup" of EVC or other variable capacitors, the method of linearly increasing the capacitor value from a minimum starting point (all switches on) is to gradually increase the number of trimmer capacitors switched into the circuit. Once the maximum number of trimmer capacitors is connected to the circuit, a coarse trimmer capacitor is connected, and the trimmer capacitors are disconnected. This process begins by increasing the number of trimmer capacitors connected to the circuit until all trimmer and coarse trimmer capacitors are connected, at which point another coarse trimmer capacitor is connected and the trimmer capacitors are disconnected. This process can continue until all coarse and trimmer capacitors are connected.

[0060] In this embodiment, all fine-tuning capacitors have the same or substantially similar values, and all coarse-tuning capacitors have the same or substantially similar values. Furthermore, the capacitance value of a coarse-tuning capacitor is approximately equal to the combined capacitance value of all fine-tuning capacitors plus any additional fine-tuning capacitors in the circuit, thus achieving a linear increase in capacitance. However, the embodiment is not limited to this. The fine-tuning capacitors (and coarse-tuning capacitors) do not need to have the same or substantially similar values. Furthermore, the capacitance value of a coarse-tuning capacitor does not need to be equal to the combined capacitance value of all fine-tuning capacitors plus any additional fine-tuning capacitors. In one embodiment, the coarse capacitance value and the fine capacitance value have a ratio substantially similar to 10:1. In another embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0061] An example of the aforementioned embodiment in an ideal setup is that the fine-tuning capacitor is 1pF and the coarse-tuning capacitor is 10pF. In this ideal setup, the capacitance is 0pF when all switches are open. When the first switch is closed, there is 1pF in the circuit. When the second switch is closed, there is 2pF in the circuit, and so on, until all nine fine-tuning switches are closed, resulting in 9pF. Then, the first 10pF capacitor is switched into the circuit, and the nine fine-tuning switches are turned on, resulting in a total capacitance of 10pF. The fine-tuning capacitor is then switched from 11pF to 19pF in the circuit. Another coarse-tuning capacitor can then be switched into the circuit, and all fine-tuning capacitors can be switched out of the circuit, thus providing 20pF. This process can be repeated until the desired capacitance is achieved.

[0062] This can be taken a step further. Using the previous example with nine 1pF capacitors and nine 10pF capacitors, the variable capacitor circuit can have even larger values ​​(100pF) to connect and disconnect the circuit. This would allow the previous capacitor array to rise to 99pF, and then the 100pF capacitors could be used for the next increment. This can be repeated further with larger increments and can also be used with any counting system. Depending on the accumulation settings, the total capacitance of the variable capacitor is increased by connecting more coarse capacitors or more fine capacitors than already connected without disconnecting the already connected coarse capacitors. Furthermore, when the total variable capacitance increases and the control circuit does not connect more coarse capacitors than already connected, the control circuit connects more fine capacitors than already connected without disconnecting the already connected fine capacitors.

[0063] Figure 5 This is a schematic diagram based on the cumulatively configured variable capacitor system 655. This diagram is used in conjunction with... Figure 4 In the case of identical reference numerals in the accompanying drawings, it should be understood that the relevant parts may have the same reference numerals as those in the drawings. Figure 4 Similar features to those discussed in the text. The variable capacitor system 655 includes a variable capacitor 651 for providing variable capacitance. The variable capacitor 651 has an input 613 and an output 630. The variable capacitor 651 includes a plurality of discrete capacitors 653 operably connected in parallel. The plurality of capacitors 653 includes a first (fine) capacitor 651a and a second (coarse) capacitor 651B. Furthermore, the variable capacitor 651 includes a plurality of switches 661. In the switches 661, one switch is operably connected in series with each of the plurality of capacitors to connect and disconnect each capacitor, thereby enabling the variable capacitor 651 to provide a varying total capacitance. The variable capacitor 651 has a variable total capacitance, which increases when the discrete capacitors 653 are connected and decreases when the discrete capacitors 653 are disconnected.

[0064] Switch 661 can be coupled to switch driver circuit 639 for driving the switch to turn on and off. Variable capacitor system 655 may also include control unit 645 operatively coupled to variable capacitor 651. Specifically, control unit 645 may be operatively coupled to driver circuit 639 for instructing driver circuit 639 to switch one or more of switches 661, thereby turning on or off one or more of capacitors 653. In one embodiment, control unit 645 may form part of a control unit that controls the variable capacitor, such as a control unit that instructs a variable capacitor in a matching network to change its capacitance to achieve impedance matching. Driver circuit 639 and control unit 645 may have the same characteristics as referenced above. Figure 4 The characteristics discussed are similar, and therefore the RF choke and filter described above can also be utilized.

[0065] In one embodiment, control circuitry 645 is configured to determine a desired coarse capacitance of a coarse capacitor; determine a desired fine capacitance of a fine capacitor; and, after calculating the desired coarse and fine capacitances, change the total variable capacitance by connecting or disconnecting at least one of the fine capacitors; and connect or disconnect at least one of the coarse adjustment capacitors. In other embodiments, coarse and fine adjustments may occur at different stages.

[0066] In an exemplary embodiment, the first capacitor 651a is a fine capacitor, each fine capacitor having a capacitance value substantially similar to the fine capacitance value, and the second capacitor 651b is a coarse capacitor, each coarse capacitor having a capacitance value substantially similar to the coarse capacitance value, which is greater than the fine capacitance value. For the purposes of this application, a capacitance is considered substantially similar to other values ​​if one value is not more or less than 15 percent (15%) larger or smaller than another value.

[0067] The variable capacitor system 655 can form part of an impedance matching network, including but not limited to... Figures 1 to 3 The impedance matching network. Variable capacitor systems can also form impedance matching networks for controlling (e.g., Figures 1 to 3 This is part of a method for providing an impedance matching network. The method may include providing a matching network, including: determining the increased total capacitance to be provided by one of the EVCs; and increasing the variable total capacitance of that EVC by connecting more coarse capacitors or more fine capacitors than already connected coarse capacitors without disconnecting the already connected coarse capacitors. Furthermore, the variable capacitance system may be incorporated into methods and systems for manufacturing semiconductors (see [link to relevant documentation]). Figures 1 to 3 ).

[0068] Using the variable capacitor system with impedance matching networks discussed above offers several advantages over other methods. An alternative to the above method is to make all capacitor values ​​different, where the first value equals the minimum desired change in capacitance. Then, as all capacitors are connected, each successive capacitor value is increased so that the capacitance change doubles from the previous value until the maximum desired capacitance value. This approach can result in achieving the same resolution and range using fewer capacitors connected and disconnected in the circuit. However, a potential problem with this setup is that once a capacitor reaches a certain value, the voltage and / or current on that particular capacitor or the current on the switch may exceed what is allowed by specifications. This forces the EVC to use multiple capacitors in parallel for each switch with lower values. This problem is particularly severe when using high voltages and / or currents. The cumulative setup discussed above avoids this level of stress on its capacitors and switches by connecting additional capacitors instead of replacing lower-capacitance capacitors with higher-capacitance ones.

[0069] Determine the capacitance value to achieve matching.

[0070] Figure 6 This is a flowchart illustrating a process 500A for impedance matching according to one embodiment. The matching network may include components similar to those discussed above. In one embodiment, utilizing... Figure 2 The matching network. In Figure 6 In the first step of exemplary process 500A, the input impedance at RF input 13 is determined (step 501A). The input impedance is based on the RF input parameters detected at RF input 13 by RF input sensor 21. RF input sensor 21 can be any sensor configured to detect the RF input parameters at RF input 13. The input parameters can be any parameter measurable at RF input 13, including voltage, current, or phase at RF input 13. In an exemplary embodiment, RF input sensor 21 detects the voltage, current, and phase at RF input 13 of matching network 11. Based on the RF input parameters detected by RF input sensor 21, control circuitry 45 determines the input impedance.

[0071] Next, control circuitry 45 determines the plasma impedance presented by plasma chamber 19 (step 502A). In one embodiment, the plasma impedance determination is based on the input impedance (determined in step 501A), the capacitance of series EVC 31, and the capacitance of shunt EVC 33. In other embodiments, plasma impedance determination can be performed using an output sensor 49 operatively coupled to the RF output, configured to detect RF output parameters. RF output parameters can be any parameters measurable at RF output 17, including voltage, current, or phase at RF output 17. RF output sensor 49 can detect the output parameters at RF output 17 of matching network 11. Based on the RF output parameters detected by RF output sensor 21, control circuitry 45 can determine the plasma impedance. In other embodiments, plasma impedance determination can be based on both RF output parameters and RF input parameters.

[0072] Once the variable impedance of plasma chamber 19 is known, control circuit 45 can determine the changes to one or both of the variable capacitors in series EVC31 and parallel EVC33 for impedance matching purposes. Specifically, control circuit 45 determines a first capacitance value for the series variable capacitor and a second capacitance value for the parallel variable capacitor (step 503A). These values ​​represent new capacitance values ​​for series EVC31 and parallel EVC33 to achieve impedance matching or at least basic impedance matching. In an exemplary embodiment, the determination of the first and second capacitance values ​​is based on the variable plasma impedance (determined in step 502A) and the fixed RF source impedance.

[0073] Once the first and second capacitance values ​​are determined, control circuit 45 generates a control signal to change at least one of the series variable capacitor and the shunt variable capacitor to the first and second capacitance values, respectively (step 504A). This is completed at approximately t = -5 μsec. The control signal instructs the switching circuit to change the variable capacitor of one or both of the series EVC31 and the shunt EVC33.

[0074] Compared to the approximately 1-2 seconds required for a matching network using VVC, this change in EVC31, 33 takes a total of approximately 9-11 microseconds. Once the switching to different variable capacitors is complete, there is a waiting period as the additional discrete capacitors constituting the EVC are added to the circuit and charged. This part of the matching tuning process takes approximately 55 μsec. Finally, the RF power distribution 403 is shown to decrease from approximately 380 mV peak-to-peak to approximately 100 mV peak-to-peak just before t=56 microseconds. This decrease in the RF power distribution 403 represents a decrease in the reflected power 407, and it occurs within a time period of approximately 10 microseconds, at which point the matching tuning process is considered complete.

[0075] Changing the series and shunt variable capacitors can include sending control signals to series driver circuit 39 and shunt driver circuit 43 to control the series and shunt variable capacitors, respectively, where series driver circuit 39 is operatively connected to series EVC 31 and shunt driver circuit 43 is operatively connected to shunt EVC 43. When EVCs 31 and 33 are switched to their desired capacitance values, the input impedance can be matched to a fixed RF source impedance (e.g., 50 ohms), resulting in impedance matching. If insufficient impedance matching is not achieved due to fluctuations in plasma impedance, the 500A process can be repeated once or multiple times to achieve impedance matching, or at least basic impedance matching.

[0076] Using matching network 11, for example Figure 2 The input impedance of the matching network shown can be expressed as follows:

[0077]

[0078] Among them, Z in It is the input impedance, Z P It is plasma impedance, Z L It is the impedance of the series inductor, Z series It is a series EVC impedance, and Z shunt This is the shunt EVC impedance. In an exemplary embodiment, the input impedance (Z) is determined using the RF input sensor 21. in The control circuit knows the EVC impedance (Z) at any given time. series and Z shunt This is because the control circuit is used to command the various discrete capacitors in each of the series and branch EVCs to turn on or off. Additionally, the series inductor impedance (Z...) L The values ​​are fixed. Therefore, the system can use these values ​​to solve for the plasma impedance (Z). P ).

[0079] Based on this determined plasma impedance (Z) P ) and the known desired input impedance ( (It is typically 50 ohms) and the known series inductor impedance (Z) L The system can determine the new series EVC impedance. ) and branch EVC impedance ( ).

[0080]

[0081] Based on the newly calculated series EVC variable impedance ( ) and branch EVC variable impedance ( The system can then determine new capacitance values ​​for the series variable capacitor (first capacitance value) and the shunt variable capacitor (second capacitance value). Impedance matching can be achieved when these new capacitance values ​​are used with the series EVC31 and the shunt EVC33, respectively.

[0082] The exemplary method of calculating the desired first and second capacitance values ​​and achieving these values ​​in a single step is significantly faster than progressively moving the two EVCs to zero the error signal or to minimize the reflected power / reflection coefficient. In semiconductor plasma processing, where faster tuning schemes are desired, this method offers a significant improvement in the tuning speed of the matching network.

[0083] Note that this invention is not limited to the process described above for impedance matching. For example, the process may use a parameter matrix, as described in U.S. Publication No. 2024 / 0177970. Figure 7 A detailed discussion follows, the entire contents of which are incorporated herein by reference.

[0084] Those skilled in the art will recognize that for matching networks using EVC, several factors may contribute to the sub-millisecond elapsed time of the impedance matching process. These factors may include the power of the RF signal, the configuration and design of the EVC, the type of matching network used, and the type and configuration of the driver circuitry used. Other factors not listed may also contribute to the total elapsed time of the impedance matching process. Therefore, the entire matching tuning process for a matching network with EVC, from the start of the process (i.e., the adjustment required to achieve impedance matching is measured and calculated by the control circuitry) to the end of the process (the point in time when the efficiency of the RF power coupled to the plasma chamber increases due to impedance matching and the reduction in reflected power), is expected to take no more than about 500 μsec. Even within a matching tuning process on the order of 500 μsec, this process time still represents a significant improvement over matching networks using VVC.

[0085] Table 1 presents data comparing the operating parameters of an example of EVC and an example of VVC. It can be seen that, in addition to enabling fast switching of the matching network, EVC has several advantages:

[0086] Table 1

[0087]

[0088] As can be seen, in addition to the potentially fast switching capabilities achievable with EVC, EVC also introduces advantages in reliability, current handling, and size. Additional advantages of using the matching network and / or the switching circuitry itself for EVC include:

[0089] The disclosed matching network does not contain any moving parts, thus reducing the likelihood of mechanical failure to the point where it can be used as part of other complete circuits in the semiconductor manufacturing process. For example, a typical EVC can be formed from a robust ceramic substrate with copper metallization to form a discrete capacitor. The elimination of moving parts also increases resistance to breakdown due to thermal fluctuations during use.

[0090] Compared to VVC, EVC has a compact size, which allows for reduced weight and volume, saving valuable space within manufacturing facilities.

[0091] The design of EVCs introduces the ability to enhance the matching network to meet the specific design needs of particular applications. EVCs can be configured with custom capacitance ranges, one example being a nonlinear capacitance range. This custom capacitance range can provide better impedance matching over a wider range of processes. As another example, a custom capacitance range can provide higher resolution in certain regions of impedance matching. Custom capacitance ranges can also enable the generation of higher ignition voltages for easier plasma impaction.

[0092] Short matching tuning processes (~500 μsec or less) allow the matching network to better keep up with plasma variations during the fabrication process, thereby increasing plasma stability and resulting in more controlled power during the fabrication process.

[0093] Using EVC as a non-mechanical device in a matching network provides greater opportunities to fine-tune the control algorithm through programming.

[0094] Compared to VVC, EVC exhibits superior low-frequency (kHz) performance.

[0095] Controlled RF power for on-chip process improvement

[0096] As mentioned above, the conditions within the plasma chamber vary slightly each time the process is run on a semiconductor wafer. This may be due to byproducts of the process gas used to coat the plasma chamber walls, which can act like small capacitors. These variations in plasma chamber conditions can cause inter-wafer variations in the thickness of the deposited film. For example, increased coating on the chamber walls can cause the thickness of the deposited film to drop below acceptable levels.

[0097] Slight changes in plasma impedance caused by variations in plasma chamber conditions can be measured by one or more sensors configured to detect parameters (e.g., voltage, current, phase, or impedance) that indicate plasma impedance associated with the plasma chamber. The sensor can be located in various locations, including outside or inside the matching network. In one embodiment, the sensor is located at the input of the plasma chamber (or the output of the matching network), such as... Figure 2Sensor 49 and Figure 3 The sensor 49 is shown.

[0098] When the matching network responds to a slight change in the plasma chamber input impedance, the configuration of the internal components of the matching network changes slightly, and the parameters associated with the matching network also change slightly. Such internal components can be, for example, one or more variable reactance elements of the matching network, such as (electronic or mechanical) variable capacitors or (electronic or mechanical) variable inductors.

[0099] In one embodiment of the disclosed system, the capacitor positions (or settings) of variable capacitors in a matching network are monitored for multiple wafers, and a correlation between film thickness and capacitor positions is determined. This correlation can be determined for multiple processes, and each relationship can be stored separately in one or more memory devices (e.g., the internal memory of the matching network). Film thickness can be determined, for example, by measuring film thickness using one or more sensors. For instance, capacitor positions can be determined based on data available to control circuitry that controls one or more capacitors to achieve impedance matching.

[0100] Figure 7 and Figure 8 An example correlation between the film thickness (y-axis) of a film deposited on a wafer and the location of a capacitor (x-axis) is shown. Figure 7 The x-axis represents the capacitor position of the first variable capacitor (C1) in the matching network, while Figure 8 The x-axis represents the location of the second variable capacitor (C2) in the matching network. These two capacitors can be, for example... Figure 2 Variable capacitors 31, 33 or Figure 3 The variable capacitors are 31A and 33A, but the invention is not limited thereto (for example, the variable capacitors can be mechanically variable, the capacitors can be arranged differently from L or π topologies, and there can be different numbers of variable capacitors, such as only one).

[0101] In this example, Figure 1 and Figure 2The curves are normalized, where the initial capacitor position and film thickness (before the change in plasma impedance caused by process gas byproducts) are normalized to 1, 1, although such normalization is not required in this invention. For each graph, trend lines 71, 81 are provided for the relevant data points. From these graphs, it can be observed that for each capacitor (C1 and C2), the capacitor position decreases as the film thickness increases (due to, for example, process gas byproducts coating the plasma chamber walls). The capacitor position can represent, for example, a percentage of the maximum capacitance that the capacitor can provide. For example, for the first capacitor (C1), normalized position 1 could correspond to 40% of the maximum capacitance of the first variable capacitor, and normalized position 2 could correspond to 50% of the maximum capacitance of the second variable capacitor. In this example, in Figure 7 In this context, the capacitor position of 0.998 will correspond to (40%)*(0.998) or 39.92% of the maximum capacitance of the first variable capacitor.

[0102] Once the correlation is stored in memory, the control circuitry of the semiconductor device processing system (e.g., control circuitry 45 discussed above) can monitor the change in the capacitor position from the starting point (e.g., 1) and can use the capacitor position to determine the change in the thickness of the deposited film.

[0103] Furthermore, another correlation may exist in the system that links the film thickness of the deposited film to the RF power fed from the RF source to the RF matching network. This second correlation data can be based on the film thickness value and the corresponding RF power setting for the RF source for each film thickness value. For example, the second correlation data could indicate that a first power setting corresponds to a first film thickness, and a second power setting corresponds to a second film thickness.

[0104] These two correlations (capacitor location versus film thickness, and film thickness versus RF power) can be used to adjust the RF power so that the film thickness returns to an acceptable range. RF source (e.g. Figures 1 to 3 The amount of RF power entering the plasma chamber can be adjusted, for example, by increasing / decreasing the RF power, by increasing / decreasing the RF power on-time, or by increasing / decreasing the number of RF power on / off cycles.

[0105] It should be noted that while the above embodiments rely on the capacitor location, this is merely one example of values ​​that can be associated with the matching network that can be used with the present invention. Instead of the capacitor location, the present invention can use any “matching network value,” where a matching network value can be understood as any value, location, or setting of a parameter associated with the matching network. For example, a matching network value can be a voltage associated with the matching network (e.g., a DC voltage), such as the voltage at input 13 or output 17 of matching network 11. In other embodiments, a matching network value can be any voltage, current, phase, impedance, or harmonic (e.g., output V / I harmonic) value associated with the matching network.

[0106] In view of the foregoing, refer to Figures 1 to 3 In one embodiment, the invention can be understood as a system 29 for regulating the RF power delivered to the plasma chamber 19. When the currently deposited film thickness is below the desired film thickness range (e.g., due to byproducts of the process gas coating the walls of the plasma chamber), the system 29 can regulate the RF power (e.g., increase the RF power).

[0107] System 29 includes a matching network 11 configured to connect an RF source 15 and a plasma chamber 19. The system also includes one or more memory devices 46 configured to (a) store first correlation data based on film thickness values ​​and a corresponding matching network value for each film thickness value, wherein each matching network value is a value, location, or setting for parameters associated with the matching network (discussed in further detail above); and (b) store second correlation data based on film thickness values ​​and a corresponding RF power setting for the RF source for each film thickness value. The correlation data may be based on sensor measurements from previous wafer operations and may form portions of one or more lookup tables. The film thickness values ​​of the first correlation data may be the same as or overlap with the film thickness values ​​of the second correlation data. The first and / or second correlation data may include representations of (a) film thickness values ​​and corresponding matching network values ​​(e.g., ...). Figures 7 to 8 (a) and / or (b) a trend line relating the film thickness value to the corresponding RF power setting (e.g. Figures 7 to 8 Trend lines (71, 81), equations, functions, or machine learning algorithms.

[0108] Note that the first and second associated data can form part of a single set of associated data. The associated data can be based on (a) film thickness values ​​and corresponding matching network values ​​for each film thickness value, where each matching network value is a value of a parameter associated with the matching network; and (b) a corresponding RF power setting for the RF source for each film thickness value. Furthermore, the control circuitry can combine these steps instead of performing separate steps of determining the film thickness and then determining the power setting. For example, the control circuitry can be configured to: (a) determine current matching network values ​​for parameters associated with the matching network for the current wafer operation of the semiconductor wafer; (b) determine a corresponding RF power setting for the RF source using the current matching network values ​​and the associated data; and (c) send a control signal to the RF source to adjust the RF power output by the RF source based on the corresponding RF power setting, thereby achieving a new film thickness within a desired film thickness range for the semiconductor wafer in the current wafer operation.

[0109] System 29 also includes control circuitry 45 (part of or separate from the matching network) operatively coupled to one or more memory devices 46. Control circuitry 45 is configured to: (a) determine, for the current wafer operation of the semiconductor wafer, current matching network values ​​for parameters associated with the matching network; (b) determine, using the current matching network values ​​and first associated data, current film thickness of the semiconductor wafer for the current wafer operation; (c) determine, using the current film thickness and second associated data, a corresponding RF power setting for the RF source; and (d) send a control signal to the RF source to adjust the RF power output by the RF source based on the corresponding RF power setting, thereby achieving a new film thickness for the semiconductor wafer for the current wafer operation within a desired film thickness range.

[0110] In one embodiment, the corresponding RF power setting is a power setting sufficient to compensate for an undesirable decrease in the film thickness value and to bring the new film thickness within the desired film thickness range. In another embodiment, the corresponding RF power setting may include an adjustment value to the current RF power setting sufficient to bring the new film thickness within the desired film thickness range.

[0111] Note that the RF source and matching circuit of the present invention can be located in the same housing. Furthermore, they can be in separate housings but electrically connected (e.g., operatively coupled to the same control circuitry). Moreover, while a single control circuitry can control both the matching circuitry and the RF source, the invention is not limited thereto. In other embodiments, the control circuitry may include more than one control circuitry.

[0112] In another respect, the present invention can be a method for regulating the RF power delivered to a plasma chamber. Figure 9A flowchart of this method is provided. The method includes: (a) storing or accessing first association data based on film thickness values ​​and corresponding matching network values ​​for each film thickness value, wherein each matching network value is a value for parameters associated with a matching network connected between an RF source and a plasma chamber (operation 51); (b) storing or accessing second association data based on film thickness values ​​and corresponding RF power settings for the RF source for each film thickness value (operation 52); (c) determining current matching network values ​​for parameters associated with the matching network for the current wafer operation of the semiconductor wafer (operation 53); (d) determining the current film thickness of the semiconductor wafer for the current wafer operation using the current matching network values ​​and the first association data (operation 54); (e) determining the corresponding RF power settings for the RF source using the current film thickness and the second association data (operation 55); and (f) adjusting the RF power output from the RF source based on the corresponding RF power settings to achieve a new film thickness for the semiconductor wafer for the current wafer operation within a desired film thickness range (operation 56).

[0113] It is worth noting that while the above discussion focuses on regulating the power delivered to the plasma chamber by adjusting the power output of the radio frequency source (to prevent changes in film thickness), the present invention is not limited thereto. For example, regulating the RF power delivered to the plasma chamber may include adjusting the reactance of a variable reactance element (VRE) forming part of a matching network. For example, the VRE may be a variable capacitor (e.g., EVC), and adjusting the variable capacitor may be a means of regulating the RF power delivered to the plasma chamber. Such adjustment of a variable capacitor to prevent changes in film thickness is discussed in detail in U.S. Patent No. 11,393,659, the entire contents of which are incorporated herein by reference (see, for example, the section entitled "Controlling the Power of the Plasma Chamber").

[0114] The methods and systems discussed in this paper offer several advantages. For example, by compensating for conditions within the plasma chamber, the plasma chamber requires less periodic maintenance, thereby increasing the uptime of the processing equipment and the overall profitability of the system.

[0115] While the embodiments of the matching network discussed herein use L or π configurations, it should be noted that the required matching network can be configured in other matching network configurations, such as a "T" configuration. Unless otherwise stated, the variable capacitors, switching circuits, and methods discussed herein can be used with any configuration suitable for the matching network.

[0116] While the embodiments discussed herein use one or more variable capacitors in the matching network to achieve impedance matching, it should be noted that any variable reactance element can be used. A variable reactance element may include one or more discrete reactance elements, wherein the reactance element is a capacitor or inductor or a similar reactive device.

[0117] While the invention has been described with reference to specific examples including the currently preferred mode of carrying out the invention, those skilled in the art will understand that many variations and substitutions of the above-described system and techniques exist. It should be understood that other embodiments can be utilized and structural and functional modifications can be made without departing from the scope of the invention. Therefore, the spirit and scope of the invention should be broadly interpreted as set forth in the appended claims.

Claims

1. A system for regulating radio frequency (RF) power delivered to a plasma chamber, the system comprising: A matching network configured to connect the RF source and the plasma chamber; One or more memory devices configured to: The system stores first associated data, which is based on membrane thickness values ​​and corresponding matching network values ​​for each membrane thickness value. Each matching network value represents the value, location, or setting of parameters associated with the matching network. Store second associated data, which is based on the film thickness value and the corresponding RF power setting for the RF source for each film thickness value; and Control circuitry, operably coupled to one or more memory devices, is configured to: For the current wafer operation of the semiconductor wafer, determine the current matching network values ​​used for the parameters associated with the matching network; Using the current matching network value and the first association data, determine the current film thickness of the semiconductor wafer for the current wafer operation; Using the current film thickness and second correlation data, determine the corresponding RF power setting for the RF source; and A control signal is sent to the RF source to adjust the RF power output by the RF source based on the corresponding RF power setting, thereby achieving a new film thickness within the desired film thickness range for the semiconductor wafer currently in operation.

2. The system according to claim 1, wherein, The corresponding RF power setting includes settings or adjustments for the RF source or the matching network, which are sufficient to allow the RF power delivered to the plasma chamber to compensate for the undesirable reduction in the membrane thickness value and to ensure that the new membrane thickness is within the desired membrane thickness range.

3. The system according to claim 2, wherein, The decrease in the film thickness value is caused by byproducts of the processing gas coating the walls of the plasma chamber.

4. The system according to claim 1, wherein, The first and second correlation data are based on sensor measurements from previous wafer operations.

5. The system according to claim 1, wherein, The first associated data forms part of the first lookup table, and the second associated data forms part of the second lookup table.

6. The system according to claim 1, wherein, The membrane thickness value of the second associated data is based on the membrane thickness value of the first associated data.

7. The system according to claim 1: in, The first associated data includes trend lines, equations, functions, or machine learning algorithms representing the relationship between the film thickness value and the corresponding matching network value; or The second associated data includes trend lines, equations, functions, or machine learning algorithms representing the relationship between the film thickness value and the corresponding RF power setting.

8. The system according to claim 1, wherein, The matching network value is the location of the variable reactance element (VRE) that forms part of the matching network.

9. The system according to claim 8, wherein, The VRE is an electronically variable capacitor that includes multiple fixed capacitors connected in parallel.

10. The system according to claim 8, wherein, The VRE is a mechanically variable capacitor, and the matching network value represents the percentage of capacitance provided by the mechanically variable capacitor.

11. The system according to claim 1, wherein, The matching network value is the DC voltage at the input or output of the matching network.

12. The system according to claim 1, wherein, The matching network values ​​are values ​​for voltage, current, impedance, or harmonics associated with the matching network.

13. A method for regulating RF power delivered to a plasma chamber, the method comprising: Store or access first associated data, which is based on film thickness values ​​and corresponding matching network values ​​for each film thickness value, wherein each matching network value is a value of a parameter associated with a matching network connected between the RF source and the plasma chamber; Store or access second associated data, which is based on the film thickness value and the corresponding RF power setting for the RF source for each film thickness value; For the current wafer operation of the semiconductor wafer, determine the current matching network values ​​used for the parameters associated with the matching network; Using the current matching network value and the first association data, determine the current film thickness of the semiconductor wafer for the current wafer operation; Using the current film thickness and second correlation data, determine the corresponding RF power setting for the RF source; and The RF power output from the RF source is adjusted based on the corresponding RF power setting to achieve a new film thickness within the desired film thickness range for the semiconductor wafer currently in operation.

14. The method according to claim 13, wherein, The corresponding RF power setting includes settings or adjustments for the RF source or the matching network, which are sufficient to allow the RF power delivered to the plasma chamber to compensate for the undesirable reduction in the membrane thickness value and to ensure that the new membrane thickness is within the desired membrane thickness range.

15. The method according to claim 14, wherein, The decrease in the film thickness value is caused by byproducts of the processing gas coating the walls of the plasma chamber.

16. The method according to claim 13, wherein, The first and second correlation data are based on sensor measurements from previous wafer operations.

17. A system for regulating RF power delivered to a plasma chamber, the system comprising: A matching network configured to connect the RF source and the plasma chamber; One or more memory devices configured to store associated data based on: The film thickness value and the corresponding matching network value for each film thickness value, wherein each matching network value is a value of a parameter associated with the matching network; and For each film thickness value, the corresponding RF power setting for the RF source; and A control circuit, operably coupled to one or more memory devices, is configured to: For the current wafer operation of the semiconductor wafer, determine the current matching network values ​​used for the parameters associated with the matching network; Use the current matching network values ​​and associated data to determine the corresponding RF power settings; and A control signal is sent to adjust the RF power delivered to the plasma chamber based on the corresponding RF power setting, thereby achieving a new film thickness within the desired film thickness range for the semiconductor wafer currently in operation.

18. The system according to claim 17, wherein, The corresponding RF power setting includes settings or adjustments for the RF source or the matching network, which are sufficient to allow the RF power delivered to the plasma chamber to compensate for the undesirable reduction in the membrane thickness value and to ensure that the new membrane thickness is within the desired membrane thickness range.

19. The system according to claim 17, wherein, The control signal is sent to the RF source, and adjusting the RF power supplied to the plasma chamber includes adjusting the RF power output by the RF source.

20. The system according to claim 17, wherein, The control signal is sent to the matching network, and adjusting the RF power delivered to the plasma chamber includes adjusting the reactance of the variable reactance element (VRE) that forms part of the matching network.

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