A semiconductor device cleaning verification method and system
By employing a verification mechanism that combines fast testing and supplementary testing in semiconductor devices, and selecting an appropriate verification method based on the device scenario, the problem of poor cleaning verification effect in existing technologies is solved, and low-cost and efficient cleaning verification is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN EXX IND AUTOMATION CO LTD
- Filing Date
- 2026-07-01
- Publication Date
- 2026-07-31
AI Technical Summary
Existing cleaning verification methods for semiconductor manufacturing equipment are insufficient in their adaptability to production environments, resulting in poor verification results.
A verification mechanism that combines rapid testing and supplementary testing is adopted. The rapid testing scheme is selected based on the scenario information of the semiconductor device, including forward verification, reverse verification or bidirectional verification. The results of the rapid testing dynamically determine whether further supplementary testing is needed. For different error types, appropriate supplementary testing schemes are selected, such as intermediate state supplementary testing or false alarm supplementary testing.
By combining low-cost rapid testing with targeted supplementary testing, we can optimize the allocation of verification resources, reduce overall verification costs, improve the accuracy of verification results, and reduce false alarms.
Smart Images
Figure CN122494534A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing equipment control technology, and specifically to a method and system for cleaning and verifying semiconductor equipment. Background Technology
[0002] In semiconductor manufacturing, equipment cleaning is a key step in ensuring process stability and product yield.
[0003] In response, traditional technologies have also proposed some methods for verifying the cleaning requirements of semiconductor manufacturing equipment.
[0004] For example, patent application CN121678573A discloses a multi-region real-time endpoint detection system and method for semiconductor chamber cleaning, relating to the field of semiconductor gas detection. The system includes a gas path unit with a main inlet, a first branch, a second branch, and a valve module for opening or closing the first or second branch. The first chamber has a first broadband light source and a first multi-channel photodetector arranged opposite each other on both sides, with each channel of the first multi-channel photodetector configured with a filter of a different center wavelength. The second chamber has multiple second photodetectors, multiple target light sources, and a displacement platform arranged opposite each other on both sides, with the target light sources mounted on the displacement platform and capable of moving relative to the second photodetectors. A control module is connected to the valve module, the first multi-channel photodetector, the displacement platform, and each target light source.
[0005] For example, patent application CN121231413A discloses a method for determining the cleaning endpoint and a system for detecting the cleaning endpoint of a thin film growth equipment chamber. The method includes: acquiring the peak concentration C of a characteristic gas and the time T for the characteristic gas to reach its peak; calibrating parameters for formal cleaning based on the peak concentration C and time T; performing formal cleaning of the process chamber based on the calibrated parameters; monitoring the characteristic gas generated during formal cleaning and acquiring the signal quality factor Q; setting a standard value G; and comparing the signal quality factor Q with the standard value G to determine the cleaning result. The system for detecting the cleaning endpoint includes a semiconductor thin film growth equipment process chamber, a tail gas emission pipeline, and a detection device; the detection device is located in the tail gas emission pipeline to detect the concentration of the characteristic gas in real time.
[0006] For example, patent application CN120146534A discloses a method, apparatus, device, and storage medium for assessing the demand for cleaning sheets. The method includes: acquiring material information of a production task and configuration information of a processing chamber to generate a first pre-allocation scheme for confirming the demand for cleaning sheets; determining whether the acquired cleaning sheet supply information can meet the demand for cleaning sheets; if not, checking the status of the production task; if the production task is in progress, adjusting the configuration information of the processing chamber to generate a second pre-allocation scheme; replacing the first pre-allocation scheme with the second pre-allocation scheme, and returning to execute the confirmation of the demand for cleaning sheets based on the generated first pre-allocation scheme.
[0007] However, the above methods still have shortcomings such as poor adaptability to production environments. Therefore, there is an urgent need for a semiconductor equipment cleaning verification method with better verification results. Summary of the Invention
[0008] The purpose of this invention is to provide a method and system for cleaning and verifying semiconductor equipment, which partially solves or alleviates the above-mentioned deficiencies in the prior art and can improve the cleaning and verification efficiency of semiconductor equipment.
[0009] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide a method for cleaning and verifying semiconductor devices, comprising: S101, Identify the scene information of the semiconductor device; S102, Based on the scenario information, configure a fast detection scheme for the semiconductor device by setting fast detection recommendation rules. The fast detection scheme includes: forward verification, reverse verification, or bidirectional verification. The forward verification verifies the semiconductor device from the perspective of the effectiveness of the cleaning operation, the reverse verification verifies whether the cleaning operation was missed, and the bidirectional verification combines the forward verification and the reverse verification. S103, The semiconductor device is inspected using the aforementioned rapid testing scheme, and the corresponding rapid testing results are obtained; S104, when the quick test result reports an error, a supplementary test scheme is selected according to the error type and the set supplementary test recommendation rules; when the quick test result does not report an error, the verification result is directly output, and the verification result is accurate; wherein, the error type includes: positive non-compliance and / or reverse non-compliance, and the supplementary test scheme includes: intermediate state supplementary test and / or artifact supplementary test; S105, the semiconductor device is further verified using the aforementioned supplementary inspection scheme, and the supplementary inspection results are obtained.
[0010] In some embodiments, when the error type is a positive non-compliance, the supplementary inspection scheme is an intermediate state supplementary inspection; or, when the error type is a reverse non-compliance, the supplementary inspection scheme is a false positive supplementary inspection.
[0011] In some embodiments, when the supplementary inspection scheme is the intermediate state supplementary inspection, S105 includes: S1051, acquire at least two preceding operations of the semiconductor device that are adjacent to the current time; S1052, determine whether the operation type of the above operations is all cleaning; If so, proceed with the following steps: S1053, determine whether at least two operations conform to a predefined operation sequence; If yes, the re-inspection result is accurate; otherwise, the re-inspection result is an error. And / or, when the supplementary inspection scheme is the spurious supplementary inspection, S105 includes: S1055, provides recommended cleaning operations based on the error type; S1056, Obtain the cleaning records of the semiconductor device within a historical set period; S1057, Determine whether there is a cleaning record containing the same type as the recommended cleaning operation; If yes, the re-inspection result is accurate; otherwise, the re-inspection result is an error.
[0012] In some embodiments, the scenario information includes: historical operation records of the semiconductor device, and future operation plans.
[0013] In some embodiments, S102 includes: S1021, when the historical operation record shows that the semiconductor device completed at least one cleaning operation in the previous first process cycle, and the future operation plan shows that the semiconductor device will not have any new process operation in the subsequent second process cycle, then the recommended fast test scheme is positive verification.
[0014] In some embodiments, S102 includes: S1022, when the historical operation record shows that the semiconductor device has maintained stable operation in the previous third process cycle, and the future operation plan shows that a preset conventional process will be triggered in the subsequent fourth process cycle, then the recommended fast detection scheme is reverse verification.
[0015] In some embodiments, S102 includes: S1023, Identify verification-related events from the historical operation records and / or the future operation plans; wherein the verification-related event is a fault event triggered by the semiconductor device in a previous third process cycle, and / or, the verification-related event is an advanced process operation triggered by the semiconductor device in a subsequent fourth process cycle. S1024, Generate a verification level based on the association information of the verification association event; S1025, determine whether the verification level is greater than the set verification threshold; If yes, then the recommended rapid detection scheme is two-way verification; otherwise, return to S1021 or S1022.
[0016] In some embodiments, when the fast detection scheme is a two-way verification, forward verification is performed on the semiconductor device first in S103; Correspondingly, when the error type is "positive not satisfied", S105 is started directly; If the supplementary verification result of S105 is accurate, then the reverse verification can be cancelled.
[0017] In some embodiments, when the rapid detection scheme is a two-way verification, S103 includes the following steps: Determine whether the previous operation of the semiconductor device was a cleaning operation; If so, perform forward verification first, and then perform reverse verification only after the forward verification passes. If not, both the forward verification and the reverse verification need to be performed.
[0018] In some embodiments, the steps further include: S100: After the semiconductor device completes a cleaning operation, a state reset operation is performed on the semiconductor device.
[0019] A second aspect of the present invention is to provide a semiconductor device cleaning and verification system, comprising: The scene recognition module is used to identify the scene information in which the semiconductor device is located; The fast test configuration module is used to configure a fast test scheme for the semiconductor device by setting fast test recommendation rules according to the scenario information. The fast test scheme includes: forward verification, reverse verification, or bidirectional verification. The forward verification verifies the semiconductor device from the perspective of the effectiveness of the cleaning operation, the reverse verification verifies whether the cleaning operation was missed, and the bidirectional verification combines the forward verification and the reverse verification. The equipment inspection module is used to inspect the semiconductor equipment using the rapid inspection scheme and obtain the corresponding rapid inspection results; The supplementary inspection scheme selection module is used to select a supplementary inspection scheme according to the error type and the set supplementary inspection recommendation rules when the rapid inspection result reports an error; when the rapid inspection result does not report an error, the verification result is directly output and the verification result is accurate; wherein, the error type includes: positive non-compliance and / or reverse non-compliance, and the supplementary inspection scheme includes: intermediate state supplementary inspection and / or spurious supplementary inspection; The supplementary verification module is used to perform supplementary verification on the semiconductor device using the supplementary inspection scheme and obtain the supplementary inspection results.
[0020] Beneficial technical effects: Through a verification mechanism that combines low-cost rapid testing with targeted supplementary testing, it is possible to dynamically determine whether further verification is needed based on the results of rapid testing, rather than performing comprehensive cleaning verification every time.
[0021] Specifically, this invention preferably selects a rapid detection scheme based on the device's scenario information, that is, choosing a more economical scheme for the current risk characteristics (such as using only reverse verification in low-risk scenarios where the device is operating stably), avoiding a one-size-fits-all approach of comprehensively screening all devices. When a rapid detection fails, this invention selects to proceed with a supplementary detection, identifying special scenarios that may have false alarms (such as continuous cleaning sequences) at a lower cost to complete the verification, thereby optimizing the allocation of verification resources.
[0022] In other words, this invention provides low-cost rapid detection for most scenarios, while offering low-cost re-verification through supplementary detection for a few abnormal scenarios. This significantly reduces overall verification costs while eliminating a large number of false alarms. Furthermore, this invention can meet the cleaning verification needs of most scenarios through the synergy of rapid detection and supplementary detection, thereby achieving a good balance between verification costs and the accuracy of verification results.
[0023] Furthermore, by setting different re-check strategies based on the characteristics of different verification methods, we can maximize the use of the root causes of errors behind different verification methods to select a more suitable and efficient re-check method, thereby greatly reducing the waste of verification resources and misjudgment.
[0024] For the common continuous cleaning sequence patterns in semiconductor equipment cleaning, a timing fault-tolerance mechanism that proceeds from positive to negative and from difficult to easy is employed to conduct a more cautious check on false positive errors that may be caused by state resets, thus avoiding false alarms. Furthermore, this timing fault-tolerance mechanism can also identify redundant verification steps (such as reverse verification) at a relatively low cost, thereby optimizing the allocation of verification resources. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.
[0026] Figure 1 A schematic flowchart of a semiconductor device cleaning and verification method provided by the present invention; Figure 2 This is a schematic diagram of the structure of a semiconductor device cleaning verification system provided by the present invention; Figure 3 This is a schematic block diagram of the structure of a computer device provided by the present invention. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0028] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.
[0029] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0030] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0031] In this document, "and / or" includes any and all combinations of one or more of the listed related items.
[0032] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.
[0033] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.
[0034] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.
[0035] Example 1: During the wafer manufacturing process, the production line equipment needs to be cleaned regularly.
[0036] Semiconductor equipment integrates a large number of sensors (pressure, temperature, radio frequency power, airflow, etc.) and mechanical components (valves, robotic arms, electrostatic chucks, etc.). During the continuous production of large quantities of wafers, these components can experience minute, imperceptible drift.
[0037] After cleaning, the status of the machine is often reset, such as clearing the previous process parameters or records.
[0038] Zeroing is crucial for wafer production line or equipment maintenance. For example, forced zeroing of accumulated deviations can prevent process drift (the equipment contains numerous sensors and mechanical components, which can experience minute, imperceptible drifts during continuous production; without data reset, these deviations can accumulate). Another example is the cleaning process itself, which drastically alters the equipment's physical state. After cleaning, the thin film on the inner wall of the chamber is removed, changing the temperature and airflow fields. If the equipment's control software retains parameters based on the old film layer from before cleaning, the old parameters will be applied to the new environment as soon as the wafer enters, directly leading to completely incorrect process parameters (such as etching rate).
[0039] However, the applicant noted that while zeroing plays a crucial role in maintaining process accuracy, it can also trigger specific timing errors. For example, if the switchover flag is cleared, the cleaning verification might falsely report that cleaning has never been performed.
[0040] Alternatively, the applicant may have noticed that resetting the site is tantamount to artificially destroying all on-site records already completed during the previous cleaning. This could create a time gap, potentially leading to errors in subsequent verification.
[0041] For this, please see Figure 1 This invention provides a method for cleaning and verifying semiconductor devices, comprising: S101, Identify the scene information of the semiconductor device; S102, Based on the scenario information, configure a fast detection scheme for the semiconductor device by setting fast detection recommendation rules. The fast detection scheme includes: forward verification, reverse verification, or bidirectional verification. The forward verification verifies the semiconductor device from the perspective of the effectiveness of the cleaning operation, the reverse verification verifies whether the cleaning operation was missed, and the bidirectional verification combines the forward verification and the reverse verification. S103, The semiconductor device is inspected using the aforementioned rapid testing scheme, and the corresponding rapid testing results are obtained; S104, when the quick test result reports an error, a supplementary test scheme is selected according to the error type and the set supplementary test recommendation rules; when the quick test result does not report an error, the verification result is directly output, and the verification result is accurate; wherein, the error type includes: positive non-compliance and / or reverse non-compliance, and the supplementary test scheme includes: intermediate state supplementary test and / or artifact supplementary test; S105, the semiconductor device is further verified using the aforementioned supplementary inspection scheme, and the supplementary inspection results are obtained.
[0042] In some embodiments, engineers can configure a rapid detection scheme for the semiconductor device by setting rapid detection recommendation rules based on the scenario information.
[0043] In some embodiments, positive verification is used to check whether the cleaning was effective. For example, positive verification relies on device status parameters (such as a particle counter and a residue sensor baseline) to determine cleaning effectiveness. If cleaning A resets these status parameters, when positive verification is performed after cleaning B is completed, the measured values may be abnormal (e.g., showing excessive residue) because the status parameters were reset. However, cleaning B itself was actually effective; the false positive result indicating poor cleaning effectiveness is simply due to the reset status parameters in cleaning A.
[0044] In some embodiments, reverse verification is used to check for any missing steps in the cleaning process. For example, reverse verification checks the device logs or status flags to confirm whether any cleaning operations have been missed. After the cleaning operation is completed, a flag indicating that cleaning is complete should be recorded; however, a status reset may clear this flag, leading to a false alarm indicating that the reverse verification is not satisfied.
[0045] In this embodiment, a verification mechanism that combines low-cost rapid testing with targeted supplementary testing can dynamically determine whether further verification is needed based on the rapid testing results, rather than performing a comprehensive cleaning verification every time.
[0046] Specifically, this invention preferably selects a rapid detection scheme based on the device's scenario information, that is, choosing a more economical scheme for the current risk characteristics (such as using only reverse verification in low-risk scenarios where the device is operating stably), avoiding a one-size-fits-all approach of comprehensively screening all devices. When a rapid detection fails, this invention selects to proceed with a supplementary detection, identifying special scenarios that may have false alarms (such as continuous cleaning sequences) at a lower cost to complete the verification, thereby optimizing the allocation of verification resources.
[0047] In other words, this invention provides low-cost rapid detection for most scenarios, while offering low-cost re-verification through supplementary detection for a few abnormal scenarios. This significantly reduces overall verification costs while eliminating a large number of false alarms. Furthermore, this invention can meet the cleaning verification needs of most scenarios through the synergy of rapid detection and supplementary detection, thereby achieving a good balance between verification costs and the accuracy of verification results.
[0048] In some embodiments, when the error type is a positive non-compliance, the supplementary inspection scheme is an intermediate state supplementary inspection; or, when the error type is a reverse non-compliance, the supplementary inspection scheme is a false positive supplementary inspection.
[0049] If the positive verification fails, it can be checked whether the previous operation was clean, whether the most recent consecutive operations are all clean, and whether their order conforms to a predefined clean sequence. In other words, intermediate state supplementary checks refer to checking whether the most recent consecutive operations are all clean, and whether the order of these operations conforms to a predefined clean sequence.
[0050] For example, if it is found that the previous operation was cleaning (A), the current operation is also cleaning (B), and A→B is predefined as a valid consecutive cleaning sequence, then it can be inferred that the positive inconsistency is a false alarm, because the operation order is correct and the effect should be satisfactory.
[0051] If the reverse verification fails, check the history to see if the same cleaning operation has just been performed (e.g., query cleaning records within the specified historical period) and check if there is a task identical to the suggested cleaning operation. If the history shows that the same cleaning operation has just been performed, then it can be determined that the reverse verification failure is a false alarm.
[0052] In other words, spurious re-inspection refers to querying cleaning records within a set historical period to check for the existence of tasks that are the same as the recommended cleaning operations.
[0053] In this embodiment, different supplementary inspection strategies are set according to the characteristics of different verification methods. This can maximize the use of the error root causes behind different verification methods to select a more suitable and efficient supplementary inspection method, thereby greatly reducing the waste of verification resources and misjudgment.
[0054] In some embodiments, when the supplementary inspection scheme is the intermediate state supplementary inspection, S105 includes: S1051, acquire at least two preceding operations of the semiconductor device that are adjacent to the current time; S1052, determine whether the operation type of the above operations is all cleaning; If so, proceed with the following steps: S1053, determine whether at least two operations conform to a predefined operation sequence; If yes, the re-inspection result is accurate; otherwise, the re-inspection result is an error. And / or, when the supplementary inspection scheme is the spurious supplementary inspection, S105 includes: S1055, provides recommended cleaning operations based on the error type; S1056, Obtain the cleaning records of the semiconductor device within a historical set period; S1057, Determine whether there is a cleaning record containing the same type as the recommended cleaning operation; If yes, the re-inspection result is accurate; otherwise, the re-inspection result is an error.
[0055] In some embodiments, historical operation records include operation logs of the equipment actually performed over a period of time, including each process, cleaning and maintenance, alarm event, parameter adjustment, etc. Future operation planning refers to the sequence of operations that the equipment will perform in the future, which can be derived from the production scheduling system, process recipe scheduling, or manually issued task lists.
[0056] For example, if the order of occurrence, time of occurrence, and duration of at least two operations are consistent with the predefined operation sequence, the supplementary inspection result can be considered accurate.
[0057] In some embodiments, the error type can be a specific cleaning step that is considered to have been missed, such as cavity plasma cleaning, gas line purging, wafer stage wiping, etc. Correspondingly, suggested cleaning operations can be given for that specific cleaning step based on the error type, such as "It is recommended to perform cavity plasma cleaning", "It is recommended to perform nitrogen purging of gas lines", "It is recommended to perform lint-free wiping of wafer stage", etc.
[0058] In some embodiments, S102 includes: S1021, when the historical operation record shows that the semiconductor device completed at least one cleaning operation in the previous first process cycle, and the future operation plan shows that the semiconductor device will not have any new process operation in the subsequent second process cycle, then the recommended fast test scheme is positive verification.
[0059] For example, an etching machine has just completed a standard dry cleaning after finishing the previous batch (historical records show the cleaning operation is complete). According to the production plan, there are no new process operations in the next cycle. Considering that the machine will be in standby mode for some time, even if there are missed cleanings, it will not affect subsequent processes. In this case, it is recommended to perform positive verification (i.e., only check whether the cleaning effect of the preceding cleaning operation meets the standard, without checking for any omissions).
[0060] In some embodiments, S102 includes: S1022, when the historical operation record shows that the semiconductor device has maintained stable operation in the previous third process cycle, and the future operation plan shows that a preset conventional process will be triggered in the subsequent fourth process cycle, then the recommended fast detection scheme is reverse verification.
[0061] For example, a deposition equipment has processed multiple batches continuously over the past 48 hours, operating stably without any alarms or anomalies. Its next step is a conventional oxide layer deposition process (which has a certain tolerance for residual contamination). In this case, the equipment is consistently stable, the cleaning effect is generally reliable, and the risks are controllable under conventional processes. Therefore, it is recommended to only perform reverse verification, ensuring that no cleaning operations have been missed.
[0062] In some embodiments, S102 includes: S1023, Identify verification-related events from the historical operation records and / or the future operation plans; wherein the verification-related event is a fault event triggered by the semiconductor device in a previous third process cycle, and / or, the verification-related event is an advanced process operation triggered by the semiconductor device in a subsequent fourth process cycle. S1024, Generate a verification level based on the association information of the verification association event; S1025, determine whether the verification level is greater than the set verification threshold; If yes, then the recommended rapid detection scheme is two-way verification; otherwise, return to S1021 or S1022.
[0063] Fault events can include events recorded in historical operation logs such as abnormal chamber pressure, plasma extinction, sudden increase in particles, and leakage alarms. Advanced process operations can include processes that are extremely sensitive to residues, such as high-precision deposition, thin gate oxidation, and ion implantation, which will be performed in the next process cycle.
[0064] In some embodiments, the correlation information for verifying related events refers to the number of fault events and / or advanced process operations.
[0065] In some embodiments, a higher verification level corresponds to a greater number of fault events and / or advanced process operations. For example, the verification level can be the sum of the number of fault events and advanced process operations. If a semiconductor equipment has 1 fault event and 2 advanced process operations, the corresponding verification level is 3.
[0066] In some embodiments, different fast detection recommendation rules can be set for different scenarios in which different semiconductor devices are used. The following will provide exemplary illustrations of typical scenarios to which different fast detection recommendation rules apply: Scenario 1: The equipment has completed a clear cleaning action, there are no new process requests, and only the cleaning effect needs to be confirmed. In this case, positive verification is applicable.
[0067] For example, after regular PM cleaning, the equipment returns to an idle state. At this time, there is no process lot waiting; it is only necessary to confirm that the cavity baseline (such as status parameters) meets the standards, and reverse checks can be omitted.
[0068] For example, when testing a new cleaning formula, if the purpose is purely research and development, it is only necessary to evaluate the physical effects of cleaning.
[0069] For example, after the first step of a continuous cleaning sequence is completed (such as after coarse washing), positive verification is used to determine whether the sequence can continue, and reverse verification can be omitted.
[0070] Scenario 2: The equipment is running online for a long time and is in a stable state. During continuous production, a routine process Lot request enters. In this case, reverse verification is applicable.
[0071] For example, in continuous production, the equipment runs smoothly within a maintenance cycle. Each process move's access check can be completed in milliseconds by quickly reading the counter with the help of reverse verification, which greatly saves time.
[0072] Another example is the dispatching of non-critical layers / low-value wafers. The cost of failure is controllable, and there is no need for time-consuming physical state forward verification.
[0073] For example, if the machine equipment is operating stably with no recent alarms or abnormal events, the health of the machine equipment is highly certain and does not warrant high-cost, high-difficulty positive verification.
[0074] Scenario 3: The equipment has just experienced a major failure event (such as abnormal cavity pressure, plasma extinction, sudden increase in particles, leakage alarm, etc.), or is about to perform a low-fault-tolerant process (such as high-precision deposition, thin gate oxidation, ion implantation, etc.). If one-sided verification may lead to the scrapping of a large number of wafers, two-way verification is preferred in this case.
[0075] For example, the first feeding after major maintenance (such as replacing core components or wet cleaning) is similar to the state of the machine being rebuilt. In order to ensure that the process parameters are adapted to the actual situation of the machine equipment, two-way verification must be performed.
[0076] For example, consider the first wafer processed after an abnormal alarm has recovered from offline recovery. At this point, the root cause is unclear (it could be a sensor false alarm, internal contamination, component displacement, or parameter drift), and the equipment may not have completely eliminated the fault. In this situation, two-way verification is preferable, checking both the effectiveness of the physical cleaning and the cleaning procedures.
[0077] For example, in high-value / low-fault-tolerant processes (such as gate oxide and critical photolithography layers), two-way inspection is preferred to avoid a large number of wafers being scrapped due to inadequate inspection.
[0078] For example, when a new process formulation is being run on this machine for the first time, the cavity environment requirements may differ, and old records cannot be directly referenced. It is necessary to verify from scratch that both sides match.
[0079] In some embodiments, when the fast detection scheme is a two-way verification, forward verification is performed on the semiconductor device first in S103; Correspondingly, when the error type is "positive not satisfied", S105 is started directly; If the supplementary verification result of S105 is accurate, then the reverse verification can be cancelled.
[0080] In some embodiments, when the rapid inspection scheme is a two-way verification, forward verification can be performed first to check the cleaning effect. Correspondingly, if the error type is "forward failure", the process directly proceeds to intermediate-state supplementary inspection without waiting for the reverse verification result. Furthermore, if the intermediate-state supplementary inspection finds that the "forward failure" error has been corrected (e.g., by tracing the operation sequence to confirm that the process is error-free), it indicates that the cleaning is effective to some extent, and reverse verification can then be performed.
[0081] In this embodiment, the present invention proposes a timing fault-tolerant mechanism under bidirectional verification, which can skip reverse verification at a specific stage (i.e., when forward verification fails but intermediate state re-verification passes). That is, when the result of intermediate state re-verification is accurate, the previous operation can be considered a cleaning operation, and it conforms to a predefined continuous cleaning sequence (e.g., main cleaning → post-chip WAC cleaning). In other words, the device is in a continuous cleaning sequence. If reverse verification is performed at this time, it not only wastes computational resources but may also generate new false alarms due to incomplete state reset data, interfering with the overall cleaning verification result. Therefore, when the result of intermediate state re-verification is accurate, reverse verification can be ignored until the cleaning sequence is completed.
[0082] In some embodiments, if forward verification fails but intermediate state check reports an error, i.e. the reason for forward failure is unknown, then reverse verification cannot be cancelled. Instead, reverse verification is required, and historical data is used for cross-verification.
[0083] In some embodiments, when the rapid detection scheme is a two-way verification, S103 includes the following steps: Determine whether the previous operation of the semiconductor device was a cleaning operation; If so, perform forward verification first, and then perform reverse verification only after the forward verification passes. If not, both the forward verification and the reverse verification need to be performed.
[0084] In some embodiments, by using the simple indicator of whether the previous operation was cleaning, it is possible to quickly identify whether the current operation is a continuous cleaning sequence scenario, and accordingly select which direction to start verification from, or even skip reverse verification.
[0085] Specifically, if the previous operation was a cleaning operation, the device is likely in a continuous cleaning sequence. In this case, forward verification is performed first, followed by reverse verification only after the forward verification passes. If the forward verification fails, an intermediate state check can be triggered immediately to confirm whether the device is indeed in a continuous cleaning sequence. If the intermediate state check passes, the device can be determined to be in a continuous cleaning sequence, and reverse verification can be skipped until the current continuous cleaning sequence ends.
[0086] In other words, for the common continuous cleaning sequence mode of semiconductor equipment cleaning, this timing fault tolerance mechanism, which proceeds from difficult to easy, allows for a more careful check of false positives that may be caused by state resets, thus avoiding false alarms. Furthermore, this timing fault tolerance mechanism can also identify unnecessary verification steps (such as reverse verification) at a relatively low cost, thereby optimizing the allocation of verification resources.
[0087] If the previous operation of the semiconductor device was not a cleaning operation, there is no possibility of a cleaning sequence intermediate state. Therefore, both verification directions need to be completed for comprehensive verification.
[0088] In some embodiments, the state reset operation may refer to resetting state variables related to the determination of cleaning verification conditions, such as cavity idle time, plasma activation times, and residual contamination.
[0089] In some embodiments, the steps further include: S100: After the semiconductor device completes a cleaning operation, a state reset operation is performed on the semiconductor device.
[0090] The applicant noted that both forward and reverse serial verification and parallel verification present numerous problems. For example, when a machine is in a continuous cleaning sequence, its cleaning task may not be completed, making reverse verification a waste of time. Alternatively, in a continuous cleaning sequence, engineers are more concerned with when the sequence will complete, and waiting for reverse verification results will delay the overall assessment.
[0091] In other words, for two-way verification scenarios, this invention can selectively and safely pass reverse verification by setting a time-series fault-tolerant mechanism based on a continuous cleaning sequence, thereby avoiding or reducing resource waste and false alarms.
[0092] Furthermore, by using the simple criterion of whether the previous operation was a cleaning operation, the execution order of bidirectional verification is determined. This allows for triggering intermediate state supplementary checks through forward verification in continuous cleaning sequence scenarios, thereby determining whether there is an opportunity to skip reverse verification. This approach enables dynamic allocation of verification resources using low-cost metrics, achieving a better balance between verification efficiency and verification result accuracy.
[0093] Please see Figure 2 The present invention also provides a semiconductor device cleaning verification system, comprising: The scene recognition module is used to identify the scene information in which the semiconductor device is located; The fast test configuration module is used to configure a fast test scheme for the semiconductor device by setting fast test recommendation rules according to the scenario information. The fast test scheme includes: forward verification, reverse verification, or bidirectional verification. The forward verification verifies the semiconductor device from the perspective of the effectiveness of the cleaning operation, the reverse verification verifies whether the cleaning operation was missed, and the bidirectional verification combines the forward verification and the reverse verification. The equipment inspection module is used to inspect the semiconductor equipment using the rapid inspection scheme and obtain the corresponding rapid inspection results; The supplementary inspection scheme selection module is used to select a supplementary inspection scheme according to the error type and the set supplementary inspection recommendation rules when the rapid inspection result reports an error; when the rapid inspection result does not report an error, the verification result is directly output and the verification result is accurate; wherein, the error type includes: positive non-compliance and / or reverse non-compliance, and the supplementary inspection scheme includes: intermediate state supplementary inspection and / or spurious supplementary inspection; The supplementary verification module is used to perform supplementary verification on the semiconductor device using the supplementary inspection scheme and obtain the supplementary inspection results.
[0094] In some embodiments, reverse verification can involve reading and comparing several counters and timestamps, a lightweight operation that takes only milliseconds. Forward verification, on the other hand, may involve sensor data acquisition, random sampling of the cavity environment, etc., and may take seconds or even minutes.
[0095] In some embodiments, reverse verification can be initiated first, leveraging its near-zero cost to quickly obtain conclusions from the historical record dimension, while forward verification is initiated in parallel or later. This allows the preparatory process for supplementary checks (such as pre-querying historical cleanup records) to be started while forward verification is still in progress, so that the merge decision can proceed immediately after the forward verification results are obtained, thus shortening the overall processing time.
[0096] In other words, this approach avoids performing time-consuming forward verification directly in non-sequential scenarios and then leaving the lightweight reverse verification for last, which would otherwise lengthen the overall process time. Instead, this invention chooses to proceed with the lighter verification first and then the heavier one, providing initial feedback more quickly, especially when reverse alarms require additional processing, allowing subsequent logic to be initiated earlier.
[0097] In other words, this invention uses whether the preceding operation type is clean as a quick judgment indicator, which can control the amount of computation while accurately entering the reverse verification scenario (continuous clean intermediate state) to achieve dynamic optimization of verification resources.
[0098] In other embodiments, the present invention proposes a two-way verification closed-loop mechanism that can simultaneously guarantee cleaning quality from both the dimensions of rationality and integrity. This mechanism performs both forward and reverse verification simultaneously in the cleaning verification of semiconductor devices, forming a two-way guarantee of cleaning quality. The two-way verification closed-loop mechanism includes: (1) Forward verification path: used to check the validity of the cleaning operation. Forward verification obtains a list of candidate rules through an intelligent configuration attachment mechanism. After matching by a progressive rule matcher, the verification execution engine determines whether the cleaning conditions are met. If the conditions are met, cleaning is allowed and the execution information is recorded. If the conditions are not met and it is not a temporal artifact, cleaning is blocked. (2) Reverse verification path: used to check for any cleaning omissions that should have been performed but were not. Reverse verification obtains the list of cleaning rules related to the current context through the intelligent configuration attachment mechanism, and the verification execution engine determines whether the cleaning conditions of each rule are met; if the conditions of a rule are met and there is no corresponding cleaning execution in the history, it is determined to be an omission of cleaning and an error is reported.
[0099] In some embodiments, the bidirectional verification closed loop further integrates a timing processing mechanism, which includes: Idle cleaning delay verification: When idle cleaning is triggered, only the idle end time and threshold are recorded, and cleaning is allowed to proceed; when the next process operation actually starts, the actual idle time is calculated and compared with the threshold. If the actual idle time is less than the threshold, the previous idle cleaning is judged to be an unreasonable execution. State reset timing fault tolerance: When forward verification fails, check whether the previous operation was a clean and whether it forms a predefined continuous clean sequence with the current clean. If so, the fault tolerance is passed. When reverse verification finds that the condition is met, check whether the same clean has just been performed in the history. If so, it is determined to be a timing artifact caused by state reset, and no omission error is reported.
[0100] This two-way verification closed-loop mechanism can prevent unreasonable cleaning execution through forward verification, prevent necessary cleaning omissions through reverse verification, and eliminate false alarms caused by state reset by combining a timing fault tolerance mechanism, thus forming a complete cleaning quality closed loop.
[0101] In some embodiments, the present invention also provides an intelligent configuration aggregator mechanism for centralized storage, two-dimensional indexing, and efficient retrieval of semiconductor device cleaning rules. This mechanism includes: (1) Centralized rule repository: All clean rule objects are stored in a global hash table. Each rule uses a unique alias as the key and the rule content as the value. Rule objects are globally unique. (2) Dual-dimensional index manager: establish spatial dimension index and time dimension index respectively. The spatial dimension index uses the process chamber identifier as the key to store the list of rule aliases attached to the chamber. The time dimension index uses the wafer fabrication node identifier as the key to store the list of rule aliases attached to the node. The wafer fabrication node includes before operation, after operation, before entering the chamber, and after exiting the chamber. (3) Rule retrieval service: Respond to rule query requests for forward and reverse verification, quickly locate the corresponding alias list by hash lookup based on the chamber identifier and / or chip node identifier in the request context, and then obtain the complete rule object from the centralized rule repository based on the alias.
[0102] In some embodiments, this application also provides a schematic block diagram of the structure of a computer device, please see... Figure 3 Computer programs can be used in situations such as Figure 3 It runs on the computer device shown. Figure 3 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The memory may include non-volatile storage media and internal memory. The non-volatile storage media may store an operating system and computer programs. The computer programs include program instructions that, when executed, cause the processor to perform arbitrary methods. The processor provides computational and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the execution of the computer programs in the non-volatile storage media; when executed by the processor, these programs cause the processor to perform arbitrary methods. The network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 3 The structures shown are merely block diagrams of a portion of the structure related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. It should be understood that the processor may be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0103] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0104] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0105] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A method for cleaning and verifying semiconductor devices, characterized in that, include: S101, Identify the scene information of the semiconductor device; S102, Based on the scenario information, configure a fast detection scheme for the semiconductor device by setting fast detection recommendation rules. The fast detection scheme includes: forward verification, reverse verification, or bidirectional verification. The forward verification verifies the semiconductor device from the perspective of the effectiveness of the cleaning operation, the reverse verification verifies whether the cleaning operation was missed, and the bidirectional verification combines the forward verification and the reverse verification. S103, The semiconductor device is inspected using the aforementioned rapid testing scheme, and the corresponding rapid testing results are obtained; S104, when the quick test result reports an error, a supplementary test scheme is selected according to the error type and the set supplementary test recommendation rules; when the quick test result does not report an error, the verification result is directly output, and the verification result is accurate; wherein, the error type includes: positive non-compliance and / or reverse non-compliance, and the supplementary test scheme includes: intermediate state supplementary test and / or artifact supplementary test; S105, the semiconductor device is further verified using the aforementioned supplementary inspection scheme, and the supplementary inspection results are obtained.
2. The semiconductor device cleaning and verification method according to claim 1, characterized in that, When the error type is that the forward condition is not met, the supplementary inspection scheme is the intermediate state supplementary inspection; or, when the error type is that the reverse condition is not met, the supplementary inspection scheme is the spurious supplementary inspection.
3. The semiconductor device cleaning and verification method according to claim 1, characterized in that, When the supplementary inspection scheme is the intermediate state supplementary inspection, S105 includes: S1051, acquire at least two preceding operations of the semiconductor device that are adjacent to the current time; S1052, determine whether the operation type of the above operations is all cleaning; If so, proceed with the following steps: S1053, determine whether at least two operations conform to a predefined operation sequence; If yes, the re-inspection result is accurate; otherwise, the re-inspection result is an error. And / or, when the supplementary inspection scheme is the spurious supplementary inspection, S105 includes: S1055, provides recommended cleaning operations based on the error type; S1056, Obtain the cleaning records of the semiconductor device within a historical set period; S1057, Determine whether there is a cleaning record containing the same type as the recommended cleaning operation; If yes, the re-inspection result is accurate; otherwise, the re-inspection result is an error.
4. The semiconductor device cleaning and verification method according to claim 1, characterized in that, The scenario information includes: historical operation records of semiconductor equipment, and future operation plans.
5. The semiconductor device cleaning and verification method according to claim 4, characterized in that, S102 includes: S1021, when the historical operation record shows that the semiconductor device completed at least one cleaning operation in the previous first process cycle, and the future operation plan shows that the semiconductor device will not have any new process operation in the subsequent second process cycle, then the recommended fast test scheme is positive verification.
6. The semiconductor device cleaning and verification method according to claim 4, characterized in that, S102 includes: S1022, when the historical operation record shows that the semiconductor device has maintained stable operation in the previous third process cycle, and the future operation plan shows that a preset conventional process will be triggered in the subsequent fourth process cycle, then the recommended fast detection scheme is reverse verification.
7. The semiconductor device cleaning and verification method according to claim 4, characterized in that, S102 includes: S1023, Identify verification-related events from the historical operation records and / or the future operation plans; wherein the verification-related event is a fault event triggered by the semiconductor device in a previous third process cycle, and / or, the verification-related event is an advanced process operation triggered by the semiconductor device in a subsequent fourth process cycle. S1024, Generate a verification level based on the association information of the verification association event; S1025, determine whether the verification level is greater than the set verification threshold; If yes, then the recommended rapid detection scheme is two-way verification; otherwise, return to S1021 or S1022.
8. The semiconductor device cleaning and verification method according to claim 1, characterized in that, When the fast detection scheme is a two-way verification, the semiconductor device is given priority for forward verification in S103; Correspondingly, when the error type is "positive not satisfied", S105 is started directly; If the supplementary verification result of S105 is accurate, then the reverse verification can be cancelled.
9. A semiconductor device cleaning and verification method according to claim 1, characterized in that, When the rapid detection scheme is a two-way verification, S103 includes the following steps: Determine whether the previous operation of the semiconductor device was a cleaning operation; If so, perform forward verification first, and then perform reverse verification only after the forward verification passes. If not, both the forward verification and the reverse verification need to be performed; And / or, the method further includes: S100: After the semiconductor device completes a cleaning operation, a state reset operation is performed on the semiconductor device.
10. A semiconductor device cleaning verification system, characterized in that, include: The scene recognition module is used to identify the scene information in which the semiconductor device is located; The fast test configuration module is used to configure a fast test scheme for the semiconductor device by setting fast test recommendation rules according to the scenario information. The fast test scheme includes: forward verification, reverse verification, or bidirectional verification. The forward verification verifies the semiconductor device from the perspective of the effectiveness of the cleaning operation, the reverse verification verifies whether the cleaning operation was missed, and the bidirectional verification combines the forward verification and the reverse verification. The equipment inspection module is used to inspect the semiconductor equipment using the rapid inspection scheme and obtain the corresponding rapid inspection results; The supplementary inspection scheme selection module is used to select a supplementary inspection scheme according to the error type and the set supplementary inspection recommendation rules when the rapid inspection result reports an error; when the rapid inspection result does not report an error, the verification result is directly output and the verification result is accurate; wherein, the error type includes: positive non-compliance and / or reverse non-compliance, and the supplementary inspection scheme includes: intermediate state supplementary inspection and / or spurious supplementary inspection; The supplementary verification module is used to perform supplementary verification on the semiconductor device using the supplementary inspection scheme and obtain the supplementary inspection results.