Electrically controlled switchable terahertz metasurface and nand gate logic encoder

Abstract

This invention discloses an electrically controlled terahertz metasurface NAND gate logic encoder. The encoder includes an encoder body, which, from bottom to top, consists of a common ground electrode, a dielectric substrate layer, and a frequency control structure tightly stacked. The frequency control structure includes a surface periodic structure and an output structure. The surface periodic structure comprises multiple transmission units arranged in a regular matrix. Each transmission unit consists of an upper transverse metal strip, a lower transverse metal strip, an upper metal patch, a lower metal patch, and four graphene patches. The upper and lower metal patches have the same structure and shape, both being semi-circular rings, with two pre-reserved notches on each metal patch. The four graphene patches fill the notches and are electrically connected. This encoder can achieve wideband NAND gate logic encoding with a modulation depth exceeding 80% within the 0.53~0.60THz range, maintaining stable logic output even when the terahertz incident wave is deflected by 30~45°.

Description

Technical Field

[0001] This invention relates to the field of terahertz electromagnetic control devices and metamaterials, specifically to an electrically controlled terahertz metasurface NAND gate logic encoder. Background Technology

[0002] With the development of 6G communication technology, the terahertz band, due to its high bandwidth characteristics, has become a key spectrum resource for realizing ultra-high-speed wireless communication. Dynamic modulation and logic encoding of terahertz waves are among the core technologies for constructing terahertz space optical communication systems. Currently, graphene-based terahertz logic encoders mostly use rectangular, cross-shaped, or non-centrosymmetric structures as resonant units. However, such structures have the following technical drawbacks: First, the simple geometry leads to severe anisotropy; when terahertz waves are incident at large angles, the resonant mode is prone to degradation and frequency drift, affecting the accuracy of the logic encoding. Second, the operating bandwidth is narrow, and the modulation depth is insufficient, making it difficult to meet the requirements of wideband communication. Furthermore, in traditional designs, to achieve independent electrical control of the graphene, a complex and delicate feeding network needs to be arranged. This network is extremely prone to breakage during micro-nano fabrication, resulting in low device yield and short lifespan. These problems restrict the application of terahertz logic encoders in practical communication systems.

[0003] The inventors' previous patent application, CN116722366A, disclosed a broadband electrically controlled terahertz metasurface NOR gate logic encoder, composed of a high-resistivity silicon layer, a polyimide layer, a common ground electrode, and a frequency control structure. The polyimide layer and the high-resistivity silicon layer are stacked, with the lower surface of the polyimide layer in contact with the upper surface of the high-resistivity silicon layer. The frequency control structure is stacked on the upper surface of the polyimide layer, and the common ground electrode is stacked on the lower surface of the high-resistivity silicon layer. The two electrode patches of the frequency control structure are each connected to the positive terminal of a DC regulated power supply via a switch, while the common ground electrode is directly connected to the negative terminal of the DC regulated power supply. This invention utilizes the characteristic of applying voltage to graphene to change its conductivity to achieve transmittance control in a specific frequency band. It can achieve the effect of outputting a broadband NOR gate digital logic terahertz signal by inputting two digital logic electrical signals. However, the encoding stability is not ideal when the terahertz wave is not incident at a perpendicular 90° angle. Summary of the Invention

[0004] This invention addresses the shortcomings of existing terahertz modulation devices, such as narrow operating bandwidth, sensitivity to incident angle, low modulation depth, and complex bias wiring, by providing an electrically controlled terahertz metasurface NAND gate logic encoder.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A terahertz metasurface NAND gate logic encoder with electronically controlled conversion includes an encoder body. The encoder body includes a common ground electrode, a dielectric substrate layer, and a frequency control structure, wherein the common ground electrode and the frequency control structure are respectively stacked on the lower and upper surfaces of the dielectric substrate layer; the frequency control structure includes a surface periodic structure and an output structure, with the surface periodic structure located in the middle of the frequency control structure; characterized in that...

[0007] The surface periodic structure consists of multiple transmission units arranged in a regular matrix. Each transmission unit comprises an upper transverse metal strip, a lower transverse metal strip, an upper metal patch, a lower metal patch, and four graphene patches. The upper and lower metal patches have identical structures and shapes, both being semi-circular rings composed of straight and curved metal strip segments. Two notches are formed on the curved metal strip segments, located at the junctions of the curved and straight metal strip segments. The upper and lower metal patches are arranged with their straight metal strip segments adjacent to each other and spaced apart. Symmetrically arranged between the upper and lower horizontal metal strips, with the straight segments of the metal strips on each metal patch being parallel to the upper and lower horizontal metal strips respectively; four graphene patches are respectively positioned at the notches of the upper and lower metal patches, and the notches on each metal patch are closed; in the three adjacent transmission units at the top, middle, and bottom, the upper horizontal metal strip in the middle transmission unit is superimposed on the lower horizontal metal strip in the transmission unit above it, and the lower horizontal metal strip in the middle transmission unit is superimposed on the upper horizontal metal strip in the transmission unit below it;

[0008] The lead-out structure is located on the outer side of the surface periodic structure and consists of two electrode patches; one electrode patch is connected to the straight metal strip of the upper metal patch in all transmission units, and the other electrode patch is connected to the straight metal strip of the lower metal patch in all transmission units.

[0009] The two electrode patches are connected to the positive terminal of the external power supply, and the common ground electrode is connected to the negative terminal of the external power supply.

[0010] This invention modulates the transmittance of incident terahertz waves by adjusting the voltage state of two electrode patches to change the Fermi level of the graphene patch, thereby completing NAND gate logic operations.

[0011] In the above technical solution, the center of the common ground electrode is perpendicularly opposite to the center of the surface periodic structure. Furthermore, the common ground electrode is a closed ring structure.

[0012] In the above technical solution, the area covered by the surface periodic structure is larger than the area of ​​the terahertz beam spot illuminating the encoder body, and can be 1.5 to 2.5 times the area of ​​the terahertz beam spot illuminating the encoder body; the area covered by the inner ring of the common ground electrode is larger than the area of ​​the terahertz beam spot illuminating the encoder body, and can be 1.5 to 2.5 times the area of ​​the terahertz beam spot illuminating the encoder body.

[0013] In the above technical solution, the external power supply is a DC regulated power supply, and the voltage range of the DC regulated power supply is 5~24V.

[0014] In the above technical solution, the upper transverse metal strip, lower transverse metal strip, upper metal patch, lower metal patch, and electrode patch are made of high-conductivity metal materials, such as gold, or gold with a titanium layer attached to the bottom surface. Furthermore, the electrode patch is comb-shaped.

[0015] In the above technical solution, the material of the dielectric substrate layer can be polyimide (PI), quartz, or sapphire, with polyimide being preferred. The thickness of the dielectric substrate layer is typically 10~30μm.

[0016] In the above technical solution, each transmission unit is symmetrical about its transverse central axis. For a specific transmission unit, the width-to-height ratio of its substrate is 1:2.55~2.70. The width of the straight metal strips, the width of the upper transverse metal strip, and the width of the lower transverse metal strip of the upper or lower metal patch are all equal to the width of the transmission unit. The height of the straight metal strips, the height of the upper transverse metal strip, and the height of the lower transverse metal strip of the upper or lower metal patch are all equal. The outer diameter of the arc-shaped metal strip constituting the upper or lower metal patch is equal to the width of its straight metal strip. The inner diameter of the arc-shaped metal strip constituting the upper or lower metal patch is 0.8~0.9 times its outer diameter. The height of the notch on the arc-shaped metal strip of the upper or lower metal patch is 0.2~0.4 times the height of the straight metal strip of the upper or lower metal patch. The distance between the straight metal strips of the upper and lower metal patches is equal to the height of the straight metal strips constituting the upper or lower metal patch.

[0017] Furthermore, the width of the substrate of the transmission unit is 70~90μm and the height is 200~220μm; the width of the straight metal strip of the upper or lower metal patch, the width of the upper transverse metal strip, and the width of the lower transverse metal strip are all 70~90μm, and their heights are all 8~12μm; the distance between the straight metal strip of the upper metal patch and the straight metal strip of the lower metal patch is 8~12μm.

[0018] Furthermore, the outer diameter of the arc-shaped metal strip constituting the upper or lower metal patch is 90~110μm, and its inner diameter is 82~92μm; the height of the notch on the arc-shaped metal strip of the upper or lower metal patch is 2~4μm.

[0019] Furthermore, in the upper or lower metal patch, the graphene patch disposed on its left side is spaced 2-4 μm from the left edge of the transmission unit it belongs to; and the graphene patch disposed on its right side is also spaced 2-4 μm from the right edge of the transmission unit it belongs to; the width of the graphene patch is 2-4 μm, and its height is equal to the height of the notch on the upper or lower metal patch.

[0020] Furthermore, the thickness of the upper metal patch, the lower metal patch, the upper transverse metal strip, and the lower transverse metal strip is 0.2~0.8μm, and the thickness of the graphene patch is 0.3~1.0nm.

[0021] In a preferred embodiment, the width of the transmission unit substrate is 80 μm and the height is 210 μm; the thickness of the upper or lower metal patch, the upper transverse metal strip, and the lower transverse metal strip is 0.2~0.8 μm; the width of the straight metal strip of the upper or lower metal patch, the width of the upper transverse metal strip, and the width of the lower transverse metal strip are all 80 μm, and their heights are all 10 μm; the outer diameter of the arc-shaped metal strip of the upper or lower metal patch is 80 μm, and its inner diameter is 64 μm; the height of the notch on the arc-shaped metal strip of the upper or lower metal patch is 3 μm; the spacing between the straight metal strips constituting the upper metal patch and the straight metal strips constituting the lower metal patch is 10 μm; the width of the graphene patch is 3 μm, the height is 3 μm, and the thickness is 0.3~1.0 nm.

[0022] Compared with the prior art, the present invention is characterized by:

[0023] 1. Wideband operating capability: Utilizing a wideband resonant mode generated by coupling multiple sets of parallel transverse metal strips (upper transverse metal strip, lower transverse metal strip, or straight segments of the upper or lower metal patch) with an arc-shaped structure, the modulation depth of the terahertz wave transmission amplitude is stably above 56% in the 0.49~0.62THz frequency band; and the modulation depth of the terahertz wave transmission amplitude exceeds 80% in the 0.53~0.60THz frequency band, meeting the wideband coverage requirements of 6G terahertz communication.

[0024] 2. Strong angular robustness: The design employs a combination of "multiple horizontal lines and double arcs" to form two highly symmetrical annular arc-shaped cavities. Utilizing the natural rotational symmetry of the annular arc structure, the logic output transmission window remains relatively stable even when the terahertz incident wave is incident at a large angle (θ deflection of 30~45°). This effectively solves the problems of resonance degradation and frequency drift during large-angle oblique incidence in existing technologies, and improves the encoding stability of the device in complex communication environments.

[0025] 3. Simplified bias wiring: This invention employs a through-type transverse metal strip design, allowing transmission units in the same row to share a through-type transverse metal strip (the upper transverse metal strip, the lower transverse metal strip, or the straight segment of the upper or lower metal patch). This design makes the bias electrode wiring in the micro-nano fabrication process extremely simple. The transverse metal strip serves both as the dipole antenna frame of the terahertz resonant structure and as a DC feed line to apply bias voltage to the graphene notch, completely eliminating the problem of needing to arrange complex and easily broken fine feed networks in traditional arrays, greatly improving the device yield and lifespan.

[0026] 4. High-performance NAND gate logic encoding: By grouping and controlling the transverse metal strips through comb-shaped lead-out electrodes, the terahertz wave transmittance is dynamically adjusted using the electronic control characteristics of the graphene Fermi level to realize NAND gate logic operations. The transmittance drops significantly below the threshold (logic 0) only when both input levels are 1; under other input combinations, the output is in a high transmittance state (logic 1), perfectly meeting the underlying logic operation requirements of terahertz space digital optical communication systems. Attached Figure Description

[0027] Figure 1 This is a three-dimensional structural diagram of the terahertz metasurface NAND gate logic encoder with electronically controlled conversion described in this invention.

[0028] Figure 2 for Figure 1 Top view.

[0029] Figure 3 for Figure 1 A schematic diagram of the structure of a single transmission unit.

[0030] Figure 4 for Figure 1 A bottom view.

[0031] Figure 5 This is a schematic diagram of the broadband logic response curves showing the terahertz wave transmittance as a function of frequency under different electrode input logic states (00, 01, 10, 11) according to the present invention.

[0032] The numbers on the map are:

[0033] 1 Common ground electrode, 2 Dielectric substrate layer, 3 Frequency control structure, 31 Upper transverse metal strip, 32 Lower transverse metal strip, 33 Upper metal patch, 34 Lower metal patch, 35 Graphene patch, 36 Electrode patch. Detailed Implementation

[0034] To better explain the technical solution of the present invention, the present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.

[0035] In this application, the meanings of width and height in the description of the transmission unit and a certain component therein are as follows: width refers to the length of the transmission unit or a certain component therein extending in the horizontal direction on the planar structural diagram of the transmission unit; height refers to the length of the transmission unit or a certain component therein extending in the vertical direction on the planar structural diagram of the transmission unit.

[0036] See Figures 1 to 4 The terahertz metasurface NAND gate logic encoder with electronic control conversion described in this invention includes an encoder body, which is composed of a common ground electrode 1 at the bottom, a dielectric substrate layer 2 in the middle, and a frequency control structure 3 at the top, which are tightly stacked from bottom to top.

[0037] A dielectric substrate layer 2 is stacked on the upper surface of the common ground electrode 1. Its shape can be any shape, such as circular, square, or polygonal, and its size is sufficient to accommodate the frequency control structure 3. The thickness of the dielectric substrate layer 2 is set to 10~30μm, ensuring both the mechanical support strength of the device and the formation of an effective electric field space between the top frequency control structure 3 and the bottom common ground electrode 1. The dielectric substrate layer 2 can be made of polyimide, quartz, or sapphire. In a preferred embodiment, polyimide is used to make the dielectric substrate layer 2, in which case the dielectric substrate layer 2 is called the polyimide layer. Using the polyimide layer as a flexible and low-loss dielectric substrate provides excellent light transmittance (refractive index) in the terahertz band. (The absorption coefficient is extremely low). In the preferred embodiment, the thickness of the dielectric substrate layer 2 is set to 20 μm.

[0038] The frequency control structure 3 is stacked on the upper surface of the dielectric substrate layer 2, and its plan view is as follows. Figure 2 As shown. The frequency control structure 3 includes a surface periodic structure and an extraction structure. The surface periodic structure is located in the middle of the frequency control structure 3 and consists of multiple transmission units arranged in a regular matrix. The extraction structure is located on the outer side of the surface periodic structure. Figure 2 In the embodiment shown, the surface periodic structure consists of 4×3 transmission units.

[0039] See Figure 3Each transmission unit is symmetrical about its transverse central axis. Each transmission unit consists of an upper transverse metal strip 31, a lower transverse metal strip 32, an upper metal patch 33, a lower metal patch 34, and four graphene patches 35. The upper transverse metal strip 31, lower transverse metal strip 32, upper metal patch 33, lower metal patch 34, and electrode patch 36 are made of gold or gold with a titanium layer attached to the bottom. The graphene patches 35 are made of single-layer graphene.

[0040] The upper transverse metal strip 31 and the lower transverse metal strip 32 extend laterally and are parallel to each other, respectively arranged at the top and bottom of the transmission unit. The upper metal patch 33 and the lower metal patch 34 have the same structure and shape, both being semi-circular rings, and both composed of straight metal strip segments and arc-shaped metal strip segments. The arc-shaped metal strip segments have two notches, which are respectively opened at the ends of the arc-shaped metal strip segments, that is, at the connection between the arc-shaped metal strip segments and the straight metal strip segments. The upper metal patch 33 and the lower metal patch 34 are symmetrically arranged between the upper transverse metal strip 31 and the lower transverse metal strip 32 with their straight metal strip segments adjacent to each other and with gaps, and the straight metal strip segments on each metal patch are parallel to the upper transverse metal strip 31 and the lower transverse metal strip 32, respectively.

[0041] This “bright mode (the metal strip in the middle of the transmission unit (the straight metal strip in the upper metal patch 33 / lower metal patch 34)) and the metal strip at the edge of the transmission unit (the upper horizontal metal strip / lower horizontal metal strip)) - dark mode (the arc-shaped metal strip with a notch)” structure can induce a strong LC resonant network in a specific frequency band through near-field coupling effect.

[0042] Moreover, the combination of the upper and lower semi-circular ring structures gives the entire transmission unit a symmetrical shape similar to a double ring. This highly symmetrical geometric structure is the key to achieving angular robustness.

[0043] Four graphene patches 35 are precisely attached to the notches on the arc-shaped metal strips constituting the upper metal patch 33 and the lower metal patch 34 using a micro-nano transfer process, thus closing the notches on each patch and functioning similarly to a "variable resistor switch". In practical applications, the height of the graphene patch 35 can be slightly greater than the height of the notch to ensure ohmic contact between the graphene patch 35 and the metal structure.

[0044] For a specific transmission unit, the width-to-height ratio of its substrate is 1:2.55~2.70. The width of the straight metal strip of the upper metal patch 33 or lower metal patch 34, the width of the upper transverse metal strip 31, and the width of the lower transverse metal strip 32 are all equal to the width of the transmission unit; the height of the straight metal strip of the upper metal patch 33 or lower metal patch 34, the height of the upper transverse metal strip 31, and the height of the lower transverse metal strip 32 are all equal; the outer diameter of the arc-shaped metal strip constituting the upper metal patch 33 or lower metal patch 34 is equal to its height. The widths of the straight metal strips are equal, and the inner diameter of the arc-shaped metal strips constituting the upper metal patch 33 or the lower metal patch 34 is 0.8 to 0.9 times its outer diameter; the height of the notch on the arc-shaped metal strip of the upper metal patch 33 or the lower metal patch 34 is 0.2 to 0.4 times the height of the straight metal strip of the upper metal patch 33 or the lower metal patch 34; the distance between the straight metal strips of the upper metal patch 33 and the straight metal strips of the lower metal patch 34 is equal to the height of the straight metal strips constituting the upper metal patch 33 or the lower metal patch 34.

[0045] Further, the width of the transmission unit substrate is 70~90μm, and the height is 200~220μm; the width of the straight metal strip of the upper metal patch 33 or the lower metal patch 34, the width of the upper transverse metal strip 31, and the width of the lower transverse metal strip 32 are all 70~90μm, and their heights are all 8~12μm; the distance between the straight metal strips of the upper metal patch 33 and the straight metal strips of the lower metal patch 34 is 8~12μm. The outer diameter (φ) of the arc-shaped metal strips constituting the upper metal patch 33 or the lower metal patch 34 is 90~110μm, and their inner diameter (φ) is 82~92μm; the height of the notch on the arc-shaped metal strip of the upper metal patch 33 or the lower metal patch 34 is 2~4μm. In the upper metal patch 33 or the lower metal patch 34, the distance between the graphene patch 35 disposed on the left side of them and the left edge of the transmission unit is 2~4μm; the distance between the graphene patch 35 disposed on the right side of the upper metal patch 33 or the lower metal patch 34 and the right edge of the transmission unit is also 2~4μm. The width of each graphene patch 35 is 2~4μm, and its height is equal to the height of the notch on the upper metal patch 33 or the lower metal patch 34. The thickness of the upper metal patch 33, the lower metal patch 34, the upper transverse metal strip 31, and the lower transverse metal strip 32 is 0.2~0.8μm, and the thickness of the graphene patch 35 is 0.3~1.0nm.

[0046] In a preferred embodiment of the present invention, the width of the transmission unit substrate is 80 μm and the height is 210 μm; the thickness of the upper metal patch 33 or lower metal patch 34, the upper transverse metal strip 31, and the lower transverse metal strip 32 is 0.2~0.8 μm; the width of the straight metal strip of the upper metal patch 33 or lower metal patch 34, the width of the upper transverse metal strip 31, and the width of the lower transverse metal strip 32 are all 80 μm, and their heights are all 10 μm; the outer diameter of the arc-shaped metal strip of the upper metal patch 33 or lower metal patch 34 is all 80 μm, and its inner diameter is all 64 μm; the height of the notch on the arc-shaped metal strip of the upper metal patch 33 or lower metal patch 34 is all 3 μm; the distance between the straight metal strip constituting the upper metal patch 33 and the straight metal strip constituting the lower metal patch 34 is 10 μm; the width of the graphene patch 35 is 3 μm, the height is 3 μm, and the thickness is 0.3~1.0 nm. The graphene patch 35 disposed on the left side of the upper metal patch 33 or the lower metal patch 34 is 3 μm away from the left edge of the transmission unit where it is located; and the graphene patch 35 disposed on the right side of the upper metal patch 33 or the lower metal patch 34 is also 3 μm away from the right edge of the transmission unit where it is located.

[0047] In the three adjacent transmission units (upper, middle, and lower), the upper horizontal metal strip 31 in the middle transmission unit is stacked with the lower horizontal metal strip 32 in the transmission unit above it, and the lower horizontal metal strip 32 in the middle transmission unit is stacked with the upper horizontal metal strip 31 in the transmission unit below it.

[0048] The lead-out structure consists of two electrode patches 36, both of which are comb-shaped. One electrode patch 36 is connected to the straight metal strip of the upper metal patch 33 in all transmission units, and the other electrode patch 36 is connected to the straight metal strip of the lower metal patch 34 in all transmission units. This group control method enables independent electrical control of the two graphene patches 35 in the transmission unit.

[0049] See Figure 4 A common ground electrode 1 is disposed on the bottom surface of the polyimide layer 2 and is fabricated into a closed ring with an inner diameter larger than the area of ​​the incident terahertz light spot, the center of which is perpendicular to the center of the surface periodic structure. This ring structure ensures a uniform bias zero potential while minimizing the physical obstruction of the transmitted terahertz wave by the metal. The common ground electrode 1 applies an electric field to the graphene patch 35 through the back-gate effect.

[0050] In the frequency control structure 3, the two electrode patches 36 are connected to the positive terminal of the external power supply, and the common ground electrode 1 is connected to the negative terminal of the external power supply. The external power supply is a DC regulated power supply with a voltage range of 5~24V. In a specific embodiment, a 12V DC regulated power supply is used.

[0051] The encoder of the present invention modulates the transmittance of the incident terahertz wave by adjusting the voltage state of the two electrode patches 36 and changing the Fermi level of the graphene patch 35, thereby completing the NAND gate logic operation.

[0052] According to the theory that graphene dominates in the terahertz band intraband transition, its dynamic surface conductivity σ can be approximated by the classical Drude model:

[0053]

[0054] Where ω is the angular frequency of the incident terahertz wave, E F Here, τ is the Fermi level, τ is the carrier scattering time, i is the imaginary unit, e is the elementary charge, and K is the energy level. B Where π is Boltzmann's constant, T is absolute temperature, and π is pi. is the reduced Planck constant.

[0055] When an electrostatic bias voltage V is applied between the top metal strip (electrode) and the bottom common ground electrode 1, g According to the parallel-plate capacitor model, the graphene layer will accumulate a high concentration of charge carriers, and its Fermi level will... A significant blue shift occurred.

[0056] When no voltage is applied (Fermi level is near the Dirac point): the carrier concentration of graphene patch 35 is extremely low, and the surface impedance is extremely high (behaving as an insulating dielectric state). At this time, the notches on the upper metal patch 33 / lower metal patch 34 are in an open circuit state, the metasurface array undergoes strong high quality factor resonance, and the electromagnetic wave transmittance is extremely high in the range of 0.5~1.5THz. At this time, the output is logic 1.

[0057] When a high voltage is applied (Fermi level jumps to 0.5 eV or above): the graphene patch 35 exhibits metallic properties, and its conductivity increases dramatically. At this time, the graphene patch 35 short-circuits the notches on the upper metal patch 33 and the lower metal patch 34, completely changing the original surface current topology path. The original broadband resonant mode is destroyed, and electromagnetic waves are largely reflected or absorbed by the structure in this frequency band, resulting in a precipitous drop in transmittance. At this time, the output is logic 0.

[0058] This invention utilizes the aforementioned physical mechanism to perform macroscopic digital logic operations. One electrode patch 36 is defined as input state variable A, and the other electrode patch 36 as input state variable B. 0V corresponds to logic input "0", and the turn-on voltage (e.g., 20V) corresponds to logic input "1". Using the transmittance T of the terahertz wave near 1.0THz as the output observation value, a threshold of 0.5 is set: when T>0.5, the output logic is determined to be "1"; when T<0.5, the output logic is determined to be "0". Based on this principle, the NAND gate logic device described in this invention has the following four operating states, such as... Figure 5 As shown:

[0059] State 1 (Input A=0, B=0): Neither of the two electrode patches 36 is biased. All lateral metal strips have no potential difference relative to the common ground electrode 1, and both graphene patches 35 are in a high-impedance state. At this time, the structure is highly transparent to incident broadband terahertz waves, with a broadband transmittance T greater than 0.4. The output logic is 1.

[0060] State 2 (Input A=0, B=1): The first electrode patch 36 is not pressurized, and the second electrode patch 36 is pressurized. At this time, the straight metal strips in the upper or lower metal patch 34 connected to the pressurized electrode patch 36 carry a high potential. The longitudinal electric field generated between these strips and the bottom ground electrode strongly dops the region of the connected graphene patch 35 (mainly affecting the Fermi level distribution at the notches on the upper metal patch 33 and lower metal patch 34). The conductivity of the graphene patch 35 increases, disrupting the overall resonant coupling, but the broadband transmission window has relatively low obstruction, and the transmittance remains around 0.35. The output logic is 1.

[0061] State 3 (Input A=1, B=0): First electrode patch 36 is pressurized, second electrode patch 36 is not pressurized. At this time, the straight metal strips in the lower metal patch 34 or upper metal patch connected to the pressurized electrode patch 36 carry a high potential. Similarly, the electric field strongly dops the graphene patch 35 at the connected notch, transforming it into a highly conductive state. The broadband transmission window has low impedance, and the transmission remains around 0.35. The output logic is 1.

[0062] State 4 (Input A=1, B=1): High potential is applied to both electrode patches 36. At this time, all transverse metal strips 31 have an electric field with respect to the common ground electrode 1, and the graphene patches 3532 throughout the structure are in a fully conductive, metal-like state. The resonant cavity is completely closed, the reflectivity of the structure reaches its peak, and the terahertz transmittance is extremely low (approaching 0.02). The output logic is 0.

[0063] As can be seen from the four states above, the output is 0 only when the input is (1,1); the output is 1 for any other input combination. This terahertz metasurface NAND gate logic encoder fully implements a pure and high-key NAND logic encoding function. Furthermore, due to the circular symmetry of the overall structure, even if the incident terahertz wave is deflected by 30~45°, the logic output transmission window remains relatively stable. Therefore, the encoder of this invention allows an incident angle θ of 0~45°.

[0064] In summary, this invention effectively overcomes the shortcomings of traditional terahertz devices, such as narrow bandwidth, angle sensitivity, and complex power feeding, through its unique metasurface structure combining a through-type transverse metal strip and an arc, and has outstanding industrial application value.

Claims

1. A terahertz metasurface NAND gate logic encoder with electronic control conversion, comprising an encoder body, the encoder body comprising a common ground electrode (1), a dielectric substrate layer (2), and a frequency control structure (3), wherein the common ground electrode (1) and the frequency control structure (3) are respectively stacked on the lower surface and the upper surface of the dielectric substrate layer (2); the frequency control structure (3) comprises a surface periodic structure and an output structure, the surface periodic structure being located in the middle of the frequency control structure (3); characterized in that, The surface periodic structure consists of multiple transmission units arranged in a regular matrix. Each transmission unit is composed of an upper transverse metal strip (31), a lower transverse metal strip (32), an upper metal patch (33), a lower metal patch (34), and four graphene patches (35). The upper metal patch (33) and the lower metal patch (34) have the same structure and shape, both being semi-circular rings composed of straight metal strip segments and arc-shaped metal strip segments. Two notches are provided on the arc-shaped metal strip segments, which are located at the connection points between the arc-shaped and straight metal strip segments. The upper metal patch (33) and the lower metal patch (34) are symmetrically arranged with their straight metal strip segments adjacent to each other and with gaps. Between the upper horizontal metal strip (31) and the lower horizontal metal strip (32), and the straight segments of the metal strips on each metal patch are parallel to the upper horizontal metal strip (31) and the lower horizontal metal strip (32) respectively; four graphene patches (35) are respectively disposed at the gaps of the upper metal patch (33) and the lower metal patch (34), and the gaps on each metal patch are closed; in the three adjacent transmission units at the upper, middle and lower positions, the upper horizontal metal strip (31) in the middle transmission unit is superimposed with the lower horizontal metal strip (32) in the transmission unit above it, and the lower horizontal metal strip (32) in the middle transmission unit is superimposed with the upper horizontal metal strip (31) in the transmission unit below it; The lead-out structure is located on the outer side of the surface periodic structure and consists of two electrode patches (36); one electrode patch (36) is connected to the straight metal strip of the upper metal patch (33) in all transmission units, and the other electrode patch (36) is connected to the straight metal strip of the lower metal patch (34) in all transmission units. The two electrode patches (36) are respectively connected to the positive terminal of the external power supply, and the common ground electrode (1) is connected to the negative terminal of the external power supply.

2. The electrically controlled switched terahertz metasurface and NAND gate logic encoder of claim 1, wherein, The center of the common ground electrode (1) is perpendicular to the center of the surface periodic structure.

3. The electrically controlled switched terahertz metasurface and NAND gate logic encoder of claim 1, wherein, The common ground electrode (1) is a closed ring structure.

4. The electrically controlled switched terahertz metasurface and NAND gate logic encoder of any of claims 1-3, wherein In the transmission unit, the width-to-height ratio of the transmission unit substrate is 1:2.55~2.70, where, The width of the straight metal strip of the upper metal patch (33) or the lower metal patch (34), the width of the upper transverse metal strip (31) and the width of the lower transverse metal strip (32) are all equal to the width of the transmission unit. The height of the straight section of the upper metal patch (33) or the lower metal patch (34), the height of the upper horizontal metal strip (31), and the height of the lower horizontal metal strip (32) are equal. The outer diameter of the arc-shaped metal strip constituting the upper metal patch (33) or the lower metal patch (34) is equal to the width of its straight metal strip, and the inner diameter of the arc-shaped metal strip constituting the upper metal patch (33) or the lower metal patch (34) is 0.8 to 0.9 times its outer diameter. The height of the notch on the arc-shaped metal strip of the upper metal patch (33) or the lower metal patch (34) is 0.2 to 0.4 times the height of the straight metal strip of the upper metal patch (33) or the lower metal patch (34); The distance between the straight metal strip of the upper metal patch (33) and the straight metal strip of the lower metal patch (34) is equal to the height of the straight metal strip that constitutes the upper metal patch (33) or the lower metal patch (34).

5. The electrically controlled switched terahertz metasurface and NAND gate logic encoder of claim 5, wherein, The width of the substrate of the transmission unit is 70~90μm and the height is 200~220μm; the width of the straight metal strip of the upper metal patch (33) or the lower metal patch (34), the width of the upper transverse metal strip (31) and the width of the lower transverse metal strip (32) are all 70~90μm, and their heights are all 8~12μm; the distance between the straight metal strip of the upper metal patch (33) and the straight metal strip of the lower metal patch (34) is 8~12μm.

6. The electrically controlled switched terahertz metasurface and NAND gate logic encoder of claim 5, wherein, The outer diameter of the arc-shaped metal strip constituting the upper metal patch (33) or the lower metal patch (34) is 90~110μm, and its inner diameter is 82~92μm; the height of the notch on the arc-shaped metal strip of the upper metal patch (33) or the lower metal patch (34) is 2~4μm.

7. The terahertz metasurface NAND gate logic encoder with electronically controlled conversion according to claim 5, characterized in that, The distance between the graphene patch (35) and the left or right edge of the transmission unit is 2~4μm; the width of the graphene patch (35) is 2~4μm, and its height is equal to the height of the notch on the upper metal patch (33) or the lower metal patch (34).

8. The terahertz metasurface NAND gate logic encoder with electronically controlled conversion according to claim 5, characterized in that, The thickness of the upper metal patch (33), the lower metal patch (34), the upper transverse metal strip (31) and the lower transverse metal strip (32) is 0.2~0.8μm, and the thickness of the graphene patch (35) is 0.3~1.0nm.

9. The terahertz metasurface NAND gate logic encoder with electronically controlled conversion according to any one of claims 1 to 3, characterized in that, The thickness of the dielectric substrate layer (2) is 10~30μm.

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