Charging circuit and charging method based on flyback converter

Abstract

This application discloses a charging circuit and method based on a flyback converter, belonging to the field of circuit technology. The circuit collects the error voltage between the input and output voltages of the flyback converter; outputs a high-level signal when a knee point is detected at the target node in the flyback converter; periodically converts the error voltage into a high-level signal in discontinuous conduction mode; or, periodically converts the error voltage into a high-level signal in low-ripple burst mode; after receiving two high-level signals, it controls the primary-side power transistor to turn on to start a charging cycle; in boundary conduction mode, it outputs a high-level signal when the target node voltage reaches the peak voltage corresponding to the error voltage; and controls the primary-side power transistor to turn off according to the high-level signal to end a charging cycle. This application can achieve adaptive matching between the switching frequency and the load size, enabling the charging circuit to simultaneously achieve high conversion efficiency and low output ripple over a wide load range from heavy load to no load.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a charging circuit and charging method based on a flyback converter. Background Technology

[0002] Flyback converters are widely used in battery charging equipment due to their simple structure, low cost, and ease of implementing multiple outputs. In flyback converter-based charging circuits, precise control of the primary-side power transistor's on / off state is typically required to achieve efficient energy conversion and stable output voltage.

[0003] One existing control method employs peak current control. Specifically, it detects the primary current and compares it with an error voltage. When the primary current reaches the peak value set by the error voltage, the primary power transistor is turned off. Simultaneously, the primary power transistor is turned back on by detecting the voltage knee point generated when the secondary current of the transformer crosses zero. This control method can achieve high conversion efficiency under heavy load conditions.

[0004] However, the aforementioned control methods still have shortcomings in application scenarios with a wide range of load variations, especially during the entire battery charging process from heavy load to light load and even no load. Under light load or no load conditions, if the converter still maintains a high switching frequency, the proportion of switching losses in the total losses will increase sharply, reducing the system's conversion efficiency under light load conditions. If the light load losses are reduced simply by lowering the switching frequency, it may lead to increased output voltage ripple, affecting the stability and safety of battery charging. Therefore, how to balance high conversion efficiency and low output ripple over a wide load range is a technical problem that urgently needs to be solved in the current flyback charging circuit design field. Summary of the Invention

[0005] This application provides a charging circuit and method based on a flyback converter to solve the problem of balancing high conversion efficiency and low output ripple over a wide load range. The technical solution is as follows: According to a first aspect of this application, a charging circuit based on a flyback converter is provided, the charging circuit including an oscillator frequency adjustment module, a sleep time adjustment module, a peak current adjustment module, a knee detection module, and a logic control module; The oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module are used to collect the error voltage between the input voltage and the output voltage of the flyback converter. The knee detection module is used to output a high-level signal when a knee is detected in the target node of the flyback converter, and output the high-level signal to the logic control module; when the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module is used to periodically convert the error voltage into a high-level signal and output the high-level signal to the logic control module; or, when the charging circuit is in low ripple burst mode, the sleep time adjustment module is used to periodically convert the error voltage into a high-level signal and output the high-level signal to the logic control module; the logic control module is used to control the primary-side power transistor to turn on after receiving the high-level signal output by the oscillator frequency adjustment module and the high-level signal output by the knee detection module, or after receiving the high-level signal output by the sleep time adjustment module and the high-level signal output by the knee detection module, to start a charging cycle; When the charging circuit is in boundary conduction mode, the peak current adjustment module is used to output a high-level signal to the logic control module when the target node voltage reaches the peak voltage corresponding to the error voltage; the logic control module is used to control the primary-side power transistor to turn off according to the high-level signal to end a charging cycle.

[0006] In one possible implementation, the oscillator frequency adjustment module includes a first current converter, an offset current source, a capacitor, an adjustment power transistor, and a first comparator; The input terminal of the first current converter serves as the input terminal of the oscillator frequency adjustment module, and the output terminal of the first current converter is connected to the input terminal of the offset current source, the first terminal of the capacitor, the drain of the regulating power transistor, and the non-inverting input terminal of the first comparator. The output terminal of the offset current source, the second terminal of the capacitor, and the source of the regulating power transistor are grounded; The gate of the regulating power transistor is connected to the driver of the primary power transistor. The inverting input of the first comparator is connected to the threshold voltage terminal, and the output of the first comparator serves as the output of the oscillator frequency adjustment module.

[0007] In one possible implementation, the oscillator frequency adjustment module is further configured to: After the error voltage is converted into a first error current by the first current converter, if the first error current is greater than the offset current generated by the offset current source, the first error current is used to charge the capacitor until the voltage of the capacitor reaches the threshold voltage output by the threshold voltage terminal, and then the first comparator is controlled to output a high-level signal; after the high-level signal is used to control the driver to output a high-level signal, the regulating power transistor is controlled to turn on so that the first comparator outputs a low-level signal. If the first error current is less than or equal to the offset current, the first comparator is controlled to continuously output a low-level signal so that the charging circuit enters the low-ripple burst mode.

[0008] In one possible implementation, the peak current regulation module includes a second current converter, an induction array, a second comparator, and a switch. The induction array includes multiple power transistors connected in parallel, and the impedance of the induction array is n times the impedance of the primary-side power transistors, where n is a positive integer. The input terminal of the second current converter serves as the first input terminal of the peak current regulation module, and the output terminal of the second current converter is connected to the drain of the induction array and the inverting input terminal of the second comparator. The source of the induction array is grounded, and the gate of the induction array serves as the second input terminal of the peak current regulation module, connected to the driver of the primary power transistor and the control terminal of the switch. The first terminal of the switch serves as the third input terminal of the peak current regulation module and is connected to the target node; the second terminal of the switch is connected to the non-inverting input terminal of the second comparator. The output of the second comparator serves as the output of the peak current adjustment module.

[0009] In one possible implementation, the peak current regulation module is further configured to: After the error voltage is converted into a second error current by the second current converter, the second error current is used to control the induction array to sample the current flowing through the primary power transistor. After the current reaches the current threshold, the switch is controlled to close, and the target node voltage is transmitted to the non-inverting input of the second comparator. When the target node voltage reaches the peak voltage corresponding to the error voltage, the second comparator is controlled to output a high-level signal.

[0010] In one possible implementation, the logic control module is further configured to: When the charging circuit is in intermittent conduction mode, a high-level signal is output to the driver according to the high-level signal output by the oscillator frequency adjustment module and the high-level signal output by the knee detection module, so that the driver controls the primary power transistor to conduct. When the charging circuit is in low ripple burst mode, a high-level signal is output to the driver according to the high-level signal output by the sleep time adjustment module and the high-level signal output by the knee detection module, so that the driver controls the primary-side power transistor to turn on. When the charging circuit is in boundary conduction mode, a low-level signal is output to the driver according to the high-level signal output by the peak current adjustment module, so that the driver controls the primary-side power transistor to turn off.

[0011] In one possible implementation, the sleep time adjustment module is further configured to: After detecting that the oscillator frequency adjustment module continuously outputs a low-level signal, it performs periodic sleep according to the error voltage, and outputs a high-level signal to the logic control module after each sleep period.

[0012] In one possible implementation, the sleep duration of the sleep time adjustment module is negatively correlated with the magnitude of the error voltage.

[0013] In one possible implementation, the target node is the connection node between the primary power transistor and the primary winding of the transformer in the flyback converter.

[0014] According to a second aspect of this application, a charging method based on a flyback converter is provided for use in the charging circuit described above, the method comprising: The oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module collect the error voltage between the input voltage and the output voltage of the flyback converter; The knee detection module outputs a high-level signal when it detects a knee at the target node, and sends the high-level signal to the logic control module. When the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module periodically converts the error voltage into a high-level signal and sends the high-level signal to the logic control module. Alternatively, when the charging circuit is in low-ripple burst mode, the sleep time adjustment module periodically converts the error voltage into a high-level signal and sends the high-level signal to the logic control module. Upon receiving the high-level signal from both the oscillator frequency adjustment module and the knee detection module, or upon receiving both the high-level signal from the sleep time adjustment module and the knee detection module, the logic control module controls the primary-side power transistor to turn on to begin a charging cycle. When the charging circuit is in boundary conduction mode, the peak current adjustment module outputs a high-level signal to the logic control module when the target node voltage reaches the peak voltage corresponding to the error voltage; the logic control module controls the primary-side power transistor to turn off according to the high-level signal to end a charging cycle.

[0015] The beneficial effects of the technical solution provided in this application include at least the following: As the load current gradually decreases from heavy load to light load and then to no load, the error voltage gradually decreases. The charging circuit adaptively operates sequentially in boundary conduction mode, intermittent conduction mode, and low-ripple burst mode based on the magnitude of the error voltage. Under heavy load, a higher switching frequency and larger peak current ensure energy transfer efficiency; under light load, the oscillator frequency adjustment module delays the reduction of the switching frequency to reduce switching losses; under no load, the low-ripple burst mode achieves extremely low static power consumption and maintains low output ripple. Thus, by delaying the switching frequency control strategy, an adaptive match between the switching frequency and the load size is achieved, enabling the charging circuit to simultaneously maintain high conversion efficiency and low output ripple across a wide load range from heavy load to no load. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a structural block diagram of a charging circuit based on a flyback converter provided in one embodiment of this application; Figure 2This is a waveform diagram of a charging circuit provided in one embodiment of this application in boundary conduction mode; Figure 3 This is a waveform diagram of a charging circuit provided in an embodiment of this application in intermittent conduction mode; Figure 4 This is a waveform diagram of a charging circuit provided in an embodiment of this application in low ripple burst mode; Figure 5 This is a flowchart of a charging method based on a flyback converter provided in one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0019] like Figure 1 As shown, it illustrates a structural block diagram of a flyback converter-based charging circuit provided in one embodiment of this application. Figure 1 The diagram only shows the reflected voltage detection circuit, error amplifier circuit, driver, and primary-side power transistor M in the flyback converter. L The primary winding, secondary winding, and load are shown; the rest are not shown. The reflected voltage detection module is connected to the input voltage terminal IN and the target node SW to sample the input voltage V of the flyback converter. IN and target node voltage V SW The input voltage V IN and target node voltage V SW It can reflect the output voltage V of the flyback converter OUT The reflected voltage detection module transmits the sampled voltage to the error amplifier circuit, which amplifies the sampled voltage to obtain the error voltage V. C The error voltage V C The output is supplied to the charging circuit. The target node SW is the primary-side power transistor M in the flyback converter. L Connection node with the primary winding of the transformer.

[0020] The charging circuit is based on the error voltage V C The size of the signal adaptively and periodically outputs control signals to the driver to control the primary-side power transistor M. L The charging circuit controls the flyback converter to operate in Boundary Conduction Mode (BCM), Discontinuous Conduction Mode (DCM), or Low Ripple Burst Mode (LRBM). When the error voltage VC When the load is large, the charging circuit operates at a higher switching frequency in boundary conduction mode to meet the energy transfer requirements under heavy load conditions.

[0021] When the error voltage V C When the load is reduced, the charging circuit correspondingly reduces the switching frequency and operates in discontinuous conduction mode to reduce switching losses under light load conditions.

[0022] When the error voltage V C When reduced to extremely low values, the charging circuit operates in a low-ripple burst mode with intermittent burst pulses, achieving low static power consumption and low output ripple under extremely light load or no-load conditions.

[0023] Through the aforementioned adaptive adjustment, the charging circuit achieves both high conversion efficiency and low output ripple over a wide load range. The specific structure of the charging circuit is described below.

[0024] The charging circuit based on the flyback converter may include an oscillator frequency adjustment module 110, a sleep time adjustment module 120, a peak current adjustment module 130, a knee detection module 140, and a logic control module 150. The oscillator frequency adjustment module 110, the sleep time adjustment module 120, and the peak current adjustment module 130 serve as input terminals of the charging circuit and are connected to an error amplification module to acquire the error voltage V between the input and output voltages of the flyback converter. C .

[0025] Knee detection module 140 is used to output a high-level signal V when a knee point is detected at the target node SW in the flyback converter. TRIG The high-level signal V TRIG The output is sent to the logic control module 150. The knee point, in the flyback converter, refers to the point where the voltage waveform at the target node SW transitions from the resonant stage to the flat stage when the secondary winding current drops to zero. The knee point signifies that the transformer has completed core reset and is the point where the primary power transistor M... L A safe moment when it can be reconnected.

[0026] When the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module 110 is used to periodically adjust the error voltage V. C Converted to a high-level signal V OSC The high-level signal V OSC The output is sent to the logic control module 150. The logic control module 150 is used to respond to the high-level signal V received from the oscillator frequency adjustment module 110. OSC and the high-level signal V output by the knee detection module 140 TRIG Then, control the primary power transistor M. L Turn on to begin a charging cycle.

[0027] When the charging circuit is in low ripple burst mode, the sleep time adjustment module 120 is used to periodically adjust the error voltage V. C Converted to a high-level signal V SLP The high-level signal V SLP The output is sent to the logic control module 150. The logic control module 150 is used to respond to the high-level signal V output from the sleep time adjustment module 120. SLP and the high-level signal V output by the knee detection module 140 TRIG Then, control the primary power transistor M. L Turn on to begin a charging cycle.

[0028] When the charging circuit is in boundary conduction mode, the peak current regulation module 130 is used to adjust the target node voltage V. SW Reaching the error voltage V C When the corresponding peak voltage is reached, a high-level signal V is output to the logic control module 150. PK ; Logic control module 150, used to respond to high-level signal V PK Control of primary power transistor M L Turn off to end a charging cycle.

[0029] The circuit structure and working principle of the oscillator frequency adjustment module 110, peak current adjustment module 130, sleep time adjustment module 120 and logic control module 150 are described in detail below.

[0030] (a) Oscillator frequency adjustment module 110 The oscillator frequency adjustment module 110 includes a first current converter V2I1, an offset current source I, a capacitor C, and an adjustment power transistor M. OSC The first comparator CMP1; wherein, the input terminal of the first current converter V2I1 serves as the input terminal of the oscillator frequency adjustment module 110, and the output terminal of the first current converter V2I1 is connected to the input terminal of the offset current source I, the first terminal of the capacitor C, and the regulating power transistor M. OSC The drain of the capacitor is connected to the non-inverting input of the first comparator CMP1; the output of the offset current source I, the second terminal of the capacitor C, and the regulating power transistor M are connected. OSC The source is grounded; adjust the power transistor M. OSC The gate and primary power transistor M L The driver is connected; the inverting input of the first comparator CMP1 is connected to the threshold voltage terminal, and the output of the first comparator CMP1 is used as the output of the oscillator frequency adjustment module 110.

[0031] The oscillator frequency adjustment module 110 is also used to: convert the error voltage V through the first current converter V2I1 CConverted into the first error current I CHG Then, if the first error current I CHG The offset current I generated by the offset current source I is greater than the offset current I. OS Then, using the first error current I CHG Charge capacitor C until the voltage across capacitor C reaches the threshold voltage V output at the threshold voltage terminal. TH_OSC At that time, the first comparator CMP1 is controlled to output a high-level signal V. OSC ; using high-level signal V OSC The control driver outputs a high-level signal V. GL Then, control and regulate the power transistor M OSC Turn on, so that the first comparator CMP1 outputs a low-level signal V. OSC Among them, the first error current I CHG With error voltage V C There is a positive correlation, that is, the error voltage V C The larger the value, the greater the first error current I. CHG The larger the error voltage V, the greater the error voltage V. C The smaller the value, the lower the first error current I. CHG The smaller.

[0032] If the first error current I CHG Greater than the offset current I OS Then, using the first error current I CHG With offset current I OS The differential current charges capacitor C, and the voltage across capacitor C increases linearly with time. When the voltage across capacitor C reaches the threshold voltage V at the threshold voltage terminal... TH_OSC When the first comparator CMP1 flips, it outputs a high-level signal V. OSC The high-level signal V OSC The output of the oscillator frequency adjustment module 110 is provided to the logic control module 150. The logic control module 150 receives the high-level signal V. OSC Then, the high-level signal V output by the knee point detection module 140 TRIG Together, they control the driver to output a high-level signal V. GL This makes the primary power transistor M L The circuit is turned on, initiating a new charging cycle. Simultaneously, the driver outputs a high-level signal V. GL It is also used to control and regulate the power transistor M. OSC Turn on. Adjust power transistor M. OSC After conduction, capacitor C regulates the power transistor M OSC Rapid discharge causes the voltage of capacitor C to return to zero, pulling the non-inverting input of the first comparator CMP1 low. The output of the first comparator CMP1 then returns to a low level, completing one oscillation cycle.

[0033] The oscillator frequency adjustment module 110 is also used to: if the first error current I CHG If the current is less than or equal to the offset current, the first comparator CMP1 will continuously output a low-level signal V. OSC This allows the charging circuit to enter a low-ripple burst mode.

[0034] If the first error current I CHG Less than or equal to the offset current I OS If the differential current is zero or negative, capacitor C cannot be charged, and the first comparator CMP1 continuously outputs a low-level signal V. OSC The oscillator frequency adjustment module 110 stops periodic switching, and the charging circuit enters a low ripple burst mode.

[0035] The output signal frequency and error voltage V of the oscillator frequency adjustment module 110 C There is a positive correlation, that is, the error voltage V C The larger the value, the greater the first error current I. CHG The larger the value, the faster the capacitor C charges and the higher the oscillation frequency; the error voltage V C The smaller the value, the lower the first error current I. CHG The smaller the value, the slower the capacitor C charges, and the lower the oscillation frequency. When the error voltage V... C Reduce to the level that makes the first error current I CHG Less than or equal to the offset current I OS At that time, the oscillator stops working.

[0036] In the above workflow, the oscillator frequency adjustment module 110 uses the first error current I... CHG With offset current I OS The method of charging capacitor C with the difference in voltage achieves the technical effect of delaying the decrease in switching frequency as the load lightens. Specifically, as the load gradually decreases from heavy to light, the error voltage V... C The corresponding decrease in the first error current I CHG This also decreases accordingly. Since the charging current of capacitor C is the first error current I... CHG With offset current I OS The difference when I CHG When the current decreases, the charging current decreases, and the voltage rise rate of capacitor C slows down until it reaches the threshold voltage V. TH_OSC The required time is extended, causing the first comparator CMP1 to output a high-level signal V. OSC The switching cycle is lengthened, and the switching frequency is correspondingly reduced. When the switching frequency is reduced, the number of switching operations per unit time decreases, and the switching losses are reduced accordingly, thereby effectively improving the switching efficiency under light load conditions.

[0037] (ii) Peak current regulation module 130 The peak current regulation module 130 includes a second current converter V2I2, an induction array, a second comparator CMP2, and a switch S. The induction array includes multiple power transistors connected in parallel, and the impedance of the induction array is equal to the impedance of the primary power transistor M. L The impedance is n times the input of the peak current adjustment module 130, where n is a positive integer. The input terminal of the second current converter V2I2 serves as the first input terminal of the peak current adjustment module 130, and the output terminal of the second current converter V2I2 is connected to the drain of the induction array and the inverting input terminal of the second comparator CMP2. The source of the induction array is grounded, and the gate of the induction array serves as the second input terminal of the peak current adjustment module 130, connected to the primary-side power transistor M. L The driver and the control terminal of switch S are connected; the first terminal of switch S serves as the third input terminal of peak current adjustment module 130 and is connected to the target node; the second terminal of switch S is connected to the non-inverting input terminal of second comparator CMP2; the output terminal of second comparator CMP2 serves as the output terminal of peak current adjustment module 130.

[0038] The peak current regulation module 130 is also used to: convert the error voltage V through the second current converter V2I2 C After being converted into a second error current, the second error current is used to control the sampling current of the induction array flowing through the primary-side power transistor M. L The current, when the current reaches the current threshold I PK After the control switch is closed, the target node voltage V is... SW The signal is transmitted to the non-inverting input of the second comparator CMP2, at the target node voltage V. SW Reaching error voltage V C When the corresponding peak voltage is reached, the second comparator CMP2 is controlled to output a high-level signal V. PK Among them, the second error current and the error voltage V C There is a positive correlation, that is, the error voltage V C The larger the value, the larger the second error current; the larger the error voltage V. C The smaller the value, the smaller the second error current.

[0039] The second error current flows through the induction array. Since the impedance of the induction array is the primary-side power transistor M... L The impedance is n times that of the current sampled by the induction array and the current sampled by the primary power transistor M. L The current is proportional to the voltage. The drain voltage of the induction array reflects the current of the primary-side power transistor M. L The magnitude of the current. As the primary power transistor M... L The increase in conduction time increases the flow of current through the primary power transistor M. L The current increases linearly. When the primary power transistor M... L The current reaches the current threshold I set by the second error current. PKAt that time, the drain voltage of the induction array triggers the control terminal of switch S, causing switch S to close. After switch S closes, the target node voltage V... SW It is transmitted to the non-inverting input of the second comparator CMP2. With the primary-side power transistor M... L The current continues to rise, and the target node voltage V SW It also continues to rise. When the target node voltage V SW Reaching the error voltage V C The corresponding peak voltage V IPK When the second comparator CMP2 flips, its output changes from low to high, and this high-level signal V... PK The peak current regulation module 130 outputs the signal, which is then supplied to the logic control module 150. The logic control module 150 receives the high-level signal V. PK Then, a low-level signal is output to the driver, causing the driver to control the primary-side power transistor M. L Turn off, ending the current charging cycle.

[0040] In the above workflow, the peak current adjustment module 130 sets the peak current threshold I. PK With error voltage V C There is a positive correlation, that is, the error voltage V C The larger the peak current threshold I is PK The higher the voltage, the more energy is transferred per charging cycle; error voltage V C The smaller the value, the lower the peak current threshold I. PK The lower the value, the less energy is transferred per charging cycle.

[0041] (III) Sleep Time Adjustment Module 120 The sleep time adjustment module 120 is also used to detect that the oscillator frequency adjustment module 110 continuously outputs a low-level signal V. OSC Then, based on the error voltage V C It performs periodic sleep mode, and after each sleep mode ends, it outputs a high-level signal V to the logic control module 150. SLP .

[0042] Specifically, the sleep time adjustment module 120 monitors the output signal of the oscillator frequency adjustment module 110 in real time. When it detects that the oscillator frequency adjustment module 110 continuously outputs a low-level signal V... OSC At this time, the sleep time adjustment module 120 determines that the current charging circuit has met the conditions for entering the low ripple burst mode. Among them, the continuous output of a low-level signal means that the first comparator CMP1 of the oscillator frequency adjustment module 110 no longer flips periodically, but outputs a stable low-level signal.

[0043] Then, the sleep time adjustment module 120 adjusts the sleep time according to the current error voltage V. CDetermine the hibernation duration T SLP Among them, the sleep duration T of the sleep time adjustment module 120 SLP With error voltage V C The magnitudes of these are negatively correlated. That is, the error voltage V C The larger the value, the longer the hibernation time T. SLP The longer; the greater the error voltage V C The smaller the value, the longer the hibernation time T. SLP The shorter.

[0044] The sleep time adjustment module 120 controls the charging circuit to enter sleep mode. During sleep mode, the charging circuit stops switching, and the primary-side power transistor M... L The system remains off to reduce static power consumption. After the sleep period ends, the sleep time adjustment module 120 outputs a high-level signal V to the logic control module 150. SLP The logic control module 150 simultaneously receives this high-level signal V. SLP The high-level signal V output by the knee point detection module 140 TRIG Control the primary power transistor M L When the circuit is turned on, it executes one or a few switching pulses to maintain the output voltage within the set range. After the switching pulses are completed, the charging circuit enters sleep mode again, forming a periodic sleep-operation low-ripple burst mode.

[0045] In the above workflow, the sleep time adjustment module 120 adjusts the sleep time according to the error voltage V. C Adaptively adjust the sleep duration. Specifically, when the load is slightly heavier (error voltage V), C When the load is slightly higher (error voltage V), the sleep duration is shorter and the burst pulse frequency is higher to ensure sufficient energy transfer; when the load is extremely light (error voltage V), the sleep duration is shorter and the burst pulse frequency is higher. C When the voltage is extremely low, the sleep duration is relatively long and the burst pulse frequency is extremely low in order to minimize static power consumption while maintaining stable output voltage and low ripple.

[0046] (iv) Logic control module 150 In this embodiment, the logic control module 150 monitors the output signals of the oscillator frequency adjustment module 110, the sleep time adjustment module 120, the peak current adjustment module 130, and the knee detection module 140 in real time, and adjusts the output signals according to the error voltage V. C The size determines the current operating mode of the charging circuit.

[0047] Specifically, the logic control module 150 is also used for: When the charging circuit is in intermittent conduction mode, according to the high-level signal V output by the oscillator frequency adjustment module 110 OSC The high-level signal V output by the knee point detection module 140 TRIGA high-level signal is output to the driver so that the driver controls the primary-side power transistor M. L Conduction; When the charging circuit is in low ripple burst mode, the high-level signal V output by the sleep time adjustment module 120 is used. SLP The high-level signal V output by the knee point detection module 140 TRIG A high-level signal is output to the driver so that the driver controls the primary-side power transistor M. L Conduction; When the charging circuit is in boundary conduction mode, according to the high-level signal V output by the peak current adjustment module 130 PK Output a low-level signal to the driver so that the driver controls the primary-side power transistor M. L Turn off.

[0048] In this embodiment, as the load gradually decreases from heavy load to light load, the error voltage V... C As the frequency gradually decreases, the switching frequency of the charging circuit exhibits a slow decreasing trend, successively passing through three stages: boundary conduction mode, intermittent conduction mode, and low ripple burst mode, as detailed below: In boundary conduction mode, the switching frequency is determined by the transformer core reset time and is at a relatively high level. When the load decreases, the error voltage V... C As the current decreases, the peak current threshold drops, the energy transferred per charging cycle decreases, and the switching frequency begins to decrease more slowly. Figure 2 The waveform of the charging circuit in boundary conduction mode is shown. In boundary conduction mode, the driver outputs a high-level signal V. GL To control the primary power transistor M L When the circuit is turned on, the primary current I P Linear increase; when the primary current I P Reaching peak current threshold I PK At that time, V GL When the signal becomes low, the primary power transistor M... L When turned off, the primary current I P The secondary current I drops rapidly to zero. S Linear decrease; when the secondary current I S When it drops to zero, the target node voltage V SW Knee point appears, V GL At this knee point, the voltage level rises again, and the primary-side power transistor M... L Reconnection was achieved.

[0049] When the error voltage V C After the voltage drops to a certain level, the charging circuit enters an intermittent conduction mode. In this mode, the switching frequency is further controlled by the oscillator frequency adjustment module 110. As mentioned earlier, the oscillator frequency adjustment module 110 adjusts the switching frequency according to the error voltage V.C The reduction in switching losses is slowed down as the switching rate decreases, and the switching losses are reduced accordingly. Figure 3 The waveform of the charging circuit in discontinuous conduction mode is shown. In discontinuous conduction mode, when the secondary current I... S After dropping to zero, the target node voltage V SW It begins to exhibit decaying oscillations; V GL It remains a low-level signal with a dead time; at some point after the dead time ends, V... GL The primary-side power transistor M becomes a high-level signal. L Once the circuit is turned on, the next charging cycle begins, and the switching frequency decreases as the load lightens.

[0050] When the error voltage V C Continue to decrease until it is less than or equal to the offset current I OS When the corresponding threshold is reached, the oscillator frequency adjustment module 110 stops periodically switching, and the charging circuit enters a low-ripple burst mode. In the low-ripple burst mode, the charging circuit no longer maintains continuous switching action, but operates in the form of burst pulses. The switching action is significantly delayed or even suspended, and only a few switching pulses are executed when necessary to maintain the output voltage. Figure 4 The waveform of the charging circuit in low ripple burst mode is shown. In low ripple burst mode, V GL The primary-side power transistor M remains at a low level during a relatively long sleep period. L Keep off, target node voltage V SW No switching action; after sleep mode ends, V GL Output one or a few high-level pulses, primary-side power transistor M L This corresponds to one or a few switching cycles being activated to perform a burst of energy transfer; after the burst ends, V GL When the signal goes low again, the charging circuit returns to sleep mode. This process repeats periodically to achieve extremely low static power consumption and low output ripple.

[0051] By employing the aforementioned control strategy of delaying the switching frequency, this embodiment achieves adaptive matching between the switching frequency and the load size. Specifically, under heavy load, a higher switching frequency is maintained to ensure energy transfer efficiency; under light load, the switching frequency is delayed to reduce switching losses; and under extremely light load, a low-ripple burst mode replaces continuous switching, further reducing power consumption and controlling output ripple. In this way, high conversion efficiency and low output ripple are balanced across the entire load range.

[0052] In summary, the flyback converter-based charging circuit provided in this application embodiment adaptively operates sequentially in boundary conduction mode, intermittent conduction mode, and low-ripple burst mode according to the magnitude of the error voltage as the load current gradually decreases from heavy load to light load and no load. Under heavy load, a higher switching frequency and a larger peak current ensure energy transfer efficiency; under light load, the oscillator frequency adjustment module delays the reduction of the switching frequency to reduce switching losses; under no load, the low-ripple burst mode achieves extremely low static power consumption and maintains low output ripple. Thus, by delaying the switching frequency control strategy, adaptive matching between the switching frequency and the load size is achieved, enabling the charging circuit to simultaneously achieve high conversion efficiency and low output ripple across a wide load range from heavy load to no load.

[0053] like Figure 5 The diagram illustrates a flowchart of a flyback converter-based charging method according to an embodiment of this application. The flyback converter-based charging method includes: Step 501: The oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module collect the error voltage between the input voltage and the output voltage of the flyback converter.

[0054] The reflected voltage detection module in the flyback converter collects the input voltage and the target node voltage, and transmits the sampled voltage to the error amplifier circuit. The error amplifier circuit amplifies the sampled voltage to obtain the error voltage, and outputs the error voltage to the oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module. The oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module receive the error voltage.

[0055] Step 502: When the knee detection module detects a knee at the target node, it outputs a high-level signal to the logic control module. When the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module periodically converts the error voltage into a high-level signal and outputs it to the logic control module. Alternatively, when the charging circuit is in low-ripple burst mode, the sleep time adjustment module periodically converts the error voltage into a high-level signal and outputs it to the logic control module. Upon receiving the high-level signals from the oscillator frequency adjustment module and the knee detection module, or upon receiving the high-level signals from the sleep time adjustment module and the knee detection module, the logic control module controls the primary-side power transistor to turn on to begin a charging cycle.

[0056] When the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module converts the error voltage into a first error current through a first current converter. If the first error current is greater than the offset current generated by the offset current source, the first error current is used to charge the capacitor until the capacitor voltage reaches the threshold voltage output at the threshold voltage terminal. At this point, the first comparator is controlled to output a high-level signal. After controlling the driver to output a high-level signal using the high-level signal, the regulating power transistor is controlled to turn on, causing the first comparator to output a low-level signal. If the first error current is less than or equal to the offset current, the first comparator is controlled to continuously output a low-level signal, causing the charging circuit to enter a low-ripple burst mode. Correspondingly, the logic control module outputs a high-level signal to the driver based on the high-level signal output by the oscillator frequency adjustment module and the high-level signal output by the knee detection module, causing the driver to control the primary-side power transistor to turn on.

[0057] When the charging circuit is in low-ripple burst mode, after detecting a continuous low-level signal from the oscillator frequency adjustment module, it periodically enters a sleep state based on the error voltage. After each sleep state, it outputs a high-level signal to the logic control module. The sleep duration of the sleep time adjustment module is negatively correlated with the magnitude of the error voltage. Correspondingly, the logic control module outputs a high-level signal to the driver based on the high-level signals from the sleep time adjustment module and the knee detection module, thereby enabling the driver to control the primary-side power transistor to turn on.

[0058] Step 503: When the charging circuit is in boundary conduction mode, the peak current adjustment module outputs a high-level signal to the logic control module when the target node voltage reaches the peak voltage corresponding to the error voltage; the logic control module controls the primary-side power transistor to turn off according to the high-level signal to end a charging cycle.

[0059] When the charging circuit is in boundary conduction mode, the peak current regulation module converts the error voltage into a second error current through a second current converter. This second error current then controls the induction array to sample the current flowing through the primary-side power transistor. Once the current reaches a current threshold, the switch closes, transmitting the target node voltage to the non-inverting input of the second comparator. When the target node voltage reaches the peak voltage corresponding to the error voltage, the second comparator outputs a high-level signal. Correspondingly, the logic control module outputs a low-level signal to the driver based on the high-level signal from the peak current regulation module, causing the driver to turn off the primary-side power transistor.

[0060] In summary, the charging method based on a flyback converter provided in this application allows the charging circuit to adaptively operate sequentially in boundary conduction mode, intermittent conduction mode, and low-ripple burst mode as the load current gradually decreases from heavy load to light load and no load, and the error voltage gradually decreases from large to small. Under heavy load, a higher switching frequency and a larger peak current ensure energy transfer efficiency; under light load, the oscillator frequency adjustment module delays the reduction of the switching frequency to reduce switching losses; and under no load, the low-ripple burst mode achieves extremely low static power consumption and maintains low output ripple. Thus, by delaying the switching frequency control strategy, adaptive matching between the switching frequency and the load size is achieved, enabling the charging circuit to simultaneously achieve high conversion efficiency and low output ripple across a wide load range from heavy load to no load.

[0061] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0062] The above description is not intended to limit the embodiments of this application. Any adjustments, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A charge circuit based on a flyback converter, characterized by, The charging circuit includes an oscillator frequency adjustment module, a sleep time adjustment module, a peak current adjustment module, a knee point detection module, and a logic control module. The oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module are used to collect the error voltage between the input voltage and the output voltage of the flyback converter. The knee detection module is used to output a high-level signal when a knee point is detected in the target node of the flyback converter, and output the high-level signal to the logic control module. When the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module is used to periodically convert the error voltage into a high-level signal and output the high-level signal to the logic control module; or, when the charging circuit is in low-ripple burst mode, the sleep time adjustment module is used to periodically convert the error voltage into a high-level signal and output the high-level signal to the logic control module; the logic control module is used to control the primary-side power transistor to turn on after receiving the high-level signal output by the oscillator frequency adjustment module and the high-level signal output by the knee detection module, or after receiving the high-level signal output by the sleep time adjustment module and the high-level signal output by the knee detection module, to start a charging cycle; When the charging circuit is in boundary conduction mode, the peak current adjustment module is used to output a high-level signal to the logic control module when the target node voltage reaches the peak voltage corresponding to the error voltage. The logic control module is used to control the primary-side power transistor to turn off according to the high-level signal, so as to end a charging cycle.

2. The charging circuit based on a flyback converter according to claim 1, characterized in that, The oscillator frequency adjustment module includes a first current converter, an offset current source, a capacitor, an adjustment power transistor, and a first comparator. The input terminal of the first current converter serves as the input terminal of the oscillator frequency adjustment module, and the output terminal of the first current converter is connected to the input terminal of the offset current source, the first terminal of the capacitor, the drain of the regulating power transistor, and the non-inverting input terminal of the first comparator. The output terminal of the offset current source, the second terminal of the capacitor, and the source of the regulating power transistor are grounded; The gate of the regulating power transistor is connected to the driver of the primary power transistor. The inverting input of the first comparator is connected to the threshold voltage terminal, and the output of the first comparator serves as the output of the oscillator frequency adjustment module.

3. The charging circuit based on a flyback converter according to claim 2, characterized in that, The oscillator frequency adjustment module is also used for: After the error voltage is converted into a first error current by the first current converter, if the first error current is greater than the offset current generated by the offset current source, the first error current is used to charge the capacitor until the voltage of the capacitor reaches the threshold voltage output by the threshold voltage terminal, and then the first comparator is controlled to output a high-level signal; after the high-level signal is used to control the driver to output a high-level signal, the regulating power transistor is controlled to turn on so that the first comparator outputs a low-level signal. If the first error current is less than or equal to the offset current, the first comparator is controlled to continuously output a low-level signal so that the charging circuit enters the low-ripple burst mode.

4. The charging circuit based on a flyback converter according to claim 1, characterized in that, The peak current regulation module includes a second current converter, an induction array, a second comparator, and a switch. The induction array includes multiple power transistors connected in parallel, and the impedance of the induction array is n times the impedance of the primary power transistor, where n is a positive integer. The input terminal of the second current converter serves as the first input terminal of the peak current regulation module, and the output terminal of the second current converter is connected to the drain of the induction array and the inverting input terminal of the second comparator. The source of the induction array is grounded, and the gate of the induction array serves as the second input terminal of the peak current regulation module, connected to the driver of the primary power transistor and the control terminal of the switch. The first terminal of the switch serves as the third input terminal of the peak current regulation module and is connected to the target node; the second terminal of the switch is connected to the non-inverting input terminal of the second comparator. The output of the second comparator serves as the output of the peak current adjustment module.

5. The charging circuit based on a flyback converter according to claim 4, characterized in that, The peak current regulation module is also used for: After the error voltage is converted into a second error current by the second current converter, the second error current is used to control the induction array to sample the current flowing through the primary power transistor. After the current reaches the current threshold, the switch is controlled to close, and the target node voltage is transmitted to the non-inverting input of the second comparator. When the target node voltage reaches the peak voltage corresponding to the error voltage, the second comparator is controlled to output a high-level signal.

6. The charging circuit based on a flyback converter according to claim 1, characterized in that, The logic control module is also used for: When the charging circuit is in intermittent conduction mode, a high-level signal is output to the driver according to the high-level signal output by the oscillator frequency adjustment module and the high-level signal output by the knee detection module, so that the driver controls the primary-side power transistor to conduct. When the charging circuit is in low ripple burst mode, a high-level signal is output to the driver according to the high-level signal output by the sleep time adjustment module and the high-level signal output by the knee detection module, so that the driver controls the primary-side power transistor to turn on. When the charging circuit is in boundary conduction mode, a low-level signal is output to the driver according to the high-level signal output by the peak current adjustment module, so that the driver controls the primary-side power transistor to turn off.

7. The charging circuit based on a flyback converter according to claim 1, characterized in that, The sleep time adjustment module is also used for: After detecting that the oscillator frequency adjustment module continuously outputs a low-level signal, it performs periodic sleep according to the error voltage, and outputs a high-level signal to the logic control module after each sleep period.

8. The charging circuit based on a flyback converter according to claim 7, characterized in that, The sleep duration of the sleep time adjustment module is negatively correlated with the magnitude of the error voltage.

9. The charging circuit based on a flyback converter according to any one of claims 1 to 8, characterized in that, The target node is the connection node between the primary power transistor and the primary winding of the transformer in the flyback converter.

10. A charging method based on a flyback converter, characterized in that, In a charging circuit as described in any one of claims 1 to 9, the method comprises: The oscillator frequency adjustment module, the sleep time adjustment module, and the peak current adjustment module collect the error voltage between the input voltage and the output voltage of the flyback converter; When the knee detection module detects a knee at the target node, it outputs a high-level signal to the logic control module. When the charging circuit is in intermittent conduction mode, the oscillator frequency adjustment module periodically converts the error voltage into a high-level signal and outputs it to the logic control module. Alternatively, when the charging circuit is in low-ripple burst mode, the sleep time adjustment module periodically converts the error voltage into a high-level signal and outputs it to the logic control module. Upon receiving both the high-level signals from the oscillator frequency adjustment module and the knee detection module, or vice versa, the logic control module controls the primary-side power transistor to turn on, thus initiating a charging cycle. When the charging circuit is in boundary conduction mode, the peak current adjustment module outputs a high-level signal to the logic control module when the target node voltage reaches the peak voltage corresponding to the error voltage; the logic control module controls the primary-side power transistor to turn off according to the high-level signal to end a charging cycle.

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