Ripple control circuit and negative voltage charge pump

Abstract

The application belongs to the field of electronic circuits and provides a ripple control circuit and a negative voltage charge pump. The circuit comprises a comparison module, a detection module, a selection module, a processing module and a clock generation module. The detection module is connected with the comparison module and the selection module respectively. The selection module is connected with the clock generation module and the input end of the processing module respectively. The first output end of the processing module is connected with the input end of the first driving module and the input end of the fourth driving module respectively. The second output end is connected with the input end of the second driving module and the input end of the third driving module respectively. The comparison module is connected with the output node of the charge pump circuit. The application detects whether the comparison signal becomes high level at the rising and falling edges of the third clock signal respectively. When the comparison signal is detected to become high level, the second phase is immediately turned on, and the flying capacitor immediately supplements the charge for the output. The application can respond to the energy demand of the output in advance by half a period, effectively reduce the negative voltage fluctuation and reduce the output ripple.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a ripple control circuit and a negative pressure charge pump. Background Technology

[0002] In today's information society, LCD (Liquid Crystal Display) screens, with their advantages of being thin and light, having perfect picture quality and fast response, have been widely used in all aspects of our lives, covering small-sized mobile phones, camcorders, and digital cameras, medium-sized laptops and desktops, as well as large-sized home TVs and large projection equipment.

[0003] In LCD display driving circuits, both positive and negative power supplies are required to control the switching of the gate, generating a positive voltage VGH and a negative voltage VGL. Among these, a charge pump is a commonly used method for generating the negative power supply in LCD driving systems.

[0004] The loop control method for the charge pump can adopt the skip mode. Although the skip mode can achieve better efficiency, the ripple is relatively large. Summary of the Invention

[0005] This application provides a ripple control circuit and a negative pressure charge pump, which can solve the problem of large ripple in existing charge pumps using a skip-cycle mode.

[0006] In a first aspect, embodiments of this application provide a negative voltage charge pump circuit, including a comparison module, a detection module, a selection module, a processing module, and a clock generation module. The detection module is connected to the comparison module and the selection module, respectively. The selection module is connected to the input terminals of the clock generation module and the processing module, respectively. The first output terminal of the processing module is used to connect to the input terminals of the first driving module and the fourth driving module in the negative voltage charge pump circuit, respectively. The second output terminal of the processing module is used to connect to the input terminals of the second driving module and the third driving module in the negative voltage charge pump circuit, respectively. The comparison module is used to connect to the output node of the negative voltage charge pump circuit. The clock generation module is used to output a first clock signal and a second clock signal to the selection module; the comparison module is used to receive a first reference voltage and a negative voltage, and output a comparison signal according to the first reference voltage and the negative voltage; the detection module is used to receive a third clock signal, and output a valid first detection signal when the comparison signal becomes high at the rising edge of the third clock signal, or output a valid second detection signal when the comparison signal becomes high at the falling edge of the third clock signal, wherein the first detection signal and the second detection signal are not valid at the same time; the selection module is used to output the first clock signal as the target clock signal when the first detection signal is valid, and output the second clock signal as the target clock signal when the second detection signal is valid; the processing module is used to process the target clock signal and output a first phase and a second phase, wherein in each switching cycle when the comparison signal is high, the switching action of the second phase precedes the switching action of the first phase.

[0007] In one possible implementation of the first aspect, the selection module includes a first switch unit and a second switch unit. The control terminal of the first switch unit is connected to the detection module, the first conducting terminal of the first switch unit is connected to the clock generation module, and the second conducting terminal of the first switch unit is connected to the input terminal of the processing module. The control terminal of the second switch unit is connected to the detection module, the first conducting terminal of the second switch unit is connected to the clock generation module, and the second conducting terminal of the second switch unit is connected to the input terminal of the processing module. The first switching unit is used to receive a first clock signal and a first detection signal, turn on when the first detection signal is valid, and output the first clock signal as the target clock signal; the second switching unit is used to receive a second clock signal and a second detection signal, turn on when the second detection signal is valid, and output the second clock signal as the target clock signal.

[0008] In one possible implementation of the first aspect, the processing module includes a frequency division unit and a dead-zone control unit. The first and second input terminals of the frequency division unit are respectively connected to the selection module, and the output terminal of the frequency division unit is connected to the input terminal of the dead-zone control unit. The first output terminal of the dead-zone control unit is used to connect to the input terminals of the first driving module and the fourth driving module in the negative voltage charge pump circuit, respectively. The second output terminal of the dead-zone control unit is used to connect to the input terminals of the second driving module and the third driving module in the negative voltage charge pump circuit, respectively. The frequency division unit is used to receive the target clock signal and perform frequency division processing on the target clock signal to obtain the fourth clock signal; the dead time control unit is used to receive the fourth clock signal and output the first phase and the second phase after dead time control.

[0009] In one possible implementation of the first aspect, the ripple control circuit further includes a first floating ground adjustment module, which is connected to the ground terminals of the comparison module, the detection module, and the fourth drive module, respectively. The first floating ground adjustment module is used to receive a comparison signal and adjust the first floating ground of the fourth drive module according to the comparison signal, so as to adjust the on-resistance of the fourth power transistor in the negative voltage charge pump circuit when the load current of the negative voltage charge pump circuit is greater than a preset threshold, and to control the fourth power transistor to turn off when the load current of the negative voltage charge pump circuit is less than a preset threshold.

[0010] In one possible implementation of the first aspect, the ripple control circuit further includes a fifth power transistor, a fifth driving module, and a second floating ground generation module. The fifth power transistor is connected in parallel with the fourth power transistor. The input terminal of the fifth driving module is connected to the first output terminal of the processing module. The output terminal of the fifth driving module is connected to the gate of the fifth power transistor. The ground terminal of the fifth driving module is connected to the second floating ground generation module. The power supply terminal of the fifth driving module is used to receive the power supply voltage. The second floating ground generation module is used to generate a second floating ground; the fifth driving module is used to receive a first phase and, when the load current of the negative pressure charge pump circuit is less than a preset threshold, control the fifth power transistor to turn on according to the first phase and the second floating ground.

[0011] In one possible implementation of the first aspect, the ripple control circuit further includes a counting module, the first terminal of which is connected to the output terminal of the frequency division unit and the input terminal of the dead zone control unit, the second terminal of which is connected to the comparison module and the detection module, the third terminal of which is connected to the gate of the fifth power transistor and the gate of the first power transistor in the negative voltage charge pump circuit, and the fourth terminal of which is connected to the gate of the second power transistor and the gate of the third power transistor in the negative voltage charge pump circuit. The counting module is used to receive a comparison signal and a fourth clock signal. After the comparison signal goes low, it counts the rising edges of the fourth clock signal. If the number of rising edges counted before the comparison signal goes high is greater than the counting threshold, it outputs a first pulse signal and a second pulse signal. The first pulse signal is used to force the fifth power transistor and the first power transistor to turn off, and the second pulse signal is used to force the second power transistor and the third power transistor to turn on.

[0012] In one possible implementation of the first aspect, the detection module includes a first AND gate, a second AND gate, a first D flip-flop, a second D flip-flop, a first NOR gate, a second NOR gate, a first OR gate, a second OR gate, a first NOT gate, and a second NOT gate. The first input terminal of the first AND gate and the input terminal of the first NOT gate are both used to receive a third clock signal. The second input terminal of the first AND gate is connected to the inverse code output terminal of the second D flip-flop. The output terminal of the first AND gate is connected to the clock input terminal of the first D flip-flop. The data input terminals of the first D flip-flop are respectively connected to the comparison module and the data input terminals of the second D flip-flop. The original code output terminal of the first D flip-flop is respectively connected to the first input terminal of the first NOR gate and the first input terminal of the first OR gate. The inverse code output is connected to the first input of the second AND gate, the second input of the second AND gate is connected to the output of the first NOT gate, the output of the second AND gate is connected to the clock input of the second D flip-flop, the original code output of the second D flip-flop is connected to the first input of the second NOR gate and the first input of the second OR gate, the second input of the first NOR gate is connected to the output of the second NOR gate, the input of the second NOT gate and the second input of the first OR gate, the output of the first OR gate is connected to the selection module, the second input of the second NOR gate is connected to the output of the first NOR gate, the output of the second NOT gate is connected to the second input of the second OR gate, and the output of the second OR gate is connected to the selection module.

[0013] In one possible implementation of the first aspect, the first floating ground adjustment module includes a third NOT gate, a first current source, a second current source, a first capacitor, a third resistor, and a sixth transistor. The input terminal of the third NOT gate is connected to the control terminal of the second current source, the comparison module, and the detection module, respectively. The output terminal of the third NOT gate is connected to the control terminal of the first current source. The first terminal of the first current source, the first terminal of the first capacitor, and the first terminal of the third resistor all receive power supply voltage. The second terminal of the first current source is connected to the first terminal of the second current source, the second terminal of the first capacitor, and the gate of the sixth transistor, respectively. The second terminal of the third resistor is connected to the source of the sixth transistor and the ground terminal of the fourth driving module, respectively. The second terminal of the second current source and the drain of the sixth transistor are both grounded.

[0014] In one possible implementation of the first aspect, the second floating ground generation module includes a first diode, a third current source, a second capacitor, a fourth resistor, and a seventh transistor. The anode of the first diode is connected to a first terminal of the third current source, a first terminal of the second capacitor, and the gate of the seventh transistor. The cathode of the first diode, the second terminal of the second capacitor, and the first terminal of the fourth resistor all receive a power supply voltage. The source of the seventh transistor is connected to a second terminal of the fourth resistor and a ground terminal of the fifth driving module. The second terminal of the third current source and the drain of the seventh transistor are both grounded.

[0015] Secondly, embodiments of this application provide a negative pressure charge pump, including the ripple control circuit described in any one of the first aspects.

[0016] Thirdly, embodiments of this application provide a display screen including the negative pressure charge pump described in the second aspect.

[0017] Fourthly, embodiments of this application provide an electronic device including the display screen described in the third aspect.

[0018] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a negative voltage charge pump circuit, including a comparison module, a detection module, a selection module, a processing module, and a clock generation module. The detection module is connected to both the comparison module and the selection module. The selection module is connected to the input terminals of both the clock generation module and the processing module. The first output terminal of the processing module is connected to the input terminals of the first driving module and the fourth driving module in the negative voltage charge pump circuit, respectively. The second output terminal of the processing module is connected to the input terminals of the second driving module and the third driving module in the negative voltage charge pump circuit, respectively. The comparison module is connected to the output node of the negative voltage charge pump circuit.

[0019] The clock generation module outputs a first clock signal and a second clock signal to the selection module; the comparison module receives a first reference voltage and a negative voltage, and outputs a comparison signal based on the first reference voltage and the negative voltage; the detection module receives a third clock signal, and outputs a valid first detection signal when the comparison signal becomes high at the rising edge of the third clock signal, or outputs a valid second detection signal when the comparison signal becomes high at the falling edge of the third clock signal, wherein the first detection signal and the second detection signal are not valid simultaneously; the selection module outputs the first clock signal as the target clock signal when the first detection signal is valid, and outputs the second clock signal as the target clock signal when the second detection signal is valid; the processing module processes the target clock signal and outputs a first phase and a second phase, wherein in each switching cycle when the comparison signal is high, the switching action of the second phase precedes the switching action of the first phase.

[0020] The ripple control circuit provided in this application detects whether the comparison signal becomes high at the rising and falling edges of the third clock signal. Once the comparison signal becomes high, the second phase is immediately activated, allowing the flying capacitor in the negative voltage charge pump circuit to immediately replenish the output with charge. Compared with traditional solutions, this application can respond to the output energy demand half a cycle earlier, thereby effectively reducing negative voltage fluctuations and lowering output ripple.

[0021] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 The schematic diagram of an existing negative pressure charge pump circuit; Figure 2 This is a schematic diagram of a ripple control circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of a ripple control circuit provided in another embodiment of this application; Figure 4 This is a schematic diagram of a ripple control circuit provided in another embodiment of this application; Figure 5 This is a schematic diagram of a ripple control circuit provided in another embodiment of this application; Figure 6This is a schematic diagram of a ripple control circuit provided in another embodiment of this application; Figure 7 This is a circuit connection diagram of the detection module; Figure 8 This is a circuit connection diagram for the selection module; Figure 9 It is a timing diagram where the falling edge of the clock arrives first; Figure 10 It is a timing diagram where the rising edge of the clock arrives first; Figure 11 This is a circuit connection diagram of the comparator module; Figure 12 This is a circuit connection diagram of the first floating ground adjustment module; Figure 13 This is a circuit connection diagram of the second floating ground generation module.

[0024] In the diagram: 10. Ripple control circuit; 11. Comparison module; 12. Detection module; 13. Selection module; 131. First switching unit; 132. Second switching unit; 14. Processing module; 141. Frequency division unit; 142. Dead zone control unit; 15. Clock generation module; 16. First floating ground adjustment module; 17. Fifth drive module; 18. Second floating ground generation module; 19. Counting module. Detailed Implementation

[0025] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0026] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0027] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0028] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0029] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0031] In LCD display driver circuits, both positive and negative power supplies are required to control the switching of the gate, generating a positive voltage VGH and a negative voltage VGL. There are two main methods for generating the negative power supply: Buck-Boost structures and charge pumps. The former uses an inductor as an energy storage element to achieve voltage rectification, while the latter uses a capacitor. Based on the specific application environment, this application selected the charge pump solution.

[0032] like Figure 1As shown, the existing negative charge pump circuit consists of four power transistors. The common terminal of the third power transistor M3 and the output capacitor Cout is the output node of the negative charge pump circuit. The negative charge pump circuit operates in two phases: a first phase A and a second phase B, which are generated by a clock generation module. The first power transistor M1 and the fourth power transistor M4 are controlled by the first phase A, while the second power transistor M2 and the third power transistor M3 are controlled by the second phase B. When the first phase A is active, the first power transistor M1 and the fourth power transistor M4 are turned on, while the second power transistor M2 and the third power transistor M3 are turned off, charging the flying capacitor Cfly through PAVDD. When the second phase B is active, the first power transistor M1 and the fourth power transistor M4 are turned off, while the second power transistor M2 and the third power transistor M3 are turned on, transferring charge from the flying capacitor Cfly to the output capacitor Cout, generating a negative voltage VGL. It should be noted that the drive signal of the first power transistor M1 is generated by the first drive module according to the first phase A; the drive signal of the fourth power transistor M4 is generated by the fourth drive module according to the first phase A; the drive signal of the second power transistor M2 is generated by the second drive module according to the second phase B; and the drive signal of the third power transistor M3 is generated by the third drive module according to the second phase B.

[0033] To achieve loop control, the gate of the fourth power transistor M4 or the second power transistor M2 can be controlled. This application adopts the method of controlling the gate of the fourth power transistor M4.

[0034] The loop control of a charge pump can employ a skip-cycle mode. The control principle is as follows: the state of the comparator signal is determined at the rising edge of the clock signal. If the comparator signal is low, the cycle is skipped; if the comparator signal is high, it operates with a 50% duty cycle. The drawback of this control method is that if the rising edge of the clock signal is interfered with, causing the comparator to fail to output the comparator signal in time, or if the rising edge of the clock signal happens to occur immediately after the comparator outputs the comparator signal, the switching action must wait until the next cycle. This exacerbates the fluctuations in the negative voltage VGL during load transients, resulting in larger ripple.

[0035] To address the aforementioned issues, this application provides a ripple control circuit. By detecting whether the comparison signal becomes high at the rising and falling edges of the third clock signal, and immediately activating the second phase upon detecting a high level, the flying capacitor in the negative voltage charge pump circuit can immediately replenish the output charge. Compared to traditional solutions, this application can respond to the output energy demand half a cycle earlier, thereby effectively reducing negative voltage fluctuations and lowering output ripple.

[0036] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0037] Figure 2A schematic diagram of a ripple control circuit according to an embodiment of this application is shown. Figure 2 As shown, the ripple control circuit 10 includes a comparison module 11, a detection module 12, a selection module 13, a processing module 14, and a clock generation module 15. The detection module 12 is connected to both the comparison module 11 and the selection module 13. The selection module 13 is connected to the input terminals of both the clock generation module 15 and the processing module 14. The first output terminal of the processing module 14 is connected to the input terminals of the first driving module and the fourth driving module in the negative voltage charge pump circuit, respectively. The second output terminal of the processing module 14 is connected to the input terminals of the second driving module and the third driving module in the negative voltage charge pump circuit, respectively. The comparison module 11 is connected to the output node of the negative voltage charge pump circuit. The output terminal of the first driving module is connected to the gate of the first power transistor M1, the output terminal of the second driving module is connected to the gate of the second power transistor M2, the output terminal of the third driving module is connected to the gate of the third power transistor M3, and the output terminal of the fourth driving module is connected to the gate of the fourth power transistor M4.

[0038] Specifically, the clock generation module 15 is used to output a first clock signal CLK1 and a second clock signal CLK1N to the selection module 13; wherein the first clock signal CLK1 and the second clock signal CLK1N are inverses of each other. The comparison module 11 is used to receive a first reference voltage VREF1 and a negative voltage VGL, and output a comparison signal Comparator_out based on the first reference voltage VREF1 and the negative voltage VGL; the detection module 12 is used to receive a third clock signal CLK, and outputs a valid first detection signal QA when the comparison signal Comparator_out becomes high at the rising edge of the third clock signal CLK, or outputs a valid second detection signal QA when the comparison signal Comparator_out becomes high at the falling edge of the third clock signal CLK. The first detection signal QA and the second detection signal QA are not valid at the same time. In this embodiment, valid means that it is in a high-level state. The third clock signal CLK is generated by an external clock and is in phase with the first clock signal CLK1. Selection module 13 outputs a first clock signal CLK1 as the target clock signal when the first detection signal QA is valid, and outputs a second clock signal CLK1N as the target clock signal when the second detection signal QB is valid. Processing module 14 processes the target clock signals and outputs a first phase A and a second phase B. During each switching cycle when the comparison signal Comparator_out is high, the switching action of the second phase B precedes the switching action of the first phase A. In this embodiment, clock generation module 15 can use an OSC (Oscillator) to generate the first clock signal CLK1 and the second clock signal CLK1N.

[0039] The ripple control circuit 10 provided in this application detects whether the comparison signal Comparator_out becomes high at the rising and falling edges of the third clock signal CLK. Once the comparison signal Comparator_out becomes high, the second phase B is immediately activated, allowing the flying capacitor Cfly in the negative voltage charge pump circuit to immediately replenish the output with charge. Compared with traditional solutions, this application can respond to the output energy demand half a cycle earlier, thereby effectively reducing the negative voltage VGL fluctuation and lowering the output ripple.

[0040] It should be noted that when the negative voltage charge pump circuit is in a light load state, the comparison signal Comparator_out goes low, and the negative voltage charge pump circuit enters the skip cycle mode. At this time, the first phase A is forcibly set to a high level and the second phase B is set to a low level, so that the negative voltage charge pump circuit stays in the switching state corresponding to the first phase A. It should be noted that this part of the control logic is conventional control logic and is not shown in the figure. At the same time, the output state of the detection module 12 remains unchanged to maintain the previously output valid detection signal (the first detection signal QA or the second detection signal QB), so that the selection module 13 maintains the previous clock selection.

[0041] In one embodiment of this application, such as Figure 3 As shown, the selection module 13 includes a first switch unit 131 and a second switch unit 132. The control terminal of the first switch unit 131 is connected to the detection module 12, the first conducting terminal of the first switch unit 131 is connected to the clock generation module 15, and the second conducting terminal of the first switch unit 131 is connected to the input terminal of the processing module 14. The control terminal of the second switch unit 132 is connected to the detection module 12, the first conducting terminal of the second switch unit 132 is connected to the clock generation module 15, and the second conducting terminal of the second switch unit 132 is connected to the input terminal of the processing module 14.

[0042] Specifically, the first switching unit 131 is used to receive the first clock signal CLK1 and the first detection signal QA, turns on when the first detection signal QA is valid, and outputs the first clock signal CLK1 as the target clock signal. The second switching unit 132 is used to receive the second clock signal CLK1N and the second detection signal QB, turns on when the second detection signal QB is valid, and outputs the second clock signal CLK1N as the target clock signal.

[0043] For example, such as Figure 8 As shown, the first switch unit 131 includes a first controlled switch S1. The control terminal of the first controlled switch S1 is connected to the detection module 12, the first conducting terminal of the first controlled switch S1 is connected to the clock generation module 15, and the second conducting terminal of the first controlled switch S1 is connected to the input terminal of the processing module 14.

[0044] The second switch unit 132 includes a second controlled switch S2. The control terminal of the second controlled switch S2 is connected to the detection module 12, the first conducting terminal of the second controlled switch S2 is connected to the clock generation module 15, and the second conducting terminal of the second controlled switch S2 is connected to the input terminal of the processing module 14.

[0045] In one embodiment of this application, such as Figure 3 As shown, the processing module 14 includes a frequency divider unit 141 and a dead-zone control unit 142. The first input terminal and the second input terminal of the frequency divider unit 141 are respectively connected to the selection module 13. That is, the first input terminal of the frequency divider unit 141 is connected to the second conducting terminal of the first switching unit 131, and the second input terminal of the frequency divider unit 141 is connected to the second conducting terminal of the second switching unit 132. The output terminal of the frequency divider unit 141 is connected to the input terminal of the dead-zone control unit 142. The first output terminal of the dead-zone control unit 142 is used to connect to the input terminal of the first driving module and the input terminal of the fourth driving module in the negative pressure charge pump circuit, respectively. The second output terminal of the dead-zone control unit 142 is used to connect to the input terminal of the second driving module and the input terminal of the third driving module in the negative pressure charge pump circuit, respectively.

[0046] Specifically, the frequency divider unit 141 receives the target clock signal and performs frequency division processing on the target clock signal to obtain the fourth clock signal CLK_OUT. In this embodiment, the frequency division ratio is 1, that is, the fourth clock signal CLK_OUT is the same as the target clock signal, which is either the first clock signal CLK1 or the second clock signal CLK1N. The dead-time control unit 142 receives the fourth clock signal CLK_OUT, and outputs the first phase A and the second phase B after dead-time control. The first phase A and the second phase B are out of phase, and the dead-time control unit 142 ensures that the first phase A and the second phase B are not simultaneously in a high-level state by inserting a preset delay internally.

[0047] In one embodiment of this application, such as Figure 4 As shown, the ripple control circuit 10 also includes a first floating ground adjustment module 16, which is connected to the ground terminals of the comparison module 11, the detection module 12, and the fourth drive module, respectively. The power supply terminal of the fourth drive module receives the power supply voltage PAVDD.

[0048] Specifically, the first floating ground adjustment module 16 receives the comparison signal Comparator_out and adjusts the first floating ground FGND1 of the fourth drive module according to the comparison signal Comparator_out. This adjusts the on-resistance of the fourth power transistor M4 in the negative charge pump circuit when the load current of the negative charge pump circuit is greater than a preset threshold (i.e., the negative charge pump circuit is in a non-light load state), ensuring stable output under load changes and achieving linear control to further reduce output ripple. Conversely, when the load current of the negative charge pump circuit is less than the preset threshold (i.e., the negative charge pump circuit is in a light load state), the fourth power transistor M4 is turned off. It should be noted that the control of the fourth power transistor M4 by the fourth drive module is based on the first phase A and the first floating ground FGND1. The first phase A controls the switching timing of M4, and the first floating ground FGND1 is used to adjust the on-resistance of the fourth power transistor M4.

[0049] When the negative voltage charge pump circuit is under light load, the fourth power transistor M4 is completely turned off. Because the Comparator_out signal is low under light load, the circuit enters a skip-cycle mode. If too many cycles are skipped, the switching frequency in skip-cycle mode may decrease to within the audible audio range, causing noise interference. To solve this problem, this application proposes the following solutions, such as... Figure 5 As shown, the ripple control circuit 10 also includes a fifth power transistor M5, a fifth drive module 17, and a second floating ground generation module 18. The fifth power transistor M5 is connected in parallel with the fourth power transistor M4. The input terminal of the fifth drive module 17 is connected to the first output terminal of the processing module 14. The output terminal of the fifth drive module 17 is connected to the gate of the fifth power transistor M5. The ground terminal of the fifth drive module 17 is connected to the second floating ground generation module 18. The power supply terminal of the fifth drive module 17 is used to receive the power supply voltage PAVDD.

[0050] Specifically, the second floating ground generation module 18 is used to generate the second floating ground FGND2. The fifth driving module 17 is used to receive the first phase A. When the load current of the negative voltage charge pump circuit is less than a preset threshold (i.e., the negative voltage charge pump circuit is in a light load state), it controls the fifth power transistor M5 to conduct according to the first phase A (which is high level at this time) and the second floating ground FGND2. After the fourth power transistor M4 is completely turned off, it charges the flying capacitor Cfly in the negative voltage charge pump circuit to provide energy for the output when necessary, thereby suppressing noise interference. It should be noted that when the negative voltage charge pump circuit is in a light load state, the first power transistor M1 is also in a conducting state to provide a charging path for the flying capacitor Cfly, so that the flying capacitor Cfly stores energy.

[0051] To completely solve the noise interference problem, this application also includes a counting module 19 in the ripple control circuit 10, such as... Figure 6 As shown, the first terminal of the counting module 19 is connected to the output terminal of the frequency division unit 141 and the input terminal of the dead zone control unit 142, respectively. The second terminal of the counting module 19 is connected to the comparison module 11 and the detection module 12, respectively. The third terminal of the counting module 19 is connected to the gate of the fifth power transistor M5 and the gate of the first power transistor M1 in the negative voltage charge pump circuit, respectively. The fourth terminal of the counting module 19 is connected to the gate of the second power transistor M2 and the gate of the third power transistor M3 in the negative voltage charge pump circuit, respectively.

[0052] Specifically, the counting module 19 receives the comparison signal Comparator_out and the fourth clock signal CLK_OUT. After the comparison signal Comparator_out goes low, it counts the rising edges of the fourth clock signal CLK_OUT. If the number of rising edges counted before the comparison signal Comparator_out goes high is greater than the counting threshold (corresponding to a switching frequency lower than a preset frequency, such as 30kHz in the skip-cycle mode), the counting module 19 outputs a first pulse signal and a second pulse signal. The first pulse signal is used to forcibly control the fifth power transistor M5 and the first power transistor M1 to turn off, and the second pulse signal is used to forcibly control the second power transistor M2 and the third power transistor M3 to turn on, so as to transfer the energy previously stored in the flying capacitor Cfly to the output. By forcibly inserting the switching action, the noise interference problem caused by excessive frequency hopping is solved. It should be noted that when the counting module 19 counts, in addition to the rising edges, it can also count the falling edges of the fourth clock signal CLK_OUT. The counting principle is the same as the rising edge counting principle, which will not be elaborated here.

[0053] In one embodiment of this application, such as Figure 11 As shown, the comparison module 11 includes a first resistor R1, a second resistor R2, and a comparator. The first terminal of the first resistor R1 receives a second reference voltage VREF2. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the negative input terminal of the comparator. The second terminal of the second resistor R2 is used to receive a negative voltage VGL. The positive input terminal of the comparator is used to receive a first reference voltage VREF1. The output terminal of the comparator is connected to the detection module 12 and the first floating ground adjustment module 16. The first reference voltage VREF1 is provided by a voltage source.

[0054] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider network. The feedback voltage is obtained based on the second reference voltage VREF2 and the negative voltage VGL. This feedback voltage is compared with the first reference voltage VREF1 to obtain the comparison signal Comparator_out, which reflects the change of the negative voltage VGL.

[0055] In one embodiment of this application, such as Figure 7 As shown, the detection module 12 includes a first AND gate AND1, a second AND gate AND2, a first D flip-flop DFF1, a second D flip-flop DFF2, a first NOR gate NOR1, a second NOR gate NOR2, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2. The first input of the first AND gate AND1 and the input of the first NOT gate NOT1 are both used to receive the third clock signal CLK. The second input of the first AND gate AND1 is connected to the inverse code output of the second D flip-flop DFF2. The output of the first AND gate AND1 is connected to the clock input of the first D flip-flop DFF1. The data input of the first D flip-flop DFF1 is connected to the data input of the comparison module 11 and the second D flip-flop DFF2, respectively. The original code output of the first D flip-flop DFF1 is connected to the first input of the first NOR gate NOR1 and the first input of the first OR gate OR1, respectively. The inverted code output of D flip-flop DFF1 is connected to the first input of the second AND gate AND2. The second input of the second AND gate AND2 is connected to the output of the first NOT gate NOT1. The output of the second AND gate AND2 is connected to the clock input of the second D flip-flop DFF2. The original code output of the second D flip-flop DFF2 is connected to the first input of the second NOR gate NOR2 and the first input of the second OR gate OR2. The second input of the first NOR gate NOR1 is connected to the output of the second NOR gate NOR2, the input of the second NOT gate NOT2, and the second input of the first OR gate OR1. The output of the first OR gate OR1 is connected to the selection module 13. The second input of the second NOR gate NOR2 is connected to the output of the first NOR gate NOR1. The output of the second NOT gate NOT2 is connected to the second input of the second OR gate OR2. The output of the second OR gate OR2 is connected to the selection module 13.

[0056] Specifically, the detection module 12 can detect the comparison signal Comparator_out at the rising and falling edges of the third clock signal CLK. If the comparison signal Comparator_out is detected to be high at the rising edge, the first detection signal QA will be high first, meaning the first detection signal QA is valid. According to the circuit structure of the detection module 12, the signal QA1 output from the original code output terminal of the first D flip-flop DFF1 is also high, and the signal output from the inverted code output terminal of the first D flip-flop DFF1 is low. This low-level signal will lock the inverted signal of the third clock signal CLK (i.e., the signal output from the first NOT gate NOT1), and this inverter signal cannot trigger the second D flip-flop DFF2. Subsequently, the selection module 13 will always select the first clock signal CLK1 as the target clock signal and output it to the frequency divider unit 141; conversely, if the comparison signal Comparator_out is detected to be high at the falling edge, the second detection signal QB will be high first, meaning the second detection signal QB is valid. According to the circuit structure of detection module 12, the signal QB1 output from the original code output terminal of the second D flip-flop DFF2 is also high, and the signal output from the inverse code output terminal of the second D flip-flop DFF2 is low. This low-level signal will lock the third clock signal CLK, that is, the first AND gate AND1 will always output a low level, and the first D flip-flop DFF1 cannot be triggered. Subsequently, selection module 13 will always select the second clock signal CLK1N as the target clock signal and output it to frequency divider unit 141.

[0057] When the comparison signal Comparator_out is low, the negative voltage charge pump circuit remains in the first phase A; when the comparison signal Comparator_out goes high, the negative voltage charge pump circuit starts working. If the comparison signal Comparator_out goes high before the falling edge of the third clock signal CLK, then... Figure 9 As shown, the second clock signal CLK1N is selected as the target clock signal. After frequency division, the target clock signal becomes the fourth clock signal CLK_OUT. The fourth clock signal CLK_OUT, after dead-time control, outputs the first phase A and the second phase B. During each switching cycle when the comparison signal Comparator_out is high, the switching action of the second phase B precedes the switching action of the first phase A. That is, the output capability is provided first by the second phase B, maintaining output stability and reducing output ripple. If the comparison signal Comparator_out is detected to go high before the rising edge of the third clock signal CLK, then... Figure 10As shown, the first clock signal CLK1 is selected as the target clock signal. After frequency division, the target clock signal is divided to obtain the fourth clock signal CLK_OUT. After dead-time control, the fourth clock signal CLK_OUT outputs the first phase A and the second phase B. In each switching cycle when the comparison signal Comparator_out is high, the switching action of the second phase B is before the switching action of the first phase A. That is, the output is provided with capability first in the second phase B to maintain output stability and reduce output ripple.

[0058] With this processing method, the loop start-up time of the negative pressure charge pump circuit can be reduced from one cycle to half a cycle. That is, this application can respond to the energy demand of the output half a cycle earlier, thereby effectively reducing the negative pressure VGL fluctuation and reducing the output ripple.

[0059] In one embodiment of this application, such as Figure 12 As shown, the first floating ground adjustment module 16 includes a third NOT gate NOT3, a first current source I1, a second current source I2, a first capacitor C1, a third resistor R3, and a sixth transistor M6. The input terminal of the third NOT gate NOT3 is connected to the control terminal of the second current source I2, the comparison module 11, and the detection module 12, respectively. The output terminal of the third NOT gate NOT3 is connected to the control terminal of the first current source I1. The first terminal of the first current source I1, the first terminal of the first capacitor C1, and the first terminal of the third resistor R3 all receive the power supply voltage PAVDD. The second terminal of the first current source I1 is connected to the first terminal of the second current source I2, the second terminal of the first capacitor C1, and the gate of the sixth transistor M6, respectively. The second terminal of the third resistor R3 is connected to the source of the sixth transistor M6 and the ground terminal of the fourth driving module, respectively. The second terminal of the second current source I2 and the drain of the sixth transistor M6 are both grounded.

[0060] Specifically, the working principle of the first floating ground adjustment module 16 is as follows: the switching state of the first current source I1 and the second current source I2 is controlled according to the comparison signal Comparator_out, thereby adjusting the first floating ground FGND1 of the fourth drive module to realize the control of the fourth power transistor M4.

[0061] When the load current of the negative voltage charge pump circuit exceeds a preset threshold (i.e., the negative voltage charge pump circuit is in a non-light load state), if the negative voltage VGL increases (absolute value decreases), then the comparison signal Comparator_out is high, controlling the first current source I1 to turn off and the second current source I2 to turn on. After the second current source I2 turns on, the gate voltage of the sixth transistor M6 continuously decreases, and its conduction level increases accordingly, causing the potential of the first floating ground FGND1 (floating ground based on the power supply voltage PAVDD) to gradually decrease. The decrease of the first floating ground FGND1 causes the gate voltage of the fourth power transistor M4 to decrease, and its on-resistance decreases accordingly, thereby improving the driving capability of the negative voltage charge pump circuit, keeping the output stable under load changes, achieving linear control, and further reducing output ripple.

[0062] When the load current of the negative voltage charge pump circuit is less than the preset threshold (i.e., the negative voltage charge pump circuit is in a light load state), the comparison signal Comparator_out is low, the first current source I1 is turned on, and the second current source I2 is turned off. At this time, the first capacitor C1 discharges. Since the current of the first current source I1 is usually set to be relatively small, it takes a long time to discharge the charge of the first capacitor C1. Therefore, when the circuit enters the light load state, the sixth transistor M6 will not be turned off immediately, that is, the first floating ground FGND1 will not be high immediately, but will be high after a period of time. In other words, the fourth transistor M4 will not be turned off immediately, but will be turned off after a period of time.

[0063] In one embodiment of this application, such as Figure 13 As shown, the second floating ground generation module 18 includes a first diode D1, a third current source I3, a second capacitor C2, a fourth resistor R4, and a seventh transistor M7. The anode of the first diode D1 is connected to the first terminal of the third current source I3, the first terminal of the second capacitor C2, and the gate of the seventh transistor M7, respectively. The cathode of the first diode D1, the second terminal of the second capacitor C2, and the first terminal of the fourth resistor R4 all receive the power supply voltage PAVDD. The source of the seventh transistor M7 is connected to the second terminal of the fourth resistor R4 and the ground terminal of the fifth driving module 17, respectively. The second terminal of the third current source I3 and the drain of the seventh transistor M7 are both grounded.

[0064] Specifically, the second floating ground generation module 18 generates a stable second floating ground FGND2 through the first diode D1, the third current source I3, the second capacitor C2, the fourth resistor R4 and the seventh transistor M7. When the negative voltage charge pump circuit is in a light load state, the fifth drive module 17 controls the fifth power transistor M5 to turn on according to the first phase A and the second floating ground FGND2, storing energy for the flying capacitor Cfly in advance so as to release it to the output when necessary, thereby suppressing noise interference.

[0065] It should be noted that when the negative pressure charge pump circuit is in a non-light load state, the fifth drive module 17 controls the fifth power transistor M5 to perform corresponding switching actions according to the first phase A and the second floating ground FGND2.

[0066] In summary, the ripple control circuit 10 provided in this application detects whether the comparison signal Comparator_out becomes high at the rising and falling edges of the third clock signal CLK. Once the comparison signal Comparator_out becomes high, the second phase is immediately activated, allowing the flying capacitor Cfly in the negative voltage charge pump circuit to immediately replenish the output with charge. Compared with traditional solutions, this application can respond to the output energy demand half a cycle earlier, thereby effectively reducing the negative voltage VGL fluctuation and lowering the output ripple.

[0067] In addition to reducing output ripple through the methods described above, this application also adjusts the first floating ground FGND1 of the fourth drive module according to the comparison signal Comparator_out, thereby adjusting the on-resistance of the fourth power transistor M4, so that the output remains stable when the load changes, thereby achieving linear control and further reducing output ripple.

[0068] This application also addresses the noise problem by connecting a fifth power transistor M5 in parallel with the fourth power transistor M4, and simultaneously setting a fifth drive module 17 and a second floating ground generation module 18. In this way, energy is stored in advance for the flying capacitor Cfly under light load to be released to the output when necessary, thereby suppressing noise interference.

[0069] This application also avoids noise interference caused by excessive frequency hopping by setting up a counting module 19 to force the switching action when the switching frequency of the skip-cycle mode is lower than the preset frequency.

[0070] This application also provides a negative pressure charge pump, including the ripple control circuit described above. Since the negative pressure charge pump provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0071] This application also provides a display screen, including the negative pressure charge pump described above. Since the display screen provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here. It should be noted that the display screen can be an LED display screen, an OLED display screen, a mini LED display screen, a micro LED display screen, an LCD display screen, etc.

[0072] This application also provides an electronic device, including the display screen described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0074] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A ripple control circuit characterised by, The system includes a comparison module, a detection module, a selection module, a processing module, and a clock generation module. The detection module is connected to both the comparison module and the selection module. The selection module is connected to the input terminals of both the clock generation module and the processing module. The first output terminal of the processing module is connected to the input terminals of the first and fourth driving modules in the negative voltage charge pump circuit. The second output terminal of the processing module is connected to the input terminals of the second and third driving modules in the negative voltage charge pump circuit. The comparison module is connected to the output node of the negative voltage charge pump circuit. The clock generation module is used to output a first clock signal and a second clock signal to the selection module; the comparison module is used to receive a first reference voltage and a negative voltage, and output a comparison signal according to the first reference voltage and the negative voltage. The detection module is used to receive a third clock signal, and outputs a valid first detection signal when the comparison signal becomes high at the rising edge of the third clock signal, or outputs a valid second detection signal when the comparison signal becomes high at the falling edge of the third clock signal. The first detection signal and the second detection signal are not valid at the same time. The selection module is used to output the first clock signal as the target clock signal when the first detection signal is valid, and output the second clock signal as the target clock signal when the second detection signal is valid. The processing module is used to process the target clock signal and output a first phase and a second phase. In each switching cycle when the comparison signal is high, the switching action of the second phase precedes the switching action of the first phase.

2. The ripple control circuit according to claim 1, characterized in that, The selection module includes a first switch unit and a second switch unit. The control terminal of the first switch unit is connected to the detection module, the first conducting terminal of the first switch unit is connected to the clock generation module, and the second conducting terminal of the first switch unit is connected to the input terminal of the processing module. The control terminal of the second switch unit is connected to the detection module, the first conducting terminal of the second switch unit is connected to the clock generation module, and the second conducting terminal of the second switch unit is connected to the input terminal of the processing module. The first switching unit is used to receive a first clock signal and a first detection signal, turn on when the first detection signal is valid, and output the first clock signal as the target clock signal; the second switching unit is used to receive a second clock signal and a second detection signal, turn on when the second detection signal is valid, and output the second clock signal as the target clock signal.

3. The ripple control circuit according to claim 1, characterized in that, The processing module includes a frequency division unit and a dead-zone control unit. The first and second input terminals of the frequency division unit are respectively connected to the selection module. The output terminal of the frequency division unit is connected to the input terminal of the dead-zone control unit. The first output terminal of the dead-zone control unit is used to connect to the input terminals of the first driving module and the fourth driving module in the negative voltage charge pump circuit, respectively. The second output terminal of the dead-zone control unit is used to connect to the input terminals of the second driving module and the third driving module in the negative voltage charge pump circuit, respectively. The frequency division unit is used to receive the target clock signal and perform frequency division processing on the target clock signal to obtain the fourth clock signal; the dead time control unit is used to receive the fourth clock signal and output the first phase and the second phase after dead time control.

4. The ripple control circuit according to claim 3, characterized in that, The ripple control circuit further includes a first floating ground adjustment module, which is connected to the ground terminals of the comparison module, the detection module, and the fourth drive module, respectively. The first floating ground adjustment module is used to receive a comparison signal and adjust the first floating ground of the fourth drive module according to the comparison signal, so as to adjust the on-resistance of the fourth power transistor in the negative voltage charge pump circuit when the load current of the negative voltage charge pump circuit is greater than a preset threshold, and to control the fourth power transistor to turn off when the load current of the negative voltage charge pump circuit is less than a preset threshold.

5. The ripple control circuit according to claim 4, characterized in that, The ripple control circuit further includes a fifth power transistor, a fifth driving module, and a second floating ground generation module. The fifth power transistor is connected in parallel with the fourth power transistor. The input terminal of the fifth driving module is connected to the first output terminal of the processing module. The output terminal of the fifth driving module is connected to the gate of the fifth power transistor. The ground terminal of the fifth driving module is connected to the second floating ground generation module. The power supply terminal of the fifth driving module is used to receive the power supply voltage. The second floating ground generation module is used to generate a second floating ground; the fifth driving module is used to receive a first phase and, when the load current of the negative pressure charge pump circuit is less than a preset threshold, control the fifth power transistor to turn on according to the first phase and the second floating ground.

6. The ripple control circuit according to claim 5, characterized in that, The ripple control circuit further includes a counting module. The first end of the counting module is connected to the output end of the frequency division unit and the input end of the dead zone control unit, respectively. The second end of the counting module is connected to the comparison module and the detection module, respectively. The third end of the counting module is connected to the gate of the fifth power transistor and the gate of the first power transistor in the negative voltage charge pump circuit, respectively. The fourth end of the counting module is connected to the gate of the second power transistor and the gate of the third power transistor in the negative voltage charge pump circuit, respectively. The counting module is used to receive a comparison signal and a fourth clock signal. After the comparison signal goes low, it counts the rising edges of the fourth clock signal. If the number of rising edges counted before the comparison signal goes high is greater than the counting threshold, it outputs a first pulse signal and a second pulse signal. The first pulse signal is used to force the fifth power transistor and the first power transistor to turn off, and the second pulse signal is used to force the second power transistor and the third power transistor to turn on.

7. The ripple control circuit according to any one of claims 1-3, characterized in that, The detection module includes a first AND gate, a second AND gate, a first D flip-flop, a second D flip-flop, a first NOR gate, a second NOR gate, a first OR gate, a second OR gate, a first NOT gate, and a second NOT gate. The first input of the first AND gate and the first NOT gate are both used to receive a third clock signal. The second input of the first AND gate is connected to the inverse code output of the second D flip-flop. The output of the first AND gate is connected to the clock input of the first D flip-flop. The data inputs of the first D flip-flop are connected to the comparison module and the data inputs of the second D flip-flop, respectively. The original code output of the first D flip-flop is connected to the first input of the first NOR gate and the first input of the first OR gate, respectively. The inverse code output of the first D flip-flop is connected to the... The first input of the second AND gate is connected, the second input of the second AND gate is connected to the output of the first NOT gate, the output of the second AND gate is connected to the clock input of the second D flip-flop, the original code output of the second D flip-flop is connected to the first input of the second NOR gate and the first input of the second OR gate, the second input of the first NOR gate is connected to the output of the second NOR gate, the input of the second NOT gate and the second input of the first OR gate, the output of the first OR gate is connected to the selection module, the second input of the second NOR gate is connected to the output of the first NOR gate, the output of the second NOT gate is connected to the second input of the second OR gate, and the output of the second OR gate is connected to the selection module.

8. The ripple control circuit according to claim 4, characterized in that, The first floating ground adjustment module includes a third NOT gate, a first current source, a second current source, a first capacitor, a third resistor, and a sixth transistor. The input terminal of the third NOT gate is connected to the control terminal of the second current source, the comparison module, and the detection module, respectively. The output terminal of the third NOT gate is connected to the control terminal of the first current source. The first terminal of the first current source, the first terminal of the first capacitor, and the first terminal of the third resistor all receive power supply voltage. The second terminal of the first current source is connected to the first terminal of the second current source, the second terminal of the first capacitor, and the gate of the sixth transistor, respectively. The second terminal of the third resistor is connected to the source of the sixth transistor and the ground terminal of the fourth driving module, respectively. The second terminal of the second current source and the drain of the sixth transistor are both grounded.

9. The ripple control circuit according to claim 5, characterized in that, The second floating ground generation module includes a first diode, a third current source, a second capacitor, a fourth resistor, and a seventh transistor. The anode of the first diode is connected to the first terminal of the third current source, the first terminal of the second capacitor, and the gate of the seventh transistor. The cathode of the first diode, the second terminal of the second capacitor, and the first terminal of the fourth resistor all receive power supply voltage. The source of the seventh transistor is connected to the second terminal of the fourth resistor and the ground terminal of the fifth driving module. The second terminal of the third current source and the drain of the seventh transistor are both grounded.

10. A negative pressure charge pump, characterized in that, Includes the ripple control circuit as described in any one of claims 1-9.

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