High power supply rejection ratio class ab output stage circuit based on single well CMOS process
By introducing a PMOS transistor with its source shorted to the substrate and a negative feedback loop into the Class AB output stage circuit, the problems of static current imbalance and power supply rejection ratio deterioration caused by collisional ionization effect in single-well CMOS process are solved, and a high power supply rejection ratio and stable output stage circuit are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU SHENYI TECHNOLOGY CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-07-31
AI Technical Summary
In single-well CMOS technology, Class AB output stages are affected by impact ionization, leading to problems such as quiescent current offset, deterioration of power supply rejection ratio, and decrease in DC gain.
A transconducting linear loop or minimum current selector structure is adopted, and a PMOS transistor with its source shorted to the substrate is introduced. The source-drain voltage of the critical NMOS transistor is clamped below the safe voltage through a negative feedback loop. Combined with a series NMOS transistor, the channel length modulation effect is mitigated, ensuring that the NMOS transistor does not undergo impact ionization.
It effectively suppresses collisional ionization effects, improves power supply rejection ratio and DC gain, and ensures the stability and performance of the circuit under single-well CMOS technology.
Smart Images
Figure CN122495828A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology. Background Technology
[0002] Class AB output stages are widely used in various analog and mixed-signal integrated circuits due to their combination of low quiescent power consumption and high drive capability. The quiescent current control of Class AB output stages is typically implemented using a transconductance linear loop or a minimum current selector combined with a feedback loop. This type of structure achieves low power consumption under quiescent conditions and high drive capability under large-signal conditions by detecting the current or voltage state across the output stage and adjusting the bias current using feedback.
[0003] However, the aforementioned static current control scheme is often affected by impact ionization in single-well CMOS technology, which has an adverse effect on circuit performance.
[0004] Impact ionization refers to the phenomenon where, under high source-drain voltage conditions, due to the strong electric field in the channel region, charge carriers gain high kinetic energy in the channel and collide with the crystal lattice, generating electron-hole pairs and ultimately forming a current component injected from the drain into the substrate. This current not only changes the actual operating current of the device but may also affect the stable operating state of the circuit through substrate coupling.
[0005] For Class AB output stages, regardless of whether a transconducting linear loop structure or a minimum current selection structure is used, there will typically be at least one NMOS transistor in the circuit, such as... Figure 1 As shown, its source-drain voltage may be close to the supply voltage minus two gate-source voltages (VDD-2VGS). Under higher supply voltage conditions, the device will be in a higher electric field state, thus significantly enhancing the impact ionization effect.
[0006] In dual-well CMOS technology, the source of an NMOS device can be shorted to its substrate using a deep N-well (DNW) structure, effectively suppressing the impact of substrate current generated by impact ionization. However, in single-well CMOS technology, the substrate of an NMOS transistor is typically fixed to ground, making independent connection between the source and substrate impossible. Therefore, when impact ionization occurs, the resulting substrate current is directly injected into the substrate. Specifically, this effect can lead to problems such as output stage quiescent current offset, deterioration of power supply rejection ratio (PSRR), and decrease in DC gain, thus limiting the performance of Class AB output stages in single-well CMOS technology. Summary of the Invention
[0007] The present invention aims to provide a Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology, so as to solve the problems of static current imbalance, power supply rejection ratio deterioration and DC gain reduction caused by impact ionization effect in the prior art.
[0008] To achieve the above objectives, the present invention adopts the following technical solution:
[0009] A high power supply rejection ratio (PSRR) Class AB output stage circuit based on single-well CMOS technology includes: a transconducting linear loop structure, wherein the transconducting linear loop structure comprises:
[0010] The first PMOS transistor has its source shorted to the substrate and its source connected to the gate of the Class AB output stage PMOS transistor.
[0011] The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor;
[0012] A negative feedback loop is connected to the first PMOS transistor and the first NMOS transistor to clamp the source-drain voltage of the first NMOS transistor below a preset voltage value.
[0013] The negative feedback loop includes a second PMOS transistor, a second NMOS transistor, and a third PMOS transistor, wherein the gate of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the second PMOS transistor is connected to its gate, the gate of the third PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the third PMOS transistor is connected to the gate of the first PMOS transistor.
[0014] When the power supply voltage increases, the source voltage of the first PMOS transistor increases. The gate voltage of the first PMOS transistor is adjusted through the negative feedback loop to stabilize it at the set voltage, thereby avoiding the impact ionization effect of the first NMOS transistor.
[0015] Furthermore, the gate of the second NMOS transistor is connected to the source of the first NMOS transistor to follow the source voltage of the first NMOS transistor.
[0016] Furthermore, the second NMOS transistor is configured in proportion to the output stage NMOS transistor.
[0017] Furthermore, the output stage quiescent current Iout and the reference current IB0 satisfy the following proportional relationship: Iout / IB0 = (W / L)³ / (W / L)⁵ × (W / L) 11 / (W / L)4, among which, (W / L)3, (W / L)5, (W / L) 11 , (W / L)4 are the width-to-length ratios of the second PMOS transistor, the third PMOS transistor, the output stage NMOS transistor, and the second NMOS transistor, respectively.
[0018] Furthermore, the present invention also includes a fourth PMOS transistor, the substrate potential of which is the same as that of the fifth PMOS transistor, and the gate of the fourth PMOS transistor is connected to a bias voltage to mitigate the influence of the channel length modulation effect of the fifth PMOS transistor on the quiescent current.
[0019] Furthermore, the gate voltages of the first NMOS transistor and the fifth PMOS transistor are provided by a bias circuit consisting of two diodes connected in series.
[0020] A high power supply rejection ratio (PSRR) Class AB output stage circuit based on single-well CMOS technology includes a minimum current selection structure and a collision ionization suppression circuit, wherein the collision ionization suppression circuit includes:
[0021] The first PMOS transistor has its source shorted to the substrate and its source connected to the drain of the common-source cascode transistor.
[0022] The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor;
[0023] The second PMOS transistor has its substrate potential shorted to the source of the first PMOS transistor, its source connected to the drain of the first PMOS transistor, and its drain connected to the drain of the first NMOS transistor.
[0024] A negative feedback loop is connected to the second PMOS transistor and the first NMOS transistor to clamp the source-drain voltage of the first NMOS transistor below a preset voltage value.
[0025] A negative feedback loop is connected to the second PMOS transistor and the first NMOS transistor to clamp the source-drain voltage of the first NMOS transistor below a preset voltage value.
[0026] The negative feedback loop includes a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor. The gate of the third PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the third PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor.
[0027] Furthermore, the third NMOS transistor is configured in proportion to the output stage NMOS transistor of the output stage.
[0028] Furthermore, the output stage quiescent current Iout and the reference current IB1 satisfy the following proportional relationship: IB1 / Iout = (W / L)2 / (W / L)1 × (W / L) 17 / (W / L)3, among which, (W / L)2, (W / L)1, (W / L) 17 , (W / L)3 are the width-to-length ratios of the third PMOS transistor, the second PMOS transistor, the output stage NMOS transistor, and the second NMOS transistor, respectively.
[0029] Compared with the prior art, the present invention has the following beneficial effects:
[0030] (1) By introducing a PMOS transistor with its source shorted to the substrate in the transconductance linear loop or minimum current selector, the high source-drain voltage originally borne by the NMOS transistor is made to effectively suppress the impact ionization effect and avoid the influence of substrate current on circuit performance. At the same time, the source-drain voltage of the critical NMOS transistor is clamped below the safe voltage through the negative feedback loop to ensure that the NMOS transistor will not undergo impact ionization, thereby improving the power supply rejection ratio and DC gain of the circuit.
[0031] (2) By setting a third NMOS transistor connected in series with the first NMOS transistor, the influence of channel length modulation effect on static current is mitigated, and the stability of static current is further improved. Attached Figure Description
[0032] Figure 1 This is a circuit schematic diagram of a transconducting linear loop structure in the prior art.
[0033] Figure 2 This is a schematic diagram of the Class AB output stage circuit of Embodiment 1 of the present invention.
[0034] Figure 3 This is a simulation comparison chart of the power supply rejection ratio of the present invention and the prior art.
[0035] Figure 4 This is a schematic diagram of the Class AB output stage circuit of Embodiment 2 of the present invention. Detailed Implementation
[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0037] It should be noted that in this document, terms such as "first" and "second" are used for descriptive purposes only to distinguish different components and do not indicate any order, quantity, or importance. Furthermore, in the accompanying drawings, the same or similar reference numerals denote the same or similar elements.
[0038] Example 1
[0039] This embodiment provides a Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology, specifically an implementation based on a transconducting linear loop structure.
[0040] like Figure 2 As shown, the circuit includes a first PMOS transistor M6, a first NMOS transistor M8, a negative feedback loop composed of a second PMOS transistor M3, a second NMOS transistor M4 and a third PMOS transistor M5, and a bias circuit composed of a third NMOS transistor M1 and a fourth NMOS transistor M2.
[0041] The source of the first PMOS transistor M6 is shorted to the substrate and connected to the gate of the Class AB output stage PMOS transistor M10. The drain of the first NMOS transistor M8 is connected to the drain of the first PMOS transistor M6. A negative feedback loop is connected to the first PMOS transistor M6 and the first NMOS transistor M8 to clamp the source-drain voltage of the first NMOS transistor M8 below a preset voltage value.
[0042] The specific connection relationship is as follows: the gate of the second PMOS transistor M3 is connected to the drain of the second NMOS transistor M4, the drain of the second PMOS transistor M3 is connected to its gate and the gate of the second PMOS transistor M3, the gate of the third PMOS transistor M5 is connected to the drain of the second NMOS transistor M4, and the drain of the third PMOS transistor M5 is connected to the gate of the first PMOS transistor M6.
[0043] The third NMOS transistor M1 and the fourth NMOS transistor M2 are connected in series between the power supply voltage VDD and ground to generate a stable voltage, providing a stable drain-source voltage margin for the first NMOS transistor M8 and ensuring that M8 operates within a safe voltage range.
[0044] The gate of the second NMOS transistor M4 is connected to the drain of the first NMOS transistor M8 to follow the source voltage of the first NMOS transistor M8. The second NMOS transistor M4 is proportionally set to the eleventh NMOS transistor M11 in the output stage, so that M4 can accurately follow the source voltage change of M8.
[0045] When the power supply voltage VDD increases, the source voltage of the first PMOS transistor M6 increases accordingly. This change is transmitted through a negative feedback loop: the increase in the source voltage of M6 leads to an increase in the gate voltage of M4, which in turn decreases the gate voltage of M5, ultimately raising the gate voltage of M6. Through the adjustment of the negative feedback loop, the gate voltage of M4 is stabilized at the set value, thereby ensuring that the source-drain voltage of M8 is maintained within a safe range and avoiding the occurrence of impact ionization effects.
[0046] To precisely control the output stage quiescent current, in this embodiment, the output stage quiescent current Iout and the reference current IB0 satisfy the following proportional relationship:
[0047] Iout / IB0 = (W / L)³ / (W / L)⁵ × (W / L) 11 / (W / L)4,
[0048] Among them, (W / L)3, (W / L)5, (W / L) 11 W / L and 4 represent the width-to-length ratios of M3, M5, M11, and M4, respectively. This ratio allows for precise replication of the output stage quiescent current, ensuring circuit stability under varying process angles and operating conditions.
[0049] To further improve the stability of the quiescent current, this embodiment also includes a fifth PMOS transistor M9, which serves as a common-source, common-gate device for M7. The gate of M9 is connected to the bias voltage to mitigate the influence of the channel length modulation effect of M7 on the quiescent current. The substrate potential of M9 is the same as that of the fourth PMOS transistor M7, and both are connected to the source of M7 to prevent M9 from undergoing impact ionization.
[0050] The gate voltages of the first NMOS transistor M8 and the fourth PMOS transistor M7 are provided by a bias circuit consisting of two diodes connected in series, ensuring the stability of the bias voltage.
[0051] In this embodiment, since there are negative feedback loops (M6-M4-M3-M5 loop) and positive feedback loops (M6-M7-M9-M8-M4-M3-M5 loop) in the transconducting linear loop, in order to ensure circuit stability.
[0052] Figure 3The graph shows a comparison of the power supply rejection ratio (PSRR) between the proposed solution and the conventional structure. As can be seen from the graph, when the power supply voltage reaches 5V, the proposed solution improves the PSRR by approximately 40dB compared to the conventional Class AB structure.
[0053] Example 2
[0054] This embodiment provides a Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology, specifically an implementation based on a minimum current selector structure, which includes a minimum current selection structure and a collision ionization suppression circuit.
[0055] like Figure 4 As shown, the collision ionization suppression circuit includes a first PMOS transistor M4, a second PMOS transistor M6, a first NMOS transistor M8, and a negative feedback loop composed of a third PMOS transistor M1, a fourth PMOS transistor M2, and a fourth NMOS transistor M3.
[0056] The source of the second PMOS transistor M6 is shorted to the source of the first PMOS transistor and connected to the substrate potential of the first PMOS transistor M4. Its source is connected to the drain of the first PMOS transistor, and its source is also connected to the drain of the cascode transistor. The drain of the first NMOS transistor M8 is connected to the drain of the second PMOS transistor M6. A negative feedback loop is connected to the second PMOS transistor M6 and the first NMOS transistor M8 to clamp the source-drain voltage of the first NMOS transistor M8 below a preset voltage value.
[0057] The specific connection relationship is as follows: the gate of the fourth NMOS transistor M3 is connected to the source of the second PMOS transistor M6, the drain of the fourth NMOS transistor M3 is connected to the gate of the second PMOS transistor M6, the drain of the third PMOS transistor M1 is connected to the gate of the second PMOS transistor M6, and its gate is connected to the gate and drain of the fourth PMOS transistor M2.
[0058] When the power supply voltage VDD increases, the source voltage of the first PMOS transistor M6 increases, which in turn increases the gate voltage of the fourth NMOS transistor M3, and consequently increases the drain voltage of M1 to follow the source voltage of M6. Through the adjustment of the negative feedback loop, the gate voltage of M3 is stabilized at the set voltage VGS, thereby preventing the impact ionization effect of M8.
[0059] To reduce system offset and power supply rejection ratio degradation caused by drain-source voltage differences, in this embodiment, the fourth NMOS transistor M3 is proportionally set to the seventeenth NMOS transistor M17 of the output stage. The output stage quiescent current Iout and the reference current IB1 satisfy the following proportional relationship:
[0060] IB1 / Iout=(W / L)2 / (W / L)1×(W / L) 17 / (W / L)3,
[0061] Among them, (W / L)2, (W / L)1, (W / L) 17 The width-to-length ratios (W / L)3 and (W / L)3 represent the width-to-length ratios of M2, M1, M17, and M3, respectively. This ratio allows for precise control of the output stage quiescent current and ensures that the drain potentials seen by M7 and M8 are identical, thereby reducing system offset.
[0062] Compared to the transconducting linear loop structure in Embodiment 1, the minimum current selector structure in this embodiment does not have a positive feedback loop, making compensation more convenient. Optionally, a Miller compensation capacitor can be provided between the gate and drain of the first PMOS transistor M6 to further improve the stability of the circuit.
[0063] Example 3
[0064] This embodiment is a further optimization of Embodiment 1 or Embodiment 2. Based on the above embodiments, a Miller compensation capacitor may also be included between the gate and drain of the first PMOS transistor M6 to compensate for stability issues caused by the positive feedback loop and ensure stable operation of the circuit under all operating conditions.
[0065] The high power supply rejection ratio (PSRR) Class AB output stage circuit based on single-well CMOS technology provided by this invention can realize a high PSRR and high stability Class AB output stage under single-well CMOS technology. It is suitable for various analog integrated circuits and mixed-signal integrated circuits with high PSRR requirements and has broad industrial application prospects.
[0066] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology, characterized in that, include: Includes a transconducting linear loop structure, the transconducting linear loop structure comprising: The first PMOS transistor has its source shorted to the substrate and its source connected to the gate of the Class AB output stage PMOS transistor. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor; A negative feedback loop is connected to the first PMOS transistor and the first NMOS transistor to clamp the source-drain voltage of the first NMOS transistor below a preset voltage value. The negative feedback loop includes a second PMOS transistor, a second NMOS transistor, and a third PMOS transistor, wherein the gate of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the second PMOS transistor is connected to its gate, the gate of the third PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the third PMOS transistor is connected to the gate of the first PMOS transistor. When the power supply voltage increases, the source voltage of the first PMOS transistor increases. The gate voltage of the first PMOS transistor is adjusted through the negative feedback loop, so that its drain voltage is stabilized at the set voltage, thereby avoiding the impact ionization effect of the first NMOS transistor.
2. The high power supply rejection ratio Class AB output stage circuit based on single-well CMOS technology according to claim 1, characterized in that, The gate of the second NMOS transistor is connected to the source of the first NMOS transistor to follow the source voltage of the first NMOS transistor.
3. The Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology according to claim 2, characterized in that, The second NMOS transistor is set in proportion to the output stage NMOS transistor.
4. The Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology according to claim 1, characterized in that, The output stage quiescent current Iout and the reference current IB0 satisfy the following proportional relationship: Iout / IB0 = (W / L)³ / (W / L)⁵ × (W / L) 11 / (W / L)4, among which, (W / L)3, (W / L)5, (W / L) 11 , (W / L)4 are the width-to-length ratios of the second PMOS transistor, the third PMOS transistor, the output stage NMOS transistor, and the second NMOS transistor, respectively.
5. A Class AB output stage circuit based on single-well CMOS technology with high power supply rejection ratio according to any one of claims 1 to 4, characterized in that, It also includes a fourth PMOS transistor, the substrate potential of which is the same as that of the fifth PMOS transistor, and the gate of the fourth PMOS transistor is connected to a bias voltage to mitigate the effect of the channel length modulation effect of the fifth PMOS transistor on the quiescent current.
6. The high power supply rejection ratio Class AB output stage circuit based on single-well CMOS technology according to claim 5, characterized in that, The gate voltages of the first NMOS transistor and the fifth PMOS transistor are provided by a bias circuit consisting of two diodes connected in series.
7. A Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology, characterized in that, include: Minimum current selection structure and collision ionization suppression circuit, wherein the collision ionization suppression circuit includes: The first PMOS transistor has its source shorted to the substrate and its source connected to the drain of the common-source cascode transistor. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor; The second PMOS transistor has its substrate potential shorted to the source of the first PMOS transistor, its source connected to the drain of the first PMOS transistor, and its drain connected to the drain of the first NMOS transistor. A negative feedback loop is connected to the second PMOS transistor and the first NMOS transistor to clamp the source-drain voltage of the first NMOS transistor below a preset voltage value. The negative feedback loop includes a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor. The gate of the third PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the third PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor.
8. A Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology according to claim 7, characterized in that, The third NMOS transistor is set in proportion to the output stage NMOS transistor of the output stage.
9. A Class AB output stage circuit with high power supply rejection ratio based on single-well CMOS technology according to claim 7, characterized in that, The output stage quiescent current Iout and the reference current IB1 satisfy the following proportional relationship: IB1 / Iout = (W / L)² / (W / L)¹ × (W / L) 17 / (W / L)3, among which, (W / L)2, (W / L)1, (W / L) 17 , (W / L)3 are the width-to-length ratios of the third PMOS transistor, the second PMOS transistor, the output stage NMOS transistor, and the second NMOS transistor, respectively.