A constant current discharge circuit for a power supply output filter capacitor

Abstract

This invention belongs to the field of electrical technology, and particularly relates to a constant current discharge circuit for a power output filter capacitor, comprising a constant current discharge module, a discharge shutdown module, and a power supply terminal; the constant current discharge module includes a first N-channel MOSFET, an NPN transistor, and a first resistor; the discharge shutdown module includes a second N-channel MOSFET and a detection circuit; the gate of the first N-channel MOSFET is connected to the power supply terminal through a charging circuit. This invention, by constructing a closed-loop constant current discharge network composed of a first N-channel MOSFET, an NPN transistor, and a current-sensing resistor, can accurately and stably discharge the residual energy on the output filter capacitor with a constant current. Combined with the unidirectional isolation effect of the anti-reverse-current MOSFET, it avoids the reverse inflow of energy into the load, making the discharge time completely deterministic and controllable.

Description

Technical Field

[0001] This invention belongs to the field of electrical technology, and in particular relates to a constant current discharge circuit for a power supply output filter capacitor. Background Technology

[0002] In the field of isolated DC / DC converter control, synchronous rectification technology is often used in the output stage. By using MOSFETs instead of diodes, the conduction loss of rectifier diodes can be significantly reduced, and filter inductors and filter capacitors are connected at the output.

[0003] However, during repeated power-on and power-off cycles, the voltage on the output capacitor does not always drop to 0V. This is especially true in high-voltage output isolated DC / DC converters. Due to the limited bandwidth of the feedback loop, the duty cycle of the first few PWM cycles during power-on soft-start is usually relatively small, while the corresponding duty cycle of the synchronous rectification drive is relatively large. This is particularly true when a synchronous rectification soft-start mechanism is not configured. This can lead to severe energy backflow into the output capacitor during the first few PWM cycles, causing a sudden change in the voltage on the output capacitor, which in turn leads to loop oscillation in the feedback loop.

[0004] This sudden change can cause control loop oscillation, typically manifesting as a brief squeal or output voltage waveform dip during startup, and carries the risk of burning out the synchronous rectifier MOSFET. Theoretically, if the voltage on the output capacitor is always 0V at each startup, then during soft start-up, the voltage on the output capacitor will always be steadily increased by the loop control, thus ensuring that the loop is always in a stable operating state.

[0005] To address the above problems, existing technologies mainly employ the following two conventional solutions, but both have significant drawbacks: Existing Solution 1: The synchronous rectification drive adopts soft start. This solution performs soft start during the slow opening of the synchronous rectification drive. After the soft start is completed, the synchronous rectification drive complements the main switch drive. However, this solution requires the selection of a dedicated controller with output synchronous rectification soft start function. Especially in digital control systems, the control timing design of this soft start is relatively complex.

[0006] Existing Solution 2: Output discharge based on dummy load. This solution uses digital control technology to detect the output voltage before each power-on. By connecting a dummy load to the output terminal to discharge the output capacitor, the control output is activated when the voltage on the output capacitor drops to 0V. If the dummy load power is selected to be too large, although the discharge speed is fast, it will continuously consume power, resulting in a decrease in the overall operating efficiency of the converter. If the dummy load power is selected to be too small, although the loss is reduced, the discharge time will be too slow, resulting in an excessively long system startup delay. Summary of the Invention

[0007] To address the issues of energy backflow and control loop oscillation caused by incomplete discharge of the output capacitor during soft start of isolated DC / DC converters, and to overcome the shortcomings of existing technologies such as complex timing of synchronous rectification soft start and difficulty in balancing system operating efficiency and start-up delay when using dummy load discharge, this invention proposes a constant current discharge circuit for the power supply output filter capacitor.

[0008] This invention is achieved through the following technical solution: A constant current discharge circuit for a power output filter capacitor is applied in a DC / DC converter having a synchronous rectification circuit, a filter inductor and an output filter capacitor, including a constant current discharge module, a discharge shutdown module and a power supply terminal. The constant current discharge module includes a first N-channel MOSFET, an NPN transistor, and a first resistor; the drain of the first N-channel MOSFET is connected to the common terminal of the filter inductor and the synchronous rectification circuit, the source of the first N-channel MOSFET is connected to the base of the NPN transistor and one end of the first resistor; the collector of the NPN transistor is connected to the gate of the first N-channel MOSFET, and the emitter of the NPN transistor and the other end of the first resistor are both connected to a reference ground; The discharge shutdown module includes a second N-channel MOSFET and a detection circuit; the drain of the second N-channel MOSFET is connected to the gate of the first N-channel MOSFET, and the source of the second N-channel MOSFET is connected to a reference ground; the gate of the second N-channel MOSFET is connected to the synchronous rectification drive signal terminal of the DC / DC converter through the detection circuit. The gate of the first N-channel MOSFET is connected to the power supply terminal through a charging circuit.

[0009] Furthermore, the charging circuit includes a second resistor and a first capacitor; One end of the second resistor is connected to the power supply terminal, and the other end of the second resistor is connected to the gate of the first N-channel MOSFET. One end of the first capacitor is connected to the gate of the first N-channel MOSFET, and the other end of the first capacitor is connected to reference ground.

[0010] Furthermore, the detection circuit includes a first diode and a second capacitor; The anode of the first diode is coupled to the synchronous rectification drive signal terminal, and the cathode of the first diode is connected to the gate of the second N-channel MOS transistor. One end of the second capacitor is connected to the gate of the second N-channel MOSFET, and the other end of the second capacitor is connected to reference ground.

[0011] Furthermore, the detection circuit also includes a third resistor and a fourth resistor; The third resistor is connected in series between the synchronous rectification drive signal terminal and the anode of the first diode; One end of the fourth resistor is connected to the gate of the second N-channel MOS transistor, and the other end of the fourth resistor is connected to reference ground. The fourth resistor is connected in parallel with the second capacitor.

[0012] Furthermore, the constant current discharge circuit also includes a spike absorption circuit; The spike absorption circuit includes a fifth resistor, a second diode, and a third capacitor; The fifth resistor is connected in parallel with the second diode. One end of the parallel connection is connected to the drain of the first N-channel MOS transistor, and the other end is connected to one end of the third capacitor. The other end of the third capacitor is connected to the reference ground. The anode of the second diode is connected to the drain of the first N-channel MOS transistor, and its cathode is connected to one end of the third capacitor.

[0013] Furthermore, the DC / DC converter also includes a reverse-current protection MOSFET and a load input capacitor; The anti-backflow MOSFET is connected in series between the output filter capacitor and the load input capacitor; The source of the anti-backflow MOSFET is connected to the output filter capacitor, the drain of the anti-backflow MOSFET is connected to one end of the load input capacitor, and the other end of the load input capacitor is connected to reference ground.

[0014] Furthermore, the synchronous rectifier circuit is a full-bridge synchronous rectifier circuit; The full-bridge synchronous rectification circuit includes a first to a fourth synchronous rectification MOS transistor, and the synchronous rectification drive signal terminal is connected to the gate of each of the synchronous rectification MOS transistors.

[0015] Furthermore, the full-bridge synchronous rectifier circuit also includes a transformer secondary winding; One end of the secondary winding of the transformer is connected to the common node of the source of the first synchronous rectifier MOS transistor and the drain of the second synchronous rectifier MOS transistor, and the other end of the secondary winding of the transformer is connected to the common node of the source of the third synchronous rectifier MOS transistor and the drain of the fourth synchronous rectifier MOS transistor. The drain of the first synchronous rectifier MOSFET and the drain of the third synchronous rectifier MOSFET are both connected to the filter inductor; The source of the second synchronous rectifier MOSFET and the source of the fourth synchronous rectifier MOSFET are both connected to the reference ground.

[0016] The beneficial effects of this invention are: (1) By constructing a closed-loop constant current discharge network consisting of a first N-channel MOSFET, an NPN transistor and a current sensing resistor, this invention can accurately and stably discharge the residual energy on the output filter capacitor with a constant current. Combined with the unidirectional isolation effect of the anti-backflow MOSFET, it avoids the reverse flow of energy at the load end, making the discharge time completely determinable and controllable. This ensures that the output capacitor voltage can be perfectly returned to zero before the synchronous rectification signal is issued each time the isolated DC / DC converter is powered on, fundamentally eliminating the problem of energy backflow and control loop oscillation caused by duty cycle mismatch during startup. (2) The present invention designs a discharge turn-off module based on synchronous rectification high-frequency pulse, namely a detector circuit composed of diodes, microfarad capacitors and a second N-channel MOS transistor. When the energy discharge is completed and the system officially outputs high-frequency PWM pulse, the high-frequency signal can instantly pump up the voltage of the detector capacitor, directly triggering the second N-channel MOS transistor to turn on, thereby forcibly pulling down and locking the gate of the constant current discharge transistor to ground potential, ensuring that the discharge circuit completely fails during the normal operation of the converter, without introducing any additional power loss, and perfectly balancing startup safety and overall operating efficiency. (3) The present invention directly reuses the intrinsic analog clamping voltage drop of the pure hardware constant current source as the status feature flag bit of the digital controller. By monitoring the voltage drop edge of the node, the digital controller can accurately sense the limit endpoint of the physical discharge of the capacitor in microseconds. This breaks the blind waiting strategy of setting a fixed soft start dead zone in traditional digital control. No matter how high the initial residual voltage of the capacitor is, or the capacitance tolerance appears after long-term use, the system can achieve zero-delay seamless connection after discharge, which greatly optimizes the dynamic start-up response speed of the power supply. (4) The adaptive advanced control logic of the present invention is based entirely on the underlying basic hardware topology. It does not require the addition of expensive high-voltage isolation differential sampling circuits or dedicated timing control chips. It can be implemented simply by connecting the existing resistor nodes to the ADC or comparator pins of the conventional controller. This not only greatly simplifies the complexity of system design, but also has extremely high engineering feasibility and economic benefits. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a constant current discharge circuit for a power output filter capacitor proposed in this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0020] Example 1 This invention proposes a specific embodiment of a constant current discharge circuit for a power output filter capacitor, which is applied to an isolated DC / DC converter equipped with a full-bridge synchronous rectification circuit.

[0021] refer to Figure 1 The secondary circuit of the isolated DC / DC converter in this embodiment includes a transformer T1, a full-bridge synchronous rectifier circuit, a filter and anti-backflow system, and a constant current discharge network. The two ends of the secondary winding of the transformer T1 are respectively connected to the midpoints of the two bridge arms of the full-bridge synchronous rectifier circuit. The full-bridge synchronous rectifier circuit includes the first to fourth synchronous rectifier MOSFETs Q2, Q3, Q5, and Q6. The gates of Q2, Q3, Q5, and Q6 are connected in series with gate resistors R1, R2, R6, and R7 and then connected to the synchronous rectifier drive signal terminal SR1 or SR2. The drains of Q2 and Q3 are connected to one end of the filter inductor L1, and the sources of Q5 and Q6 are connected to the reference ground GND.

[0022] The other end of the filter inductor L1 is connected to one end of the output filter capacitor C1. The negative terminal of C1 is connected to the reference ground GND. A reverse current protection MOSFET Q7 is connected in series between the output filter capacitor C1 and the load input capacitor C2. The source of the reverse current protection MOSFET Q7 is connected to one end of C1, and the drain is connected to one end of C2. The other end of C2 is grounded. The reverse current protection MOSFET Q7 is driven by the ORing control circuit and is used to block the reverse current from C2 to C1.

[0023] As the core of this embodiment, the constant current discharge network consists of a constant current discharge module, a discharge shutdown module, a charging circuit, and a spike absorption circuit. The constant current discharge module includes a first N-channel MOSFET Q4, an NPN transistor Q9, and a first resistor R8. The drain of MOSFET Q4 is connected to the common terminal of the filter inductor L1 and the full-bridge synchronous rectifier circuit. The source of Q4 is connected to the base of NPN transistor Q9 and one end of resistor R8. The collector of NPN transistor Q9 is connected to the gate of Q4, and its emitter and the other end of resistor R8 are both connected to reference ground GND.

[0024] The charging circuit includes a second resistor R4 and a first capacitor C4. The power supply terminal SVDD +12V is connected to one end of the resistor R4, and the other end of the R4 is connected to the gate of the MOSFET Q4. The capacitor C4 is connected in parallel between the gate of Q4 and the reference ground GND. The spike absorption circuit includes a fifth resistor R3, a second diode D1 and a third capacitor C3. The resistor R3 is connected in parallel with the diode D1. The cathode of D1 is connected to the drain of Q4, and the anode is connected to C3. One end of this parallel combination is connected to the drain of the MOSFET Q4, and the other end is connected to the reference ground GND after being connected in series with the capacitor C3. The discharge shutdown module includes a second N-channel MOSFET Q8 and a detection circuit consisting of a first diode D2, a second capacitor C5, a third resistor R5, and a fourth resistor R9. The synchronous rectification drive signal terminal SR1 is connected to the anode of diode D2 after being connected in series with resistor R5, and the cathode of D2 is connected to the gate of MOSFET Q8. The microfarad capacitor C5 and the pull-down resistor R9 are connected in parallel and are connected between the gate of MOSFET Q8 and the reference ground GND. The drain of MOSFET Q8 is connected to the gate of MOSFET Q4, and the source is connected to the reference ground GND.

[0025] In terms of dynamic working principle, the operation of the entire circuit is divided into a constant current discharge stage before soft start and a shutdown stage during normal operation. In the initial power-on state, the power supply terminal SVDD prioritizes power supply for startup. At this time, the synchronous rectification drive signals SR1 and SR2 are both at low level, and the anti-backflow MOSFET Q7 is in the off state. The current provided by SVDD flows through resistor R4 to charge capacitor C4. When the voltage on C4 is charged to the drive threshold voltage of MOSFET Q4, Q4 starts to conduct. As C4 continues to charge, Q4 is fully turned on. During the conduction of Q4, the residual energy on the output filter capacitor C1 will be discharged through the hardware circuit L1-Q4-R8. Let the discharge current be I. When the discharge current I flows through the first resistor R8, a voltage drop V is generated across R8, i.e., V=I×R8. When this voltage V exceeds 0.7V, the base-emitter junction of NPN transistor Q9 is forward biased and turns on, thereby pulling down the gate drive voltage of MOSFET Q4 and forcing Q4 to change to the cutoff region.

[0026] During operation, the base of transistor Q9 is always kept in a dynamic equilibrium state of about 0.7V. At this time, resistor R8, transistor Q9 and MOSFET Q4 together form a closed-loop constant current circuit. By setting or adjusting the resistance value of resistor R8 in the hardware, the magnitude of the discharge current can be precisely controlled, thereby ensuring that the energy on the output filter capacitor C1 is completely and stably discharged before the synchronous rectification drive signal is issued.

[0027] Furthermore, due to the isolation effect of the anti-backflow MOSFET Q7, the energy on the load input capacitor C2 cannot flow back. The system only needs to perform constant current discharge on C1 with a fixed capacitance, making the discharge time completely deterministic and controllable. When the energy on the output filter capacitor C1 is completely discharged, the converter enters the working state. The synchronous rectification drive signal SR1 starts to emit a high-frequency PWM pulse signal. This high-frequency signal quickly charges the detector capacitor C5 through resistor R5 and diode D2. Since C5 is a microfarad capacitor and SR1 is a high-frequency signal, the voltage on C5 is rapidly pumped up and effectively maintained at a high level of SVDD. This high level keeps MOSFET Q8 fully turned on, forcibly pulling the gate drive voltage of MOSFET Q4 down to GND. At this point, MOSFET Q4 is completely turned off, the entire discharge circuit completely fails, and the system exits the operating state, ensuring that no additional power loss is introduced during normal operation of the DC / DC converter.

[0028] Example 2 Based on the pure hardware circuit topology of Embodiment 1, the present invention further provides an adaptive embodiment based on analog state feedback and digital logic interaction. While maintaining all components and their physical connections unchanged in Embodiment 1, this embodiment introduces an additional master digital controller such as a DSP or MCU chip, and connects the output voltage VOUT signal to the analog-to-digital converter (ADC) sampling pin or the input pin of the internal analog comparator of the digital controller. At the same time, the digital controller is responsible for generating and outputting the aforementioned synchronous rectification drive signals SR1 and SR2.

[0029] In terms of dynamic control logic, when the isolated DC / DC converter is powered on, the SVDD power supply is started first, and the digital controller forces the synchronous rectification drive signals SR1 and SR2 to remain low during the initialization phase. At this time, the first N-channel MOSFET Q4 is turned on after a delay through the external RC charging network, and the hardware constant current discharge circuit begins to autonomously discharge the energy remaining in the output filter capacitor C1. During the constant current discharge, due to the negative feedback clamping effect of the hardware closed loop, the current flowing through the first resistor R8 remains constant, so that the voltage at this state characteristic detection point is strictly clamped at the base-emitter conduction voltage drop of the NPN transistor Q7 (approximately a dynamic balance voltage of about 0.7V). The digital controller monitors the output voltage in real time through the sampling pin. When it detects that the voltage at this node is in the preset high-level logic range (e.g., 0.5V to 0.8V), the internal logic of the digital controller determines that the system is in a safe discharge state and continues to suspend the output of the main circuit.

[0030] As the energy on the output filter capacitor C1 is gradually drained, the voltage across it will eventually be insufficient to maintain the set constant discharge current. At this point, the actual current flowing through the first resistor R8 will drop sharply, causing the output voltage state characteristic to decrease below a preset value. Once the digital controller detects that the voltage at this characteristic point exceeds the preset low-level judgment threshold (e.g., below 0.5V), it triggers a falling edge interrupt, immediately determining that the output filter capacitor C1 has completely completed zero-discharge. In the microsecond instant of judgment completion, the digital controller implements a zero-delay response, actively and immediately issuing a high-frequency synchronous rectification drive signal SR1 or SR2, officially starting the working cycle of the full-bridge converter. At the same time, the issued high-frequency synchronous rectification drive signal immediately triggers the second N-channel MOSFET Q8 to fully conduct through the detection network composed of the first diode D2 and the second capacitor C5, forcibly pulling down and locking the gate drive voltage of the first N-channel MOSFET Q4 to ground potential, causing the entire constant current discharge hardware network to permanently exit the current operating cycle.

[0031] This embodiment integrates analog circuits and digital control technology. Regardless of whether the initial residual voltage of the output capacitor is high or low, or whether the capacitance value decays or tolerances occur after long-term use, the digital controller can accurately sense the physical limit discharge endpoint and achieve seamless timing handshake of discharge complete and stop. While ensuring the complete elimination of control loop oscillation and backflow risk, the system startup delay time is compressed to an absolute minimum.

[0032] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A constant current discharge circuit for an output filter capacitor applied to a DC / DC converter having a synchronous rectification circuit, a filter inductor, and an output filter capacitor, characterized by comprising: a constant current discharge circuit for an output filter capacitor comprising: a constant current circuit for an output filter capacitor; a discharge circuit for an output filter capacitor; and a control circuit for an output filter capacitor. Includes a constant current discharge module, a discharge shutdown module, and a power supply terminal; The constant current discharge module includes a first N-channel MOSFET, an NPN transistor, and a first resistor; the drain of the first N-channel MOSFET is connected to the common terminal of the filter inductor and the synchronous rectification circuit, the source of the first N-channel MOSFET is connected to the base of the NPN transistor and one end of the first resistor; the collector of the NPN transistor is connected to the gate of the first N-channel MOSFET, and the emitter of the NPN transistor and the other end of the first resistor are both connected to a reference ground; The discharge shutdown module includes a second N-channel MOSFET and a detection circuit; the drain of the second N-channel MOSFET is connected to the gate of the first N-channel MOSFET, and the source of the second N-channel MOSFET is connected to a reference ground; the gate of the second N-channel MOSFET is connected to the synchronous rectification drive signal terminal of the DC / DC converter through the detection circuit. The gate of the first N-channel MOSFET is connected to the power supply terminal through a charging circuit.

2. A constant current discharging circuit for discharging a filter capacitor of a power supply output according to claim 1, characterized in that, The charging circuit includes a second resistor and a first capacitor; One end of the second resistor is connected to the power supply terminal, and the other end of the second resistor is connected to the gate of the first N-channel MOSFET. One end of the first capacitor is connected to the gate of the first N-channel MOSFET, and the other end of the first capacitor is connected to reference ground.

3. A constant current discharging circuit for discharging a power supply output filter capacitor according to claim 1, wherein, The detection circuit includes a first diode and a second capacitor; The anode of the first diode is coupled to the synchronous rectification drive signal terminal, and the cathode of the first diode is connected to the gate of the second N-channel MOS transistor. One end of the second capacitor is connected to the gate of the second N-channel MOSFET, and the other end of the second capacitor is connected to reference ground.

4. The constant current discharging circuit of a power output filter capacitor according to claim 1, characterized in that, The detection circuit also includes a third resistor and a fourth resistor; The third resistor is connected in series between the synchronous rectification drive signal terminal and the anode of the first diode; One end of the fourth resistor is connected to the gate of the second N-channel MOS transistor, and the other end of the fourth resistor is connected to reference ground. The fourth resistor is connected in parallel with the second capacitor.

5. The constant current discharging circuit of a power output filter capacitor according to claim 1, characterized in that, The constant current discharge circuit also includes a spike absorption circuit; The spike absorption circuit includes a fifth resistor, a second diode, and a third capacitor; The fifth resistor is connected in parallel with the second diode. One end of the parallel connection is connected to the drain of the first N-channel MOS transistor, and the other end is connected to one end of the third capacitor. The other end of the third capacitor is connected to the reference ground. The anode of the second diode is connected to the drain of the first N-channel MOS transistor, and its cathode is connected to one end of the third capacitor.

6. A constant current discharging circuit for discharging a power supply output filter capacitor as defined in claim 1, wherein, The DC / DC converter also includes a reverse-current protection MOSFET and a load input capacitor; The anti-backflow MOSFET is connected in series between the output filter capacitor and the load input capacitor; The source of the anti-backflow MOSFET is connected to the output filter capacitor, the drain of the anti-backflow MOSFET is connected to one end of the load input capacitor, and the other end of the load input capacitor is connected to reference ground.

7. A constant current discharging circuit for discharging a power supply output filter capacitor as defined in claim 1, wherein, The synchronous rectifier circuit is a full-bridge synchronous rectifier circuit. The full-bridge synchronous rectification circuit includes a first to a fourth synchronous rectification MOS transistor, and the synchronous rectification drive signal terminal is connected to the gate of each of the synchronous rectification MOS transistors.

8. The constant current discharge circuit for a power output filter capacitor according to claim 1, characterized in that, The full-bridge synchronous rectifier circuit also includes a transformer secondary winding; One end of the secondary winding of the transformer is connected to the common node of the source of the first synchronous rectifier MOS transistor and the drain of the second synchronous rectifier MOS transistor, and the other end of the secondary winding of the transformer is connected to the common node of the source of the third synchronous rectifier MOS transistor and the drain of the fourth synchronous rectifier MOS transistor. The drain of the first synchronous rectifier MOSFET and the drain of the third synchronous rectifier MOSFET are both connected to the filter inductor; The source of the second synchronous rectifier MOSFET and the source of the fourth synchronous rectifier MOSFET are both connected to the reference ground.

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