High-voltage input active voltage equalization and snubber circuit

Abstract

This application discloses a high-voltage input active voltage equalization and buffer circuit, including: an input bus capacitor unit, an active bus management circuit, a subsequent input capacitor unit, and an auxiliary power supply circuit. The input bus capacitor unit, active bus management circuit, subsequent input capacitor unit, and auxiliary power supply circuit are connected sequentially, and an input bypass circuit is located between the input bus capacitor unit and the active bus management circuit. By replacing the passive voltage equalization method with an active voltage equalization method, the voltage equalization circuit is simplified, thereby solving the technical problem of complex circuit structure caused by the use of passive voltage equalization methods in related technologies.

Description

Technical Field

[0001] This application relates to the field of electrical technology, and more specifically, to a high-voltage input active equalization and buffer circuit. Background Technology

[0002] With the continuous growth in power demands on data center racks driven by artificial intelligence and high-performance computing, high-voltage DC (HVDC) power supply architectures have become a significant industry trend due to their substantial advantages in improving power efficiency and reducing transmission losses. In this architecture, the high-voltage DC bus output from the front-end AC / DC converter powers subsequent LLC (LLC resonant converter) or DAB (dual active bridge converter) converters. Limited by the voltage ratings of power devices and capacitors, the bus capacitor bank is typically constructed using a series capacitor configuration. Traditional solutions often employ parallel voltage-equalizing resistors for static voltage equalization. However, due to the dispersion of capacitor values, leakage current, and equivalent resistance, passive voltage equalization methods struggle to achieve dynamic voltage compensation, easily leading to long-term overvoltage aging of individual capacitors and reduced system reliability. Furthermore, the continuous no-load losses generated by the voltage-equalizing resistors contradict the system's high-efficiency design goals. In scenarios involving transient input voltage drops or power outages, the power supply system must possess sufficient hold-up time to support data protection. Current technologies typically increase energy storage by increasing the bus capacitor capacity, but this contradicts the design trend towards high power density. Furthermore, during high-current transient load switching in applications such as AI accelerators, simply increasing the capacitance is insufficient to effectively suppress large fluctuations in bus voltage, limiting dynamic response speed. Therefore, how to extend hold-up time and improve transient stability under full-load conditions while maintaining high power density is a current bottleneck for high-voltage DC systems. As the core of the control and drive circuitry, the auxiliary power supply is typically connected across the high-voltage series bus. Due to the voltage imbalance of the series capacitors, the auxiliary power supply must adapt to an extremely wide voltage input range, increasing the difficulty of transformer design and reducing conversion efficiency. Introducing an independent high-voltage active voltage equalization circuit would increase the number of components, complicate control logic, and raise system costs, hindering highly integrated and compact circuit design. Summary of the Invention

[0003] This application provides a high-voltage input active voltage equalization and buffer circuit to at least solve the technical problem that the voltage equalization circuit in the related art has a relatively complex circuit structure due to the use of passive voltage equalization.

[0004] According to one aspect of the embodiments of this application, a high-voltage input active voltage equalization and buffer circuit is provided, comprising: an input bus capacitor unit, an active bus management circuit, a subsequent input capacitor unit, and an auxiliary power supply circuit, wherein the input bus capacitor unit, the active bus management circuit, the subsequent input capacitor unit, and the auxiliary power supply circuit are connected in sequence, and the input bypass circuit is disposed between the input bus capacitor unit and the active bus management circuit; the input bus capacitor unit is disposed between the positive terminal and the negative terminal of the DC voltage input, and the input bus capacitor unit includes: a first bus capacitor and a second bus capacitor connected in series. The capacitor is used to output voltage to the active bus management circuit; the active bus management circuit includes: a first voltage balancing circuit and a second voltage balancing circuit symmetrically arranged, used to balance the voltage of the first bus capacitor and the second bus capacitor; the subsequent input capacitor unit includes: a first subsequent capacitor and a second subsequent capacitor, used to output voltage to the auxiliary power supply circuit; the auxiliary power supply circuit is used to balance the voltage of the first subsequent capacitor and the second subsequent capacitor; the input bypass circuit is used to provide a path for the high-voltage input active voltage equalization and buffer circuit when the input voltage of the high-voltage input active voltage equalization and buffer circuit is higher than a preset voltage.

[0005] Optionally, the first terminal of the first voltage balancing circuit is connected to the first node, the second terminal of the first voltage balancing circuit is connected to the positive terminal of the DC input voltage, and the third terminal of the first voltage balancing circuit is connected to the first midpoint node. The first terminal of the second voltage balancing circuit is connected to the second node, the second terminal of the second voltage balancing circuit is connected to the negative terminal of the DC input voltage, and the third terminal of the second voltage balancing circuit is connected to the first midpoint node. The connection point between the third terminal of the first voltage balancing circuit and the third terminal of the second voltage balancing circuit constitutes the second midpoint node, which is connected to the first midpoint node. The first node is located between the first target point and the second target point, and the second node is located between the third target point and the fourth target point. The first target point is the connection point between the input bus capacitor unit and the positive terminal of the DC input voltage, the second target point is the connection point between the subsequent input capacitor unit and the positive terminal of the DC input voltage, the third target point is the connection point between the input bus capacitor unit and the negative terminal of the DC input voltage, and the fourth target point is the connection point between the subsequent input capacitor unit and the negative terminal of the DC input voltage. The first midpoint node is the connection point between the first bus capacitor and the second bus capacitor.

[0006] Optionally, the first voltage balancing circuit includes: a first switching transistor, a second switching transistor, and a first energy storage inductor, wherein the first energy storage inductor is connected to both the first and second switching transistors, and the first switching transistor is connected to the second switching transistor; the second voltage balancing circuit includes: a third switching transistor, a fourth switching transistor, and a second energy storage inductor, wherein the second energy storage inductor is connected to both the third and fourth switching transistors, the third switching transistor is connected to the fourth switching transistor, and the second switching transistor is also connected to the third switching transistor; the first voltage balancing circuit is used to adjust the duty cycle of the first and second switching transistors to transfer energy from the first bus capacitor to the second bus capacitor when the voltage of the first bus capacitor is higher than the voltage of the second bus capacitor, until the voltage of the first bus capacitor and the voltage of the second bus capacitor are in a balanced state; the second voltage balancing circuit is used to adjust the duty cycle of the third and fourth switching transistors to transfer energy from the second bus capacitor to the first bus capacitor when the voltage of the first bus capacitor is lower than the voltage of the second bus capacitor, until the voltage of the first bus capacitor and the voltage of the second bus capacitor are in a balanced state.

[0007] Optionally, the auxiliary power supply circuit includes: a first primary winding and a second primary winding, wherein the first primary winding and the second primary winding are connected in series, the magnetic cores of the first primary winding and the second primary winding are the same and the number of turns of the windings are equal; the first primary winding is used to charge the first subsequent capacitor; the second primary winding is used to charge the second subsequent capacitor.

[0008] Optionally, when the active bus management circuit is not in operation, the auxiliary power supply circuit is also used to control the voltage of the first bus capacitor and the voltage of the second bus capacitor to be in a balanced state.

[0009] Optionally, the input bypass circuit includes a positive input bypass circuit and a negative input bypass circuit, wherein the positive input bypass circuit is disposed between the positive terminal of the DC voltage input and the first node, and the negative input bypass circuit is disposed between the negative terminal of the DC voltage input and the second node.

[0010] Optionally, the active bus management circuit is also used to control the first bus capacitor and the second bus capacitor to supply power to the subsequent input capacitor unit when the input voltage is less than a preset voltage threshold.

[0011] Optionally, the active bus management circuit is further configured to control the first bus capacitor and the second bus capacitor to supply power to the subsequent input capacitor unit until the output voltage between the first node and the second node equals the reference voltage when the output voltage between the first node and the second node is lower than the reference voltage; the active bus management circuit is further configured to control the subsequent input capacitor unit to supply power to the first bus capacitor and the second bus capacitor until the output voltage between the first node and the second node equals the reference voltage when the output voltage between the first node and the second node is higher than the reference voltage.

[0012] Optionally, the active bus management circuit is also used to independently control the voltage of the first bus capacitor and the second bus capacitor to be in a balanced state when the second midpoint node and the third midpoint node are disconnected.

[0013] Optionally, the auxiliary power supply circuit is also used to independently control the charging voltage of the first and second stage capacitors to be in a balanced state when the second midpoint node and the third midpoint node are disconnected.

[0014] In this embodiment, an input bus capacitor unit, an active bus management circuit, a subsequent input capacitor unit, and an auxiliary power supply circuit are employed. The input bus capacitor unit, active bus management circuit, subsequent input capacitor unit, and auxiliary power supply circuit are connected sequentially. The input bypass circuit is located between the input bus capacitor unit and the active bus management circuit. The input bus capacitor unit is located between the positive and negative terminals of the DC voltage input and includes a first bus capacitor and a second bus capacitor connected in series, used to output voltage to the active bus management circuit. The active bus management circuit includes a symmetrically arranged first voltage balancing circuit and a second... A dual voltage balancing circuit is used to balance the voltages of the first bus capacitor and the second bus capacitor. The subsequent input capacitor unit includes a first subsequent capacitor and a second subsequent capacitor, used to output voltage to the auxiliary power supply circuit. The auxiliary power supply circuit is used to balance the voltages of the first subsequent capacitor and the second subsequent capacitor. An input bypass circuit is used to provide a path for the high-voltage input active voltage equalization and buffer circuit when the input voltage of the high-voltage input active voltage equalization and buffer circuit is higher than the preset voltage. By replacing the passive voltage equalization method with an active voltage equalization method, the voltage equalization circuit is simplified, thereby solving the technical problem that the voltage equalization circuit in related technologies has a relatively complex circuit structure due to the use of passive voltage equalization. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1This is a schematic diagram of a high-voltage input active voltage equalization and buffer circuit structure according to an embodiment of this application;

[0017] Figure 2 This is a partial structural schematic diagram of a high-voltage input active voltage equalization and buffer circuit according to an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of another high-voltage input active voltage equalization and buffer circuit structure according to an embodiment of this application;

[0019] Figure 4 This is a schematic diagram of another high-voltage input active voltage equalization and buffer circuit structure according to an embodiment of this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] The information collected in this application embodiment is information and data authorized by the user or fully authorized by all parties. The collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data all comply with the relevant laws, regulations and standards of the relevant regions, and necessary confidentiality measures have been taken. It does not violate public order and good morals, and provides corresponding operation entry points for users to choose to authorize or reject the automated decision results. If the user chooses to reject, the process will proceed to the expert decision-making process.

[0023] Figure 1 This is a schematic diagram of a high-voltage input active voltage equalization and buffer circuit according to an embodiment of this application, as shown below. Figure 1 As shown, the circuit includes:

[0024] The system comprises an input bus capacitor unit 100, an active bus management circuit 300, a subsequent input capacitor unit 400, and an auxiliary power supply circuit 500. These components are connected sequentially. An input bypass circuit 200 is positioned between the input bus capacitor unit 100 and the active bus management circuit 300. The input bus capacitor unit 100 is located between the positive terminal (HVDC+) and the negative terminal (HVDC-) of the DC input voltage. The input bus capacitor unit 100 includes a first bus capacitor C1 and a second bus capacitor C2 connected in series, used to supply power to the active bus. The bus management circuit 300 outputs voltage; the active bus management circuit 300 includes: a symmetrically arranged first voltage balancing circuit 310 and a second voltage balancing circuit 320, used to balance the voltages of the first bus capacitor C1 and the second bus capacitor C2; the downstream input capacitor unit 400 includes: a first downstream capacitor C3 and a second downstream capacitor C4, used to output voltage to the auxiliary power supply circuit 500; the auxiliary power supply circuit 500 is used to balance the voltages of the first downstream capacitor C3 and the second downstream capacitor C4; the input bypass circuit 200 is used to provide a path for the high-voltage input active voltage equalization and buffer circuit when the input voltage of the high-voltage input active voltage equalization and buffer circuit is higher than a preset voltage.

[0025] By employing an input bus capacitor unit, an active bus management circuit, a subsequent input capacitor unit, and an auxiliary power supply circuit, wherein the input bus capacitor unit, active bus management circuit, subsequent input capacitor unit, and auxiliary power supply circuit are connected sequentially; the input bus capacitor unit is positioned between the positive and negative terminals of the DC voltage input and includes a first bus capacitor and a second bus capacitor connected in series, used to output voltage to the active bus management circuit; the active bus management circuit includes a symmetrically arranged first voltage balancing circuit and a second voltage balancing circuit, used to balance the voltages of the first bus capacitor and the second bus capacitor; the subsequent input capacitor unit includes a first subsequent capacitor and a second subsequent capacitor, used to output voltage to the auxiliary power supply circuit; the auxiliary power supply circuit is used to balance the voltages of the first subsequent capacitor and the second subsequent capacitor. By replacing the passive voltage equalization method with an active voltage equalization method, the voltage equalization circuit is simplified, thereby solving the technical problem of complex circuit structure caused by the use of passive voltage equalization methods in related technologies. A detailed explanation follows.

[0026] like Figure 2As shown, the first terminal of the first voltage balancing circuit 310 is connected to the first node A, the second terminal of the first voltage balancing circuit 310 is connected to the positive terminal of the DC input voltage (HVDC+), and the third terminal of the first voltage balancing circuit is connected to the first midpoint node O1. The first terminal of the second voltage balancing circuit 320 is connected to the second node B, the second terminal of the second voltage balancing circuit is connected to the negative terminal of the DC input voltage (HVDC-), and the third terminal of the second voltage balancing circuit 320 is connected to the first midpoint node O1. The connection point between the third terminals of the first and second voltage balancing circuits forms the second midpoint node O2, and the second midpoint node O2 is connected to the first midpoint node B. O1, the first node A is located between the first target point and the second target point, the second node B is located between the third target point and the fourth target point, the first target point is the connection point between the input bus capacitor unit 100 and the positive terminal of the DC voltage input (HVDC+), the second target point is the connection point between the subsequent input capacitor unit 400 and the positive terminal of the DC voltage input (HVDC+), the third target point is the connection point between the input bus capacitor unit 100 and the negative terminal of the DC voltage input (HVDC-), the fourth target point is the connection point between the subsequent input capacitor unit 400 and the negative terminal of the DC voltage input (HVDC-), and the first midpoint node O1 is the connection point between the first bus capacitor C1 and the second bus capacitor C2.

[0027] like Figure 2 As shown, the first voltage balancing circuit 310 includes: a first switch Q1, a second switch Q2, and a first energy storage inductor L1, wherein the first energy storage inductor L1 is connected to both the first switch Q1 and the second switch Q2, and the first switch Q1 is connected to the second switch Q2; the second voltage balancing circuit 320 includes: a third switch Q3, a fourth switch Q4, and a second energy storage inductor L2, wherein the second energy storage inductor L2 is connected to both the third switch Q3 and the fourth switch Q4, the third switch Q3 is connected to the fourth switch Q4, and the second switch Q2 is also connected to the third switch Q3; the first voltage balancing circuit 310 is used for the first bus capacitor C1 When the voltage of the first bus capacitor C1 is higher than the voltage of the second bus capacitor C2, the duty cycle of the first switch Q1 and the second switch Q2 is adjusted to transfer the energy in the first bus capacitor C1 to the second bus capacitor C2 until the voltage of the first bus capacitor C1 and the voltage of the second bus capacitor C2 are in a balanced state; the second voltage balancing circuit 320 is used to adjust the duty cycle of the third switch Q3 and the fourth switch Q4 when the voltage of the first bus capacitor C1 is lower than the voltage of the second bus capacitor C2, to transfer the energy in the second bus capacitor C2 to the first bus capacitor C1 until the voltage of the first bus capacitor C1 and the voltage of the second bus capacitor C2 are in a balanced state.

[0028] like Figure 3As shown, the high-voltage input active voltage equalization and buffer circuit also includes an input bypass circuit (not shown in the figure). The input bypass circuit includes a positive input bypass circuit 210 and a negative input bypass circuit 220. The positive input bypass circuit is located between the positive terminal of the DC voltage input (HVDC+) and the first node A, and the negative input bypass circuit is located between the negative terminal of the DC voltage input (HVDC-) and the second node B. The auxiliary power supply circuit 500 includes a first primary winding NP1 and a second primary winding NP2. The first primary winding NP1 and the second primary winding NP2 are connected in series. The magnetic cores of the first primary winding NP1 and the second primary winding NP2 are the same, and the number of turns of the windings are equal. The first primary winding NP1 is used to charge the first subsequent capacitor C3. The second primary winding NP2 is used to charge the second subsequent capacitor C4.

[0029] In practical application scenarios, the working principle of the high-voltage input active voltage equalization and buffer circuit in this application embodiment is as follows: When the active bus management circuit 300 is in a non-working state, the auxiliary power supply circuit 500 is also used to control the voltage of the first bus capacitor C1 and the voltage of the second bus capacitor C2 to be in a balanced state.

[0030] The active bus management circuit 300 is also used to control the first bus capacitor C1 and the second bus capacitor C2 to supply power to the subsequent input capacitor unit 400 when the input voltage is less than a preset voltage threshold.

[0031] The active bus management circuit 300 is further configured to, when the output voltage between the first node A and the second node B is lower than the reference voltage Vref, control the first bus capacitor C1 and the second bus capacitor C2 to supply power to the subsequent input capacitor unit 400 until the output voltage between the first node A and the second node B equals the reference voltage Vref; the active bus management circuit 300 is also configured to, when the output voltage between the first node A and the second node B is higher than the reference voltage Vref, control the subsequent input capacitor unit 400 to supply power to the first bus capacitor C1 and the second bus capacitor C2 until the output voltage between the first node A and the second node B equals the reference voltage Vref. The active bus management circuit 300 is also configured to, when the second midpoint node O2 and the third midpoint node O3 are disconnected, independently control the voltage of the first subsequent capacitor C3 and the second subsequent capacitor C4 to be in a balanced state. The auxiliary power supply circuit 500 is also configured to, when the second midpoint node O2 and the third midpoint node O3 are disconnected, independently control the charging voltage of the first subsequent capacitor C3 and the second subsequent capacitor C4 to be in a balanced state.

[0032] To better illustrate the high-voltage input active voltage equalization and buffering circuit in the embodiments of this application, the working principle of the high-voltage input active voltage equalization and buffering circuit in the embodiments of this application is specifically explained in conjunction with the accompanying drawings. Figure 1 For example, the system includes an input bus capacitor unit 100, an active bus management circuit 300, a symmetrically arranged first voltage balancing circuit 310 and second voltage balancing circuit 320, a subsequent input capacitor unit 400, and an auxiliary power supply circuit 500. The input bus capacitor unit 100 is connected between the positive terminal HVDC+ and the negative terminal HVDC- of the high-voltage DC input. The input bus capacitor unit 100 includes a first bus capacitor C1 and a second bus capacitor C2 connected in series, and the connection point of C1 and C2 forms a first midpoint node O1.

[0033] The input capacitor unit 400 is connected between the first node A and the second node B to provide transient energy support for the subsequent converter (e.g., an LLC resonant converter). The input capacitor unit 400 includes a first subsequent capacitor C3 and a second subsequent capacitor C4 connected in series, and their connection point forms a third midpoint node O3. O3 can be selectively connected to O2 (e.g., controlled by a switch).

[0034] like Figure 2 The active bus management circuit 300 includes a symmetrically arranged first voltage balancing circuit 310 and a second voltage balancing circuit 320. The first voltage balancing circuit 310 is connected between the first node A and HVDC+, and has a third terminal connected to O1; the second voltage balancing circuit 320 is connected between the second node B and HVDC-, and also has a third terminal connected to O1. The connection point between the third terminals of the first voltage balancing circuit 310 and the second voltage balancing circuit 320 forms a third midpoint node O2, which is connected to the first midpoint node O1. The active bus management circuit 300 performs a first function and a second function: the first function is to actively balance the voltages of C1 and C2; the second function is to regulate the bus output voltage Vbus between points A and B.

[0035] The first voltage balancing circuit 310 adopts a Boost converter topology, including a first switch Q1, a second switch Q2, and a first energy storage inductor L1. The drain of Q1 is connected to the first node A, the source of Q1 is connected to the drain of Q2 to form the first switching node S1, the source of Q2 is connected to O2, one end of L1 is connected to S1, and the other end of L1 is connected to HVDC+. The second voltage balancing circuit 320 adopts an Inverting Boost converter topology, including a third switch Q3, a fourth switch Q4, and a second energy storage inductor L2. The source of Q4 is connected to the second node B, the drain of Q4 is connected to the source of Q3 to form the second switching node S2, the drain of Q3 is connected to O2, one end of L2 is connected to S2, and the other end of L2 is connected to HVDC-. In this embodiment, O2 is connected to O1. In this embodiment, the active bus management circuit 300 controls the duty cycle of Q1~Q4 to adjust the bidirectional energy flow between C1 and C2, thereby achieving active voltage balancing. Specifically, when the voltage of C1 is detected to be higher than the voltage of C2, Q1 and Q2 are controlled to operate in Boost mode, transferring part of the energy stored in C1 to C2 through L1; when the voltage of C1 is detected to be lower than the voltage of C2, Q3 and Q4 are controlled to operate in Inverting Boost mode, transferring part of the energy stored in C2 to C1 through L2.

[0036] Simultaneously, the active bus management circuit 300 dynamically adjusts the bus output voltage Vbus between points A and B by regulating the switching states of Q1~Q4. When Vbus falls below the preset reference value Vref due to input voltage fluctuations or load changes, the circuit operates in boost mode, transferring the energy stored in C1 and C2 to the subsequent input capacitor unit 400, causing Vbus to rise back to Vref. When Vbus is higher than Vref, the circuit operates in reverse mode, feeding back the excess energy in the subsequent input capacitor unit 400 to C1 and C2, causing Vbus to fall back to Vref. Through this bidirectional energy flow control, stable regulation of the bus output voltage is achieved. Optionally, Vref corresponds to the optimal efficiency operating point of the subsequent LLC converter, such as the input voltage corresponding to its resonant frequency.

[0037] like Figure 3As shown, the Oring circuit (input bypass circuit 200) includes a positive Oring circuit (positive input bypass circuit) 210 and a negative Oring circuit (negative input bypass circuit) 220. The input Oring circuit includes a positive Oring circuit 210 and a negative Oring circuit 220. The positive Oring circuit 210 is connected between HVDC+ and the first node A, and the negative Oring circuit 220 is connected between HVDC- and the second node B. In this embodiment, both the positive Oring circuit 210 and the negative Oring circuit 220 are implemented by ideal diode circuits composed of switching transistors and their control circuits. These circuits have low forward voltage and fast response speed, providing a low-loss path for the main power circuit when the input voltage is higher than a preset value, and quickly turning off when the input voltage is reverse biased to prevent current backflow. It is understood that in other embodiments, the Oring circuit 200 can also be implemented by diodes.

[0038] The auxiliary power supply circuit 500 is an isolated converter with a two-stage primary winding connected in series. In this embodiment, a flyback converter is used as an example. The auxiliary power supply circuit 500 includes a transformer T1. The primary side of T1 has a first primary winding NP1 and a second primary winding NP2, which are connected in series and their series connection point is connected to O3. The other end of NP1 is connected to the first node A, and the other end of NP2 is connected to the second node B. The secondary windings NS1-NSn of T1 are used to generate the control power supply Vcc, which powers the control circuit, drive circuit, and cooling fan.

[0039] Since NP1 and NP2 are wound on the same magnetic core with the same number of turns, according to the principle of magnetic coupling, the induced voltages of NP1 and NP2 are always equal. Therefore, the voltage between point A and O3 is equal to the voltage between O3 and point B. This characteristic results in a dual voltage equalization effect:

[0040] Firstly, for the input bus capacitor unit 100, when the active bus management circuit 300 is not operating (e.g., in a light-load sleep state), the static voltages of C1 and C2 are automatically balanced through the auxiliary power supply circuit 500. According to the magnetomotive force balance principle, the ampere-turns of NP1 and NP2 automatically tend to be consistent under the effect of common core coupling, forcing the voltages of C1 and C2 to remain balanced. At this time, the unidirectional conducting element in the input Oring circuit 200 blocks any possible circulating current.

[0041] Secondly, for the subsequent input capacitor unit 400, the voltage across NP1 acts between A and O3, charging C3; the voltage across NP2 acts between O3 and B, charging C4. Since the voltages of the two windings are equal, C3 and C4 automatically achieve series voltage equalization at point O3, eliminating the need for an additional voltage equalization circuit.

[0042] The following describes the operating modes of the high-voltage input active voltage equalization circuit in this embodiment: In normal operating mode: the input voltage is normal, the input Oring circuit 200 is turned on, and the active bus management circuit 300 operates in voltage equalization and regulation mode, simultaneously charging C3 and C4. The auxiliary power supply circuit 500 draws power from C1 and C2 to provide operating power to the control circuit. In power-down retention mode: when the input power fails and the bus voltage drops below the threshold, the active bus management circuit 300 is forced to operate in boost mode, efficiently transferring the energy stored in C1 and C2 to C3 and C4, maintaining voltage stability between points A and B and extending the power-down retention time.

[0043] It is understood that this embodiment uses a Boost+Inverting Boost topology, such as... Figure 3 As shown, this mainly achieves energy regulation in the boost direction. In other embodiments, if a topology with bidirectional buck-boost capability, such as Buck-Boost or half-bridge, is used, a wider range of output voltage regulation can be achieved. For example, when the input voltage is higher than the target output voltage, buck mode can be used for voltage reduction; when the input voltage is lower than the target output voltage, boost mode can be used for voltage increase. These variations all fall within the scope of protection of this application.

[0044] Figure 4 An input active voltage equalization circuit using a Buck-Boost converter topology is shown, such as... Figure 4 As shown, the first voltage balancing circuit 310 and the second voltage balancing circuit 320 of the active bus management circuit 300 adopt a Buck-Boost converter topology. The specific connection method is similar to that in Embodiment 1, and will not be described again here.

[0045] Those skilled in the art will understand that the first voltage balancing circuit 310 and the second voltage balancing circuit 320 of the active bus management circuit 300 can flexibly select Boost, Buck, Buck-Boost, half-bridge and other topologies according to the actual requirements of the input and output voltage range.

[0046] When the high-voltage input active voltage equalization circuit proposed in this embodiment is applied to a high-voltage DC input power supply system, the circuit includes: an input bus capacitor unit connected between the positive terminal HVDC+ and the negative terminal HVDC- of the high-voltage DC input, the input bus capacitor unit including a first bus capacitor C1 and a second bus capacitor C2 connected in series, their connection point forming a first midpoint node O1; and an input Oring circuit including a positive Oring circuit and a negative Oring circuit, the positive Oring circuit being connected between the positive terminal HVDC+ of the high-voltage DC input and the first node A, and the negative Oring circuit being connected to the negative terminal HVDC- of the high-voltage DC input. Between VDC- and the second node B, an input Oring circuit is used to provide a low-loss path for the main power when the input voltage is higher than a preset value, and has unidirectional conduction characteristics to prevent current backflow; the active bus management circuit includes a symmetrically arranged first voltage balancing circuit and a second voltage balancing circuit; the first voltage balancing circuit has a first terminal, a second terminal, and a third terminal, the first terminal being connected to the first node A, the second terminal being connected to the positive terminal HVDC+ of the high-voltage DC input, and the third terminal being connected to the first midpoint node O1; the second voltage balancing circuit has a first terminal, a second terminal, and a third terminal, the first terminal being connected to the second node B, and the second terminal being connected to the negative terminal HVDC- of the high-voltage DC input. The third terminal is connected to the first midpoint node O1; the connection point between the third terminal of the first voltage balancing circuit and the third terminal of the second voltage balancing circuit forms the second midpoint node O2, and the second midpoint node O2 is connected to the first midpoint node O1; the active bus management circuit is used to perform the first and second functions: the first function is to actively balance the voltage of the first bus capacitor C1 and the second bus capacitor C2; the second function is to adjust the bus output voltage between the first node A and the second node B; the subsequent input capacitor unit is connected between the first node A and the second node B to provide transient energy support for the subsequent converter, and the subsequent input capacitor unit includes the first subsequent capacitor C3 and C2 connected in series. The second stage capacitor C4 has its connection point forming the third midpoint node O3, which can be selectively connected to the second midpoint node O2. The auxiliary power supply circuit is an isolated converter with a two-stage primary winding series structure, including a transformer T1. The primary side of the transformer T1 has a first primary winding NP1 and a second primary winding NP2. The first primary winding NP1 and the second primary winding NP2 are connected in series, and their series connection point is connected to the fourth midpoint node O3. The other end of the first primary winding NP1 is connected to the first node A, and the other end of the second primary winding NP2 is connected to the second node B. The secondary winding of the auxiliary power supply circuit is used to generate control power.The active bus management circuit includes a first voltage balancing circuit comprising a Boost converter consisting of a first switching transistor, a second switching transistor, and a first energy storage inductor; and a second voltage balancing circuit comprising an Inverting Boost converter consisting of a third switching transistor, a fourth switching transistor, and a second energy storage inductor. In the first voltage balancing circuit, the second terminal of the first switching transistor is connected to the first terminal of the second switching transistor to form a first switching node, the first terminal of the first switching transistor is connected to the first node A, the second terminal of the second switching transistor is connected to the second midpoint node O2, one end of the first energy storage inductor is connected to the first switching node, and the other end of the first energy storage inductor is connected to the positive terminal HVDC+ of the high-voltage DC input. In the second voltage balancing circuit, the second terminal of the fourth switching transistor is connected to the first terminal of the third switching transistor to form a second switching node, the first terminal of the fourth switching transistor is connected to the second node B, the second terminal of the third switching transistor is connected to the second midpoint node O2, one end of the second energy storage inductor is connected to the second switching node, and the other end of the second energy storage inductor is connected to the negative terminal HVDC- of the high-voltage DC input. The second midpoint node O2 is connected to the first midpoint node O1.

[0047] The active bus management circuit regulates the bidirectional energy flow between the first bus capacitor C1 and the second bus capacitor C2 by controlling the duty cycles of the first, second, third, and fourth switching transistors. When the voltage of the first bus capacitor C1 is higher than the voltage of the second bus capacitor C2, the first voltage balancing circuit is activated to transfer some of the energy stored in the first bus capacitor C1 to the second bus capacitor C2. When the voltage of the first bus capacitor C1 is lower than the voltage of the second bus capacitor C2, the second voltage balancing circuit is activated to transfer some of the energy stored in the second bus capacitor C2 to the first bus capacitor C1. Through the coordinated control of the first and second voltage balancing circuits, active voltage balancing between the first bus capacitor C1 and the second bus capacitor C2 is achieved. The input Oring circuit works in conjunction with the auxiliary power supply circuit to automatically balance the voltages of the first bus capacitor C1 and the second bus capacitor C2 of the input bus capacitor unit when the active bus management circuit is not in operation. The auxiliary power supply circuit is an isolated converter with two primary windings connected in series and a common core structure, including but not limited to flyback converters or forward converters. Its first primary winding NP1 and second primary winding NP2 are wound on the same magnetic core, and ampere-turn balance is achieved through magnetic coupling. The input Oring circuit includes unidirectional conduction circuits connected in series in each primary winding branch. The circuit is used to conduct when the input power supply is normally powered and to prevent circulating current between the branch where the first primary winding NP1 is located and the branch where the second primary winding NP2 is located. When the active bus management circuit is not in operation, the static voltage of the first bus capacitor C1 and the second bus capacitor C2 is automatically balanced by the auxiliary power supply circuit: according to the principle of magnetomotive force balance, the ampere-turns of the first primary winding NP1 and the second primary winding NP2 automatically tend to be consistent under the action of common magnetic core coupling, forcing the voltage of the first bus capacitor C1 and the second bus capacitor C2 of the input bus capacitor unit to remain balanced.

[0048] The auxiliary power supply circuit uses a series connection of two primary windings to automatically achieve voltage balance between the first and second stage capacitors C3 and C4. The first primary winding NP1 is connected between the first node A and the third midpoint node O3, and the second primary winding NP2 is connected between the third midpoint node O3 and the second node B. Since the first and second primary windings NP1 and NP2 are wound on the same magnetic core with the same number of turns, their induced voltage amplitudes are identical, ensuring that the voltage across the first primary winding NP1 and the second primary winding NP2 remains equal. The voltage across the first primary winding NP1 acts between the first node A and the third midpoint node O3, charging the first stage capacitor C3. The voltage across the second primary winding NP2 acts between the third midpoint node O3 and the second node B, charging the second stage capacitor C4. Because the voltages of the two primary windings are equal, the first and second stage capacitors C3 and C4 automatically achieve series voltage equalization at the third midpoint node O3.

[0049] The active bus management circuit features a power-down retention mode: when the input voltage between the positive terminal HVDC+ and the negative terminal HVDC- of the high-voltage DC input drops below a threshold, the active bus management circuit operates in boost mode, transferring the energy stored in the first bus capacitor C1 and the second bus capacitor C2 to the area between the first node A and the second node B, thus extending the power-down retention time. The active bus management circuit also regulates the bus output voltage between the first node A and the second node B: it monitors the amplitude of the bus output voltage. When the bus output voltage deviates from a preset reference value due to input voltage fluctuations or load changes, it stabilizes the bus output voltage to the preset reference value by controlling the bidirectional flow of energy between the first bus capacitor C1, the second bus capacitor C2, and the subsequent input capacitor unit. The preset reference value corresponds to the optimal efficiency operating point of the subsequent converter, which may include, but is not limited to, LLC resonant converters or DAB converters. The first and second voltage balancing circuits of the active bus management circuit include, but are not limited to, one of the following topologies: Boost converter topology for boost applications; Buck converter topology for buck applications; Buck-Boost converter topology for buck-boost applications; and non-isolated half-bridge converter topology. The third midpoint node O3 can be selectively disconnected from the second midpoint node O2. When the third midpoint node O3 is disconnected from the second midpoint node O2, the voltage balancing of the first bus capacitor C1 and the second bus capacitor C2 is independently achieved by the active bus management circuit, and the voltage balancing of the first downstream capacitor C3 and the second downstream capacitor C4 is independently achieved by the auxiliary power supply circuit.

[0050] It should be noted that the above circuit is used in high-voltage DC input power supply systems, including but not limited to: data center server power supplies; electric vehicle charging piles; on-board chargers; and high-voltage DC uninterruptible power supplies.

[0051] The high-voltage input active voltage equalization circuit provided in this embodiment achieves active voltage equalization through an active bus management circuit, while the auxiliary power supply circuit utilizes the magnetic coupling principle to form a passive voltage equalization path. When the input power fails, the active bus management circuit operates in boost mode, efficiently transferring the energy stored in the input bus capacitor unit to the subsequent stage, extending the power failure hold-up time. The active bus management circuit dynamically adjusts the bus output voltage to always match the optimal efficiency operating point of the subsequent converter, improving the overall system energy efficiency.

[0052] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0053] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0054] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0055] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0056] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0057] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0058] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A high-voltage input active voltage equalization and buffer circuit, characterized in that, include: The system includes an input bus capacitor unit, an active bus management circuit, a subsequent input capacitor unit, an input bypass circuit, and an auxiliary power supply circuit. The input bus capacitor unit, the active bus management circuit, the subsequent input capacitor unit, and the auxiliary power supply circuit are connected in sequence, and the input bypass circuit is located between the input bus capacitor unit and the active bus management circuit. The input bus capacitor unit is disposed between the positive terminal of the DC voltage input and the negative terminal of the DC voltage input. The input bus capacitor unit includes a first bus capacitor and a second bus capacitor connected in series, which are used to output voltage to the active bus management circuit. The active bus management circuit includes: a first voltage balancing circuit and a second voltage balancing circuit arranged symmetrically, used to balance the voltage of the first bus capacitor and the second bus capacitor; The post-stage input capacitor unit includes: a first post-stage capacitor and a second post-stage capacitor, used to output voltage to the auxiliary power supply circuit; The auxiliary power supply circuit is used to balance the voltages of the first and second post-stage capacitors. The input bypass circuit is used to provide a path for the high-voltage input active voltage equalization and buffer circuit when the input voltage of the high-voltage input active voltage equalization and buffer circuit is higher than a preset voltage.

2. The high-voltage input active voltage equalization and buffer circuit according to claim 1, characterized in that, The first terminal of the first voltage balancing circuit is connected to the first node, the second terminal of the first voltage balancing circuit is connected to the positive terminal of the DC input voltage, and the third terminal of the first voltage balancing circuit is connected to the first midpoint node. The first terminal of the second voltage balancing circuit is connected to the second node, the second terminal of the second voltage balancing circuit is connected to the negative terminal of the DC input voltage, and the third terminal of the second voltage balancing circuit is connected to the first midpoint node. The connection point between the third terminal of the first voltage balancing circuit and the third terminal of the second voltage balancing circuit constitutes the second midpoint node. The second midpoint node is connected to the first midpoint node. The first node is located between the first target point and the second target point, and the second node is located between the third target point and the fourth target point. The first target point is the connection point between the input bus capacitor unit and the positive terminal of the DC input voltage, the second target point is the connection point between the subsequent input capacitor unit and the positive terminal of the DC input voltage, the third target point is the connection point between the input bus capacitor unit and the negative terminal of the DC input voltage, the fourth target point is the connection point between the subsequent input capacitor unit and the negative terminal of the DC input voltage, and the first midpoint node is the connection point between the first bus capacitor and the second bus capacitor.

3. The high-voltage input active voltage equalization and buffer circuit according to claim 2, characterized in that, The first voltage balancing circuit includes: a first switching transistor, a second switching transistor, and a first energy storage inductor, wherein the first energy storage inductor is connected to the first switching transistor and the second switching transistor, and the first switching transistor is connected to the second switching transistor. The second voltage balancing circuit includes: a third switch, a fourth switch, and a second energy storage inductor, wherein the second energy storage inductor is connected to the third switch and the fourth switch respectively, the third switch is connected to the fourth switch, and the second switch is also connected to the third switch; The first voltage balancing circuit is used to adjust the duty cycle of the first switch and the second switch when the voltage of the first bus capacitor is higher than the voltage of the second bus capacitor, so as to transfer the energy in the first bus capacitor to the second bus capacitor until the voltage of the first bus capacitor and the voltage of the second bus capacitor are in a balanced state. The second voltage balancing circuit is used to adjust the duty cycle of the third and fourth switching transistors when the voltage of the first bus capacitor is lower than the voltage of the second bus capacitor, so as to transfer the energy in the second bus capacitor to the first bus capacitor until the voltage of the first bus capacitor and the voltage of the second bus capacitor are in a balanced state.

4. The high-voltage input active voltage equalization and buffer circuit according to claim 1, characterized in that, The auxiliary power supply circuit includes: a first primary winding and a second primary winding, wherein the first primary winding and the second primary winding are connected in series, and the magnetic cores of the first primary winding and the second primary winding are the same and the number of turns of the windings are equal. The first primary winding is used to charge the first subsequent capacitor; The second primary winding is used to charge the second subsequent capacitor.

5. The high-voltage input active voltage equalization and buffer circuit according to claim 4, characterized in that, When the active bus management circuit is in a non-operating state, the auxiliary power supply circuit is also used to control the voltage of the first bus capacitor and the voltage of the second bus capacitor to be in a balanced state.

6. The high-voltage input active voltage equalization and buffer circuit according to claim 5, characterized in that, The input bypass circuit includes a positive input bypass circuit and a negative input bypass circuit, wherein the positive input bypass circuit is disposed between the positive terminal of the DC voltage input and the first node, and the negative input bypass circuit is disposed between the negative terminal of the DC voltage input and the second node.

7. The high-voltage input active voltage equalization and buffer circuit according to claim 1, characterized in that, The active bus management circuit is also used to control the first bus capacitor and the second bus capacitor to supply power to the subsequent input capacitor unit when the input voltage is less than a preset voltage threshold.

8. The high-voltage input active voltage equalization and buffer circuit according to claim 1, characterized in that, The active bus management circuit is also used to control the first bus capacitor and the second bus capacitor to supply power to the subsequent input capacitor unit until the output voltage between the first node and the second node is equal to the reference voltage when the output voltage between the first node and the second node is lower than the reference voltage. The active bus management circuit is also used to control the subsequent input capacitor unit to supply power to the first bus capacitor and the second bus capacitor until the output voltage between the first node and the second node is equal to the reference voltage when the output voltage between the first node and the second node is higher than the reference voltage.

9. The high-voltage input active voltage equalization and buffer circuit according to claim 2, characterized in that, The active bus management circuit is also used to independently control the voltage of the first bus capacitor and the second bus capacitor to be in a balanced state when the second midpoint node and the third midpoint node are disconnected.

10. The high-voltage input active voltage equalization and buffer circuit according to claim 2, characterized in that, The auxiliary power supply circuit is also used to independently control the charging voltage of the first and second post-stage capacitors to be in a balanced state when the second midpoint node and the third midpoint node are disconnected.

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