Cascaded two-stage power converter and multiphase power supply system including the converter

Abstract

The integrated circuit includes: a first-stage circuit, a second-stage circuit, a synchronous communication module, and an I / O communication module. The first-stage circuit is configured to receive a first-stage input voltage through a first-stage input terminal and divide that voltage to generate a first-stage output voltage. The second-stage circuit is configured to receive the first-stage output voltage through a second-stage input terminal and regulate that first-stage output voltage to generate a second-stage output voltage. The synchronous communication module is configured to couple with the synchronous communication module of another integrated circuit in a multiphase power supply system and share a clock signal with that other integrated circuit. The I / O communication module is configured to communicate with a host controller.

Description

Technical Field

[0001] This disclosure generally relates to the field of electrical circuits, and more specifically, but not limited to, cascaded two-stage power converters with optimized thermal design and multiphase power supply systems including multiple such two-stage power converters. Background Technology

[0002] Traditional voltage regulator designs typically employ a single-stage architecture. Such designs require power MOSFETs to cover the entire input voltage range with a safety margin. This limitation can lead to the use of high-resistivity, low-efficiency power MOSFETs, thus reducing overall performance. Furthermore, the voltage drop across the inductor is often high, reducing system efficiency. More seriously, thermal stress is concentrated in specific areas of the system rather than being uniformly distributed. Summary of the Invention

[0003] In one embodiment, an integrated circuit for a switching power supply is applicable to a multiphase power system including multiple such integrated circuits. The integrated circuit includes: a first-stage input terminal, a first-stage output terminal, a second-stage input terminal, a first-stage circuit, a second-stage circuit, a synchronization communication module, and an input / output communication module. The first-stage input terminal is configured to receive a first-stage input voltage. The first-stage output terminal is configured to output a first-stage output voltage lower than the first-stage input voltage, and is configured to couple with the first-stage output terminals of other integrated circuits in the multiphase power system. The second-stage input terminal is configured to couple with the first-stage output terminal to receive the first-stage output voltage. The first-stage circuit is configured to receive the first-stage input voltage through the first-stage input terminal and divide the first-stage input voltage to generate the first-stage output voltage. The second-stage circuit is configured to receive the first-stage output voltage through the second-stage input terminal and regulate the first-stage output voltage to generate a second-stage output voltage. The synchronization communication module is configured to connect to the synchronization communication module of another integrated circuit among the multiple integrated circuits and synchronize a clock signal with that other integrated circuit. The input / output communication module is configured to communicate with the host controller.

[0004] A multiphase power supply system includes multiple integrated circuits. Each integrated circuit includes a first-stage input terminal, a first-stage output terminal, a second-stage input terminal, a first-stage circuit, a second-stage circuit, a synchronization communication module, and an input / output communication module. The first-stage input terminal is configured to receive a first-stage input voltage. The first-stage output terminal is configured to output a first-stage output voltage lower than the first-stage input voltage, and is configured to couple with the first-stage output terminals of other integrated circuits in the multiphase power supply system. The second-stage input terminal is configured to couple with the first-stage output terminal to receive the first-stage output voltage. The first-stage circuit is configured to receive the first-stage input voltage through the first-stage input terminal and divide the first-stage input voltage to generate the first-stage output voltage. The second-stage circuit is configured to receive the first-stage output voltage through the second-stage input terminal and regulate the first-stage output voltage to generate a second-stage output voltage. The synchronization communication module is configured to connect to the synchronization communication module of another integrated circuit among the multiple integrated circuits and synchronize a clock signal with the other integrated circuit. The input / output communication module is configured to communicate with a host controller.

[0005] It should be understood that the description in this section is not intended to identify key or important features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0006] The invention can be further understood by referring to the following detailed description and accompanying drawings, wherein the same elements are represented by the same reference numerals. These drawings are for illustrative purposes only and may show only a portion of the device, and are not necessarily drawn to scale.

[0007] Figure 1 A schematic diagram of a power converter 100 according to an embodiment of the present invention is shown.

[0008] Figure 2A A schematic diagram of a single-phase charge pump according to an embodiment of the present invention is shown.

[0009] Figure 2B A schematic diagram of a multiphase charge pump according to an embodiment of the present invention is shown.

[0010] Figure 3 A schematic diagram of a power converter 300 according to an embodiment of the present invention is shown.

[0011] Figure 4 A schematic diagram of a multiphase power supply system 400 according to an embodiment of the present invention is shown.

[0012] Figure 5A schematic diagram of a multiphase power supply system 500 according to another embodiment of the present invention is shown.

[0013] Figure 6 A schematic diagram of a power converter IC 600 according to another embodiment of the present invention is shown. Detailed Implementation

[0014] Various embodiments of the invention will now be described. In the following description, specific details, such as example circuits and example values ​​for these circuit components, are included to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that this disclosure may be practiced without one or more specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, processes, or operations have not been shown or described in detail to avoid obscuring aspects of this disclosure.

[0015] Throughout the specification and claims, the phrases “in one embodiment,” “in some embodiments,” “in one implementation,” and “in some implementations” encompass combinations and sub-combinations of the various features herein, as well as variations and modifications thereof. These phrases used herein do not necessarily refer to the same embodiment, although they may. Those skilled in the art will understand that the meaning of the foregoing terms is not intended to limit the terminology, but merely to provide illustrative examples. Note that when an element is “connected to” or “coupled to” another element, this means that the element is directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element via another element. Specific features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide functionality. Furthermore, it should be understood that the accompanying drawings provided herein are for explanation to those skilled in the art and are not necessarily drawn to scale.

[0016] Figure 1 A schematic diagram of a power converter 100 according to an embodiment of the present invention is shown.

[0017] like Figure 1 As shown, the power converter 100 includes a first-stage circuit 110 and a second-stage circuit 120. Figure 1 In the example, the first-stage circuit 110 uses a voltage divider in the form of a charge pump (CP), and the second-stage circuit 120 includes a multiphase regulator.

[0018] The first-stage circuit 110 receives the input voltage VIN at node 101 and outputs an intermediate voltage V_INT at node 102. In one embodiment, the first-stage circuit 110 can function as a voltage divider, converting the larger input voltage VIN into a smaller intermediate voltage V_INT. In one embodiment, the intermediate voltage V_INT is half the input voltage VIN. The intermediate voltage V_INT is connected as an input voltage to the second-stage circuit 120. The second-stage circuit 120 adjusts the intermediate voltage V_INT to the output voltage VOUT at node 201.

[0019] The charge pump 110 can be a single-phase or multi-phase charge pump. Figure 2A A schematic diagram of a single-phase charge pump 110A according to an embodiment of the present invention is shown. Figure 2A As shown, the charge pump 110A includes four switches (i.e., a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4), which are connected in series between node 101 and reference ground, and connected to a flying capacitor CF. The flying capacitor CF is coupled between the common node of the first switch Q1 and the second switch Q2, and between the common node of the third switch Q3 and the fourth switch Q4. Figure 1 The first-stage circuit 110 shown is a single-phase charge pump. However, the first-stage circuit 110 can also be configured as a multi-phase pump. Figure 2B A schematic diagram of a multiphase charge pump 110B is shown, which includes two such... Figure 2A The repeated single-phase configuration is shown.

[0020] The charge pump switches operate according to a clock signal from a clock module (not shown). For example, during half a clock cycle, a specific switch of the charge pump is turned on while the others are turned off; subsequently, during the remaining half cycle, the on / off states of these switches are reversed. Figure 2A Taking the charge pump shown as an example: the first switch Q1 and the third switch Q3 can be in the same state, and the second switch Q2 and the fourth switch Q4 can be in the same state and complement the states of Q1 and Q3.

[0021] Refer again Figure 1 The second-stage circuit 120 includes a multiphase regulator, comprising buck converters 121-X (i.e., 121-1, 121-2, ..., 121-N). In one embodiment, N ≥ 2. Each buck converter 121-X may include a buck controller ( Figure 1The circuit includes (not shown), a switching circuit (e.g., a high-side switch HS and a low-side switch LS), output inductors L (i.e., L1, L2, ..., LN) that connects switching nodes LX (i.e., LX1, LX2, ..., LXN) to the output voltage VOUT at node 201, and a buck output capacitor COUT_BUCK for smoothing and filtering the output voltage VOUT. The buck controller regulates the current flowing through the corresponding inductors by controlling the complementary on and off states of the high-side switch HS and the low-side switch LS, thereby converting the intermediate voltage V_INT into the output voltage VOUT at node 201.

[0022] In one embodiment, voltage divider 110 is configured to halve the input voltage (i.e., from 12V to 6V). Therefore, the second-stage circuit 120 can now utilize power MOSFETs with lower rated voltages compared to a conventional single-stage multiphase regulator, thereby improving efficiency. Furthermore, the reduced input voltage of the buck converter means a significant decrease in the voltage across the inductor during the magnetization phase (current drops from 10.9V (12V-1.1V) to 4.9V (6V-1.1V)), which reduces both ripple and AC power losses across the inductor.

[0023] Figure 3 A schematic diagram of a power converter 300 according to an embodiment of the present invention is shown.

[0024] like Figure 3 As shown, the power converter 300 includes a first-stage circuit 310, a second-stage circuit 320, an electronic fuse 330, an active voltage clamp 340, a CP clock module 350, an input / output (I / O) communication module 360, and a synchronous communication module 370.

[0025] The first-stage circuit 310 and the second-stage circuit 320 are... Figure 1 The specific implementations of the first-stage circuit 110 and the second-stage circuit 120 are shown. In one embodiment, the power converter 300 can be integrated and implemented as a power management integrated circuit (PMIC) or implemented as an independent voltage regulator in the form of an application-specific integrated circuit (IC). These ICs require the configuration of necessary peripheral components, such as capacitors (e.g., flying capacitor CF, output capacitor COUT_CP, and buck output capacitor COUT_BUCK) and inductors (e.g., inductors L1, L2, ..., LN).

[0026] The first-stage circuit 310 receives the input voltage (also known as the first-stage input voltage) from the input terminal VIN (also known as the first-stage input terminal) via eFuse 330. The first-stage circuit 310 divides the input voltage Vin to a lower intermediate voltage V_INT (also known as the first-stage output voltage) and outputs the intermediate voltage V_INT at the output terminal CPOUT (e.g., also known as the first-stage output terminal). The active voltage clamp 340 clamps the input voltage Vin at a predetermined voltage level.

[0027] The eFuse 330 includes a current sensing circuit to monitor the current flowing through the first-stage circuit 310. When the current flowing through the eFuse 330 exceeds a threshold, the eFuse 330 will disconnect the input voltage Vin from the first-stage circuit 310. In addition to isolation, the power converter 300 also provides current clamping and voltage clamping functions to prevent system board damage under fault conditions.

[0028] The disconnect function of eFuse 330 can be implemented in several ways. For example, eFuse 330 can connect a switch (such as a MOSFET) in series between the input voltage Vin and the first-stage circuit 310. This switch is normally closed and opens when overvoltage and / or overcurrent is detected. eFuse 330 can also integrate an active clamping circuit to bypass energy to ground when overvoltage is detected. Deploying eFuse 330 near the input voltage Vin enhances input voltage-dependent protection. eFuse 330 and active voltage clamp 340 enable the first-stage circuit 310 to accommodate a wide range of input voltages (e.g., 3.3V to 48V) to meet various application requirements. eFuse 330 can also include slew rate control. That is, eFuse 330 can be configured to provide the input voltage Vin to the first-stage circuit 310 so that the input voltage is reflected at the output terminal of the first-stage circuit 310 in a slew rate controlled manner.

[0029] like Figure 3 As shown, the first-stage circuit 310 includes a CP logic and control circuit 311, a CP driver 312, and a CP switching circuit 313.

[0030] The CP logic and control circuit 311 controls the switching operation of the switches in the charge pump 310 based on the clock signal CLK provided by the CP clock module 350. For example, during half a clock cycle, a specific switch in the charge pump 310 is turned on while the remaining switches are turned off; subsequently, during the remaining half cycle, the on and off states of these switches are reversed. In one embodiment, the clock module 350 may include a clock generator (such as an oscillator) and a clock phase shifter. The CP logic and control circuit 311 can generate switch control signals CTRL_Q1, CTRL_Q2, CTRL_Q3, and CTRL_Q4 to control the on and off states of switches Q1-Q4. This circuit may also provide additional functions such as enabling / disabling the power converter and outputting a power supply normal signal.

[0031] The CP driver 312 is configured to generate drive signals DRIV_Q1-DRIV_Q4 based on the switch control signals CTRL_Q1-CTRL_Q4 respectively. The CP driver 312 enhances the driving capability of the corresponding switch control signals. Ideally, when the system is in a stable operating state, the drive signals DRIV_Q1-DRIV_Q4 remain synchronized / consistent with the corresponding switch control signals CTRL_Q1-CTRL_Q4.

[0032] The second-stage circuit 320 receives the intermediate voltage V_INT generated by the first-stage circuit 310 through the power input terminal PIN (also known as the second-stage input terminal) and converts the intermediate voltage into a regulated output voltage VOUT (also known as the second-stage output voltage VOUT). The second-stage circuit 320 includes a multi-phase buck converter. Each phase includes a buck controller 321_X (i.e., 321_1, 321_2, ..., 321_N), a buck driver 322_X (i.e., 322_1, 322_2, ..., 322_N), and a switching circuit 323_X (i.e., 323_1, 323_2, ..., 323_N, each including a high-side switch HS and a low-side switch LS), and is connected to the output inductor LX (i.e., L1, L2, ..., LN) and the buck output capacitor COUT_BUCK through the switching terminals SWX (i.e., SW1, SW2, ..., SWN) to generate the output voltage VOUT. The buck controller 321_X controls the complementary on / off switching of the high-side switch HS and the low-side switch LS of each phase, thereby regulating the current flowing through the corresponding inductor LX. Thus, the multi-phase cooperative conversion of the intermediate voltage V_INT into the output voltage VOUT. Specifically, each buck controller 321_X can generate high-side switch control signals HCTL_X (e.g., HCTL_1, HCTL_2, ..., HCTL_N) and low-side switch control signals LCTL_X (e.g., LCTL_1, LCTL_2, ..., LCTL_N) based on feedback signals. In one embodiment, the switch control signals are pulse width modulation (PWM) signals. In embodiments using PWM control methods such as voltage control and current control, the buck controller 321_X can amplify the difference between the feedback signal and the reference signal, and then compare this amplified difference signal with a ramp signal to generate the switch control signals. In one embodiment, the buck controller 321_X can operate in a critical on-state mode controlled by constant on-time (COT).

[0033] It is important to understand that the buck controller 321_X can be implemented using any suitable control mode and circuit structure, as long as it can control the power level. This application does not restrict the topology and control mode of the buck controller.

[0034] Each buck driver 322_X is configured to generate a high-side drive signal HDRV_X (i.e., HDRV_1, HDRV_2, ..., HDRV_N) based on the corresponding high-side switch control signal HCTL_X, and a low-side drive signal LDRV_X (i.e., LDRV_1, LDRV_2, ..., LDRV_N) based on the corresponding low-side switch control signal LCTL_X. The buck driver 322_X enhances the driving capability of the high-side switch control signal HCTL_X and the low-side switch control signal LCTL_X (i.e., by increasing the amplitude difference between their logic high and low levels). Ideally, when the system is in a stable operating state, the high-side drive signal HDRV_X and the low-side drive signal LDRV_X remain synchronized / consistent with the logic states of the corresponding high-side switch control signal HCTL_X and low-side switch control signal LCTL_X, respectively.

[0035] The I / O communication module 360 ​​is used to communicate with other devices (such as a host controller). This module may include a Universal Asynchronous Receiver / Transmitter (UART) communication module, a Serial Peripheral Interface (SPI) communication module, an I2C / I3C communication module, etc. Figure 3 In the example shown, the I / O communication module 360 ​​is an I2C / I3C communication module, which can communicate with another device (such as a host) based on the I2C / I3C protocol through the SDA and SCL terminals.

[0036] Two-stage power converters offer several advantages: First, they achieve discrete two-stage operation and distributed heat dissipation within a uniform design size, effectively mitigating thermal stress on the design board. Second, the first-stage circuit places the eFuse near the power input terminal, enabling input voltage-related protection for the system board and improving design reliability. This circuit covers a wide voltage range from 3.3V to 48V to adapt to different application scenarios. Third, the integrated charge pump structure of the first-stage circuit minimizes power consumption and improves thermal stress. Fourth, the low input voltage of the second-stage circuit supports the use of low-voltage devices, thereby maximizing the overall solution's efficiency. Fifth, placing the second-stage circuit near the load side enables superior local load regulation performance.

[0037] Figure 4 A schematic diagram of a multiphase power supply system 400 according to an embodiment of the present invention is shown.

[0038] like Figure 4 As shown, the multiphase power system 400 includes multiple power converter ICs connected in parallel. For example, each power converter IC may be a power management integrated circuit (PMIC). Figure 4This includes PMIC_1, PMIC_2, ..., PMIC_M. In one embodiment, M ≥ 2. In one embodiment, PMIC_1-PMIC_M have the same structure. In a specific embodiment, PMIC_X (e.g., PMIC_1, PMIC_2, ..., or PMIC_M) may be... Figure 3 The power converter 300 shown is implemented in a specific way.

[0039] like Figure 4 As shown, PMIC_X includes a first-level circuit 410, a second-level circuit 420, a clock module 450, a synchronous communication module 460, an I / O communication module 470, and a set of terminals IN, CFP, CFN, CPOUT, SYN, PIN, SDA, SCL, and SW1, SW2, ..., SWN. PMIC_X may include several other units or modules that perform corresponding functions. To avoid obscuring the core content of this embodiment, these functional units or modules are not described here.

[0040] The first-stage circuit 410 receives the input voltage Vin from terminal VIN and outputs the intermediate voltage V_INT at terminal CPOUT. The second-stage circuit 410 receives the intermediate voltage V_INT output by the first-stage circuit 410 from the PIN terminal and converts this intermediate voltage into the output voltage VOUT. Figure 4 As shown, in one embodiment, the CPOUT terminals of all PMICs are connected to a common output node to provide an intermediate voltage V_INT. In another embodiment, a shared capacitor COUT_CP is connected to this common output node.

[0041] To reduce output current ripple and support the use of smaller, lighter capacitors (such as the shared capacitor COUT_CP and the flying capacitors on each PMIC), this application proposes a method for precisely synchronizing the switching clock cycles of the first-stage circuits in each PMIC of a system 400.

[0042] In one embodiment, the host controller typically communicates via a digital communication bus (such as I...). 2 The host controller (either C or SPI) communicates individually with each PMIC, and this communication is implemented via the corresponding I / O communication module 470 within each PMIC. In one embodiment, the host controller is typically integrated into a system-on-a-chip (SoC) or a main microprocessor (MPU) / processor. For example, Figure 4 The I / O communication module 470 shown is an I2C / I3C communication module, which can communicate with the host controller through the SDA and SCL terminals based on the I2C / I3C protocol.

[0043] The host controller may send a first signal to each PMIC informing it of the total number M (i.e., the value of M) of the PMICs in the system 400. In one embodiment, the host controller may write the value of M into a dedicated volatile configuration register (not shown) within each PMIC. The control logic (not shown) within each PMIC may calculate the phase difference (e.g., 360° / M, where M is the total number of PMICs) between the clocks of every two adjacent PMICs based on the total number M of the PMICs in the system. In another embodiment, the host controller may also directly send the phase difference value to each PMIC.

[0044] In one embodiment, the host controller may further send a second signal to each PMIC informing it of its corresponding serial number / index (e.g., '1', '2', ..., or 'M'). In another embodiment, the host controller may write the serial number / index of each PMIC into a dedicated volatile configuration register (not shown) within each PMIC. This serial number / index is a unique identifier for each PMIC in the multiphase power system, used to distinguish each PMIC. It should be understood that the serial number / index may correspond to the physical connection order of the ICs, or it may exist independently of that order. In another embodiment, the M value (or phase difference) and the serial number / index of each PMIC may be pre-programmed and stored in a non-volatile memory register (such as internal EEPROM or flash memory) within each PMIC. For example, users (such as manufacturers in the production testing or development phase) may write the required parameters into the register via specific hardware or software communication modules (typically a JTAG interface, proprietary programming tools, or even physical configuration pins / jumps on the PCB). After receiving the reference clock CLK_1 from the master PMIC, the clock module in the slave device can shift the received reference clock CLK_1 to generate the corresponding local clock (such as CLK_2, CLK_3, ..., CLK_M).

[0045] In one embodiment, the PMIC with serial number "1" can be set as the master device, while other PMICs with serial numbers "2", ..., or "M" are set as slave devices. Figure 4 In the illustrated embodiment, the first PMIC (e.g., PMIC_1) can operate as a master device, and the remaining PMICs (e.g., PMIC_2, PMIC_3, ..., PMIC_M) can operate as slave devices. In another embodiment, a PMIC with a different serial number / index (e.g., '2') can be set as a master device, and the remaining PMICs can be set as slave devices. This application is not limited to this.

[0046] In a stable operating state, the switching frequency and phase of the first-stage circuit 410 in each PMIC are equal to the frequency and phase of its local clock (e.g., CLK_1, CLK_2, CLK_3, ..., CLK_M). In one embodiment, clocks CLK_1, CLK_2, CLK_3, ..., CLK_M constitute a set of clock signals sharing the same frequency and having uniform sequential phase differences. For example, when M = 2, the phase difference between clocks CLK_1 and CLK_2 is 180°; when M = 3, the phase difference between CLK_1 and CLK_2 is 120°, the phase difference between CLK_2 and CLK_3 is 120°, and so on.

[0047] PMIC_1 (or its internal clock module 450) can generate a reference clock CLK_1 and synchronize this reference clock with other slave PMICs via the corresponding synchronization communication module 460 and communication terminal SYN. ​​For example... Figure 3 The clock module 450 typically includes a clock generator (such as an oscillator) and a clock phase shifter. When a PMIC (i.e., PMIC_1) is set as the master device (i.e., assigned a sequence number / index '1'), the clock generator in the master device is enabled to generate the reference clock CLK_1, while the clock phase shifter is disabled.

[0048] Each slave device receives a reference clock CLK_1 via its respective communication module (e.g., 460) and SYN terminal. When a PMIC (i.e., PMIC_2, PMIC_3, ..., PMIC_M) is set as a slave device (i.e., assigned a serial number / index as '2', '3', ..., or 'M'), the clock generator within the slave device is disabled, and a clock phase shifter is enabled to shift the reference clock signal, thereby generating a local clock signal. In one embodiment, the clock phase shifter shifts the received reference clock CLK_1 according to the phase difference and its serial number / index to generate a local clock (e.g., CLK_2, CLK_3, ..., CLK_M). For example, when M = 4, the phase difference is 90°. The first PMIC (i.e., the master device) uses CLK_1, the second PMIC (i.e., PMIC_2) can shift CLK_1 by 90°, the third PMIC (i.e., PMIC_3) can shift it by 180°, and the fourth PMIC (i.e., PMIC_4) can shift it by 270°.

[0049] This approach ensures that the first-stage circuitry in all PMICs in a multiphase configuration operates precisely, synchronously, and interleaved.

[0050] Figure 5 A schematic diagram of a multiphase power supply system 500 according to another embodiment of the present invention is shown.

[0051] like Figure 5As shown, the multiphase power system 500 includes M PMICs, which are connected in a stacked or series manner and can communicate with each other in a daisy-chain manner. For example, as Figure 4 As shown, the second PMIC (e.g., PMIC_2) is connected to the first PMIC (e.g., PMIC_1), the third PMIC (e.g., PMIC_3) is connected to the second PMIC (e.g., PMIC_2), and so on. In one embodiment, PMIC_1 to PMIC_M have the same structure. Figure 5 As shown, the CPOUT terminals of all PMICs are connected to a common output node to provide an intermediate voltage V_INT. In one embodiment, a shared capacitor COUT_CP is connected to this common output node.

[0052] In one embodiment, the first PMIC (e.g., PMIC_1) can act as the master device, and the remaining PMICs (e.g., PMIC_2, PMIC_3, ..., PMIC_M) can act as slave devices.

[0053] The master device connects to the host controller and can communicate directly with it. For example, in Figure 5 In the example shown, the master device can communicate with the host controller via the SDA and SCL terminal pairs based on the I2C / I2C protocol. The host controller can send a signal to PMIC_1 to inform it of the total number M of PMICs in the system (i.e., the value of M). The control logic (not shown) inside PMIC_1 can calculate the phase difference (e.g., 360° / M, where M is the total number of PMICs) between the clocks of every two adjacent PMICs based on the total number M of PMICs in the system. For example, when M = 4, the phase difference is 90°. In another embodiment, the host controller can also send this phase difference directly to PMIC_1.

[0054] In one embodiment, PMIC_1 can store the phase difference in its dedicated volatile configuration register and transmit it via terminal PASS_1 to its next adjacent slave device (e.g., PMIC_2). Similarly, PMIC_2 can receive the phase difference via terminal TAKE_2, store it in its dedicated volatile configuration register, and transmit it via terminal PASS_2 to its next adjacent slave device (e.g., PMIC_3), and so on, until all PMICs are aware of the phase difference between their local clock and the clocks of their adjacent PMICs in the link.

[0055] In one embodiment, during normal operation of the power system 500, PMIC_1 (or its internal clock module) generates a reference clock CLK_1 and uses this clock to control the operation of the first-stage circuit switches in PMIC_1. PMIC_1 then transmits clock CLK_1 to the next-stage PMIC (i.e., PMIC_2) via the PASS_1 terminal. PMIC_2 receives the local clock (CLK_1) from the preceding PMIC (i.e., PMIC_1) via the TAKE_2 terminal and performs a phase shift on the received PMIC_1 clock signal according to the phase difference, thereby generating its own local clock CLK_2. PMIC_2 uses clock CLK_2 to control the switching of its first-stage circuit switches and transmits this clock signal; this clock is then sent to the next-stage PMIC (e.g., PMIC_3) via the PASS_2 terminal. Similarly, PMIC_3 can receive the local clock (CLK_2) of the preceding PMIC (PMIC_2) via the TAKE_3 terminal, and adjust the phase of the received PMIC_2 clock signal according to the phase difference to generate its own local clock CLK_3, and so on. Thus, the final PMIC (PMIC_M) can receive the local clock (CLK_M-1) of the preceding PMIC (PMIC_M-1) via the TAKE_M terminal, and adjust the phase of the received PMIC_M-1 clock signal according to the phase difference to generate its own local clock CLK_M.

[0056] Figure 6 A schematic diagram of a power converter IC 600 according to another embodiment of the present invention is shown. The power converter IC 600 is... Figure 5 The specific implementation of any of the power management ICs (PMICs) shown has the necessary components (e.g., capacitors) located outside the IC.

[0057] Compared to Figure 3 The power converter 300 shown, and the synchronous communication module 670 in the power converter IC 600 are configured, for example, in a multiphase power system including a stacked (series) structure of multiple interconnected PMICs (e.g., Figure 5 In the multiphase power supply system 500 shown, communication with another device is achieved via corresponding terminals (e.g., TAKE_X and PASS_X terminals) in a daisy-chain manner. For example, communication module 670 may include a daisy-chain communication module that interacts with the daisy-chain communication modules of adjacent PMICs via a daisy-chain communication protocol. In another embodiment, communication module 670 transmits and / or receives signals differentially. For example, communication module 670 may be connected to two pairs of terminals, and signals transmitted between adjacent PMICs are transmitted and received in pairs on the paired terminals. The paired signals have equal amplitude but opposite polarities, and the information to be transmitted can be represented by the difference between the two signals. For simplicity, the connection to the signal is omitted. Figure 3The module in the power converter 300 shown is described similarly.

[0058] For example, when the power converter IC 600 is used as a multiphase power supply system (such as...) Figure 5 When the power converter IC 600 acts as the master device in the multiphase power supply system 500 shown, the I / O communication module 660 will be enabled, and the power converter IC 600 can communicate directly with the host through the I / O communication module 660. For example, when the power converter IC 600 acts as the master device, it can directly receive the signal of the total number M (i.e., the value of M) of PMICs in the system or the phase difference between the local clocks of any two adjacent PMICs from the host controller through the I / O communication module 660 and the corresponding SDA and SCL pins, and transmit the phase difference and its local clock to the next adjacent power converter IC through the communication module 670 and the corresponding PASS pin.

[0059] When the power converter IC 600 acts as a slave device in the multiphase power system 500 (e.g., located in the middle or at the end of a daisy-chain structure), the I / O communication module 660 can be disabled, and communication with the master or other ICs can be achieved via one or more adjacent PMICs through a daisy-chain configuration. For example, when the power converter IC 600 operates as a slave device, it can receive the phase difference and local clock signal of the previous PMIC through the communication module 670 and the corresponding TAKE pin, and transmit the phase difference and its own local clock signal through the communication module 670 and the corresponding PASS pin.

[0060] The specific embodiments and accompanying drawings described above are merely common examples of the present invention. Obviously, various additions, modifications, and substitutions can be made without departing from the spirit and scope of the invention as defined in the claims. Those skilled in the art should understand that the present invention can be varied in form, structure, layout, proportion, materials, elements, components, and other aspects in practical applications according to specific environments and working requirements, without departing from the inventive principles. Therefore, the embodiments disclosed herein are for illustrative purposes only and not for limitation. The scope of the present invention is defined by the appended claims and their legal equivalents, and is not limited to the preceding description.

Claims

1. An integrated circuit for a switching power supply, suitable for a multiphase power supply system including multiple such integrated circuits, said integrated circuit comprising: The first-stage input terminal is configured to receive the first-stage input voltage; The first-stage output terminal is configured to output a first-stage output voltage lower than the first-stage input voltage, and the first-stage output terminal is configured to couple with the first-stage output terminals of other integrated circuits in the multiphase power supply system. The second-stage input terminal is configured to be coupled to the first-stage output terminal to receive the first-stage output voltage; The first-stage circuit is configured to receive the first-stage input voltage through the first-stage input terminal and divide the first-stage input voltage to generate the first-stage output voltage; The second-stage circuit is configured to receive the first-stage output voltage through the second-stage input terminal and adjust the first-stage output voltage to generate the second-stage output voltage. A synchronization communication module is configured to connect to the synchronization communication module of another integrated circuit among the plurality of integrated circuits and synchronize a clock signal with the other integrated circuit; and The input / output communication module is configured to communicate with the host controller.

2. The integrated circuit according to claim 1, wherein, The integrated circuit also includes a clock module, which includes a clock generator and a clock phase shifter.

3. The integrated circuit according to claim 2, wherein: When the integrated circuit is configured as the master device in the multiphase power system, the clock generator is enabled to generate a reference clock signal, while the clock phase shifter is disabled. The reference clock signal serves as the local clock signal of the master device, and the operation of the switches in the first-stage circuit of the integrated circuit is controlled by the reference clock signal. When the integrated circuit is configured as a slave device in the multiphase power system, the clock generator is disabled, and the clock phase shifter is enabled to generate a local clock signal for the integrated circuit, and the operation of the switches in the first-stage circuit of the integrated circuit is controlled by the local clock signal.

4. The integrated circuit according to claim 3, wherein: When the integrated circuit is configured as the master device, the synchronization communication module is configured to share the reference clock signal with the synchronization communication modules of the other integrated circuits among the plurality of integrated circuits excluding the integrated circuit itself. as well as When the integrated circuit is configured as the slave device, the clock phase shifter receives the reference clock signal from the master device through a corresponding synchronization communication module, and shifts the reference clock signal according to the phase difference and the serial number of the integrated circuit in the multiphase power system, thereby generating the local clock signal.

5. The integrated circuit according to claim 4, wherein, The integrated circuit is coupled to the host controller through the input / output communication module to receive the total number of the multiple integrated circuits in the multiphase power system and the serial number of the integrated circuit in the multiphase power system, and is configured to obtain the phase difference based on the total number.

6. The integrated circuit according to claim 3, wherein, The plurality of integrated circuits are connected in a daisy-chain structure in the multiphase power supply system, and the synchronous communication module is configured to be coupled to the input / output communication module, a receiving terminal and a transmitting terminal, wherein... When the integrated circuit is configured as a master device, the input / output communication module is enabled to receive the total number of the plurality of integrated circuits in the multiphase power system from the host controller, and the synchronization communication module is configured to transmit the phase difference and the reference clock signal to the next integrated circuit through the transmission terminal. When the integrated circuit is configured as a slave device, the input / output communication module is disabled, and the integrated circuit uses the synchronous communication module to receive the previous local clock signal from the previous integrated circuit via the receiving terminal, performs a shift calculation on the previous local clock according to the phase difference to generate the local clock signal of the integrated circuit, and uses the synchronous communication module to send the local clock signal to the next integrated circuit via the transmitting terminal.

7. The integrated circuit according to claim 4 or 6, wherein, The phase difference is the phase difference between the local clock signals of any two adjacent integrated circuits in the multiphase power supply system.

8. The integrated circuit according to claim 1, wherein, The first-stage circuit includes a charge pump that uses the clock signal to control the operation of multiple switches.

9. The power converter according to claim 8, wherein, The charge pump is a multiphase charge pump.

10. The power converter according to claim 8, wherein, The charge pump is a single-phase charge pump.

11. The power converter according to claim 1, wherein, The second stage circuit is a buck converter.

12. A multiphase power supply system, comprising: Multiple integrated circuits, wherein each integrated circuit includes: The first-stage input terminal is configured to receive the first-stage input voltage; The first-stage output terminal is configured to output a voltage lower than the first-stage input voltage. The first-stage output voltage, wherein the first-stage output terminal is configured to couple with the first-stage output terminal of other integrated circuits in the multiphase power supply system; The second-stage input terminal is configured to be coupled to the first-stage output terminal to receive the first-stage output voltage; The first-stage circuit is configured to receive the first-stage input voltage through the first-stage input terminal and divide the first-stage input voltage to generate the first-stage output voltage; The second-stage circuit is configured to receive the first-stage output voltage through the second-stage input terminal and adjust the first-stage output voltage to generate the second-stage output voltage. A synchronization communication module is configured to connect to the synchronization communication module of another integrated circuit among the plurality of integrated circuits and synchronize a clock signal with the other integrated circuit; and The input / output communication module is configured to communicate with the host controller.

13. The multiphase power supply system according to claim 12, wherein, Each integrated circuit also includes a clock module, which includes a clock generator and a clock phase shifter.

14. The multiphase power supply system according to claim 13, wherein, One of the plurality of integrated circuits is configured as a master device, and the remaining integrated circuits are configured as slave devices, wherein... The clock generator in the master device is enabled to generate a reference clock signal, and the clock phase shifter in the master device is disabled, wherein the reference clock signal serves as the local clock signal of the master device, and the operation of the switches in the first-stage circuit of the master device is controlled by the reference clock signal; and The clock generator in the slave device is disabled, and the clock phase shifter in the slave device is enabled to generate a local clock signal for the slave device, wherein the operation of the switches in the first-stage circuit of the slave device is controlled by the local clock signal.

15. The multiphase power supply system according to claim 14, wherein... The master device's synchronization communication module is configured to share the reference clock signal with the slave device's synchronization communication module; and The clock phase shifter of the slave device is configured to receive the reference clock signal of the master device and shift the reference clock signal according to the phase difference and the serial number of the slave device in the multiphase power system, thereby generating the local clock signal of the slave device.

16. The multiphase power supply system according to claim 15, wherein, Each integrated circuit is coupled to the host controller via the input / output communication module to receive the total number of integrated circuits in the multiphase power system and the serial number of each integrated circuit in the multiphase power system, and is configured to obtain the phase difference based on the total number.

17. The multiphase power supply system according to claim 14, wherein, The multiple integrated circuits are connected in a daisy-chain structure in the multiphase power supply system, and the synchronous communication module of each integrated circuit is coupled to a corresponding input / output communication module, a receiving terminal, and a transmitting terminal. The input / output communication module in the master device is enabled to receive the total number of integrated circuits in the multiphase power system from the host controller, and the synchronization communication module in the master device is configured to transmit the phase difference and the reference clock signal to the next integrated circuit through the transmission terminal. The input / output communication module in each device is disabled, and each slave device is configured to: receive a previous local clock signal from the previous integrated circuit via the receiving terminal using the synchronous communication module, generate the slave device's local clock signal by shifting the previous local clock according to the phase difference, and transmit the local clock signal to the next integrated circuit via the transmitting terminal using the synchronous communication module.

18. The multiphase power supply system according to claim 15 or 17, wherein, The phase difference is the phase difference between the local clock signals of any two adjacent integrated circuits in the multiphase power supply system.

19. The multiphase power supply system according to claim 16, wherein, The multiphase power system also includes a host controller.

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