High-efficiency BUCK converter

Abstract

This invention relates to a high-efficiency BUCK converter. It includes: a BUCK topology unit; and a converter controller that acquires the load state of the connected BUCK topology unit. When the BUCK topology unit operates in heavy-load high-frequency CCM mode, the converter controller configures the BUCK topology unit to operate at a first switching frequency; when the BUCK topology unit operates in light-load low-frequency DCM mode, the converter controller configures the BUCK topology unit to operate at a second switching frequency; when the operating mode of the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, the converter controller synchronously provides a ramp compensation current to perform subharmonic compensation. This invention can improve the operating efficiency of the BUCK converter and also improve the stability and reliability of its operation.

Description

Technical Field

[0001] This invention relates to a BUCK converter, and more particularly to a high-efficiency BUCK converter. Background Technology

[0002] BUCK converters are widely used in DC-DC switching power supply chips, providing efficient voltage conversion for portable electronic devices, automotive electronics, industrial control, and communication equipment. Therefore, efficiency is a key factor in measuring the performance of DC-DC converters.

[0003] For synchronous BUCK converters, losses mainly consist of conduction losses (PR) caused by the on-resistance of the power switches and the DC equivalent series resistance of the inductors, switching losses (PS) related to the switching frequency, and static losses (PQ) of the control circuit. The efficiency can be expressed as:

[0004] in, For efficiency, For conduction loss, For switching losses, For static losses, This refers to the input power.

[0005] Under light load conditions, switching losses are the main factor limiting the efficiency of the BUCK converter, and these losses are primarily determined by the switching frequency. However, under heavy load conditions, conduction losses dominate, limiting the efficiency of the BUCK converter. Since peak current-mode control has advantages such as fast response and built-in cycle-by-cycle current limiting, it is currently the most commonly used method to control the operation of BUCK converters.

[0006] Furthermore, for BUCK converters with peak current mode control, the PWM modulation frequency is fixed during the design. However, when the BUCK converter operates in continuous conduction mode and the duty cycle exceeds 50%, there will be an inherent open-loop instability phenomenon, which will cause oscillation problems caused by subharmonics, thus affecting the stability and reliability of the BUCK converter.

[0007] In summary, for BUCK converters using peak current mode control, improving the efficiency and operational stability of the BUCK converter is a key technical issue that needs to be addressed. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a high-efficiency BUCK converter, which can improve the working efficiency of the BUCK converter and improve the stability and reliability of the BUCK converter.

[0009] According to the technical solution provided by the present invention, a high-efficiency BUCK converter is provided, the BUCK converter comprising: The BUCK topology unit is used to perform synchronous rectified voltage conversion. The converter controller acquires the load status of the connected BUCK topology unit, configures the operating mode of the BUCK topology unit based on the load status, and configures the switching frequency of the BUCK topology unit in the corresponding operating mode based on the peak current mode control method, so as to configure the duty cycle of the BUCK topology unit in each operating mode. The operating modes of the BUCK topology unit include heavy-load high-frequency CCM mode or light-load low-frequency DCM mode. When the BUCK topology unit operates in heavy-load high-frequency CCM mode, the converter controller configures the BUCK topology unit to operate at the first switching frequency. When the BUCK topology unit operates in light-load low-frequency DCM mode, the converter controller configures the BUCK topology unit to operate at a second switching frequency, and the second switching frequency is lower than the first switching frequency. When the operating mode of the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, the converter controller synchronously provides ramp compensation current to use the ramp compensation current for subharmonic compensation. When the BUCK topology unit switches from heavy-load high-frequency CCM mode to light-load low-frequency DCM mode, the converter controller synchronously shuts off the ramp compensation current to reduce power consumption after entering the light-load low-frequency DCM mode.

[0010] The conversion controller includes a drive signal generation circuit, a voltage and current loop, and an adjustable frequency oscillator, wherein... Based on the load state of the BUCK topology unit, the drive signal generation circuit generates a corresponding operating mode indication signal. Based on the operating mode indication signal, the adjustable frequency oscillator generates a corresponding clock signal and loads the generated clock signal into the drive signal generation circuit as the set signal for the switching cycle of the BUCK topology unit in the corresponding operating mode. When the operating mode indicator signal indicates that the BUCK topology unit is operating in the heavy-load high-frequency CCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the first switching frequency, and the voltage and current loop generates a ramp compensation current adapted to the clock signal. When the operating mode indication signal indicates that the BUCK topology unit is operating in the light-load low-frequency DCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the second switching frequency, and the voltage and current loop is controlled to stop providing ramp compensation current based at least on the operating mode indication signal. The voltage and current loop is adapted to the BUCK topology unit and generates a PWM modulation signal as a reset signal for the switching cycle based on the load state of the BUCK topology unit. When generating the PWM modulation signal, the slope compensation circuit is used to perform subharmonic compensation. Based on the clock signal, PWM modulation signal, and load state of the BUCK topology unit, the drive signal generation circuit generates a set of drive control signals corresponding to the operating mode of the BUCK topology unit, wherein... The drive control signal includes at least one high-side drive signal and at least one low-side drive signal that is complementary to the high-side drive signal, and there is a dead time between the high-side drive signal and the low-side drive signal, so as to drive the working state of the BUCK topology unit based on the drive control signal.

[0011] The adjustable frequency oscillator includes an oscillation charging and discharging circuit, a hysteresis comparator circuit, and an oscillation latch circuit, wherein... The oscillation charging and discharging node of the oscillation charging and discharging circuit is adapted and connected to the hysteresis comparator circuit. When the node voltage of the oscillating charge / discharge node rises to the second threshold voltage of the hysteresis comparison, the hysteresis comparison circuit drives the oscillating latch circuit to output a high-level clock signal, and at the same time drives the oscillating latch circuit to output an effective discharge control signal. Based on an effective discharge control signal, the oscillation charging and discharging circuit is controlled to be in a discharge state, so that the voltage of the oscillation charging and discharging node drops. When the voltage of the oscillation charging and discharging node drops to the first threshold voltage of the hysteresis comparison, the hysteresis comparison circuit drives the oscillation latch circuit to output a low-level clock signal, and at the same time drives the oscillation latch circuit to output an invalid discharge control signal, so that the oscillation charging and discharging circuit re-enters the charging state. When the operating mode indication signal indicates that the BUCK topology unit is operating in the heavy-load high-frequency CCM mode, the charging and discharging slope of the oscillation charging and discharging circuit is configured based on the operating mode indication signal so that the oscillation frequency of the clock signal output by the oscillation latch circuit is the first switching frequency. When the operating mode indication signal indicates that the BUCK topology unit is operating in the light-load low-frequency DCM mode, the charging and discharging slope of the oscillation charging and discharging circuit is configured based on the operating mode indication signal so that the oscillation frequency of the clock signal output by the oscillation latch circuit is the second switching frequency.

[0012] The drive signal generation circuit includes a main RS flip-flop, a mode switching circuit, a zero-crossing detection circuit, and a signal generation and processing circuit, wherein... The set terminal of the master RS ​​flip-flop receives the clock signal, the reset terminal of the master RS ​​flip-flop receives the PWM modulation signal, and the Q terminal of the master RS ​​flip-flop is connected to the signal generation and processing circuit to load the master trigger signal into the signal generation and processing circuit. The zero-crossing state of the inductor current of the BUCK topology unit is detected by a zero-crossing detection circuit to generate a zero-crossing detection state signal characterizing the load state of the BUCK topology unit, and the zero-crossing detection state signal is sent to the mode switching circuit and the signal generation and processing circuit. Based on the zero-crossing detection state signal, the mode switching circuit generates an operating mode indication signal and sends the generated operating mode indication signal to the signal generation and processing circuit and the adjustable frequency oscillator. When generating the operating mode indication signal, at least the low-side drive signal generated by the signal generation and processing circuit and the zero-crossing detection status signal of at least two switching cycles are used. When there is a valid zero-crossing detection status signal for two consecutive switching cycles, the mode switching circuit generates a valid operating mode indication signal to indicate that the BUCK topology unit is currently operating in light-load low-frequency DCM mode; otherwise, it indicates that the BUCK topology unit is currently operating in heavy-load high-frequency CCM mode. Based on the zero-crossing detection state signal and the main trigger signal, the signal generation and processing circuit generates the corresponding drive control signal.

[0013] The mode switching circuit includes a zero-crossing detection latch circuit and an indication signal generation circuit adapted and connected to the zero-crossing detection latch circuit, wherein... Under the action of the low-side drive signal, the zero-crossing detection latch circuit latches the zero-crossing detection status signal for two consecutive switching cycles; The zero-crossing detection latch circuit latches the zero-crossing detection status signal for two consecutive switching cycles, and the indicator signal generation circuit generates a corresponding operating mode indicator signal, wherein... When the zero-crossing detection status signal is valid for two consecutive switching cycles, the indicator signal generation circuit generates a valid operating mode indicator signal. When the zero-crossing detection status signal is invalid for two consecutive switching cycles, the indicator signal generation circuit generates an invalid operating mode indicator signal. When the zero-crossing detection status signals of two switching cycles are inconsistent, the operating mode indication signal remains unchanged.

[0014] The mode switching circuit also includes a ramp compensation pre-enable control circuit, wherein... Based on the operating mode indication signal and the zero-crossing detection latch circuit latching the zero-crossing detection signal for two consecutive switching cycles, the slope compensation pre-enable control circuit generates the slope compensation pre-enable control signal, wherein... When the operating mode indicator signal is active and the zero-crossing detection circuit detects for the first time that the inductor current has not crossed zero in one switching cycle, the slope compensation pre-enable control circuit generates an active slope compensation pre-enable control signal. Based on an effective slope compensation pre-enable control signal, the voltage and current loop is controlled to synchronously provide slope compensation current.

[0015] The voltage and current loop includes a voltage loop unit, a current loop unit, and a main comparator, wherein... The voltage loop unit includes a voltage error amplifier, which amplifies the error voltage between the working sampling voltage and the voltage loop reference voltage to generate an error voltage signal, and then loads the error voltage signal onto the negative terminal of the main comparator. The current loop unit includes a current sampling ramp compensation circuit, wherein the current sampling ramp compensation circuit includes a current sampling circuit and a ramp compensation circuit. Based on the high-side drive signal and the operating mode indication signal, a current sampling circuit is configured to sample the inductor current when the BUCK topology unit is working, so as to generate an inductor current sampling signal. When the operating mode indicator signal is active, the ramp compensation current output by the ramp compensation circuit is turned off, so as to generate a current detection signal based on the inductor current sampling signal. When the operating mode indicator signal is invalid, the ramp compensation circuit is controlled to provide the corresponding ramp compensation current based on the clock signal of the adjustable frequency oscillator and the operating mode indicator signal, and a current detection signal is generated based on the ramp compensation current and the inductor current sampling signal. The current detection signal is applied to the positive terminal of the main comparator, and the output terminal of the main comparator is connected to the drive signal generation circuit to send a PWM modulation signal to the drive signal generation circuit.

[0016] The BUCK topology unit includes a switching transistor network, an output inductor adapted and connected to the switching transistor network, and an output capacitor adapted and connected to the output inductor. The switching network includes two switching assemblies connected in parallel. Each switching assembly includes a high-side power transistor and a low-side power transistor that is adapted and connected to the high-side power transistor. At one end of the output inductor, the high-side power transistors and low-side power transistors within each switching transistor assembly are adapted and connected to form a topology reference node. The other end of the output inductor is connected to one end of the output capacitor to form a load connection node, and the other end of the output capacitor is grounded. When the BUCK topology network operates in heavy-load high-frequency CCM mode, the two switching transistor components within the switching transistor network operate in parallel. When the BUCK topology network operates in light-load low-frequency DCM mode, one of the switching transistor components in the switching transistor network is selected to operate. When configuring any switching transistor assembly to operate, the following are included: When the topology reference node is in the charging phase, the high-side power transistor is turned on by the high-side drive signal, while the low-side power transistor belonging to the same switching transistor component is in the off state. When the topology reference node is in the discharge phase, the high-side power transistor is turned off, and the low-side power transistor belonging to the same switching transistor assembly is turned on through the low-side drive signal.

[0017] The current sampling circuit is adapted to the topology reference node and samples the current flowing through the output inductor during the charging phase. The current sampling circuit includes a sampling transistor group, a node voltage transfer circuit, and a current mirror compensation output circuit, wherein... The sampling tube group consists of at least two sampling tubes connected in parallel. At least one high-side power transistor is turned on by driving the high-side drive signal, and the node voltage transfer circuit is also driven by the high-side drive signal to transfer the voltage of the topology reference node to the two sampling transistors. When the BUCK topology network operates in high-frequency heavy-load CCM mode, the two sampling transistors are turned on based on the operating mode indication signal, and the operating voltage of the two sampling transistors is exactly the same as the corresponding operating voltage of the two high-side power transistors, so as to generate charging sampling current using the two turned sampling transistors. The current mirror compensation output circuit is connected to the slope compensation circuit. The charging sampling current is mirrored to the current mirror compensation output circuit and superimposed with the slope compensation circuit to generate a current detection signal. When the BUCK topology network operates in light-load low-frequency DCM mode, only one sampling tube in the sampling tube group is configured to be turned on based on the operating mode indication signal, and the operating voltage of the sampling tube is the same as that of the high-side power tube in the on state, so as to generate a charging sampling current using the sampling tube. The charging sampling current is mirrored to the current mirror compensation output circuit, and the inductor current sampling signal is output through the current mirror compensation output circuit. During the discharge phase of the topology reference node, the node voltage transfer circuit provides a static bias current and applies the static bias current to the sampling transistor group and the current mirror compensation output circuit based on the high-side drive signal to maintain the node voltage transfer circuit, the sampling transistor group and the current mirror compensation output circuit in the working state.

[0018] The slope compensation circuit includes a slope voltage circuit, a slope current generation circuit, and a slope current mirror path, wherein... When the operating mode indicator signal is invalid, including: During the low-level range of the clock signal, the ramp voltage circuit charges the ramp voltage node to generate a ramp reference voltage at the ramp voltage node, and applies the ramp reference voltage to the ramp current generation circuit. During the high-level range of the clock signal, the ramp voltage node is discharged to pull down the ramp reference voltage of the ramp voltage node and apply the ramp reference voltage to the ramp current generation circuit. Based on the ramp reference voltage, the ramp current generation circuit generates a ramp compensation current, and the ramp compensation current is superimposed on the current sampling circuit through the ramp current mirror path to generate a current detection signal based on the ramp compensation current and the inductor current sampling signal. When the operating mode indicator signal is valid, it includes: The voltage of the ramp voltage node is clamped to zero potential based on the operating mode indication signal, and the current path of the ramp current mirror path is turned off based on the high-side drive signal to shut down the ramp compensation current output by the ramp compensation circuit.

[0019] Advantages of this invention: The operating modes of the BUCK topology unit include heavy-load high-frequency CCM mode or light-load low-frequency DCM mode. When the BUCK topology unit operates in heavy-load high-frequency CCM mode, the converter controller configures the BUCK topology unit to operate at a first switching frequency. When the BUCK topology unit operates in light-load low-frequency DCM mode, the converter controller configures the BUCK topology unit to operate at a second switching frequency, and the second switching frequency is lower than the first switching frequency. When the operating mode of the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, the converter controller synchronously provides a ramp compensation current to perform subharmonic compensation. When the operating mode of the BUCK topology unit switches from heavy-load high-frequency CCM mode to light-load low-frequency DCM mode, the converter controller synchronously shuts off the ramp compensation current to reduce power consumption after entering the light-load low-frequency DCM mode, thereby improving the operating efficiency of the BUCK converter and enhancing the stability and reliability of the BUCK converter operation. Attached Figure Description

[0020] Figure 1 This is a circuit block diagram of one embodiment of the BUCK converter of the present invention.

[0021] Figure 2 This is a circuit schematic diagram of one embodiment of the zero-crossing detection latch circuit of the present invention.

[0022] Figure 3 This is a circuit schematic diagram of one embodiment of the indicator signal generation circuit of the present invention.

[0023] Figure 4 This is a circuit diagram of one embodiment of the slope compensation pre-enabled control circuit of the present invention.

[0024] Figure 5 This is a circuit schematic diagram of one embodiment of the adjustable frequency oscillator of the present invention.

[0025] Figure 6 This is a circuit diagram of one embodiment of the current sampling slope compensation circuit of the present invention. Detailed Implementation

[0026] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0027] To improve the efficiency, stability, and reliability of the BUCK converter, this invention provides a high-efficiency BUCK converter, specifically, the BUCK converter includes: The BUCK topology unit is used to perform synchronous rectified voltage conversion. The converter controller acquires the load status of the connected BUCK topology unit, configures the operating mode of the BUCK topology unit based on the load status, and configures the switching frequency of the BUCK topology unit in the corresponding operating mode based on the peak current mode control method, so as to configure the duty cycle of the BUCK topology unit in each operating mode. The operating modes of the BUCK topology unit include heavy-load high-frequency CCM mode or light-load low-frequency DCM mode. When the BUCK topology unit operates in heavy-load high-frequency CCM mode, the converter controller configures the BUCK topology unit to operate at the first switching frequency. When the BUCK topology unit operates in light-load low-frequency DCM mode, the converter controller configures the BUCK topology unit to operate at a second switching frequency, and the second switching frequency is lower than the first switching frequency. When the operating mode of the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, the converter controller synchronously provides ramp compensation current to use the ramp compensation current for subharmonic compensation. When the BUCK topology unit switches from heavy-load high-frequency CCM mode to light-load low-frequency DCM mode, the converter controller synchronously shuts off the ramp compensation current to reduce power consumption after entering the light-load low-frequency DCM mode.

[0028] Similar to existing technologies, the BUCK converter of the present invention may include a BUCK topology unit and a conversion controller. The BUCK topology unit can realize synchronous rectification and provide the required conversion voltage to the load. The BUCK topology unit can adopt a commonly used form. The BUCK topology unit will be described in detail below.

[0029] Furthermore, depending on the load connected to the BUCK topology unit, the BUCK topology unit can operate in different modes. For example, the BUCK topology unit can operate in heavy-load high-frequency CCM (Continuous Conduction Mode) mode or light-load low-frequency DCM (Discontinuous Conduction Mode) mode. Specifically, when the BUCK topology unit operates in heavy-load high-frequency CCM mode, it indicates that the load current is large (heavy load), and the inductor current is always greater than zero throughout the entire switching cycle and will not drop to zero. When the BUCK topology unit operates in light-load low-frequency DCM mode, it indicates that when the load current is very small (light load), the inductor current will drop to zero in each switching cycle and remain at zero for a period of time (discontinuous current).

[0030] In order to adapt to different load conditions, after determining the load condition of the BUCK topology unit, the operating mode of the BUCK topology unit should be configured. In one embodiment of the present invention, after configuring the operating mode of the BUCK topology unit, the switching frequency of the BUCK topology unit in the corresponding operating mode can be configured based on the peak current mode control method, thereby configuring the operating duty cycle of the BUCK topology unit in each operating mode. The correspondence between the switching frequency and the operating duty cycle is consistent with the prior art, and will not be described in detail here.

[0031] Compared to the fixed clock frequency operation method in the prior art, in one embodiment of the present invention, when the BUCK topology unit is configured to operate in heavy-load high-frequency CCM mode, the converter controller should configure the BUCK topology unit to operate at the first switching frequency. When the BUCK topology unit is configured to operate in light-load low-frequency DCM mode, the converter controller should configure the BUCK topology unit to operate at the second switching frequency. The first switching frequency is greater than the second switching frequency, thereby enabling the BUCK topology unit to operate at a higher switching frequency in heavy-load high-frequency CCM mode, which can reduce the size of inductors and capacitors and optimize dynamic response; while the BUCK topology unit operates at a lower switching frequency in light-load low-frequency DCM mode, which can reduce switching losses and improve light-load efficiency.

[0032] Similar to existing technologies, when the BUCK topology operates in heavy-load high-frequency CCM mode with a duty cycle greater than 50%, the disturbance is amplified cycle by cycle, causing alternating changes in the inductor current waveform, i.e., subharmonic oscillation, which severely affects system stability. In peak current control mode and light-load low-frequency DCM mode, the inductor current starts from zero in each switching cycle, eliminating the cycle-by-cycle propagation of disturbances and thus preventing subharmonic oscillations.

[0033] To avoid stability issues caused by subharmonic oscillations, in one embodiment of the present invention, when the operating mode of the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, the converter controller synchronously provides a ramp compensation current. This ramp compensation current is used for subharmonic compensation, preventing instability caused by small disturbances introduced in the heavy-load high-frequency CCM mode. Of course, the converter controller still needs to provide ramp compensation current during the operation of the heavy-load high-frequency CCM mode; that is, ramp compensation current is required both during the switching process and during operation in the heavy-load high-frequency CCM mode. Furthermore, when the operating mode of the BUCK topology unit switches from heavy-load high-frequency CCM mode to light-load low-frequency DCM mode, the converter controller synchronously shuts off the ramp compensation current to reduce power consumption after entering the light-load low-frequency DCM mode.

[0034] In one embodiment of the present invention, the BUCK topology unit includes a switching transistor network, an output inductor adapted and connected to the switching transistor network, and an output capacitor adapted and connected to the output inductor, wherein, The switching network includes two switching assemblies connected in parallel. Each switching assembly includes a high-side power transistor and a low-side power transistor that is adapted and connected to the high-side power transistor. At one end of the output inductor, the high-side power transistors and low-side power transistors within each switching transistor assembly are adapted and connected to form a topology reference node. The other end of the output inductor is connected to one end of the output capacitor to form a load connection node, and the other end of the output capacitor is grounded.

[0035] Figure 1 The figure shows an embodiment of the BUCK converter of the present invention. In the figure, L0 is the output inductor and C0 is the output capacitor. Figure 1 The figure illustrates one embodiment of a switching network. In this embodiment, PMOS transistor PM0 and NMOS transistor NM0 form one switching component, and PMOS transistor PM1 and NMOS transistor MN1 form another switching component. In this configuration, the BUCK topology unit can perform synchronous rectification voltage conversion. PMOS transistors PM0 and PM1 are both high-side power transistors, and NMOS transistors NM0 and NM1 are both low-side power transistors. Specifically, the source terminals of PMOS transistors PM0 and PM1 are connected to the power supply V. IN The connections are as follows: the drain terminal of PMOS transistor PM0 is connected to the drain terminal of NMOS transistor NM0 and the first terminal of the output inductor; the drain terminal of PMOS transistor PM1 is connected to the drain terminal of NMOS transistor NM1 and the first terminal of the output inductor; and the source terminals of both NMOS transistor NM0 and NMOS transistor NM1 are grounded. Figure 1 In this context, SW is the topology reference node formed by the connection.

[0036] Furthermore, the node formed by the interconnection of the output inductor and the output capacitor can be a load connection node, which can be connected to a load. In other words, the load connection node can serve as the output terminal of the BUCK converter of this invention. Figure 1 V in OUT This refers to the transformed voltage output through the load connection node. Therefore, it can be seen that when the BUCK converter of this invention is working, it transforms the power supply V... IN Converted to transformed voltage V OUT And provide it to the load.

[0037] In one embodiment of the present invention, the conversion controller includes a drive signal generation circuit, a voltage-current loop, and an adjustable frequency oscillator, wherein, Based on the load state of the BUCK topology unit, the drive signal generation circuit generates a corresponding operating mode indication signal. Based on the operating mode indication signal, the adjustable frequency oscillator generates a corresponding clock signal and loads the generated clock signal into the drive signal generation circuit as the set signal for the switching cycle of the BUCK topology unit in the corresponding operating mode. When the operating mode indicator signal indicates that the BUCK topology unit is operating in the heavy-load high-frequency CCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the first switching frequency, and the voltage and current loop generates a ramp compensation current adapted to the clock signal. When the operating mode indication signal indicates that the BUCK topology unit is operating in the light-load low-frequency DCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the second switching frequency, and the voltage and current loop is controlled to stop providing ramp compensation current based at least on the operating mode indication signal. The voltage and current loop is adapted to the BUCK topology unit and generates a PWM modulation signal as a reset signal for the switching cycle based on the load state of the BUCK topology unit. When generating the PWM modulation signal, the slope compensation circuit is used to perform subharmonic compensation. Based on the clock signal, PWM modulation signal, and load state of the BUCK topology unit, the drive signal generation circuit generates a set of drive control signals corresponding to the operating mode of the BUCK topology unit, wherein... The drive control signal includes at least one high-side drive signal and at least one low-side drive signal that is complementary to the high-side drive signal, and there is a dead time between the high-side drive signal and the low-side drive signal, so as to drive the working state of the BUCK topology unit based on the drive control signal.

[0038] In practical implementation, a drive control signal can be generated through a drive signal generation circuit, and a frequency-adjustable clock signal can be generated through an adjustable frequency oscillator. The generated clock signal is then loaded into the drive signal generation circuit as a switch cycle set signal. To meet peak current mode control requirements, the converter controller should also include a voltage-current loop. In addition, the voltage-current loop can provide slope compensation current. The details of the drive signal generation circuit, the adjustable frequency oscillator, and the voltage-current loop will be explained below.

[0039] It should be understood that the drive control signals generated by the drive signal generation circuit should be compatible with the BUCK topology unit, such as the switching transistor network within the BUCK topology unit. Figure 1 When the switching transistor network includes two switching transistor components, the drive control signal generated by the drive signal generation circuit should include at least one high-side drive signal and one low-side drive signal, and the high-side drive signal and the low-side drive signal should be complementary. The high-side drive signal can drive the high-side power transistor to turn on, and the low-side drive signal can drive the low-side power transistor to turn on. Figure 1 In the embodiment shown, PMOS transistors PM0 and PM1 can be turned on by a high-side drive signal, and NMOS transistors NM0 and NM1 can be turned on by a low-side drive signal. Since the high-side power transistors and low-side power transistors are generally different types of MOS transistors, and the low-side drive signal and the high-side drive signal are complementary, the high-side power transistors and low-side power transistors in the same switching transistor assembly will not be turned on simultaneously.

[0040] Specifically, when PMOS transistors PM0 and / or PM1 are turned on, while NMOS transistors NM0 and NM1 remain off, the topology reference node can be charged, which also means the output inductor can be charged; when PMOS transistors PM0 and PM1 are both turned off, while NMOS transistors NM0 and / or NM1 are turned on, the topology reference node can be discharged.

[0041] Figure 1In the diagram, PCTRL is the high-side drive signal, and NCTRL is the low-side drive signal. All other diagrams represent the same meaning; please refer to this explanation. In practical implementation, PMOS transistors PM0 and PM1 can be simultaneously driven to conduct using the same high-side drive signal, and NMOS transistors NM0 and NM1 can be simultaneously driven to conduct using the same low-side drive signal. Of course, when the switching network includes two switching components, each switching component can be controlled by different high-side and low-side drive signals. When the two switching components in the switching network operate synchronously, PMOS transistors PM0 and PM1 should be driven synchronously under two high-side drive signals. For details on synchronous turn-on or synchronous turn-off, and the corresponding synchronous operation of NMOS transistors NM0 and NM1, please refer to this explanation. It is understandable that when two switching transistor components in a switching transistor network are not working synchronously, if only one switching transistor component is selected to work, the corresponding high-side drive signal and low-side drive signal can drive the corresponding high-side power transistor and low-side power transistor respectively, based on the specific requirements of meeting the charging and discharging needs of the topology reference node.

[0042] In one embodiment of the present invention, when the BUCK topology network operates in heavy-load high-frequency CCM mode, the two switching transistor components in the switching transistor network operate in parallel. When the BUCK topology network operates in light-load low-frequency DCM mode, one of the switching transistor components in the switching transistor network is selected to operate. When configuring any switching transistor assembly to operate, the following are included: When the topology reference node is in the charging phase, the high-side power transistor is turned on by the high-side drive signal, while the low-side power transistor belonging to the same switching transistor component is in the off state. When the topology reference node is in the discharge phase, the high-side power transistor is turned off, and the low-side power transistor belonging to the same switching transistor assembly is turned on through the low-side drive signal.

[0043] Specifically, when two switching transistors in a switching network operate in parallel, it means that the two switching transistors operate synchronously, such as two high-side power transistors being turned on simultaneously. When only one switching transistor in the switching network is selected to operate, that is, when the two switching transistors are configured to operate asynchronously, such as one of the two high-side power transistors being turned on, in specific implementations, when the two switching transistors are driven by different high-side drive signals and low-side drive signals respectively, the state of the drive control signal generated by the drive signal generation circuit can be controlled to select one switching transistor to operate; or, a selection circuit can be used to select the desired switching transistor to operate, depending on whether the desired switching transistor can be selected. The method of selecting synchronous or asynchronous operation of the switching transistors can be selected as needed, and will not be elaborated here.

[0044] It should be understood that when the BUCK topology network operates in heavy-load high-frequency CCM mode, the two switching transistor components in the switching transistor network operate in parallel, which can reduce the equivalent on-resistance and reduce conduction loss; while when the BUCK topology network operates in light-load low-frequency DCM mode, only one switching transistor component in the switching transistor network operates, which can reduce gate drive loss by reducing the number of operating switching transistor components.

[0045] For each switching transistor component, when the high-side power transistor is turned on and the low-side power transistor alternately completes one turn-on operation, the topology reference node experiences one charging phase and one discharging phase. This constitutes one switching cycle for each switching transistor component. It should be understood that for the switching transistor network, during multiple switching cycles, a pulsed square wave can be generated at the topology reference node. This pulsed square wave, in conjunction with the output inductor and output capacitor, can produce a transformed voltage.

[0046] When the drive signal generation circuit generates the aforementioned drive control signal, it should use the clock signal generated by the adjustable frequency oscillator as the switch cycle set signal and the PWM modulation signal generated by the voltage and current loop as the switch cycle reset signal. The frequency of the high-side drive signal should be consistent with the frequency of the clock signal. During operation, when the clock signal used as the switch cycle set signal is at its rising edge, the high-side drive signal can drive the high-side power transistor to turn on. When the PWM modulation signal used as the switch cycle reset signal is valid (e.g., the PWM modulation signal is at a high level), the high-side power transistor is turned off, and the low-side power transistor is turned on.

[0047] To correspond with the operating mode of the BUCK topology, the adjustable frequency oscillator should generate a clock signal based on the operating mode indication signal of the drive signal generation circuit. Specifically, when the operating mode indication signal indicates that the BUCK topology is operating in heavy-load high-frequency CCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator should be the first switching frequency. Furthermore, a voltage-current loop should be configured to generate a ramp compensation current adapted to the clock signal. The adaptation of the ramp compensation circuit to the clock signal will be explained in detail below with reference to the figures. In one embodiment of the present invention, when the operating mode indication signal indicates that the BUCK topology is operating in light-load low-frequency DCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the second switching frequency, and the voltage-current loop is controlled to stop providing ramp compensation current at least based on the operating mode indication signal.

[0048] In one embodiment of the present invention, the drive signal generation circuit includes a main RS flip-flop, a mode switching circuit, a zero-crossing detection circuit, and a signal generation and processing circuit, wherein, The set terminal of the master RS ​​flip-flop receives the clock signal, the reset terminal of the master RS ​​flip-flop receives the PWM modulation signal, and the Q terminal of the master RS ​​flip-flop is connected to the signal generation and processing circuit to load the master trigger signal into the signal generation and processing circuit. The zero-crossing state of the inductor current of the BUCK topology unit is detected by a zero-crossing detection circuit to generate a zero-crossing detection state signal characterizing the load state of the BUCK topology unit, and the zero-crossing detection state signal is sent to the mode switching circuit and the signal generation and processing circuit. Based on the zero-crossing detection state signal, the mode switching circuit generates an operating mode indication signal and sends the generated operating mode indication signal to the signal generation and processing circuit and the adjustable frequency oscillator. When generating the operating mode indication signal, at least the low-side drive signal generated by the signal generation and processing circuit and the zero-crossing detection status signal of at least two switching cycles are used. When there is a valid zero-crossing detection status signal for two consecutive switching cycles, the mode switching circuit generates a valid operating mode indication signal to indicate that the BUCK topology unit is currently operating in light-load low-frequency DCM mode; otherwise, it indicates that the BUCK topology unit is currently operating in heavy-load high-frequency DCM mode. Based on the zero-crossing detection state signal and the main trigger signal, the signal generation and processing circuit generates the corresponding drive control signal.

[0049] Figure 1 In the embodiment shown, RS1 is the master RS ​​flip-flop, ZCD is the zero-crossing detection circuit, mode switching is the mode switching circuit, LOGIC is the signal generation and processing circuit, and the output of the adjustable frequency oscillator is connected to the set terminal of the master RS ​​flip-flop to load the clock signal onto the master flip-flop; the reset terminal of the master RS ​​flip-flop receives the PWM modulation signal. The Q terminal of the master RS ​​flip-flop, the zero-crossing detection circuit, and the mode switching circuit are all connected to the signal generation and processing circuit, which can generate drive control signals. That is, the signal generation and processing circuit should be adapted and connected to the switching transistor network.

[0050] Similar to existing technologies, a zero-crossing detection circuit can be used to detect the zero-crossing state of the inductor current within a BUCK topology cell. The load state of the BUCK topology cell is then determined based on the detected zero-crossing state. The zero-crossing detection circuit can adopt commonly used forms, specifically designed to detect the zero-crossing state of the inductor current. After detecting the zero-crossing state of the inductor current, a zero-crossing detection status signal is generated. This signal is typically a digital signal. Figure 2 V in ZCD This is the zero-crossing detection status signal. Generally, when the zero-crossing detection circuit detects that the inductor current has crossed zero, the zero-crossing detection status signal is high; otherwise, the zero-crossing detection status signal is low.

[0051] Depend on Figure 1 It is understood that the zero-crossing detection status signal should be sent to both the mode switching circuit and the signal generation and processing circuit simultaneously. Subsequently, based on the zero-crossing detection status signal, the mode switching circuit can generate an operating mode indication signal. Of course, the generated operating mode indication signal must also be loaded into the signal generation and processing circuit. As explained above, the operating mode indication signal must also be sent to the adjustable frequency oscillator. It is also understood that when the signal generation and processing circuit generates the drive control signal, it should at least be based on the zero-crossing detection status signal, the operating mode signal, and the main trigger signal generated from the Q input of the main RS flip-flop.

[0052] In one embodiment of the present invention, the mode switching circuit includes a zero-crossing detection latch circuit and an indication signal generation circuit adapted and connected to the zero-crossing detection latch circuit, wherein, Under the action of the low-side drive signal, the zero-crossing detection latch circuit latches the zero-crossing detection status signal for two consecutive switching cycles; The zero-crossing detection latch circuit latches the zero-crossing detection status signal for two consecutive switching cycles, and the indicator signal generation circuit generates a corresponding operating mode indicator signal, wherein... When the zero-crossing detection status signal is valid for two consecutive switching cycles, the indicator signal generation circuit generates a valid operating mode indicator signal. When the zero-crossing detection status signal is invalid for two consecutive switching cycles, the indicator signal generation circuit generates an invalid operating mode indicator signal. When the zero-crossing detection status signals of two switching cycles are inconsistent, the operating mode indication signal remains unchanged.

[0053] Figure 2 The figure illustrates one embodiment of a zero-crossing detection latch circuit. The zero-crossing detection latch circuit may include D flip-flops DK1 and D flip-flops DK2. The D terminal of D flip-flop DK1 receives the zero-crossing detection state signal. The Q terminal of D flip-flop DK1 is connected to the D terminal of D flip-flop DK2. The Q terminal of D flip-flop DK2 is connected to an indicator signal generation circuit. Furthermore, the CLK terminals of both D flip-flops DK1 and DK2 are connected to a low-side drive signal. When the low-side drive signal is high, the zero-crossing detection state signal can be latched. That is, during the period when the low-side power transistor is on, D flip-flops DK1 and DK2 latch the zero-crossing detection state signal, ensuring accurate sampling of the inductor current zero-crossing state once per switching cycle.

[0054] Figure 3The figure illustrates one embodiment of an indicator signal generation circuit. The indicator signal generation circuit may include a NAND gate NAND1, an OR gate OR1, and an RS flip-flop RS2. The output of the NAND gate NAND1 is connected to the reset terminal of the RS flip-flop RS2, and the output of the OR gate OR1 is connected to the set terminal of the RS flip-flop RS2. The operating mode indicator signal is output through the Q terminal of the RS flip-flop RS2, i.e., MODE is the operating mode indicator signal. In addition, Q0 is the zero-crossing detection state signal generated by the D flip-flop DK2, and Q1 is the zero-crossing detection state signal generated by the D flip-flop DK1.

[0055] Specifically, when Q1Q0 is 11, it indicates that the inductor current has crossed zero for two consecutive switching cycles, meaning the BUCK breakout unit is operating in light-load, low-frequency DCM mode. In this case, the operating mode indication signal output from the Q terminal of RS flip-flop RS2 is high. When Q1Q0 = 00, it indicates that the inductor current has not crossed zero for two consecutive switching cycles, meaning the inductor current has entered a continuous conduction state. In this case, the operating mode indication signal output from the Q terminal of RS flip-flop RS2 is low. When Q1Q0 is 01 or 10, it indicates that the current inductor current crossing zero is an intermediate transition state. RS flip-flop RS2 maintains the previous operating mode indication signal unchanged, ensuring that the operating mode will not switch erroneously due to transient disturbances.

[0056] As can be seen from the above description, when the operating mode indicator signal is in an active state, the operating mode indicator signal is at a high level; when the operating mode indicator signal is in an inactive state, the operating mode indicator signal is at a low level. That is, when the operating mode indicator signal is at a high level, it indicates that the BUCK topology unit is currently operating in the light-load low-frequency DCM mode; otherwise, it indicates that the BUCK topology unit is currently operating in the heavy-load high-frequency CCM mode.

[0057] In one embodiment of the present invention, the adjustable frequency oscillator includes an oscillation charging and discharging circuit, a hysteresis comparison circuit, and an oscillation latch circuit, wherein, The oscillation charging and discharging node of the oscillation charging and discharging circuit is adapted and connected to the hysteresis comparator circuit. When the node voltage of the oscillating charge / discharge node rises to the second threshold voltage of the hysteresis comparison, the hysteresis comparison circuit drives the oscillating latch circuit to output a high-level clock signal, and at the same time drives the oscillating latch circuit to output an effective discharge control signal. Based on an effective discharge control signal, the oscillation charging and discharging circuit is controlled to be in a discharge state, so that the voltage of the oscillation charging and discharging node drops. When the voltage of the oscillation charging and discharging node drops to the first threshold voltage of the hysteresis comparison, the hysteresis comparison circuit drives the oscillation latch circuit to output a low-level clock signal, and at the same time drives the oscillation latch circuit to output an invalid discharge control signal, so that the oscillation charging and discharging circuit re-enters the charging state. When the operating mode indication signal indicates that the BUCK topology unit is operating in the heavy-load high-frequency CCM mode, the charging and discharging slope of the oscillation charging and discharging circuit is configured based on the operating mode indication signal so that the oscillation frequency of the clock signal output by the oscillation latch circuit is the first switching frequency. When the operating mode indication signal indicates that the BUCK topology unit is operating in the light-load low-frequency DCM mode, the charging and discharging slope of the oscillation charging and discharging circuit is configured based on the operating mode indication signal so that the oscillation frequency of the clock signal output by the oscillation latch circuit is the second switching frequency.

[0058] Figure 5 The diagram illustrates a circuit schematic of an embodiment of an adjustable frequency oscillator. The oscillation charging and discharging circuit may include PMOS transistors PM2 and PM3. The gate terminals of both PMOS transistors PM2 and PM3 are connected to a bias voltage VBP1. The source terminal of PMOS transistor PM2 is connected to the source terminal of PMOS transistor PM3. The drain terminal of PMOS transistor PM2 is connected to the drain terminal of NMOS transistor NM4, the drain terminal of NMOS transistor NM2, the gate terminal of NMOS transistor NM2, and the gate terminal of NMOS transistor NM3. The drain terminal of PMOS transistor PM3 is connected to the drain terminal of NMOS transistor NM3, one end of capacitor C1, and one end of switch TG0 to form an oscillating charge-discharge node. Figure 5 In the diagram, A represents the oscillation charging and discharging node. The other end of switch TG0 is connected to one end of capacitor C2. The source terminals of NMOS transistors NM4, NM2, and NM3, the other end of capacitor C1, and the other end of capacitor C2 are all grounded. The operating state of switch TG0 is controlled by the operating mode indicator signal. When the operating mode indicator signal is high, switch TG0 is turned on, and capacitor C2 is connected in parallel with capacitor C1. When the operating mode indicator signal is low, switch TG0 is turned off, and capacitor C2 cannot be connected for operation.

[0059] For the bias voltage VBP1, it should be ensured that PMOS transistors PM2 and PM3 are stably biased in the saturation region, that is, satisfying the following: ,in, These are the gate-source voltages of PMOS transistors PM2 and PM3. The drain-source voltages of PMOS transistors PM2 and PM3 under saturation conditions are given. Therefore, the bias voltage VP1 acts on PMOS transistors M2 and M3, determining the magnitude of the current I0, which can indirectly determine the oscillation frequency.

[0060] Figure 5In this circuit, the hysteresis comparator circuit may include comparator COMP2 and comparator COMP3. The non-inverting input of comparator COMP2 and the inverting input of comparator COMP3 are both connected to the oscillation charging / discharging node. The inverting input of comparator COMP2 is connected to V... REF / 2, the non-inverting input of comparator COMP3 is connected to V. REF At this point, the first threshold voltage for hysteresis comparison should be V. REF / 2, the second threshold voltage for hysteresis comparison is V REF This allows for a dual-threshold hysteresis comparison window, causing the voltage at the oscillating charge / discharge node to oscillate between VREF / 2 and VREF. After passing through comparators COMP2 and COMP3, a stable periodic square wave signal, V, can be generated. REF This is the reference voltage used in the voltage-current loop.

[0061] Figure 5 The oscillation latch circuit includes NAND gates NAND2 and NAND gates NAND3. One end of NAND gate NAND2 is connected to the output of comparator COMP2, and the other input of NAND gate NAND2 is connected to the output of NAND gate NAND3 and the input of inverter INV3. The output of NAND gate NAND2 is connected to one input of NAND gate NAND3 and the input of inverter INV2, and the other input of NAND gate NAND3 is connected to the output of comparator COMP3. A clock signal can be output through the output of inverter INV2, and a discharge control signal can be output through inverter INV3. The discharge control signal output by inverter INV3 is applied to the gate of NMOS transistor NM4. Figure 5 In this context, CLK represents the clock signal, and V_DIS represents the discharge control signal.

[0062] In practical implementation, PMOS transistors PM2 and PM3 can form a current mirror with a current mirror ratio of 2:1. If the reference charging current provided by the PM3 branch is I0, then the mirror current provided by the PM2 branch is 2I0. NMOS transistor NM4 acts as a discharge enable switch. When the discharge control signal is high, NMOS transistor NM4 is turned on. At this time, the gates of the current mirror transistors NM2 and NM3 can be forcibly pulled to ground, causing NMOS transistors NM2 and NM3 to be turned off. The reference charging current provided by the PM3 branch can then charge the oscillation charge-discharge node. Specifically, the reference charging current I0 charges the capacitor array at the oscillation charge-discharge node, and the voltage of the oscillation charge-discharge node rises linearly with a slope of I0 / CTOTAL, where CTOTAL is the capacitance value of the capacitor array at the oscillation charge-discharge node.

[0063] When the voltage of the oscillating charge / discharge node rises to VREF, the output of comparator COMP3 flips, causing the discharge control signal to go low. This turns off NMOS transistor NM4 and enables NMOS transistors NM2 and NM3. Setting the width-to-length ratio of the corresponding conductive channels of NMOS transistors NM2 and NM3 to 1:8, the current flowing through NMOS transistor NM2 is 2I0, and the discharge current flowing through NMOS transistor NM3 is 16I0. For the oscillating charge / discharge node, according to Kirchhoff's laws, after subtracting the reference charging current I0 continuously injected by PMOS transistor PM3, the net discharge current of the oscillating charge / discharge node is 15I0. That is, the voltage of the oscillating charge / discharge node decreases linearly with a slope of 15I0 / CTOTAL.

[0064] When the voltage of the oscillating charge / discharge node drops to VREF / 2, the output of comparator COMP2 flips, the clock signal goes low, and the discharge control signal flips high, recharging the oscillating charge / discharge node; when the voltage of the oscillating charge / discharge node rises again to V... REF At this time, the clock signal flips to a high level again, and the discharge control signal flips to a low level again, re-entering the discharge phase of the oscillation charging and discharging node. Repeating the above charging and discharging process generates a stable periodic square wave signal, which is the clock signal. According to the principle of charge balance, the sum of the charging time and the discharging time constitutes a complete oscillation period. Through derivation, the oscillation frequency of the clock signal is approximately f = 15I0 / (8*V). REF *CTOTAL).

[0065] To achieve dual-mode frequency switching, a programmable capacitor array is set at the oscillation charging / discharging node. Capacitor C1 is a fixed base capacitor, while capacitor C2 is connected via switch TG0. In light-load, low-frequency DCM mode, because the operating mode indicator signal (MODE) is high, switch TG0 is turned on, and capacitor C2 is connected to the circuit. At this time, the total capacitance CTOTAL (C1+C2) is large, and the oscillation frequency is low. In heavy-load, high-frequency CCM mode, because the operating mode indicator signal is low, switch TG0 is turned off, and capacitor C2 is disconnected. At this time, the total capacitance CTOTAL (C1) is small, and the oscillation frequency is high. Therefore, the oscillation frequency of the clock signal and the switching frequency of the BUCK topology unit can be dynamically adjusted according to the load condition to optimize the conversion efficiency across the entire load range. It can be understood that when the clock signal is obtained using the above method, the frequency can be flexibly adjusted by controlling the connection state of capacitor C2. The circuit structure is simple and requires no additional frequency adjustment loop.

[0066] In one embodiment of the present invention, the voltage-current loop includes a voltage loop unit, a current loop unit, and a main comparator, wherein, The voltage loop unit includes a voltage error amplifier, which amplifies the error voltage between the working sampling voltage and the voltage loop reference voltage to generate an error voltage signal, and then loads the error voltage signal onto the negative terminal of the main comparator. The current loop unit includes a current sampling ramp compensation circuit, wherein the current sampling ramp compensation circuit includes a current sampling circuit and a ramp compensation circuit. Based on the high-side drive signal and the operating mode indication signal, a current sampling circuit is configured to sample the inductor current when the BUCK topology unit is working, so as to generate an inductor current sampling signal. When the operating mode indicator signal is active, the ramp compensation current output by the ramp compensation circuit is turned off, so as to generate a current detection signal based on the inductor current sampling signal. When the operating mode indicator signal is invalid, the ramp compensation circuit is controlled to provide the corresponding ramp compensation current based on the clock signal of the adjustable frequency oscillator and the operating mode indicator signal, and a current detection signal is generated based on the ramp compensation current and the inductor current sampling signal. The current detection signal is applied to the positive terminal of the main comparator, and the output terminal of the main comparator is connected to the drive signal generation circuit to send a PWM modulation signal to the drive signal generation circuit.

[0067] Figure 1 The diagram illustrates one embodiment of the voltage-current loop. In the diagram, EA1 is a voltage error amplifier. The non-inverting input of the voltage error amplifier is connected to the voltage loop reference voltage. The non-inverting input of the voltage error amplifier is connected to one end of resistor R10 and one end of resistor R20. The other end of resistor R20 is grounded. One end of resistor R10 is connected to the load connection node. That is, the transformation voltage V can be achieved through resistors R10 and R20. OUT Sampling is performed to obtain the working sampling voltage. Figure 1 In the middle, V FB The sampling voltage is Vc, the error voltage signal is Vc, and COMP1 is the main comparator. Furthermore, Figure 1 The figure also illustrates one embodiment of a current loop unit. The current loop unit may include a current sampling ramp compensation circuit connected to node SW and to the positive terminal of the master comparator. The output terminal of the master comparator is connected to the set terminal of the master RS ​​flip-flop.

[0068] In specific implementation, the current sampling ramp compensation circuit may include a current sampling circuit and a ramp compensation circuit. The current sampling circuit can sample the inductor current flowing through the output inductor. Specifically, when sampling the inductor current, it should be based on the high-side drive signal and the operating mode indication signal.

[0069] As explained above, when the operating mode indicator signal is high, it indicates that the BUCK topology unit is operating in light-load, low-frequency DCM mode. In this case, the ramp compensation current output by the ramp compensation circuit should be turned off, and only the inductor current sampling signal should be used to generate the current detection signal. When the operating mode indicator signal is inactive, it indicates that the BUCK topology unit is operating in heavy-load, high-frequency CCM mode. In this case, the ramp compensation circuit should be controlled to output the ramp compensation current, and the ramp compensation current should be superimposed with the inductor current sampling signal to generate the corresponding circuit detection signal.

[0070] It should be noted that when the voltage and current loops are formed by the voltage loop unit, the current loop unit, and the main comparator, the principle of generating the PWM modulation signal using the peak current mode control method is the same as that of the existing technology. For the specific principle of generating the PWM modulation signal, please refer to the description of the existing BUCK converter. That is, the main comparator compares the current detection signal with the error voltage signal to load the PWM modulation signal to the set terminal of the main RS flip-flop, which is consistent with the existing technology and will not be elaborated here.

[0071] In one embodiment of the present invention, the current sampling circuit is adapted to the topology reference node and samples the current flowing through the output inductor during the charging phase. The current sampling circuit includes a sampling transistor group, a node voltage transfer circuit, and a current mirror compensation output circuit, wherein... The sampling tube group consists of at least two sampling tubes connected in parallel. At least one high-side power transistor is turned on by driving the high-side drive signal, and the node voltage transfer circuit is also driven by the high-side drive signal to transfer the voltage of the topology reference node to the two sampling transistors. When the BUCK topology network operates in high-frequency heavy-load CCM mode, the two sampling transistors are turned on based on the operating mode indication signal, and the operating voltage of the two sampling transistors is exactly the same as the corresponding operating voltage of the two high-side power transistors, so as to generate charging sampling current using the two turned sampling transistors. The current mirror compensation output circuit is connected to the slope compensation circuit. The charging sampling current is mirrored to the current mirror compensation output circuit and superimposed with the slope compensation circuit to generate a current detection signal. When the BUCK topology network operates in light-load low-frequency DCM mode, only one sampling tube in the sampling tube group is configured to be turned on based on the operating mode indication signal, and the operating voltage of the sampling tube is the same as that of the high-side power tube in the on state, so as to generate a charging sampling current using the sampling tube. The charging sampling current is mirrored to the current mirror compensation output circuit, and the inductor current sampling signal is output through the current mirror compensation output circuit. During the discharge phase of the topology reference node, the node voltage transfer circuit provides a static bias current and applies the static bias current to the sampling transistor group and the current mirror compensation output circuit based on the high-side drive signal to maintain the node voltage transfer circuit, the sampling transistor group and the current mirror compensation output circuit in the working state.

[0072] because Figure 1 The switching transistor network includes two switching transistor assemblies. Therefore, the sampling tube group of the present invention should include at least two sampling tubes. Generally, the sampling tube group preferably contains two sampling tubes, which are connected in parallel. Figure 6 The circuit in [1] is the circuit sampling circuit, and PMOS transistors PM6 and PM7 are two parallel sampling transistors.

[0073] Since the BUCK converter uses peak current-mode control, current sampling only needs to be performed during the charging phase of the output inductor. In one embodiment of the invention, this is achieved by detecting the voltage V at the SW node during the output inductor charging phase. SW Converting this signal into a corresponding current signal yields the corresponding inductor current sampling signal. It should be noted that during peak current mode control, the detected peak value of the inductor current is not the average value or the complete waveform. Furthermore, during the freewheeling phase, the inductor current decreases linearly, and the current during this phase does not participate in the comparison of the peak current or the generation of the PWM modulation signal. Therefore, in one embodiment of this invention, sampling can be performed only during the charging phase, and not during the freewheeling phase, thereby reducing the power consumption of the current sampling circuit.

[0074] In order to accurately sample the inductor current during the charging phase, the operation of the node voltage transfer circuit should be controlled by the high-side drive signal. Specifically, when at least one high-side power transistor is driven to turn on by the high-side drive signal, the node voltage transfer circuit is also driven to work by the high-side drive signal to transfer the voltage of the topology reference node to the two sampling transistors. The case of driving one or two high-side power transistors to turn on by the high-side drive signal can be referred to the corresponding description above, which will not be repeated here.

[0075] Figure 6 The diagram illustrates one embodiment of a node voltage transfer circuit, which includes a PMOS transistor PM4. The gate of the PMOS transistor PM4 receives a high-side drive signal, and the source of the PMOS transistor PM4 is connected to a topology reference node to transfer the voltage V of the topology reference node. SW The load is applied to the source terminal of PMOS transistor PM4. The drain terminal of PMOS transistor PM4 is connected to the inverting input of operational amplifier A0, the drain electrode of PMOS transistor PM5, and the drain terminal of NMOS transistor NM6. The source terminals of NMOS transistor NM5 and NMOS transistor NM6 are grounded. The gate of NMOS transistor NM6 is connected to the gate of NMOS transistor NM5, the drain of NMOS transistor NM5, and current source I1. The source terminals of PMOS transistors PM5, PM6, and PM7 are all connected to power supply V. IN The non-inverting input of operational amplifier A0 is connected to the drain terminals of PMOS transistors PM6 and PM7. The gate terminal of PMOS transistor PM6 is grounded, while the gate terminal of PMOS transistor PM7 is connected to the operating mode indicator signal.

[0076] Figure 6 The figure also shows an embodiment of a current mirror compensation output circuit. The current mirror compensation output circuit may include NMOS transistors NM7 and NMOS transistors NM8. The gate terminals of NMOS transistors NM7 and NM8 are connected to the output terminal of operational amplifier A0. The drain terminal of NMOS transistor NM7 is connected to the non-inverting input of operational amplifier A0, the drain terminal of PMOS transistor PM6, and the drain terminal of PMOS transistor PM7. The source terminals of NMOS transistors NM7 and NMOS transistor NM8 are grounded.

[0077] The drain terminal of NMOS transistor NM8 is connected to the drain terminal of PMOS transistor PM8, the gate terminal of PMOS transistor PM8, and the gate terminal of PMOS transistor PM9. The source terminals of PMOS transistors PM8 and PM9 are both connected to the transformation voltage V. OUT The drain terminal of PMOS transistor PM9 is connected to one end of resistor R0 and the slope compensation circuit to obtain the inductor current sampling signal through the drain terminal of PMOS transistor PM9. It should be noted that when a voltage conversion voltage V is used... OUT During power supply, due to the transformation voltage V OUT The lower voltage, which powers the internal analog circuitry, reduces the static power consumption of the BUCK converter in this invention.

[0078] In practice, the gate terminal of PMOS transistor PM5 receives the inverted signal of the high drive signal, that is... Figure 6 In this context, ~PCTRL represents the inverted signal of the high-side drive signal. When the high-side drive signal is low, ~PCTRL is high. In this case, the high-side drive signal can drive the corresponding high-side power transistor to turn on, thus charging the output inductor, and the inductor current i... L The linear increase occurs. Simultaneously, PMOS transistor PM4 is turned on, while PMOS transistor PM5 is turned off.

[0079] For ease of explanation, PMOS transistor PM0 is used as the main switch and PMOS transistor PM1 as the auxiliary switch. In this case, when the high-side drive signal is low, at least PMOS transistor PM0 is turned on. Since both PMOS transistors PM0 and PM4 operate in the linear region, the drain-source voltage drop is negligible. Figure 6 The voltage at node B is pulled up to the voltage V at node SW. SW Utilizing the "virtual short" characteristic of operational amplifier A0, the voltage at node F is clamped to match the voltage at node B, i.e.: V B =V F =V SW Specifically, node B is the node formed by connecting the inverting input of operational amplifier A0 to the drain terminals of PMOS transistors PM4, PM5, and NMOS transistor NM6. Similarly, it can be determined that... Figure 6 The formation of node F in the middle.

[0080] In practical implementation, PMOS transistor PM6 is used as the main sampling transistor. Since the gate of PMOS transistor PM6 is grounded, it remains in the on state during operation. The width-to-length ratio of the conductive channel of PMOS transistor PM6 is generally much smaller than that of the corresponding conductive channel of the high-side power transistor. For example, the ratio of the width-to-length ratio of the conductive channel of PMOS transistor PM0 to that of PMOS transistor PM6 is N:1.

[0081] When the voltage at node F and the voltage at node B are both V SW Then, for PMOS transistor PM0, the source of PMOS transistor PM0 is connected to the power supply VIN, the gate of PMOS transistor PM0 is connected to a low level, and the source of PMOS transistor PM0 is connected to a voltage V. SW For PMOS transistor PM6, the source terminal of PMOS transistor PM6 is connected to the power supply VIN, the gate terminal of PMOS transistor PM6 is grounded, and the drain terminal of PMOS transistor PM6 is connected to the voltage V. SW Therefore, it can be seen that PMOS transistor PM6 and PMOS transistor PM0 have exactly the same operating voltage. In this case, PMOS transistor PM6 can sample the current on PMOS transistor PM0. The same operating voltage conditions can be described here. When charging the output inductor, the inductor current i... L After sampling by PMOS transistor PM6, the current flowing out from the drain terminal of PMOS transistor PM6 can be obtained.

[0082] It is understandable that by using PMOS transistor PM7 as the sampling transistor, the number of switching transistors can be adapted to different operating conditions during current sampling, such as light-load low-frequency DCM mode and heavy-load high-frequency CCM mode. For example, in light-load low-frequency DCM mode, PMOS transistor PM7 is off because the operating mode indicator signal is high, while in heavy-load high-frequency CCM mode, PMOS transistor PM7 is on because the operating mode indicator signal is low. In this case, PMOS transistor PM7 can be used to sample the current of PMOS transistor PM1, which acts as the high-side power transistor. Specifically, PMOS transistor PM7 and PMOS transistor PM6 have the same dimensions. When PMOS transistor PM7 is on, referring to the explanation of the same operating voltage mentioned above, PMOS transistor PM7 and PMOS transistor PM1 have the same operating voltage, and PMOS transistor PM7 can be used to sample the current of PMOS transistor PM1.

[0083] In light-load, low-frequency DCM mode, only PMOS transistor PM0 is selected as the high-side power transistor. In this case, the current flowing through PMOS transistor PM0 is the inductor current i. L By sampling the current across PMOS transistor PM0 using PMOS transistor PM6, the current flowing out from the drain terminal of PMOS transistor PM6 can be obtained, which is... Figure 6 In the case of I2, the current I3 should be i. L / N.

[0084] In heavy-load high-frequency CCM mode, since both PMOS transistors PM0 and PM1 act as high-side power transistors, each carries half of the inductor current. Therefore, when current sampling of PMOS transistor PM0 is performed using PMOS transistor PM6, and current sampling of PMOS transistor PM1 is performed using PMOS transistor PM7, the current flowing from the drain terminals of PMOS transistors PM6 and PM7 is i. L / (2N), at this point, we can obtain Figure 6 The current I3 in the middle should be i L / N, which shows that the charging sampling current is the same regardless of whether it is in the light load low frequency DCM mode or the heavy load high frequency DCM mode.

[0085] In practical implementation, NMOS transistors NM7 and NM8 can form a current mirror, and the width-to-length ratio of the corresponding conductive channels of NMOS transistors NM7 and NM8 can be 8:1. Therefore, based on the current mirror relationship, we can obtain... Figure 6 In the context of I4, specifically, I4 = i L / 8N. Generally, PMOS transistors PM8 and PM9 should be of the same size. PMOS transistors PM8 and PM9 can form a current mirror. Therefore, after mirroring, the current I4 can be reflected to obtain the current I5 flowing from the drain of PMOS transistor PM9. In this case, I5 = I4. It can be understood that current I5 is the inductor current sampling signal. Since the drain of PMOS transistor PM9 is grounded through resistor R0, the inductor current sampling signal can be converted into a voltage. Figure 6 VSENSE in this context refers to the current detection signal, meaning that the current detection signal in this invention is a voltage signal.

[0086] When the high-side drive signal is high, both the high-side power transistor and PMOS transistor PM4 are off, while PMOS transistor PM5 is on. When NMOS transistors NM0 and / or NM1 are on, the charging of the output inductor is in the freewheeling phase. Due to the "virtual short" characteristic of operational amplifier A0, the voltage at node B is still equal to the voltage at node F. At this time, the current source I1 acts as the bias current. Since NMOS transistors NM5 and NM6 form a 1:1 current mirror, the bias current output by current source I1, after being mirrored by the current mirror, yields current I2, and current I2 = I1.

[0087] When PMOS transistors PM5 and PM6 are power transistors of the same size, after PM5 is turned on, both PMOS transistors PM5 and PM6 have the same operating voltage, resulting in a current I2 flowing out of the drain of PMOS transistor PM6. Generally, the bias current I1 is relatively small, and therefore, the current flowing out of the drain of PMOS transistor PM6 is also relatively small. Thus, as explained above, the current flowing out of the drain of PMOS transistor PM9 is fixed at a small bias current, such as I1 / 8. In practical implementation, the bias current I1 ensures the normal operating point of operational amplifier A0, thereby maintaining the stable operation of the entire current sampling circuit during the non-sampling phase and preparing for the rapid start-up of the next switching cycle.

[0088] As can be seen from the above description, the current sampling circuit of the present invention has a simple structure, uses a very small sampling tube to replicate the current, and the current mirror compensation output circuit can output a voltage-type current detection signal. In the non-sampling stage, the current sampling circuit consumes only a small static bias current, resulting in low power consumption. By sampling through the sampling tube and replicating the current through the current mirror to obtain the final inductor current sampling signal, the current sampling circuit is not affected by changes in PVT (Process, Voltage, Temperature), resulting in high sampling accuracy.

[0089] In one embodiment of the present invention, the slope compensation circuit includes a slope voltage circuit, a slope current generation circuit, and a slope current mirror path, wherein, When the operating mode indicator signal is invalid, including: During the low-level range of the clock signal, the ramp voltage circuit charges the ramp voltage node to generate a ramp reference voltage at the ramp voltage node, and applies the ramp reference voltage to the ramp current generation circuit. During the high-level range of the clock signal, the ramp voltage node is discharged to pull down the ramp reference voltage of the ramp voltage node and apply the ramp reference voltage to the ramp current generation circuit. Based on the ramp reference voltage, the ramp current generation circuit generates a ramp compensation current, and the ramp compensation current is superimposed on the current sampling circuit through the ramp current mirror path to generate a current detection signal based on the ramp compensation current and the inductor current sampling signal. When the operating mode indicator signal is valid, it includes: The voltage of the ramp voltage node is clamped to zero potential based on the operating mode indication signal, and the current path of the ramp current mirror path is turned off based on the high-side drive signal to shut down the ramp compensation current output by the ramp compensation circuit.

[0090] Figure 6 [2] in the diagram refers to the slope compensation circuit. Figure 6 In this circuit, the ramp voltage circuit may include a PMOS transistor NM10 and an NMOS transistor NM9. The gate of the NMOS transistor NM10 is connected to the SLOPE_OFF signal, and the gate of the NMOS transistor NM9 is connected to the clock signal. The drain terminals of the NMOS transistors NM10 and NM9 are connected to the current source I6, one end of the capacitor C3, and the gate of the PMOS transistor PM10. The drain terminal of the PMOS transistor PM10, the other end of the capacitor C3, the source terminal of the NMOS transistor NM9, and the source terminal of the NMOS transistor NM10 are all grounded.

[0091] Figure 6 The figure also shows an embodiment of the ramp current generation circuit. The ramp current generation circuit includes an operational amplifier A1 and a resistor R1. The inverting terminal of the operational amplifier A1 is connected to the current source I7 and the source terminal of the PMOS transistor PM10. The non-inverting terminal of the operational amplifier A1 is connected to one end of the resistor R1 and the ramp current mirror path. The other end of the resistor R1 is connected to...

[0092] Figure 6In the diagram, the ramp current mirror path includes PMOS transistors PM11, PM12, PM13, and PM14. The output of operational amplifier A1 is connected to the gate of PMOS transistor PM11 and the drain of PMOS transistor PM13. The drain of PMOS transistor PM11 is connected to the non-inverting input of operational amplifier A1 and resistor R1. The sources of PMOS transistors PM11, PM14, and PM12 are all connected to the transformation voltage V. OUT The gate of PMOS transistor PM14 is connected to the EN_SLOPE signal. The drain of PMOS transistor PM14 is connected to the gate of PMOS transistor PM12 and the source of PMOS transistor PM13. The gate of PMOS transistor PM13 is connected to the EN_SLOPE signal. The drain of PMOS transistor PM12 is connected to the drain of PMOS transistor PM9 and resistor R0 so that the slope compensation current and the inductor current sampling signal can be superimposed.

[0093] Figure 6 CLK in the diagram refers to the clock signal. As explained above, the frequency of the clock signal is the same as the frequency of the high-side drive signal. When generating the slope compensation current, it should correspond to the low-level period of the clock signal. Therefore, the low-level pulse width of the clock signal essentially determines the maximum duty cycle limit, ensuring that the inductor current signal can obtain effective slope compensation in each switching cycle. The SLOPE_OFF signal is in phase with the operating mode indicator signal. The SLOPE_OFF signal can be obtained by buffering the operating mode indicator signal. The EN_SLOPE signal is the inverse of the EN_SLOPE signal. Specifically, by using two cascaded inverters to form a buffer to buffer the operating mode indicator signal, the SLOPE_OFF signal can be obtained, and the load capacity can be enhanced to meet subsequent drive requirements.

[0094] In addition, the ~EN_SLOPE signal and the EN_SLOPE signal can also be generated based on the operating mode indicator signal. For example, the EN_SLOPE signal can be generated by passing the operating mode indicator signal through an inverter, and the ~EN_SLOPE signal can be generated by passing the EN_SLOPE signal through another inverter. Of course, other methods can also be used to generate the required ~EN_SLOPE signal and EN_SLOPE signal based on the operating mode indicator signal.

[0095] Specifically, when the EN_SLOPE signal is low (heavy-load high-frequency CCM mode), ramp compensation is enabled, and ~EN_SLOPE is high; when EN_SLOPE is high (light-load low-frequency DCM mode), ramp compensation is disabled, and ~EN_SLOPE is low.

[0096] As explained above, the signal generation and processing circuit should include a buffer unit and a drive control signal generation unit. Based on the operating mode indication signal, the buffer unit can generate the aforementioned SLOPE_OFF, ~EN_SLOPE, and EN_SLOPE signals. Therefore, the form of the buffer unit should be such that it can generate the required SLOPE_OFF, ~EN_SLOPE, and EN_SLOPE signals. The drive control signal generation unit can adopt a commonly used form, specifically designed to generate the corresponding drive control signals based on the zero-crossing detection state signal and the main trigger signal.

[0097] for Figure 6 In the slope compensation circuit shown, when the clock signal is low, the NMOS transistor NM9 is turned off. At this time, the current I6 charges the capacitor C3, generating a linear voltage with a slope of I6 / C3. This voltage is applied to the gate of the PMOS transistor PM10, which can act as a source follower. Under the action of the current source I7 providing a fixed bias current I7, the source terminal voltage V at the source terminal of the PMOS transistor PM10 is... D Following the gate potential of the PMOS transistor PM7, the voltage V at node D is... D The slope remains at I6 / C3, where the voltage V at node D is... D This is the slope reference voltage.

[0098] Based on the characteristics of operational amplifiers, the voltage at the non-inverting input of an operational amplifier is equal to the voltage V. D , that is Figure 6 The voltage at node E is V. D At this time, a current I8 = V can be generated in resistor R1. D The slope of the current I8 is I6 / (R1*C3), and the current I8 here is the slope compensation current. PMOS transistors PM11 and PM12 form a 1:1 current mirror, so that the final slope compensation current I9 is ​​equal to the current I8, and the slope is also I6 / (R1*C3).

[0099] When the clock signal CLK is high, NMOS transistor NM9 is turned on, and capacitor C3 is quickly discharged to ground. At this time, the gate voltage of PMOS transistor PM10 is pulled to ground. Since the bias current I7 is constant, PMOS transistor PM10 is always turned on, and the voltage V... D The voltage is pulled down to a lower value, so the current I8 generated by the clamping of the operational amplifier A1 is also reduced to a lower quiescent value, ensuring that the ramp compensation current is reset to the initial level before the start of the next switching cycle, thus avoiding compensation accumulation.

[0100] To completely shut off the ramp compensation current in light-load, low-frequency DCM mode, an NMOS transistor NM10 is added. The gate voltage state is controlled by the SLOPE_OFF signal. As can be seen from the description of the SLOPE_OFF signal, in light-load, low-frequency DCM mode, the SLOPE_OFF signal is high, and the NMOS transistor NM10 is turned on. At this time, the voltage across capacitor C3 is clamped to zero, eliminating the invalid charging and discharging introduced by the continuous switching of NMOS transistor NM9 with the clock signal.

[0101] The conduction state of PMOS transistor PM13 is controlled by the EN_SLOPE signal, and the conduction state of PMOS transistor PM14 is controlled by the ~EN_SLOPE signal. Specifically, when the EN_SLOPE signal is low, PMOS transistor PM13 is turned on and PMOS transistor PM14 is turned off. At this time, the gate of PMOS transistor PM12 is normally biased, and a slope compensation current can be output from the drain terminal of PMOS transistor PM12. When the EN_SLOPE signal is high, PMOS transistor PM13 is turned off, and PMOS transistor PM14 is turned on. At this time, the gate of PMOS transistor PM12 is pulled to the conversion voltage V through the turned PMOS transistor PM14. OUT This allows PMOS transistor PM12 to be turned off, meaning that by turning on PMOS transistor PM14, the ramp compensation current output through PMOS transistor PM12 can be turned off.

[0102] In practice, an enable switch is set for operational amplifier A1. When operational amplifier A1 is enabled, its output terminal outputs normally. When operational amplifier A1 is disabled, its output terminal outputs a high level.

[0103] When the operating mode indicator signal indicates the effective state of the light-load low-frequency DCM mode, the SLOPE_OFF signal is high, driving the NMOS transistor NM10 to turn on. At this time, the voltage across capacitor C3 is pulled down to zero. Current sources I6 and I7 are grounded through capacitor C3, the voltage at node D is 0, operational amplifier A1 is turned off and outputs a high level. When the EN_SLOPE signal is high, PMOS transistor PM13 is turned off and turned on. At this time, PMOS transistor PM12 is turned off, and the output path of the ramp compensation current is turned off, thus shutting down the ramp compensation current output and achieving zero static power consumption.

[0104] When the operating mode indicator signal is in an invalid state representing heavy-load high-frequency CCM, the SLOPE_OFF signal is low, the NMOS transistor NM10 is in the off state, and the ramp compensation current output by the ramp compensation circuit is related to the clock signal. That is, the ramp compensation current can be output in the low level segment of the clock signal, while in the high level segment of the clock signal, the entire ramp generation circuit maintains low bias current operation.

[0105] Understandably, when the drain terminal of PMOS transistor PM12 is connected to PMOS transistor PM9 and resistor R0, resistors R1 and R0 should generally have the same resistance value. Therefore, when a slope compensation current exists, it can be superimposed on the inductor current sampling signal; otherwise, the inductor current detection signal is directly generated based on the inductor current sampling signal. In specific implementation, the slope of the slope compensation current is I6 / C3. Therefore, the output current of current source I6 and / or the capacitance value of capacitor C3 can be changed to obtain the required slope. The obtained slope should be designed to effectively compensate for subharmonics, that is, to avoid instability caused by subharmonic oscillations in heavy-load high-frequency CCM mode.

[0106] In peak current mode control, when the duty cycle exceeds 50%, small disturbances in the inductor current will be amplified cycle by cycle in subsequent cycles, i.e. This leads to subharmonic oscillations. Adding slope compensation is equivalent to superimposing a slope of [value missing] onto the current sampling signal. The slope voltage, the perturbation recursive relationship becomes When the slope of the ramp voltage satisfies hour, The disturbance decays periodically, and the system returns to stability. Here, the slope of the ramp compensation current is I6 / C3, and the slope of the compensation voltage superimposed on the sampling resistor R0 is I6·R0 / C3. By reasonably selecting the values ​​of the current source I6 and the capacitor C3, the compensation slope can meet the above stability conditions, thus effectively suppressing subharmonic oscillations.

[0107] In the above explanation, D represents the duty cycle of the output voltage conversion, and n represents the number of switching cycles. The deviation in the initial inductor current caused by the disturbance. This represents the deviation in inductor current after n switching cycles. The rising slope of the sampled voltage during the inductor charging phase; This represents the slope of the sample voltage decrease during the inductor discharge phase.

[0108] In one embodiment of the present invention, the mode switching circuit further includes a ramp compensation pre-enable control circuit, wherein, Based on the operating mode indication signal and the zero-crossing detection latch circuit latching the zero-crossing detection signal for two consecutive switching cycles, the slope compensation pre-enable control circuit generates the slope compensation pre-enable control signal, wherein... When the operating mode indicator signal is active and the zero-crossing detection circuit detects for the first time that the inductor current has not crossed zero in one switching cycle, the slope compensation pre-enable control circuit generates an active slope compensation pre-enable control signal. Based on an effective slope compensation pre-enable control signal, the voltage and current loop is controlled to synchronously provide slope compensation current.

[0109] Figure 4 An embodiment of the slope compensation pre-enable control circuit of the present invention is shown. The figure shows that the slope compensation pre-enable control circuit includes an inverter INV1, an AND gate AND1, and an OR gate OR2, wherein... The input of inverter INV1 is connected to the working mode indication signal. One end of AND gate AND1 is connected to the output of D flip-flop DK2, and the other end of AND gate AND1 is connected to the inverted signal output by D flip-flop DK1. The outputs of inverter INV1 and AND gate AND1 are both connected to the output of OR gate OR2. The EN_PRE output of OR gate OR2 is the ramp compensation pre-enable control signal.

[0110] Since the active operating mode signal is high, when the operating mode indicator signal is active, the inverter INV1 outputs a low level, and when the operating mode indicator signal is inactive, the inverter INV1 outputs a high level. When the zero-crossing detection circuit first detects that the inductor current has crossed zero in one switching cycle, as explained above, the signal Q0 output from the Q terminal of D flip-flop DK2 is high, while the signal Q1 output from the Q terminal of D flip-flop DK1 is low. At this time, the output from AND gate AND1 is high. Figure 4 As can be seen from the description here, the slope compensation pre-enable control signal is active high.

[0111] As explained above, the operation of operational amplifier A1 requires enable control. In one embodiment of the present invention, when the slope compensation pre-enable control signal is valid, current sources I6 and I7 and operational amplifier A1 are first enabled. Current sources I6 and I7, along with operational amplifier A1, establish the operating point, ensuring that the slope reference voltage at node D reaches a stable state before compensation is officially enabled. This guarantees that the correct compensation slope is output simultaneously with slope compensation being enabled. Specifically, enabling slope compensation here means that the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, i.e., the mode switching circuit receives an effective operating mode switching signal.

Claims

1. A high-efficiency BUCK converter, characterized in that, The BUCK converter includes: The BUCK topology unit is used to perform synchronous rectified voltage conversion. The converter controller acquires the load status of the connected BUCK topology unit, configures the operating mode of the BUCK topology unit based on the load status, and configures the switching frequency of the BUCK topology unit in the corresponding operating mode based on the peak current mode control method, so as to configure the duty cycle of the BUCK topology unit in each operating mode. The operating modes of the BUCK topology unit include heavy-load high-frequency CCM mode or light-load low-frequency DCM mode. When the BUCK topology unit operates in heavy-load high-frequency CCM mode, the converter controller configures the BUCK topology unit to operate at the first switching frequency. When the BUCK topology unit operates in light-load low-frequency DCM mode, the converter controller configures the BUCK topology unit to operate at a second switching frequency, and the second switching frequency is lower than the first switching frequency. When the operating mode of the BUCK topology unit switches from light-load low-frequency DCM mode to heavy-load high-frequency CCM mode, the converter controller synchronously provides ramp compensation current to use the ramp compensation current for subharmonic compensation. When the BUCK topology unit switches from heavy-load high-frequency CCM mode to light-load low-frequency DCM mode, the converter controller synchronously shuts off the ramp compensation current to reduce power consumption after entering the light-load low-frequency DCM mode.

2. The high-efficiency BUCK converter according to claim 1, characterized in that: The conversion controller includes a drive signal generation circuit, a voltage and current loop, and an adjustable frequency oscillator, wherein... Based on the load state of the BUCK topology unit, the drive signal generation circuit generates a corresponding operating mode indication signal. Based on the operating mode indication signal, the adjustable frequency oscillator generates a corresponding clock signal and loads the generated clock signal into the drive signal generation circuit as the set signal for the switching cycle of the BUCK topology unit in the corresponding operating mode. When the operating mode indicator signal indicates that the BUCK topology unit is operating in the heavy-load high-frequency CCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the first switching frequency, and the voltage and current loop generates a ramp compensation current adapted to the clock signal. When the operating mode indication signal indicates that the BUCK topology unit is operating in the light-load low-frequency DCM mode, the frequency of the clock signal generated by the adjustable frequency oscillator is the second switching frequency, and the voltage and current loop is controlled to stop providing ramp compensation current based at least on the operating mode indication signal. The voltage and current loop is adapted to the BUCK topology unit and generates a PWM modulation signal as a reset signal for the switching cycle based on the load state of the BUCK topology unit. When generating the PWM modulation signal, the slope compensation circuit is used to perform subharmonic compensation. Based on the clock signal, PWM modulation signal, and load state of the BUCK topology unit, the drive signal generation circuit generates a set of drive control signals corresponding to the operating mode of the BUCK topology unit, wherein... The drive control signal includes at least one high-side drive signal and at least one low-side drive signal that is complementary to the high-side drive signal, and there is a dead time between the high-side drive signal and the low-side drive signal, so as to drive the working state of the BUCK topology unit based on the drive control signal.

3. The high-efficiency BUCK converter according to claim 2, characterized in that: The adjustable frequency oscillator includes an oscillation charging and discharging circuit, a hysteresis comparator circuit, and an oscillation latch circuit, wherein... The oscillation charging and discharging node of the oscillation charging and discharging circuit is adapted and connected to the hysteresis comparator circuit. When the node voltage of the oscillating charge / discharge node rises to the second threshold voltage of the hysteresis comparison, the hysteresis comparison circuit drives the oscillating latch circuit to output a high-level clock signal, and at the same time drives the oscillating latch circuit to output an effective discharge control signal. Based on an effective discharge control signal, the oscillation charging and discharging circuit is controlled to be in a discharge state, so that the voltage of the oscillation charging and discharging node drops. When the voltage of the oscillation charging and discharging node drops to the first threshold voltage of the hysteresis comparison, the hysteresis comparison circuit drives the oscillation latch circuit to output a low-level clock signal, and at the same time drives the oscillation latch circuit to output an invalid discharge control signal, so that the oscillation charging and discharging circuit re-enters the charging state. When the operating mode indication signal indicates that the BUCK topology unit is operating in the heavy-load high-frequency CCM mode, the charging and discharging slope of the oscillation charging and discharging circuit is configured based on the operating mode indication signal so that the oscillation frequency of the clock signal output by the oscillation latch circuit is the first switching frequency. When the operating mode indication signal indicates that the BUCK topology unit is operating in the light-load low-frequency DCM mode, the charging and discharging slope of the oscillation charging and discharging circuit is configured based on the operating mode indication signal so that the oscillation frequency of the clock signal output by the oscillation latch circuit is the second switching frequency.

4. The high-efficiency BUCK converter according to claim 2, characterized in that: The drive signal generation circuit includes a main RS flip-flop, a mode switching circuit, a zero-crossing detection circuit, and a signal generation and processing circuit, wherein... The set terminal of the master RS ​​flip-flop receives the clock signal, the reset terminal of the master RS ​​flip-flop receives the PWM modulation signal, and the Q terminal of the master RS ​​flip-flop is connected to the signal generation and processing circuit to load the master trigger signal into the signal generation and processing circuit. The zero-crossing state of the inductor current of the BUCK topology unit is detected by a zero-crossing detection circuit to generate a zero-crossing detection state signal characterizing the load state of the BUCK topology unit, and the zero-crossing detection state signal is sent to the mode switching circuit and the signal generation and processing circuit. Based on the zero-crossing detection state signal, the mode switching circuit generates an operating mode indication signal and sends the generated operating mode indication signal to the signal generation and processing circuit and the adjustable frequency oscillator. When generating the operating mode indication signal, at least the low-side drive signal generated by the signal generation and processing circuit and the zero-crossing detection status signal of at least two switching cycles are used. When there is a valid zero-crossing detection status signal for two consecutive switching cycles, the mode switching circuit generates a valid operating mode indication signal to indicate that the BUCK topology unit is currently operating in light-load low-frequency DCM mode; otherwise, it indicates that the BUCK topology unit is currently operating in heavy-load high-frequency CCM mode. Based on the zero-crossing detection state signal and the main trigger signal, the signal generation and processing circuit generates the corresponding drive control signal.

5. The high-efficiency BUCK converter according to claim 4, characterized in that: The mode switching circuit includes a zero-crossing detection latch circuit and an indication signal generation circuit adapted and connected to the zero-crossing detection latch circuit, wherein... Under the action of the low-side drive signal, the zero-crossing detection latch circuit latches the zero-crossing detection status signal for two consecutive switching cycles; The zero-crossing detection latch circuit latches the zero-crossing detection status signal for two consecutive switching cycles, and the indicator signal generation circuit generates a corresponding operating mode indicator signal, wherein... When the zero-crossing detection status signal is valid for two consecutive switching cycles, the indicator signal generation circuit generates a valid operating mode indicator signal. When the zero-crossing detection status signal is invalid for two consecutive switching cycles, the indicator signal generation circuit generates an invalid operating mode indicator signal. When the zero-crossing detection status signals of two switching cycles are inconsistent, the operating mode indication signal remains unchanged.

6. The high-efficiency BUCK converter according to claim 4, characterized in that: The mode switching circuit also includes a ramp compensation pre-enable control circuit, wherein... Based on the operating mode indication signal and the zero-crossing detection latch circuit latching the zero-crossing detection signal for two consecutive switching cycles, the slope compensation pre-enable control circuit generates the slope compensation pre-enable control signal, wherein... When the operating mode indicator signal is active and the zero-crossing detection circuit detects for the first time that the inductor current has not crossed zero in one switching cycle, the slope compensation pre-enable control circuit generates an active slope compensation pre-enable control signal. Based on an effective slope compensation pre-enable control signal, the voltage and current loop is controlled to synchronously provide slope compensation current.

7. The high-efficiency BUCK converter according to any one of claims 2 to 6, characterized in that: The voltage and current loop includes a voltage loop unit, a current loop unit, and a main comparator, wherein... The voltage loop unit includes a voltage error amplifier, which amplifies the error voltage between the working sampling voltage and the voltage loop reference voltage to generate an error voltage signal, and then loads the error voltage signal onto the negative terminal of the main comparator. The current loop unit includes a current sampling ramp compensation circuit, wherein the current sampling ramp compensation circuit includes a current sampling circuit and a ramp compensation circuit. Based on the high-side drive signal and the operating mode indication signal, a current sampling circuit is configured to sample the inductor current when the BUCK topology unit is working, so as to generate an inductor current sampling signal. When the operating mode indicator signal is active, the ramp compensation current output by the ramp compensation circuit is turned off, so as to generate a current detection signal based on the inductor current sampling signal. When the operating mode indicator signal is invalid, the ramp compensation circuit is controlled to provide the corresponding ramp compensation current based on the clock signal of the adjustable frequency oscillator and the operating mode indicator signal, and a current detection signal is generated based on the ramp compensation current and the inductor current sampling signal. The current detection signal is applied to the positive terminal of the main comparator, and the output terminal of the main comparator is connected to the drive signal generation circuit to send a PWM modulation signal to the drive signal generation circuit.

8. The high-efficiency BUCK converter according to claim 7, characterized in that: The BUCK topology unit includes a switching transistor network, an output inductor adapted and connected to the switching transistor network, and an output capacitor adapted and connected to the output inductor. The switching network includes two switching assemblies connected in parallel. Each switching assembly includes a high-side power transistor and a low-side power transistor that is adapted and connected to the high-side power transistor. At one end of the output inductor, the high-side power transistors and low-side power transistors within each switching transistor assembly are adapted and connected to form a topology reference node. The other end of the output inductor is connected to one end of the output capacitor to form a load connection node, and the other end of the output capacitor is grounded. When the BUCK topology network operates in heavy-load high-frequency CCM mode, the two switching transistor components within the switching transistor network operate in parallel. When the BUCK topology network operates in light-load low-frequency DCM mode, one of the switching transistor components in the switching transistor network is selected to operate. When configuring any switching transistor assembly to operate, the following are included: When the topology reference node is in the charging phase, the high-side power transistor is turned on by the high-side drive signal, while the low-side power transistor belonging to the same switching transistor component is in the off state. When the topology reference node is in the discharge phase, the high-side power transistor is turned off, and the low-side power transistor belonging to the same switching transistor assembly is turned on through the low-side drive signal.

9. The high-efficiency BUCK converter according to claim 8, characterized in that: The current sampling circuit is adapted to the topology reference node and samples the current flowing through the output inductor during the charging phase. The current sampling circuit includes a sampling transistor group, a node voltage transfer circuit, and a current mirror compensation output circuit, wherein... The sampling tube group consists of at least two sampling tubes connected in parallel. At least one high-side power transistor is turned on by driving the high-side drive signal, and the node voltage transfer circuit is also driven by the high-side drive signal to transfer the voltage of the topology reference node to the two sampling transistors. When the BUCK topology network operates in high-frequency heavy-load CCM mode, the two sampling transistors are turned on based on the operating mode indication signal, and the operating voltage of the two sampling transistors is exactly the same as the corresponding operating voltage of the two high-side power transistors, so as to generate charging sampling current using the two turned sampling transistors. The current mirror compensation output circuit is connected to the slope compensation circuit. The charging sampling current is mirrored to the current mirror compensation output circuit and superimposed with the slope compensation circuit to generate a current detection signal. When the BUCK topology network operates in light-load low-frequency DCM mode, only one sampling tube in the sampling tube group is configured to be turned on based on the operating mode indication signal, and the operating voltage of the sampling tube is the same as that of the high-side power tube in the on state, so as to generate a charging sampling current using the sampling tube. The charging sampling current is mirrored to the current mirror compensation output circuit, and the inductor current sampling signal is output through the current mirror compensation output circuit. During the discharge phase of the topology reference node, the node voltage transfer circuit provides a static bias current and applies the static bias current to the sampling transistor group and the current mirror compensation output circuit based on the high-side drive signal to maintain the node voltage transfer circuit, the sampling transistor group and the current mirror compensation output circuit in the working state.

10. The high-efficiency BUCK converter according to claim 7, characterized in that: The slope compensation circuit includes a slope voltage circuit, a slope current generation circuit, and a slope current mirror path, wherein... When the operating mode indicator signal is invalid, including: During the low-level range of the clock signal, the ramp voltage circuit charges the ramp voltage node to generate a ramp reference voltage at the ramp voltage node, and applies the ramp reference voltage to the ramp current generation circuit. During the high-level range of the clock signal, the ramp voltage node is discharged to pull down the ramp reference voltage of the ramp voltage node and apply the ramp reference voltage to the ramp current generation circuit. Based on the ramp reference voltage, the ramp current generation circuit generates a ramp compensation current, and the ramp compensation current is superimposed on the current sampling circuit through the ramp current mirror path to generate a current detection signal based on the ramp compensation current and the inductor current sampling signal. When the operating mode indicator signal is valid, it includes: The voltage of the ramp voltage node is clamped to zero potential based on the operating mode indication signal, and the current path of the ramp current mirror path is turned off based on the high-side drive signal to shut down the ramp compensation current output by the ramp compensation circuit.

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