Power circuit and integrated circuit
By introducing first and second power transistors in parallel into the power circuit and using feedback signals and current ratio adjustment, the problems of inconsistent LDO output voltage and difficult current control are solved, achieving stable voltage and low-loss power supply.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SILERGY SEMICON TECH (HANGZHOU) CO LTD
- Filing Date
- 2026-02-13
- Publication Date
- 2026-07-31
AI Technical Summary
In the prior art, the output voltages of two low dropout linear regulators (LDOs) are not necessarily exactly the same, and the output current is not easy to control, resulting in large power losses.
By introducing first and second power transistors into the power circuit and controlling them by first and second control circuits respectively, and by using feedback signals and current ratio adjustment, the output voltage is ensured to be stable and the current is distributed according to a preset ratio.
It achieves stable output voltage and controlled current ratio, reduces power loss, improves power supply capacity, and can operate within a wider load range.
Smart Images
Figure CN122495847A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics, and more specifically, to a power circuit and an integrated circuit. Background Technology
[0002] When driving large loads, the existing technology directly couples two low dropout regulators (LDOs) in parallel to drive the load. Each LDO includes a power transistor and a control loop, and each control loop independently controls the corresponding power transistor.
[0003] In the existing technology, since the control circuits in the two LDOs control the corresponding power transistors independently, the output voltages of the two LDOs are not necessarily the same, and the output currents of the two LDOs are not easy to control. If a resistor is connected in series with the power transistor in each LDO, the existing technology will also cause a large power loss. Summary of the Invention
[0004] In view of this, the present invention proposes a power circuit and integrated circuit to solve the technical problems in the prior art where the output voltages of two LDOs are not necessarily completely the same and the output currents of two LDOs are not easy to control.
[0005] This invention provides a power circuit for driving a load, comprising: an input terminal and an output terminal; a first power transistor coupled between the input terminal and the output terminal to output a first output current; a second power transistor coupled between the input terminal and the output terminal to output a second output current; a first control circuit receiving a feedback signal and a reference voltage signal characterizing the output voltage of the output terminal to generate a first drive signal; and a second control circuit receiving a first current characterizing the first output current and a second current characterizing the second output current to generate a second drive signal; wherein the load is coupled between the output terminal and ground potential to receive the first output current and the second output current, thereby generating the output voltage; the control terminal of the first power transistor receives the first drive signal, and the control terminal of the second power transistor receives the second drive signal.
[0006] In one embodiment, the second control circuit adjusts the ratio of the first current and the second current so that the first output current and the second output current are provided to the load in a preset ratio.
[0007] In one embodiment, the power circuit further includes: a first current generating circuit configured to generate the first current and such that the ratio of the first output current to the first current is M; and a second current generating circuit configured to generate the second current and such that the ratio of the second output current to the second current is N, wherein M and N are positive integers.
[0008] In one embodiment, the second control circuit receives the first current and the second current, and generates a corresponding second drive signal, such that the ratio of the first current and the second current is K; wherein the ratio of the product of M and K to N is consistent with the preset ratio.
[0009] In one embodiment, the ratio of the first current to the second current is adjusted to 1, so that the first current and the second current are equal, and the preset ratio is equal to the ratio of M and N.
[0010] In one embodiment, the second control circuit includes: a second control signal generating circuit that receives the first current and the second current to generate a second voltage signal, wherein the second voltage signal is positively correlated with the difference between the first current and the second current; and a second drive signal generating circuit that receives the second voltage signal to generate a second drive signal, wherein the second drive signal is positively correlated with the second voltage signal.
[0011] In one embodiment, the second control signal generating circuit includes: a current-controlled current source, one input terminal of which receives a first current, the other input terminal of which receives a second current, and an output terminal of which generates a first control current; and a current-to-voltage conversion circuit, coupled to the output terminal of the current-controlled current source, receiving the first control current to generate the second voltage signal.
[0012] In one embodiment, the second drive signal generating circuit includes: a second buffer, which receives the second voltage signal and outputs the second drive signal.
[0013] In one embodiment, the first current generating circuit obtains the first current by means of a current mirror or current replication.
[0014] In one embodiment, the first current generating circuit includes a third power transistor, the first power terminal of the third power transistor is coupled to the first power terminal of the first power transistor, the control terminal of the third power transistor is coupled to the control terminal of the first power transistor, and the second power terminal of the third power transistor generates the first current.
[0015] In one embodiment, the first current generating circuit includes: a third power transistor, the first power terminal of which is coupled to the first power terminal of the first power transistor, and the control terminal of which is coupled to the control terminal of the first power transistor; and a first current mirror circuit, the input terminal of which is coupled to the second power terminal of the third power transistor, and the output terminal of which generates the first current.
[0016] In one embodiment, the first current generating circuit includes: a first resistor coupled between the first power transistor and the input terminal; a second resistor, the first end of which is coupled to the input terminal; a third power transistor, the first power terminal of which is coupled to the second end of the second resistor, and the second power terminal of which generates the first current; and a third control circuit, the first input terminal of which is coupled to the common terminal of the first resistor and the first power transistor, the second input terminal of which is coupled to the common terminal of the second resistor and the third power transistor, and the output terminal of which is coupled to the control terminal of the third power transistor.
[0017] In one embodiment, the second current generating circuit obtains the second current by means of a current mirror or current replication.
[0018] In one embodiment, the second current generating circuit includes a fourth power transistor, a first power terminal of the fourth power transistor is coupled to a first power terminal of the second power transistor, a control terminal of the fourth power transistor is coupled to a control terminal of the second power transistor, and a second power terminal of the fourth power transistor generates the second current.
[0019] In one embodiment, the second current generating circuit includes a fourth power transistor, the first power terminal of which is coupled to the first power terminal of the second power transistor, and the control terminal of which is coupled to the control terminal of the second power transistor; and a second current mirror circuit, the input terminal of which is coupled to the second power terminal of the fourth power transistor, and the output terminal of which generates the second current.
[0020] In one embodiment, the first control circuit includes: a first control signal generating circuit that receives the feedback signal and the reference voltage signal to generate a first voltage signal, wherein the first voltage signal is positively correlated with the difference between the feedback signal and the reference voltage signal; and a first drive signal generating circuit that receives the first voltage signal to generate a first drive signal, wherein the first drive signal is positively correlated with the first voltage signal.
[0021] In one embodiment, the first control signal generating circuit includes a first operational amplifier, a first input terminal of the first operational amplifier receiving the reference voltage signal, a second input terminal of the first operational amplifier receiving the feedback signal, and an output terminal of the first operational amplifier generating a first voltage signal.
[0022] In one embodiment, the first drive signal generating circuit includes: a first buffer, which receives the first voltage signal and outputs the first drive signal.
[0023] This invention also provides an integrated circuit, comprising at least one of the first power transistor, the second power transistor, the first control circuit, and the second control circuit described in any one of the preceding embodiments.
[0024] This invention also provides another integrated circuit, comprising at least one of the second power transistor, the first control circuit, and the second control circuit described in any of the above embodiments.
[0025] Compared with the prior art, the technical solution of the present invention has the following advantages: The power circuit in the embodiment of the present invention is used to drive a load, including: an input terminal and an output terminal; a first power transistor coupled between the input terminal and the output terminal to output a first output current; a second power transistor coupled between the input terminal and the output terminal to output a second output current; a first control circuit receiving a feedback signal and a reference voltage signal characterizing the output voltage of the output terminal to generate a first drive signal; and a second control circuit receiving a first current characterizing the first output current and a second current characterizing the second output current to generate a second drive signal; wherein, the load is coupled between the output terminal and ground potential to receive the first output current and the second output current, thereby generating the output voltage; the control terminal of the first power transistor receives the first drive signal, and the control terminal of the second power transistor receives the second drive signal. In this invention, the control of the first and second power transistors is not completely independent. The first control circuit 1 of the first power transistor is independently controlled, with the output voltage Vo at the control output terminal o as a stable value. The second control circuit 2 of the second power transistor is not independently controlled; it receives a first current Is1 representing the current of the first power transistor Q1. Therefore, the power circuit of this invention not only stabilizes the output voltage at the output terminal o, but also controls the ratio of the current flowing through the first power transistor to the current flowing through the second power transistor. Simultaneously, the power loss of the power circuit in this invention is relatively small. In this invention, the second control circuit adjusts the ratio of the first current and the second current to ensure that the first output current and the second output current are supplied to the load according to a preset ratio. This reduces the current and losses through a single power switch under a fixed load, giving the power circuit of this invention a stronger power supply capability and allowing it to operate over a wider load range. The power circuit of this invention can adaptively distribute the current of the first and second power transistors according to a preset ratio, thereby improving the power supply capability and maintaining a stable output voltage. The power circuit of this invention provides stable control for the parallel operation of the first and second power transistors, enabling them to distribute current according to a preset ratio and maintain a stable output voltage under any load. Attached Figure Description
[0026] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0027] Figure 1 This is a circuit diagram of a first embodiment of the power circuit of the present invention;
[0028] Figure 2 This is a circuit diagram of a second embodiment of the power circuit of the present invention;
[0029] Figure 3 This is a circuit diagram of a third embodiment of the power circuit of the present invention;
[0030] Figure 4 This is a circuit diagram of Embodiment 4 of the power circuit of the present invention. Detailed Implementation
[0031] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0032] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0033] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0034] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."
[0035] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0036] Figure 1 This is a circuit diagram of a first embodiment of the power circuit of the present invention. Figure 1 As shown, the power circuit is used to drive the load. The power circuit includes an input terminal IN, an output terminal o, a first power transistor Q1, a second power transistor Q2, a first control circuit 1, and a second control circuit 2. The input terminal IN receives the input voltage Vcc; the output terminal o is coupled to one end of the load, and the other end of the load is grounded. The first power transistor Q1 is coupled between the input terminal IN and the output terminal o to generate a first output current Io1. The second power transistor Q2 is coupled between the input terminal IN and the output terminal o to generate a second output current Io2. That is, the first power transistor Q1 and the second power transistor Q2 are connected in parallel between the input terminal IN and the output terminal o. The first control circuit 1 receives a feedback signal VFB characterizing the output voltage Vo at the output terminal o and a reference voltage signal Vref to generate a first drive signal G1. The output terminal of the first control circuit 1 is coupled to the control terminal of the first power transistor Q1, that is, the first drive signal G1 is provided to the control terminal of the first power transistor Q1 to drive the first power transistor Q1. The second control circuit 2 receives a first current Is1 representing the first output current Io1 and a second current Is2 representing the second output current Io2 to generate a second drive signal G2. The output terminal of the second control circuit 2 is coupled to the control terminal of the second power transistor Q2, that is, the second drive signal G2 is provided to the control terminal of the second power transistor Q2 to drive the second power transistor Q2. The load is coupled between the output terminal o and ground potential to receive the first output current Io1 and the second output current Io2, thereby generating an output voltage Vo.
[0037] In this embodiment, the first output current Io1 is configured to flow through the first power transistor Q1, and the second output current Io2 is configured to flow through the second power transistor Q2. This invention does not impose any limitations on this. The current Io flowing through the load is equal to the sum of the first output current Io1 and the second output current Io2, i.e., Io = Io1 + Io2.
[0038] Optionally, the feedback signal VFB is a voltage divider of the output voltage Vo at the output terminal o.
[0039] In this embodiment, the second control circuit 2 adjusts the ratio of the first current Is1 and the second current Is2 so that the first output current Io1 and the second output current Io2 are provided to the load in a preset ratio.
[0040] Furthermore, the power circuit also includes a first current generating circuit ( Figure 1 (not shown in the diagram) and second current generating circuit ( Figure 1(Not shown in the diagram) A first current generating circuit is configured to generate a first current Is1, such that the ratio of the first output current Io1 to the first current Is1 is M; a second current generating circuit is configured to generate a second current Is2, such that the ratio of the second output current Io2 to the second current Is2 is N, where M and N are positive integers. That is, the first current generating circuit is used to sample the first output current Io1, and the second current generating circuit is used to sample the second output current Io2.
[0041] The second control circuit 2 receives the first current Is1 and the second current Is2, and generates a corresponding second drive signal G2, thereby making the ratio of the first current Is1 and the second current Is2 K; wherein, the ratio of the product of M and K to N is consistent with the preset ratio, that is, the preset ratio = (M*K) / N. In a preferred embodiment, the ratio of the first current Is1 and the second current Is2 is adjusted to 1, that is, K=1, so that the values of the first current Is1 and the second current Is2 are equal. At this time, the preset ratio is equal to M / N. The following description uses K=1 as an example, but the present invention does not limit this.
[0042] This invention, through the configuration of the first control circuit 1, establishes a negative feedback control loop formed by the first control circuit 1 and the first power transistor Q1, thereby controlling the output voltage Vo at the output terminal o to a stable value. Further, through the negative feedback control loop formed by the second control circuit 2 and the second power transistor Q2, the ratio of the first current Is1 and the second current Is2 is adjusted to control the first output current Io1 and the second output current Io2 to be supplied to the load according to a preset ratio. This invention does not limit the structure of the first control circuit 1 and the second control circuit 2; any circuit that can achieve the functions of the first control circuit 1 and the second control circuit 2 in this embodiment is within the protection scope of this invention.
[0043] The present invention does not limit the structure of the first current generating circuit and the second current generating circuit. Any circuit that can realize the functions of the first current generating circuit and the second current generating circuit in this embodiment is within the protection scope of the present invention.
[0044] In this embodiment, the first power transistor Q1 and the second power transistor Q2 are P-type MOSFETs, but the present invention is not limited to this. In other embodiments, the first power transistor Q1 and the second power transistor Q2 are various power transistors such as N-type MOSFETs, PNP transistors, or NPN transistors. The first power transistor Q1 and the second power transistor Q2 can be the same type of power transistor or different types of power transistors.
[0045] Figure 2This is a circuit diagram of a second embodiment of the power circuit of the present invention. The difference from the first embodiment is that a schematic specific structure of the first control circuit 1, the second control circuit 2, the first current generating circuit 3, and the second current generating circuit 4 is shown.
[0046] In this embodiment, the first current generating circuit 3 obtains the first current Is1 by means of a current mirror or current replication, and the second current generating circuit 4 obtains the second current Is2 by means of a current mirror or current replication.
[0047] In this embodiment, the first current generating circuit 3 includes a third power transistor Q3. The first power terminal of the third power transistor Q3 is coupled to the first power terminal of the first power transistor Q1, and the control terminal of the third power transistor Q3 is coupled to the control terminal of the first power transistor Q1. The second power terminal of the third power transistor Q3 generates a first current Is1. Thus, the third power transistor Q3 and the first power transistor Q1 form a current replication circuit. The third power transistor Q3 can be considered as a sampling circuit, sampling the current Io1 flowing through the first power transistor Q1 to obtain the first current Is1 characterizing the current Io1 flowing through the first power transistor Q1. Assuming the size ratio of the first power switch Q1 to the third power switch Q3 is M, then the ratio of the current Io1 flowing through the first power switch Q1 to the current Is1 flowing through the third power switch Q3 is M, i.e., Io1 = M * Is1.
[0048] In this embodiment, the second current generating circuit 4 includes a fourth power transistor Q4. The first power terminal of the fourth power transistor Q4 is coupled to the first power terminal of the second power transistor Q2, and the control terminal of the fourth power transistor Q4 is coupled to the control terminal of the second power transistor Q2. The second power terminal of the fourth power transistor Q4 generates a second current Is2. Thus, the second power transistor Q2 and the fourth power transistor Q4 form a current replication circuit. The fourth power transistor Q4 can be considered as a sampling circuit, sampling the current Io2 flowing through the second power transistor Q2 to obtain the first current Is2 characterizing the current Io2 flowing through the second power transistor Q2. Assuming the size ratio of the second power switch Q2 to the fourth power switch Q4 is N, then the ratio of the current Io2 flowing through the second power switch Q2 to the current Is2 flowing through the fourth power switch Q4 is N, i.e., Io2 = N * Is2.
[0049] In this embodiment, the negative feedback control loop formed by the second control circuit 2 and the second power transistor Q2 makes the first current Is1 equal to the second current Is2, i.e., K=1. Thus, the ratio of the current Io1 flowing through the first power switch Q1 to the current Io2 flowing through the second power switch Q2 is M:N, i.e., Io1:Io2=M:N, thereby controlling the ratio of the current Io1 flowing through the first power transistor Q1 to the current Io2 flowing through the second power transistor Q2.
[0050] The power circuit also includes a feedback signal generation circuit to generate a feedback signal VFB characterizing the output voltage Vo at the output terminal o. In this embodiment, the feedback signal generation circuit includes resistors R01 and R02, which are connected in series between the output terminal o and ground potential. The feedback signal VFB is configured as the voltage at the common terminal of resistors R01 and R02. This invention does not limit the structure of the feedback signal generation circuit. Optionally, the power circuit also includes a first capacitor C1, which is connected in parallel with the load.
[0051] The first control circuit 1 includes a first control signal generation circuit 11 and a first drive signal generation circuit 12. The first control signal generation circuit 11 receives a feedback signal VFB and a reference voltage signal Vref that characterize the output voltage Vo of the output terminal o, and generates a first voltage signal, wherein the first voltage signal is positively correlated with the difference between the feedback signal VFB and the reference voltage signal Vref. The first drive signal generation circuit 12 receives the first voltage signal and generates a first drive signal G1, wherein the first drive signal G1 is positively correlated with the first voltage signal. The first drive signal G1 is provided to the control terminal of the first power transistor Q1.
[0052] Specifically, in this embodiment, the first control signal generation circuit 11 includes a first operational amplifier A1. The first input terminal of the first operational amplifier A1 receives a reference voltage signal Vref, and the second input terminal of the first operational amplifier A1 receives a feedback signal VFB characterizing the output voltage Vo at the output terminal o. The output terminal of the first operational amplifier A1 generates a first voltage signal. In this embodiment, the first input terminal is an inverting input terminal, and the second input terminal is a non-inverting input terminal; this is not a limitation of the present invention. The present invention does not limit the structure of the first control signal generation circuit 11. In another embodiment, the first control signal generation circuit 11 includes a transconductance amplifier and a third resistor. The two input terminals of the transconductance amplifier respectively receive the reference voltage signal Vref and the feedback signal VFB characterizing the output voltage Vo at the output terminal o. The third resistor is coupled between the output terminal of the transconductance amplifier and ground potential. The output terminal of the transconductance amplifier generates an output current and generates a first voltage signal across the third resistor. In one embodiment, the first drive signal generation circuit 12 includes a first buffer. The first buffer receives the first voltage signal and outputs a first drive signal G1 to increase the driving capability of the first voltage signal. The present invention does not limit the structure of the first driving signal generation circuit, and any first driving signal generation circuit with increased driving capability is within the protection scope of the present invention.
[0053] The negative feedback control loop formed by the first control circuit 1 and the first power transistor Q1 stabilizes the feedback signal VFB, which characterizes the output voltage Vo at the output terminal O, at the reference voltage signal Vref, thereby controlling the output voltage Vo at the output terminal O to a stable value.
[0054] The second control circuit 2 includes a second control signal generation circuit 21 and a second drive signal generation circuit 22. The second control signal generation circuit 21 receives a first current Is1 and a second current Is2 to generate a second voltage signal, wherein the second voltage signal is positively correlated with the difference between the first current Is1 and the second current Is2; the second drive signal generation circuit 22 receives the second voltage signal to generate a second drive signal G2, wherein the second drive signal G2 is positively correlated with the second voltage signal, and the second drive signal G2 is provided to the control terminal of the second power switch Q2.
[0055] Specifically, in one embodiment, the second control signal generation circuit 21 includes a current-controlled current source and a current-to-voltage conversion circuit. The first input terminal of the current-controlled current source receives a first current Is1, and the second input terminal receives a second current Is2. The output terminal of the current-controlled current source generates a first output current. The current-to-voltage conversion circuit receives the first output current to generate a second voltage signal. In this embodiment, the first input terminal is an inverting input terminal, and the second input terminal is a non-inverting input terminal. In one implementation, the current-to-voltage conversion circuit includes a fourth resistor coupled between the output terminal of the current-controlled current source and ground potential. The output terminal of the current-controlled current source generates an output current and generates a second voltage signal across the fourth resistor. Optionally, the current-to-voltage conversion circuit includes a second capacitor, and the second capacitor and the fourth resistor are connected in parallel. This invention does not limit the structure of the second control signal generation circuit 21 and the current-to-voltage conversion circuit.
[0056] The second drive signal generation circuit 22 includes a second buffer. The second buffer receives the second voltage signal and outputs a second drive signal G2 to increase the driving capability of the second voltage signal. This invention does not limit the structure of the second drive signal generation circuit; any second drive signal generation circuit that increases the driving capability is within the protection scope of this invention.
[0057] In this embodiment, the negative feedback control loop formed by the second control circuit 2 and the second power transistor Q2 makes the first current Is1 equal to the second current Is2, thereby controlling the ratio of the current Io1 flowing through the first power transistor Q1 to the current Io2 flowing through the second power transistor Q2, so that the ratio of the current Io1 flowing through the first power transistor Q1 to the current Io2 flowing through the second power transistor Q2 is equal to a preset ratio M / N. By adjusting the ratio of the first current and the second current, the first output current and the second output current are provided to the load according to the preset ratio.
[0058] In this invention, the control of the first and second power transistors is not completely independent. The first control circuit 1 of the first power transistor is independently controlled, with the output voltage Vo at the control output terminal o as a stable value. The second control circuit 2 of the second power transistor is not independently controlled; it receives a first current Is1 representing the current of the first power transistor Q1. Therefore, the power circuit of this invention not only stabilizes the output voltage at the output terminal o, but also controls the ratio of the current flowing through the first power transistor to the current flowing through the second power transistor. Simultaneously, the power loss of the power circuit in this invention is relatively small. In this invention, the second control circuit adjusts the ratio of the first current and the second current to ensure that the first output current and the second output current are supplied to the load according to a preset ratio. This reduces the current and losses through a single power switch under a fixed load, giving the power circuit of this invention a stronger power supply capability and allowing it to operate over a wider load range. The power circuit of this invention can adaptively distribute the current of the first and second power transistors according to a preset ratio, thereby improving the power supply capability and maintaining a stable output voltage. The power circuit of this invention provides stable control for the parallel operation of the first and second power transistors, enabling them to distribute current according to a preset ratio and maintain a stable output voltage under any load.
[0059] In this embodiment, at least one of the first power transistor Q1, the second power transistor Q2, the first control circuit 1, the second control circuit 2, the first current generating circuit 3, the second current generating circuit 4, and the feedback signal generating circuit is integrated on a single chip; however, this invention does not limit the scope of the invention. In a preferred embodiment, the first power transistor Q1, the second power transistor Q2, the first control circuit 1, the second control circuit 2, the first current generating circuit 3, the second current generating circuit 4, and the feedback signal generating circuit are integrated on a single chip.
[0060] In this embodiment, both the first power transistor Q1 and the second power transistor Q2 are P-type MOSFETs, but this invention is not limited to this. In other embodiments, the first power transistor Q1 and the second power transistor Q2 can be various power transistors such as N-type MOSFETs, PNP transistors, or NPN transistors. Furthermore, the first power transistor Q1 and the second power transistor Q2 can be the same type of power transistor or different types of power transistors.
[0061] In this embodiment, the first power terminal is the source and the second power terminal is the drain.
[0062] Figure 3 This is a circuit diagram of Embodiment 3 of the power circuit of the present invention; the difference between this embodiment and Embodiment 2 is that the structure of the first current generating circuit 3 is different.
[0063] In this embodiment, the first current generating circuit 3 includes a first resistor R1, a second resistor R2, a third power transistor Q3, and a third control circuit. The first resistor R1 is coupled between the first power transistor Q1 and the input terminal IN. The first end of the second resistor R2 is coupled to the input terminal IN, and the second end of the second resistor R2 is coupled to the first power terminal of the third power transistor Q3. The second power terminal of the third power transistor Q3 generates a first current Is1. The first input terminal of the third control circuit is coupled to the common terminal of the first resistor R1 and the first power transistor Q1. The second input terminal of the third control circuit is coupled to the common terminal of the second resistor R2 and the third power transistor Q3. The output terminal of the third control circuit is coupled to the control terminal of the third power transistor Q3. In this embodiment, the third control circuit includes a second operational amplifier A2. The first input terminal and the second input terminal of the second operational amplifier A2 are respectively coupled to the common terminal of the first resistor R1 and the first power transistor Q1, and the common terminal of the second resistor R2 and the third power transistor Q3. Its output terminal is coupled to the common terminal of the second resistor R2 and the third power transistor Q3. The first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal. This invention does not impose any limitations on this.
[0064] The negative feedback control loop formed by the third control circuit and the third power transistor Q3 makes the voltage at the common terminal of the first resistor R1 and the first power transistor Q1 equal to the voltage at the common terminal of the second resistor R2 and the third power transistor Q3. As a result, the voltage difference across the first resistor R1 and the second resistor R2 is equal. Since the voltage difference across the first resistor R1 and the second resistor R2 is equal, the ratio of the current Io1 flowing through the first power transistor Q1 to the current Is1 flowing through the third power transistor is equal to R2 / R1, that is, M = R2 / R1.
[0065] The rest of the structure is similar to that of Embodiment 2, and will not be described in detail here.
[0066] In this embodiment, at least one of the second power transistor Q2, the first control circuit 1, the second control circuit 2, the third power switch Q3, the second resistor R2, the third control circuit, the second current generating circuit 4, and the feedback signal generating circuit is integrated on a single chip; this invention does not limit the scope of the invention. In a preferred embodiment, the second power transistor Q2, the first control circuit 1, the second control circuit 2, the third power switch Q3, the second resistor R2, the third control circuit, the second current generating circuit 4, and the feedback signal generating circuit are all integrated on a single chip.
[0067] In this embodiment, the first resistor R1 and the first power transistor Q1 are located outside the chip. Customers can select the size of the first power transistor Q1 and / or the resistance value of the first resistor R1 as needed, thus adapting to more application scenarios.
[0068] In this embodiment, the first power transistor Q1 is a P-type MOSFET. In another embodiment, the first power transistor Q1 is a PNP transistor, in which case the first power terminal is the emitter of the PNP transistor, the second power terminal is the collector of the PNP transistor, and the control terminal is the base of the PNP transistor. This invention does not impose any limitations on this.
[0069] In this embodiment, the structure of the second current generating circuit 4 is similar to that of the second current generating circuit 4 in Embodiment 2, and the present invention does not limit it. In another embodiment, the second current generating circuit 4 can be configured similarly to the first current generating circuit 3 in Embodiment 3.
[0070] Figure 4 This is a circuit diagram of Embodiment 4 of the power circuit of the present invention. The difference from Embodiment 2 is that the first power transistor Q1 and the second power transistor Q2 are N-type MOSFETs, the structures of the first current generating circuit 3 and the second current generating circuit 4 are different, and the mechanism of the second drive signal generating circuit 21 in the second control circuit 2 is different. The remaining parts are similar to Embodiment 2 and will not be described in detail here.
[0071] Specifically, the first current generating circuit 3 includes a third power transistor Q3 and a first current mirror circuit. The first power terminal of the third power transistor Q3 is coupled to the first power terminal of the first power transistor Q1, and the control terminal of the third power transistor Q3 is coupled to the control terminal of the first power transistor Q1. The input terminal of the first current mirror circuit is coupled to the second power terminal of the third power transistor Q3, and the output terminal of the first current mirror circuit generates a first current Is1. At this time, the first power transistor Q1 and the third power transistor Q3 form a current replication circuit. Further, the first current mirror circuit includes a fifth power transistor Q5 and a sixth power transistor Q6. The second power terminal of the fifth power transistor Q5 is coupled to the second power terminal of the third power transistor Q3, and the first power terminal of the fifth power transistor Q5 is coupled to the input terminal IN. The first power terminal of the sixth power transistor Q6 is coupled to the first power terminal of the fifth power transistor Q5, and the control terminal of the sixth power transistor Q6 is coupled to the control terminal of the fifth power transistor Q5. The second power terminal of the fifth power transistor Q5 is coupled to its own control terminal, and the second power terminal of the sixth power transistor Q6 generates the first current Is1.
[0072] The second current generating circuit 4 includes a fourth power transistor Q4 and a second current mirror circuit. The first power terminal of the fourth power transistor Q4 is coupled to the first power terminal of the second power transistor Q2, and the control terminal of the fourth power transistor Q4 is coupled to the control terminal of the second power transistor Q2. The input terminal of the second current mirror circuit is coupled to the second power terminal of the fourth power transistor Q4, and the output terminal of the second current mirror circuit generates a second current Is2. At this time, the second power transistor Q2 and the fourth power transistor Q4 form a current replication circuit. The second current mirror circuit includes a seventh power transistor Q7 and an eighth power transistor Q8. The second power terminal of the seventh power transistor Q7 is coupled to the second power terminal of the fourth power transistor Q4, and the first power terminal of the seventh power transistor Q7 is coupled to the input terminal IN. The first power terminal of the eighth power transistor Q8 is coupled to the first power terminal of the seventh power transistor Q7, and the control terminal of the eighth power transistor Q8 is coupled to the control terminal of the seventh power transistor Q7. The second power terminal of the seventh power transistor Q7 is coupled to its own control terminal, and the second power terminal of the eighth power transistor Q8 generates a second current Is2.
[0073] The second control signal generation circuit 21 includes a current-controlled current source and a current-to-voltage conversion circuit. The first input terminal of the current-controlled current source receives a first current Is1, the second input terminal of the current-controlled current source receives a second current Is2, and the output terminal of the current-controlled current source generates a first output current. The current-to-voltage conversion circuit receives the first output current to generate a second voltage signal. In this embodiment, the first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal.
[0074] The rest of the process is similar to the embodiments and will not be described in detail here.
[0075] In this embodiment, the current Io through the load is equal to the sum of the currents flowing through the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4. Since the currents flowing through the third power transistor Q3 and the fourth power transistor Q4 are small, they can be ignored. Therefore, it can be considered that the current Io through the load is equal to the sum of the currents flowing through the first power transistor Q1 and the second power transistor Q2.
[0076] In this embodiment, the first power transistor Q1 and the second power transistor Q2 are N-type MOSFETs. However, this is not a limitation. For example, in another embodiment, the first power transistor Q1 and the second power transistor Q2 are NPN transistors.
[0077] In this embodiment, at least one of the first power transistor Q1, the second power transistor Q2, the first control circuit 1, the second control circuit 2, the first current generating circuit 3, the second current generating circuit 4, and the feedback signal generating circuit is integrated on a single chip; this invention does not limit the scope of the invention. In a preferred embodiment, the first power transistor Q1, the second power transistor Q2, the first control circuit 1, the second control circuit 2, the first current generating circuit 3, the second current generating circuit 4, and the feedback signal generating circuit are all integrated on a single chip.
[0078] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.
[0079] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A power circuit for driving a load, characterized by, include: One input terminal and one output terminal; A first power transistor is coupled between the input terminal and the output terminal to output a first output current; A second power transistor is coupled between the input terminal and the output terminal to output a second output current; The first control circuit receives a feedback signal and a reference voltage signal characterizing the output voltage of the output terminal, so as to generate a first drive signal; and The second control circuit receives a first current representing the first output current and a second current representing the second output current to generate a second drive signal. The load is coupled between the output terminal and ground potential to receive the first output current and the second output current, thereby generating the output voltage; The control terminal of the first power transistor receives the first drive signal, and the control terminal of the second power transistor receives the second drive signal.
2. The power circuit according to claim 1, characterized in that, The second control circuit adjusts the ratio of the first current and the second current so that the first output current and the second output current are provided to the load in a preset ratio.
3. The power circuit according to claim 1 or 2, characterized in that, Also includes: A first current generating circuit is configured to generate the first current, such that the ratio of the first output current to the first current is M. and A second current generating circuit is configured to generate the second current, such that the ratio of the second output current to the second current is N, where M and N are positive integers.
4. The power circuit according to claim 3, characterized in that, The second control circuit receives the first current and the second current, and generates a corresponding second drive signal, such that the ratio of the first current and the second current is K; wherein the ratio of the product of M and K to N is consistent with the preset ratio.
5. The power circuit according to claim 4, characterized in that, The ratio of the first current to the second current is adjusted to 1, so that the first current and the second current are equal, and the preset ratio is equal to the ratio of M and N.
6. The power circuit according to claim 1, characterized in that, The second control circuit includes: A second control signal generating circuit receives the first current and the second current to generate a second voltage signal, wherein the second voltage signal is positively correlated with the difference between the first current and the second current; and The second drive signal generating circuit receives the second voltage signal to generate the second drive signal, wherein the second drive signal and the second voltage signal are positively correlated.
7. The power circuit according to claim 6, characterized in that, The second control signal generation circuit includes: A current-controlled current source receives a first current at one input terminal and a second current at the other input terminal, and generates a first control current at its output terminal; and A current-to-voltage conversion circuit is coupled to the output of a current-controlled current source and receives the first control current to generate the second voltage signal.
8. The power circuit according to claim 6, characterized in that, The second drive signal generation circuit includes: a second buffer, which receives the second voltage signal and outputs the second drive signal.
9. The power circuit according to claim 3, characterized in that, The first current generating circuit obtains the first current by means of a current mirror or current replication.
10. The power circuit according to claim 9, characterized in that, The first current generating circuit includes a third power transistor. The first power terminal of the third power transistor is coupled to the first power terminal of the first power transistor, the control terminal of the third power transistor is coupled to the control terminal of the first power transistor, and the second power terminal of the third power transistor generates the first current.
11. The power circuit according to claim 9, characterized in that, The first current generating circuit includes: The third power transistor has its first power terminal coupled to the first power terminal of the first power transistor, and its control terminal coupled to the control terminal of the first power transistor; and The first current mirror circuit has its input terminal coupled to the second power terminal of the third power transistor, and its output terminal generates the first current.
12. The power circuit according to claim 3, characterized in that, The first current generating circuit includes: A first resistor is coupled between the first power transistor and the input terminal. The second resistor has its first end coupled to the input terminal; The third power transistor has its first power terminal coupled to the second terminal of the second resistor, and its second power terminal generates the first current; and The third control circuit has a first input terminal coupled to the common terminal of the first resistor and the first power transistor, a second input terminal coupled to the common terminal of the second resistor and the third power transistor, and an output terminal coupled to the control terminal of the third power transistor.
13. The power circuit according to claim 3, characterized in that, The second current generating circuit obtains the second current through a current mirror or current replication.
14. The power circuit according to claim 13, characterized in that, The second current generating circuit includes a fourth power transistor. The first power terminal of the fourth power transistor is coupled to the first power terminal of the second power transistor, the control terminal of the fourth power transistor is coupled to the control terminal of the second power transistor, and the second power terminal of the fourth power transistor generates the second current.
15. The power circuit according to claim 13, characterized in that, The second current generating circuit includes: The fourth power transistor has its first power terminal coupled to the first power terminal of the second power transistor, and its control terminal coupled to the control terminal of the second power transistor; and The second current mirror circuit has its input terminal coupled to the second power terminal of the fourth power transistor, and its output terminal generates the second current.
16. The power circuit according to claim 1, characterized in that, The first control circuit includes: A first control signal generation circuit receives the feedback signal and the reference voltage signal to generate a first voltage signal, wherein the first voltage signal is positively correlated with the difference between the feedback signal and the reference voltage signal; and A first drive signal generating circuit receives the first voltage signal to generate the first drive signal, wherein the first drive signal and the first voltage signal are positively correlated.
17. The power circuit according to claim 16, characterized in that, The first control signal generation circuit includes a first operational amplifier. The first input terminal of the first operational amplifier receives the reference voltage signal, the second input terminal of the first operational amplifier receives the feedback signal, and the output terminal of the first operational amplifier generates a first voltage signal.
18. The power circuit according to claim 16, characterized in that, The first drive signal generation circuit includes: a first buffer, which receives the first voltage signal and outputs the first drive signal.
19. An integrated circuit, characterized in that, include: At least one of the first power transistor, the second power transistor, the first control circuit, and the second control circuit as described in any one of claims 1-18.
20. An integrated circuit, characterized in that, include: At least one of the second power transistor, the first control circuit, and the second control circuit as described in any one of claims 1-18.