Battery charge-discharge power conversion system with super capacitor

Abstract

This invention relates to the field of power electronic conversion technology and discloses a battery charging and discharging power conversion system with a supercapacitor, comprising: a battery management subsystem, with a battery management chip as the core, including charging and discharging drive, equalization dissipation and sampling circuits, to realize state monitoring, equalization management and safety protection of the lithium battery pack; a four-switch bidirectional Buck-Boost power conversion subsystem, adopting a same polarity topology, consisting of power switches, inductors and input / output capacitors, to realize bidirectional energy transfer between the lithium battery and the supercapacitor; and a control and communication system, adopting a layered architecture, with the outer power scheduling layer performing double S-curve smoothing planning and the inner current control layer adjusting the inductor current based on an improved sliding mode control framework; wherein, the battery management subsystem introduces a sparse pulse equalization strategy to solve the problem that traditional dissipative equalization heat loss and equalization effect are difficult to balance.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, and more specifically to a battery charging and discharging power conversion system with a supercapacitor. Background Technology

[0002] With the rapid development of new energy technologies, lithium batteries have been widely used in energy storage systems and power supply due to their high energy density. However, in applications requiring high-power, fast response and frequent bidirectional energy flow, relying solely on lithium batteries makes it difficult to balance the conflict between transient power surges and cycle life. Supercapacitors, with their high power density, long cycle life, and rapid charge / discharge capabilities, are combined with lithium batteries to form a hybrid energy storage system. The supercapacitors handle transient high-power charge / discharge surges to alleviate the power stress on the lithium batteries, making this a crucial technology for improving overall system performance. In this hybrid architecture, energy exchange between the lithium battery pack and the supercapacitor pack is achieved through a bidirectional power converter. The battery management subsystem (BMS) is responsible for lithium battery status monitoring and safety protection, while the control and communication system handles power scheduling and closed-loop regulation.

[0003] In terms of battery management, existing technologies generally adopt dissipative balancing schemes. By setting a fixed voltage threshold, when the voltage of a single cell reaches the threshold, the balancing MOSFET and balancing resistor are continuously turned on to dissipate the excess power of the high-voltage cell as heat energy, so as to achieve voltage consistency between cells.

[0004] However, this method has significant inherent drawbacks: if the equalization is turned on for a long time with a high duty cycle in order to ensure equalization speed and consistency, the equalization resistor will continue to heat up, leading to increased system power consumption, accelerated cell temperature rise, and even overheating safety risks; if the equalization time is shortened in order to reduce heat generation and loss, the equalization will be insufficient, the cell voltage difference will not be effectively converged, and the usable capacity and cycle life of the battery pack will be directly reduced.

[0005] In addition, existing balancing strategies are mostly passive and reactive, only activated after voltage deviation has formed. They lack the ability to predict voltage drift trends and are difficult to intervene effectively in the early stages of imbalance. Summary of the Invention

[0006] The present invention aims to provide a battery charging and discharging power conversion system with a supercapacitor to solve the technical problem that traditional dissipative equalization is difficult to balance heat loss and equalization effect due to continuous conduction.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a battery charging and discharging power conversion system with a supercapacitor, comprising: The battery management subsystem includes a charging and discharging drive circuit with a battery management chip as its core, an equalization and dissipation circuit, and a sampling circuit, which are used to monitor the state of the lithium battery pack, manage the equalization, and provide multi-level safety protection. The four-switch bidirectional Buck-Boost power conversion subsystem adopts a four-switch same-polarity Buck-Boost topology and consists of power switches Q1~Q4, power inductor L, input capacitor connected to the lithium battery side and output capacitor connected to the supercapacitor side, realizing bidirectional energy transfer between the lithium battery pack and the supercapacitor pack. The control and communication system adopts a layered architecture coupling an outer power scheduling layer and an inner current control layer. The outer power scheduling layer converts the power command into an inductor current setpoint after smoothing it using a bis-S curve. The inner current control layer performs closed-loop tracking regulation of the inductor current based on an improved sliding mode control framework. The battery management subsystem is configured with a sparse pulse equalization strategy based on voltage change rate prediction. When the static voltage difference threshold and dynamic trend prediction conditions are met, the sparse pulse equalization strategy turns on the equalization branch of the equalization dissipation circuit in an intermittent pulse manner, and keeps the equalization branch off during non-pulse periods.

[0008] The principle and advantages of this scheme are as follows: In practical applications, the battery management subsystem monitors the voltage and rate of change of each cell in the lithium battery pack in real time through the sampling circuit. When a cell simultaneously meets the static voltage difference threshold condition and the dynamic trend prediction condition, it indicates that the current voltage deviation has reached the equalization trigger threshold and the voltage change rate indicates that the voltage difference is increasing. The control unit drives the equalization MOS transistor of the corresponding equalization branch to conduct in an intermittent pulse manner, so that the high-voltage cell releases excess power in the form of pulse through the equalization resistor. During non-pulse periods, the equalization branch is kept off and no current flows through the equalization resistor. The polarization voltage naturally decays during the cell's resting period to assist in voltage difference convergence.

[0009] This sparse pulse equalization strategy achieves forward prediction through voltage change rate, transforming the equalization action from a passive post-event response to an active trend intervention. It accurately triggers equalization in the early stages of voltage imbalance, avoiding the lag of traditional solutions that only start after the voltage difference has formed. At the same time, the intermittent pulse method significantly reduces the average conduction time and power consumption of the equalization circuit, so that the equalization resistor is in a zero-current off state during non-pulse periods. This greatly reduces continuous heat generation and energy loss, alleviating cell temperature rise and system thermal management pressure. Meanwhile, the concentrated energy dissipation during the pulse period ensures equalization speed and consistency, promoting effective convergence of cell voltage difference.

[0010] This solution solves several technical problems associated with traditional dissipative balancing, such as the difficulty in balancing heat loss and balancing effect due to continuous conduction, the lack of forward-looking prediction capability in passive post-event balancing, and the resulting increase in system power consumption, accelerated cell temperature rise, overheating safety risks, reduced usable capacity of battery packs, and shortened cycle life. While balancing low loss and high balancing efficiency, it effectively improves the usable capacity of battery packs, cycle life, and system operation safety.

[0011] Preferably, as an improvement, the battery management subsystem is configured with a sparse pulse equalization strategy based on voltage change rate prediction, wherein the equalization trigger determination of the sparse pulse equalization strategy simultaneously satisfies: Static voltage difference condition: voltage of the i-th cell series With the current highest single-cell voltage difference Greater than the static pressure difference threshold ; Dynamic trend prediction condition: the voltage change rate of the i-th cell string. Greater than the trend coefficient The product of the average rate of change of voltage of all cells; After triggering, the controller periodically... Intermittent equalization is activated, with a single activation duration of:

[0012] in The pulse coefficient, 0 < <1, To balance the resistance value, To balance the maximum allowable balancing current of the branch; The interval between adjacent pulses is: .

[0013] The beneficial effects of this improvement are: the battery management subsystem monitors the voltage and rate of change of each individual cell in the lithium battery pack in real time through a sampling circuit. When a certain individual cell simultaneously meets the static voltage difference condition and the dynamic trend prediction condition, the controller periodically... The equalization process is intermittently activated, with the duration of each activation adaptively determined by the voltage difference, while the interval between adjacent pulses remains off. This strategy achieves proactive prediction through the voltage change rate, transforming the equalization action from a passive, reactive response to an active trend intervention. It precisely triggers equalization in the early stages of voltage imbalance trends, avoiding the lag of traditional solutions that only initiate equalization after a voltage difference has formed.

[0014] The intermittent pulse mode significantly reduces the average conduction time and power consumption of the equalization circuit, so that the equalization resistor is in a zero-current off state during non-pulse periods, thereby greatly reducing continuous heat generation and energy loss, alleviating cell temperature rise and system thermal management pressure, while the concentrated energy dissipation during the pulse period ensures equalization speed and consistency, promoting effective convergence of cell voltage difference.

[0015] Preferably, as an improvement, the double S-curve smoothing plan divides the power command change process into seven stages: acceleration segment, acceleration segment, deceleration segment, constant speed segment, acceleration-deceleration segment, deceleration segment, and deceleration-deceleration segment, so that the first derivative of the power command is continuous, the second derivative is continuous, and the third derivative is bounded. The outer power scheduling layer will smooth the power command Converted to inductor current setpoint according to the mapping relationship :

[0016] Battery voltage, This is the voltage of the supercapacitor.

[0017] The beneficial effects of this improvement are as follows: By using a seven-segment double S-curve planning method, the power command and its first and second derivatives remain continuous, effectively suppressing the current surge and mechanical stress caused by power step jumps, avoiding transient overcurrent surges to the lithium battery pack and supercapacitor pack, reducing voltage and current stress on the power converter, and reducing electromagnetic interference and noise; at the same time, the boundedness of the third derivative ensures the smooth and controllable power change process, making the inductor current setpoint more consistent. The transition is smoother, avoiding the acceleration abrupt change problem at the inflection point of traditional linear ramp planning, thereby improving the dynamic quality of power dispatch and the stability of system response, and extending the service life of power switching tubes and energy storage components.

[0018] Preferably, as an improvement, the improved sliding mode control framework includes: Sliding surface constructed using the inductor current tracking error e and its integral term

[0019] in, For the target inductor current, This is the actual inductor current. , These are the parameters of the sliding surface; And the improved exponential approach law:

[0020] Among them, ε, , α and λ are positive constants. , , Boundary layer thickness and ; Saturation function The value is s / Φ when |s|≤Φ, and sgn(s) when |s|>Φ.

[0021] The beneficial effect of this improvement is that the inner current control layer constructs a sliding surface using the inductor current tracking error e and its integral term. Furthermore, an improved exponential reaching law is adopted, which introduces an adaptive gain term on top of the conventional exponential reaching term. The approach speed can be adaptively adjusted according to the absolute value of the sliding surface: when the system state is far from the sliding surface, the gain term approaches 1, ensuring a faster approach speed; when the system state is close to the sliding surface, the gain term increases, effectively suppressing chattering; simultaneously, through the power term... ( )and ( The combination of these terms provides a strong approaching force when far from the sliding surface, and a fine adjustment when approaching the sliding surface, using a large power term, in conjunction with a saturation function. A linearized smooth transition is achieved within the boundary layer. This improvement effectively resolves the contradiction between approach speed and chatter suppression in traditional sliding mode control. While accelerating the system response speed, it significantly reduces high-frequency chattering of the control quantity, reduces switching stress and electromagnetic interference on the power switch, improves the tracking accuracy of the inductor current and the robustness of the closed-loop system, and enables the power converter to maintain stable current control performance under parameter perturbations and load disturbances.

[0022] Preferably, as an improvement, the inner current control layer is further configured with a two-stage cascaded extended state observer, including: First-level extended state observer, configuring the first observer bandwidth For observing slowly changing low-frequency disturbances, the state equation is:

[0023] in, This is a first-order current observation value. This is a Level 1 disturbance observation. , ; For the input voltage of the converter, Where is the output voltage of the converter, D is the current duty cycle, and L is the inductance value of the power inductor. Second-level extended state observer, configuring the second observer bandwidth and Estimating residuals using first-order current As input to observe high-frequency disturbances, its state equation is:

[0024] in, These are secondary current observations. These are second-order disturbance observations. , ; The total disturbance estimate is And a feedforward is introduced to correct the equivalent control duty cycle:

[0025] in For the original equivalent control duty cycle, The equivalent control duty cycle after compensation.

[0026] The beneficial effect of this improvement is that the inner current control layer is configured with two cascaded extended state observers, one of which has a lower bandwidth. To observe slowly changing low-frequency disturbances, such as parameter drift caused by cell aging and internal resistance changes caused by temperature variations, the secondary extended state observer is configured with a high bandwidth. and This improvement uses the residual of the first-stage current estimation as input to observe high-frequency disturbances, such as switching noise and transient disturbances caused by load changes. The sum of the two-stage disturbance observations is used as the total disturbance estimate d(t) and introduced into the feedforward to compensate for and correct the original equivalent control duty cycle. This improvement achieves refined observation and compensation for wide-frequency domain disturbances through a cascaded observation structure with frequency band separation: the first-stage observer ensures steady-state estimation accuracy in the low-frequency band, while the second-stage observer ensures dynamic response speed in the high-frequency band, avoiding the trade-off between disturbance observation accuracy and response speed inherent in single-bandwidth observers. Simultaneously, the total disturbance feedforward compensation effectively offsets the impact of internal and external disturbances on the current control loop, significantly improving the system's anti-interference capability and control accuracy, reducing dependence on precise mathematical models, and enhancing the robust adaptive capability of the power converter under complex operating conditions.

[0027] Preferably, as an improvement, the inner current control layer is further configured with a di / dt feedback damping vibration suppression element: Rate of change of inductor current High-frequency resonant components are extracted using a high-pass filter; Constructing a damping feedback duty cycle ,in The damping coefficient is... This represents the rate of change of the high-frequency current after high-pass filtering. Amplitude limiting constraint is applied to the damping feedback duty cycle. ; The compensated equivalent control duty cycle Switching control duty cycle With the damping feedback duty cycle Combined into the final PWM output duty cycle: .

[0028] The beneficial effect of this improvement is that the inner current control layer can sample the rate of change of the inductor current. High-frequency resonant components are extracted using a high-pass filter, and a damping feedback duty cycle is constructed. After applying a limiting constraint to the damping feedback duty cycle, the final PWM output duty cycle is synthesized by combining it with the compensated equivalent control duty cycle and switching control duty cycle. This improvement introduces the high-frequency component of the inductor current change rate as active damping feedback, effectively increasing the damping coefficient of the converter in the resonant frequency band. This effectively suppresses the high-frequency LC resonance caused by parasitic parameters of the power inductor and input / output capacitors, avoiding damage to the power switching transistors and inductor cores from resonant current spikes. Simultaneously, high-pass filtering ensures that the damping feedback only acts on the high-frequency resonant band without affecting low-frequency control performance. The limiting constraint prevents overmodulation of the damping circuit under extreme disturbances, ensuring the system's stability margin. This improves the dynamic response quality of the inner current loop, reduces electromagnetic noise and conducted interference, and extends the reliable operating life of the power converter.

[0029] Preferably, as an improvement, the system is configured with a shockless switching strategy between Buck mode and Boost mode, and the shockless switching strategy is executed in the following sequence: Zero-crossing current detection uses a Hall sensor to monitor the inductor current in real time. ,when The current is determined to be zero when it falls below a set threshold. Turn off the active switch in the current mode, allowing the inductor to enter freewheeling mode until the current decays naturally. Dead-time wait, ensuring that the turn-off time of all switching transistors is greater than the turn-off delay of the MOSFETs; The new mode soft start starts the PWM of the new mode with zero duty cycle and gradually increases the duty cycle to the target value according to the double S curve plan; The sliding surface is reset, and the integral history error of the sliding controller is cleared after the switching is completed.

[0030] The beneficial effects of this improvement are as follows: The system is configured with a shockless switching strategy between Buck and Boost modes, executing in the sequence of current zero-crossing detection → turning off the active switch of the current mode → dead-time waiting → soft-start of the new mode → sliding surface reset. This improvement ensures that the inductor current naturally decays to near zero at the moment of switching through current zero-crossing detection, avoiding current surges and voltage spikes during load switching; turning off the active switch of the current mode allows the inductor to enter freewheeling state, and the dead-time waiting ensures reliable turn-off of the MOSFET and prevents short circuits between the upper and lower bridge arms; the new mode is soft-started with zero duty cycle and the duty cycle is gradually increased according to the double S-curve, avoiding current surges and voltage oscillations after mode switching; and the zeroing of the sliding surface integral history error eliminates integral saturation and state memory interference at the moment of switching. This solution effectively solves the power surge and electromagnetic interference problems caused by current surges, voltage spikes, and integral saturation in traditional mode switching, achieving a smooth and shockless transition between Buck / Boost bidirectional modes, protecting the power switch and energy storage components, and improving the dynamic reliability and mode switching quality of the hybrid energy storage system.

[0031] Preferably, as an improvement, the system is also configured with dual backflow prevention logic: The hardware anti-backflow layer utilizes the enable pin of the isolation driver chip, which is controlled by the current direction signal. When a reverse current trend is detected, the driver signal is blocked by hardware. The software anti-backflow layer verifies the consistency between the direction of the inductor current observed by the two-stage cascaded expansion state observer and the direction of the command current, and in conjunction with the hardware current zero-crossing detection output, allows mode switching to be performed only when the directions are consistent and the current has crossed zero.

[0032] The beneficial effects of this improvement are as follows: the system is equipped with dual protection through both hardware and software anti-backflow layers. The hardware layer utilizes the enable pin of the isolated driver chip, controlled by the current direction signal. When a reverse current trend is detected, the driver signal is blocked, achieving a nanosecond-level fast response. The software layer performs consistency verification between the inductor current direction observed by two cascaded extended state observers and the command current direction. Combined with hardware current zero-crossing detection output, mode commutation is only allowed when the directions are consistent and the current has crossed zero. This improvement constructs a deep protection system from rapid hardware blocking to intelligent software verification through a multi-factor verification mechanism involving both hardware and software. The hardware layer provides low-level rapid protection unaffected by software delays and faults, while the software layer achieves accurate judgment and logical interlocking of commutation conditions through state observation and direction verification. This effectively prevents current backflow caused by control timing errors, sensor failures, or electromagnetic interference, avoiding damage to the lithium battery pack and supercapacitor pack from backflow current and the risk of power converter failure. This significantly improves the operational safety and fault tolerance of the hybrid energy storage system.

[0033] Preferably, as an improvement, each equalization branch of the equalization dissipation circuit is connected in parallel with a small-capacity ceramic capacitor to filter out high-frequency noise caused by the switching of the MOS transistor.

[0034] The beneficial effects of this improvement are as follows: each balancing branch of the balancing dissipation circuit has a small-capacity ceramic capacitor connected in parallel across its terminals. This improvement utilizes the high-frequency, low-impedance characteristics of the ceramic capacitor to effectively filter out high-frequency noise and voltage spikes generated during MOSFET switching, suppressing electromagnetic interference to the battery sampling circuit caused by the balancing branch switching action, and improving voltage sampling accuracy and the reliability of balancing trigger determination. Simultaneously, the parallel capacitor absorbs the inductive spike energy at the moment of MOSFET turn-off, mitigating the impact of the voltage change rate dv / dt on the MOSFET's gate and source, reducing switching losses and EMI radiation, and protecting the balancing MOSFET from voltage stress damage, thereby improving the electromagnetic compatibility performance and long-term operational reliability of the balancing circuit. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating the overall system framework of an embodiment of the present invention.

[0036] Figure 2 This is a flowchart of the sparse pulse equalization strategy according to an embodiment of the present invention.

[0037] Figure 3 This is a flowchart illustrating the hierarchical control process according to an embodiment of the present invention. Detailed Implementation

[0038] The following detailed description illustrates the specific implementation method: Example This technical solution proposes a battery charge / discharge power conversion system with a supercapacitor, consisting of three parts: a battery management subsystem (BMS), a four-switch bidirectional Buck-Boost power conversion subsystem, and a control and communication system. The system realizes bidirectional energy transfer, charge / discharge control, status monitoring, and multi-level safety protection between the lithium battery pack and the supercapacitor, and is suitable for energy storage and power supply scenarios requiring high-power, fast response, and bidirectional energy flow.

[0039] The system topology adopts a four-switch, same-polarity Buck-Boost structure, ensuring that the input and output maintain the same polarity to avoid the risk of reverse connection. The bidirectional energy flow path is: lithium battery pack. Power converter The supercapacitor bank is managed by the BMS (Battery Management System), which is responsible for the state monitoring, equalization management, and safety protection of the lithium battery bank. The DSP (Digital Signal Processor) controller is responsible for the closed-loop control of the power converter and the execution of energy dispatch strategies. The two communicate with each other via a CAN bus to exchange status information and control commands.

[0040] The basics are as follows: Figure 1As shown, a battery charging and discharging power conversion system with a supercapacitor includes: The Battery Management Subsystem (BMS) uses the Zhongying SH367309 as the core control chip, and is equipped with charging and discharging drive circuits, equalization and dissipation circuits, sampling circuits, temperature detection circuits and EEPROM storage circuits to achieve comprehensive management of 16-cell lithium battery packs.

[0041] The charging and discharging circuit uses multiple MOSFETs to form the main power path. The CHG pin of the SH367309 controls the charging MOSFET. The DSG pin controls the conduction and cutoff of the discharge MOSFET. The on and off states.

[0042] During power-on startup, the pre-charge MOSFET is closed first. Through pre-charge resistor The input capacitor of the power converter is charged with current limiting. After the capacitor voltage approaches the battery pack voltage, the main MOSFET is then closed. This enables smooth startup and avoids surge current impact.

[0043] Each cell string is equipped with an independent equalization MOSFET. With dissipation resistance (i=1,2,…,16), forming a dissipative equilibrium branch.

[0044] Traditional dissipative equalization typically employs a fixed voltage threshold triggering control method. Once the voltage of a single cell reaches the set threshold, the equalization MOSFET and equalization resistor remain continuously turned on, dissipating excess power as heat to achieve voltage consistency between cells. To ensure fast equalization speed and good consistency, equalization needs to be on for extended periods with a high duty cycle, causing the equalization resistor to continuously heat up and its temperature to rise rapidly. This not only increases system power consumption but also accelerates cell aging and may even pose an overheating safety risk. Conversely, reducing the equalization on-time to decrease heat generation and losses leads to insufficient equalization, poor consistency improvement, and ineffective convergence of cell voltage differences, directly reducing the usable capacity and cycle life of the battery pack.

[0045] This solution introduces a sparse pulse equalization strategy based on voltage change rate prediction without changing the original dissipative equalization hardware structure, upgrading it from passive post-event equalization to active trend prediction and short-time pulse working mode.

[0046] As attached Figure 2 As shown, the balanced triggering determination logic is as follows: Let the voltage of the i-th cell be... Voltage change rate .

[0047] Balanced triggering requires two conditions to be met simultaneously: Static differential pressure threshold:

[0048] in, This is the highest single-cell voltage currently available; This is the static differential pressure threshold, which can be set to 50mV.

[0049] Dynamic trend prediction:

[0050] The trend coefficient is used to predict the voltage change rate and can be set to 2.0. If the voltage rise rate of the battery cell string is significantly higher than the average level of the group, it indicates that an imbalance trend is forming.

[0051] When both of the above conditions are met, the controller cycles... It can be set from 1s to 10s to intermittently activate equalization, with a single conduction duration of:

[0052] in, pulse coefficient (0 < <1), used to control the conduction duration of a single equalization pulse, can be 0.2-0.3; This refers to the voltage difference between battery cells; To balance the resistance value, To balance the maximum allowable balancing current of the branch MOSFETs, the interval between adjacent pulses is:

[0053] This solution can identify and initiate equalization before the cell imbalance fully develops, only when a voltage drift trend is observed. During the critical voltage drift window, equalization energy is injected in the form of short pulses, rather than continuous conduction. The equalization branch remains off during the remaining periods, fully utilizing the RC relaxation effect and natural voltage decay characteristics of the cell during rest to assist voltage difference convergence. This ensures equalization speed without relying on continuous energy consumption. Through this look-ahead, short-duration, intermittent sparse pulse control method, this solution effectively avoids the excessive equalization and severe heat generation problems caused by continuous conduction. While maintaining an equalization convergence speed and consistency improvement comparable to traditional continuous equalization, the effective duty cycle of the equalization circuit is significantly reduced to 10%~30%, thereby reducing the average heat generation power of the equalization branch by approximately 60%~70%. Each balancing branch is connected in parallel with a small-capacity ceramic capacitor. =100nF, used to filter out high-frequency noise caused by MOSFET switching, stabilize the individual voltage sampling node, and improve voltage sampling accuracy.

[0054] The sampling circuit includes voltage sampling, current sampling, and temperature sampling. Specifically, voltage sampling is achieved by connecting a 16-channel individual voltage setting resistor divider network to the SH367309's built-in multiplexed ADC, with a sampling accuracy of ±5mV; current sampling is achieved by connecting a sampling resistor in series in the main power circuit. The signal is amplified by an instrumentation amplifier and then sent to an ADC; temperature sampling is achieved by setting multiple NTC thermistors distributed at key locations in the battery pack, with a sampling interval of 1 second.

[0055] The protection logic covers multiple levels of protection, including overcharge, over-discharge, charging overcurrent, discharging overcurrent, short circuit, over-temperature, and under-temperature. Fault status is recorded in real time through register flag bits and uploaded via the CAN bus.

[0056] Specific circuit structure: In the charging, discharging, and balancing circuit of the battery management subsystem, the positive terminal of the battery is simultaneously connected to the charging MOSFET. Source and discharge MOSFETs The source and pre-charged MOSFET The source of the charging MOSFET; Controlled by the CHG pin of SH367309, the discharge MOSFET Controlled by the DSG pin, both drains are shorted and connected to the positive input P+ of the power converter; pre-charge MOSFET Drain series precharge resistor It is also connected to P+ for current-limited charging of the subsequent capacitor during the power-on phase; the battery's total negative terminal is directly connected to the power converter's input negative terminal P-, forming a common ground loop.

[0057] Each cell string corresponds to one balancing branch, which is powered by a balancing MOSFET. With equalization resistor The circuit is configured in series, with the source of the balancing MOSFET connected to the positive terminal of the battery cell, and the balancing resistor connected to the negative terminal. The gate of the balancing MOSFET is driven by an independent pin of the BMS, achieving dissipative balancing. Small-capacity ceramic capacitors are connected in parallel across each balancing branch to filter out noise. The individual cell voltage, charge / discharge current, and temperature are accessed through an independent sampling network to the ADC channel of the BMS chip, enabling real-time status acquisition.

[0058] The above connections are all conventional and well-known connections for lithium battery protection systems. Those skilled in the art can uniquely determine the circuit structure and implement it based on the above description.

[0059] In the EEPROM storage circuit, an I2C interface EEPROM chip, such as the AT24C256, is used to store protection threshold parameters, equalization coefficients, delay configurations, and operating history. It supports power-off data retention and online modification via a host computer. The equalization coefficient is as follows: , , Operational history, such as charge / discharge cycle count, cumulative ampere-hours, and fault records.

[0060] The four-switch bidirectional Buck-Boost power conversion subsystem adopts a four-switch same-polarity Buck-Boost topology and consists of a main control DSP, an isolation sampling circuit, a Hall current sampling circuit, an isolation drive circuit, and an auxiliary power supply circuit.

[0061] The four-switch Buck-Boost topology consists of power MOSFETs Q1~Q4, a power inductor L, and an input capacitor. Output capacitor Composition. Input capacitor Connect to the lithium battery side, output capacitor Connect to the supercapacitor side. Energy flow from the lithium battery to the supercapacitor is defined as positive, and the reverse as negative.

[0062] The supercapacitor bank is used as a high-power, fast-response energy storage buffer unit to withstand transient charging and discharging power surges and share the power stress of the lithium battery pack.

[0063] In a four-switch bidirectional Buck-Boost topology, there are Buck mode and Boost mode. In Boost mode, power switch Q1 remains normally on, Q2 remains off, and Q4 and Q3 perform high-frequency complementary switching to achieve boost regulation. Q3 acts as a synchronous rectifier and conducts during the freewheeling phase. Energy flows from the lithium battery side to the supercapacitor side. In Buck mode, power switch Q3 remains normally on, Q4 remains off, and Q1 and Q2 perform high-frequency complementary switching to achieve buck regulation. Q2 acts as a synchronous rectifier and conducts during the freewheeling phase. Energy flows from the supercapacitor side to the lithium battery side. During the mode switching transition, a soft-start sequence and current zero-crossing detection technology enable seamless switching between the two modes.

[0064] Voltage isolation sampling: A Nanochip NSI1311 isolation amplifier is used for sampling the lithium battery side voltage. With over-electric side voltage After resistor voltage division and isolation acquisition, the voltage division ratio is 1:100, and then converted into a 0~3.3V low voltage signal and sent to the DSP ADC. The isolation withstand voltage is 5000Vrms, and the linearity is 0.1%.

[0065] Current sampling: Employs a Coretech CC6920 bidirectional Hall current sensor with a range of ±50A and a sensitivity of 40mV / A to detect inductor current. Lossless sampling is achieved. The Hall output is then fed into the DSP ADC after passing through an RC low-pass filter, with the RC low-pass filter cutoff frequency being 10kHz.

[0066] Isolation Driver: Utilizing the Naxin Micro NSi6602 dual-channel isolation driver chip, it receives the complementary PWM signal with dead time output from the DSP to drive the high-side and low-side MOSFETs. The dead time is configured by the DSP hardware module, such as 200ns, to prevent shoot-through between the high and low-side MOSFETs.

[0067] Auxiliary power supply: A flyback isolated power supply is used to convert the battery voltage into 12V, 5V and 3.3V multi-channel regulated outputs respectively; 12V is used for drive power supply, 5V is used for Hall sensor and communication power supply, and 3.3V is used for DSP and sampling chip power supply; power ground and signal ground are electrically isolated through isolation transformer and optocoupler.

[0068] Specific circuit structure: The four-switch bidirectional Buck-Boost converter consists of power switches Q1, Q2, Q3, Q4, power inductor L, and lithium battery-side input capacitor. and supercapacitor side output capacitor Composition. Q1 drain is connected to the positive electrode of the lithium battery. +, the source of Q2 is connected to the left end of the power inductor L; the drain of Q2 is connected to the left end of the inductor L, and the source is connected to the system power ground GND; the drain of Q3 is connected to the positive terminal of the supercapacitor. +, the source of Q1 is connected to the right end of inductor L; the drain of Q4 is connected to the right end of inductor L, and the source is connected to system power ground GND. In Boost mode, Q1 is normally on and Q2 is off, Q4 and Q3 are high-frequency complementary switches, and Q3 operates as a synchronous rectifier; in Buck mode, Q3 is normally on and Q4 is off, Q1 and Q2 are high-frequency complementary switches, and Q2 operates as a synchronous rectifier.

[0069] Both the lithium battery side and the supercharger side achieve voltage sampling through the isolation amplifier NSI1311, and the inductor current is sampled without loss through the CC6920 bidirectional Hall sensor; the four PWM signals drive Q1-Q4 respectively through the NSi6602 isolation driver chip, and the auxiliary power supply provides 12V, 5V and 3.3V multi-channel isolated power supply.

[0070] The battery management subsystem described in this embodiment includes charge / discharge drive, equalization dissipation, sampling protection circuitry, and a four-switch bidirectional Buck converter. The main power topology, isolated sampling, isolated drive, and auxiliary power supply circuit of the Boost power conversion subsystem are all conventional and mature circuit structures in the field. With the connection nodes, potential relationships, drive timing, and signal flow of all key components such as power switches, inductors, capacitors, resistors, sampling sensors, driver chips, and power supplies fully described, those skilled in the art can draw a complete circuit diagram and implement it without ambiguity based on the textual description. There are no technical defects such as unclear descriptions or impossibilities.

[0071] The four-switch bidirectional Buck-Boost power conversion subsystem adopts a layered architecture: the outer power scheduling layer is responsible for power allocation decisions between the lithium battery and the supercapacitor; the inner current control layer is responsible for the closed-loop regulation of the power converter's current. The two layers are connected by a current setpoint. coupling.

[0072] As attached Figure 3 As shown, if the power command issued by the host computer is directly put into use, its step-like change will cause a sharp jump in the inductor current, forming a transient current surge and voltage spike, affecting the charging stability and threatening the safety of the device. This solution introduces a double S-curve smoothing planning algorithm from the field of robot motion control to process the power command issued by the host computer. Smoothing preprocessing is performed to achieve a shock-free transition of power commands. The bis-s curve programming requires that the third derivative of power with respect to time be continuous, satisfying the following relationship: Assume that the change in power command must satisfy the continuity of jerk J, that is, the derivative of power P with respect to time satisfies:

[0073] Where J(t) is a piecewise constant: taken during the acceleration phase. Take 0 for the constant speed segment and 0 for the deceleration segment. .

[0074] Integrating sequentially, we obtain: (Power change acceleration) (rate of power change) (Smoothed power command) Planning constraints include: maximum acceleration Maximum speed Starting power Endpoint power .

[0075] The smoothing process of the double S-curve is divided into seven stages: acceleration, deceleration, constant speed, acceleration / deceleration, and deceleration / deceleration. Each stage corresponds to a different derivative of the power command. Acceleration segment: Third derivative (jerk) The second derivative (power acceleration) continues to rise; Acceleration phase: Third derivative The second derivative remains constant, while the first derivative (power change rate) increases at a constant rate. Deceleration / Acceleration Phase: Third Derivative The second derivative gradually decreases to zero; In the uniform velocity phase: the first derivative remains constant, and the power changes smoothly; Acceleration / deceleration phase: Third derivative The second derivative increases in the opposite direction; Deceleration phase: Third derivative The second derivative is constant, while the first derivative decreases at a constant rate. Deceleration phase: Third derivative The second derivative gradually returns to zero.

[0076] The plan ensures that the first derivative (power change rate) of the power command is continuous, the second derivative (acceleration) is continuous, and the third derivative (jerk) is bounded, thus eliminating current spikes caused by power command step changes at the source.

[0077] After smoothing is complete, the smoothing power command needs to be... It needs to be converted to the inductor current setpoint. Based on power conservation (ignoring converter losses), a simplified mapping relationship is adopted using a safety-priority control level, as follows:

[0078] in, Get the current battery voltage With supercapacitor voltage The smaller of the two voltages is used as the denominator to ensure that the current setpoint is within the physically feasible range. This mapping employs a conservative estimation strategy, using the smaller of the two voltages as the denominator to ensure that the current setpoint is within the physically feasible range, avoiding control failure caused by duty cycle saturation, and can be updated in real time to adapt to dynamic changes in the two voltages. In this scheme, this mapping is only used to generate the current setpoint for control; the actual current tracking accuracy is guaranteed by the sliding mode controller and is not affected by this simplified model.

[0079] The simplified mapping is acceptable when the voltage difference between the two sides is greater than 10%; when the voltages are close, the system limits the maximum duty cycle change rate, and the deviation is corrected by the sliding mode controller in a closed loop.

[0080] The inner current loop employs an improved sliding mode control framework to address the technical contradiction between current overshoot and response speed during mode switching in bidirectional Buck-Boost converters. The sliding surface is defined by the inductor current tracking error and its differential and integral terms, as follows:

[0081]

[0082]

[0083] Where e is the current error, For the target inductor current, This is the actual inductor current. is the current error rate; s is the sliding surface, i.e., the total error index; , These are the parameters of the sliding surface; Used to amplify errors; The integral term is used to eliminate steady-state error, ensuring that the current is neither too low nor too high. The introduction of the integral term eliminates steady-state error, overcoming the problem of steady-state error in traditional PD-type sliding mode surfaces under constant disturbances.

[0084] To balance approaching speed and chatter suppression, an improved exponential approaching law is designed:

[0085] In the formula, ε is the rate of change of the sliding surface; , α and λ are positive constants. λ>0 is the gain adjustment coefficient. The smaller λ is, the greater the far-field approach gain and the faster the convergence speed; the larger λ is, the closer the approach gain is to 1 and the smoother the convergence. ε represents the rate of approach; α represents the rate of exponential decay; λ is the smoothing coefficient. , To control the intensity; , The coefficients are power coefficients, satisfying , .

[0086] The saturation function replaces the traditional symbolic function sgn(s):

[0087] Boundary layer thickness , and 1 Ensure that the boundary layer falls entirely within the near-field region |s|<1 of the power term. When the system state is outside the boundary layer (|s|>Φ), the saturation function is equivalent to the sign function, ensuring rapid convergence; when it enters the boundary layer (|s|≤Φ), the control quantity changes continuously, effectively suppressing chattering.

[0088] Index Term The function of this term is: when |s| is large, this term approaches (1+λ) / λ>1, which enhances the approach speed; when |s| is small, this term approaches 1, which avoids excessive switching gain that could cause chattering.

[0089] In the formula, ( This is used to enhance the convergence speed near the origin and improve steady-state accuracy. ( This is used to enhance convergence speed far from the origin and improve dynamic response. The parallel combination of double-power terms ensures non-singularity throughout, balancing speed in the long term with stability in the short term.

[0090] Based on the state-space averaged model of the Buck-Boost topology, the dynamic equation for the inductor current is:

[0091] Where L is inductance, Input voltage, Where D is the output voltage and D is the duty cycle. The equivalent series resistance of the inductor. This represents the actual current.

[0092] make =0, thus obtaining the equivalent control quantity that maintains the system's operation on the sliding surface:

[0093] in, It is the rate of change of the reference inductor current, a known quantity obtained through pre-analytical calculation using the bis-s curve power smoothing programming, used to replace the differential of the actual current that cannot be directly measured. .

[0094] The switching control variable used to drive rapid convergence of the driving state is obtained from the improved exponential reaching law:

[0095] in, This is to effectively control the duty cycle and stabilize the current. The duty cycle is used for bias correction, enabling current tracking quickly and without jitter.

[0096] To compensate for lumped disturbances such as input voltage fluctuations, inductor parameter errors, dead-zone effects, and device voltage drops, this scheme employs a two-stage cascaded extended state observer (CESO) to perform real-time observation and feedforward compensation of the total system disturbance.

[0097] Definition of lumped disturbance: The uncertainty in the dynamic equation of the inductor current is unified into a lumped disturbance d(t):

[0098] in, Where L is the inductor current and L is the power inductance value; This refers to the input voltage of the converter. d(t) represents the output voltage of the converter; D is the current duty cycle. d(t) represents the lumped disturbance, including input voltage fluctuations. Inductance deviation Equivalent voltage loss caused by dead time MOSFET on-state voltage drop wait.

[0099] The cascaded extended state observer design expands d(t) into a new system state, letting:

[0100]

[0101] Level 1 ESO (Low-Frequency Disturbance Observer): Bandwidth Observe slowly changing disturbances, such as temperature drift, parameter aging, and slow voltage shift; its state equation is:

[0102] in, This is a first-order current observation value. This is a Level 1 disturbance observation. , For the first-level observer gain, , ; The error in the first-stage current observation drives the convergence of the first-stage observer.

[0103] Second-level ESO (High-Frequency Disturbance Observer): Bandwidth The residual of the current estimation of the first stage was observed. It is specifically designed to capture high-frequency disturbances that have not been processed by the first stage, and its state equation is:

[0104] in, These are secondary current observations. These are second-order disturbance observations. , For the second-level observer gain; , .

[0105] Adding the two estimates together and multiplying by the inductance L to restore the actual disturbance voltage, we obtain the total disturbance estimate:

[0106] This cascaded structure avoids the excessive amplification of high-frequency noise by a single high-gain observer, achieving an optimal balance between perturbation observation speed and noise suppression.

[0107] Total disturbance estimate Feedforward compensation is introduced to correct the equivalent duty cycle:

[0108] in, This is the original equivalent control duty cycle; This is the compensated equivalent duty cycle; through this compensation, the sliding mode controller only needs to handle a small amount of observation error, which can significantly reduce the switching gain and further suppress chattering.

[0109] At the instant the power switch operates, the parasitic inductance and capacitance of the PCB, along with the junction capacitance of the MOSFET, form a high-frequency resonant branch. This causes high-frequency ringing and spikes in the inductor current, threatening device safety and increasing electromagnetic interference. Therefore, a di / dt feedback damping vibration suppression circuit is implemented. Rate of change of inductor current High-frequency resonant components are extracted using a high-pass filter, for example, with a cutoff frequency of 50kHz; and a damping feedback duty cycle is constructed.

[0110] in This is the damping coefficient, used to adjust the vibration suppression intensity; The duty cycle is used for damping compensation; HF represents the high-frequency components after high-pass filtering. This represents the rate of change of the high-frequency current after high-pass filtering.

[0111] This feedback is equivalent to adding a virtual damping resistor in the resonant circuit, which quickly consumes the resonant energy and suppresses current spikes and oscillations.

[0112] To avoid the high-frequency compensation affecting the system's steady-state operating point, a limiting constraint is set on the damping duty cycle:

[0113] in, The upper limit of the damping duty cycle is set to 0.05 in this embodiment. The bandwidth of the di / dt damping loop is about 100kHz, which is much higher than the bandwidth of the current loop of about 2kHz. The two are decoupled from each other in the frequency domain and will not affect the dynamic performance of the main sliding mode controller.

[0114] The compensated equivalent control duty cycle Switching control duty cycle Duty cycle with damping compensation By combining the results, the final PWM output duty cycle is obtained:

[0115] Will The output is sent to the PWM register of the DSP to drive the power switching transistor.

[0116] The system operates in a bidirectional energy flow scenario, requiring frequent switching between Buck and Boost modes. To avoid current surges, voltage overshoots, and device stress during switching, this solution employs a shockless switching strategy involving zero-crossing current detection, soft start, and smooth transition between Buck and Boost modes.

[0117] The Buck / Boost mode switching process includes: Zero-crossing current detection uses a Hall sensor to monitor the inductor current in real time. ,when This embodiment sets the current to zero-crossing condition. The current is 0.5A, corresponding to a CC6920 output of 20mV. It needs to be used with a 10ms moving average filter to avoid noise-induced false triggering. PWM shutdown first turns off the active switching transistor of the current mode, allowing the inductor to enter freewheeling state and wait for the inductor current to decay naturally to zero. Dead zone wait, keep all switching transistors off for a period of time. , >MOSFET turn-off delay; ensures that the original mode switching transistor is completely turned off to avoid shoot-through; The new mode soft start starts the PWM of the new mode with zero duty cycle, and gradually increases the duty cycle to the target value according to the double S curve plan; Reset the sliding surface. After switching, reset the sliding surface area components to avoid the accumulation of historical errors that could lead to impact.

[0118] This sequence ensures passive switching through current zero-crossing detection and active smooth transition through double S-curve soft start, achieving shock-free commutation.

[0119] The voltage of a supercapacitor may be higher than that of a lithium battery, posing a risk of energy flowing back into the battery. The system employs both hardware and software anti-backflow logic: Hardware layer: The enable pin of the driver chip NSi6602 is controlled by the current direction signal. When a reverse current trend is detected, the driver is blocked by hardware. Software layer: The direction of inductor current observed by cascaded ESO is consistent with the direction of command current to generate a valid direction signal; at the same time, the zero-crossing flag is output by hardware current zero-crossing detection; mode switching is only allowed when the directions are consistent and the current has crossed zero to avoid reverse backflow and shoot-through risks.

[0120] The control and communication system adopts a dual-interrupt hierarchical control architecture, combined with a DSP real-time scheduling mechanism, to allocate control tasks with different real-time requirements to scheduling units with different cycles, thereby achieving a reasonable match between complex algorithms and hardware computing power.

[0121] For example, the high-speed interrupt cycle is set to 20μs, which mainly completes core control tasks that are strongly related to current, such as inductor current sampling, sliding surface calculation, total duty cycle synthesis, and PWM register refresh. The medium-speed interrupt cycle is set to 100μs, which is used to perform cascaded ESO disturbance observer state update, di / dt damping vibration suppression calculation, working mode state machine jump and multi-level fault protection logic judgment. The 1ms main loop cycle is responsible for non-real-time tasks such as double S-curve power smoothing planning, CAN data transmission and reception, and EEPROM operation history storage.

[0122] By using a three-level task hierarchical scheduling system, high real-time control tasks can be prioritized for execution, while avoiding waste of computing resources and program overload, thus improving system stability.

[0123] In terms of communication, the system adopts the CAN 2.0B extended frame communication protocol with a baud rate of 500kbps to realize reliable command interaction and status data upload between the host computer and the lower controller.

[0124] The system comprises several key components: frame ID 0x100 is used by the host computer to send power commands, charge / discharge direction commands, and system start / stop control commands to the slave computer; frame ID 0x200 is used by the slave computer to upload information about the battery pack's total voltage, charge / discharge current, estimated SOC, and highest and lowest individual cell voltages to the host computer; frame ID 0x201 is used to upload information about the supercapacitor's voltage, current, and temperature; and frame ID 0x300 is used to upload system fault codes, protection action status, and a bitmap showing the equalization status. The system supports remote setting of charge / discharge direction, current or power limits, and start / stop commands, and can upload the entire system's operating status in real time, enabling remote monitoring and debugging.

[0125] A battery charging and discharging power conversion system with a supercapacitor executes in an orderly manner according to the complete logic of initialization, standby, startup, operation, commutation, and fault protection after power-on, realizing fully automated, stable, and safe operation.

[0126] During the power-on initialization phase, the BMS first performs a comprehensive inspection of the 16-cell lithium battery pack, checking the individual cell voltages, total voltage, temperature, and fault status. After confirming no abnormalities, it closes the pre-charge MOSFET and performs current-limited soft charging of the power converter input capacitors through the pre-charge resistor. When the capacitor voltage approaches the battery pack voltage, it turns off the pre-charge MOSFET and switches to the main discharge MOSFET for power supply, completing a smooth power-on start-up. Simultaneously, the DSP completes peripheral initialization, register configuration, and EEPROM parameter loading, entering a state waiting for CAN commands.

[0127] In standby mode, the power converter stops working, the BMS continuously monitors the battery pack's various states and keeps protection functions enabled, and the supercapacitor and lithium battery pack maintain electrical isolation with no energy flow. During startup, after receiving a power command from the host computer, the BMS comprehensively determines whether charging and discharging are permitted based on the current battery SOC, temperature, and fault status. If the conditions are met, the DSP initiates a dual S-curve power smoothing algorithm to convert the command into a shock-free inductor current setpoint.

[0128] During normal operation, the system employs a tiered interrupt execution control logic: high-speed interrupts perform current sampling, sliding mode closed-loop calculation, and PWM duty cycle refresh; medium-speed interrupts perform ESO disturbance observation, di / dt damping vibration suppression, and operating mode state machine scheduling; the DSP adjusts the duty cycle in real time to ensure fast and stable current tracking of commands. During the commutation transition phase, when the energy flow direction needs to be switched, the system automatically performs a series of operations, including current zero-crossing detection, PWM shutdown, dead-time waiting, double-S soft start, and sliding mode surface reset, to achieve low-impact, low-peak switching between Buck mode and Boost mode.

[0129] During the fault handling phase, if the BMS detects faults such as overcharge, over-discharge, overcurrent during charging / discharging, short circuit, overtemperature, or undertemperature, it immediately reports the fault information to the host computer via the CAN bus and performs protective actions such as shutting down the charging / discharging MOSFET and blocking the power converter drive. If the DSP detects faults such as overcurrent, overvoltage, or abnormal drive, it will immediately block the PWM output in hardware and simultaneously notify the BMS to perform linkage protection to ensure the safety of the system and battery pack.

[0130] The above descriptions are merely embodiments of the present invention, and common knowledge such as specific technical solutions and / or characteristics are not described in detail here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical solutions of the present invention, and these should also be considered within the scope of protection of the present invention. These modifications and improvements will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A battery charging and discharging power conversion system with a supercapacitor, characterized in that, include: The battery management subsystem includes a charging and discharging drive circuit with a battery management chip as its core, an equalization and dissipation circuit, and a sampling circuit, which are used to monitor the state of the lithium battery pack, manage the equalization, and provide multi-level safety protection. The four-switch bidirectional Buck-Boost power conversion subsystem adopts a four-switch same-polarity Buck-Boost topology and consists of power switches Q1~Q4, power inductor L, input capacitor connected to the lithium battery side and output capacitor connected to the supercapacitor side, realizing bidirectional energy transfer between the lithium battery pack and the supercapacitor pack. The control and communication system adopts a layered architecture coupling an outer power scheduling layer and an inner current control layer. The outer power scheduling layer converts the power command into an inductor current setpoint after smoothing it using a bis-S curve. The inner current control layer performs closed-loop tracking regulation of the inductor current based on an improved sliding mode control framework. The battery management subsystem is configured with a sparse pulse equalization strategy based on voltage change rate prediction. When the static voltage difference threshold and dynamic trend prediction conditions are met, the sparse pulse equalization strategy turns on the equalization branch of the equalization dissipation circuit in an intermittent pulse manner, and keeps the equalization branch off during non-pulse periods.

2. The battery charging and discharging power conversion system with a supercapacitor according to claim 1, characterized in that: The battery management subsystem is configured with a sparse pulse equalization strategy based on voltage change rate prediction. The equalization trigger determination of the sparse pulse equalization strategy simultaneously satisfies the following: Static voltage difference condition: voltage of the i-th cell series With the current highest single-cell voltage difference Greater than the static pressure difference threshold ; Dynamic trend prediction condition: the voltage change rate of the i-th cell string. Greater than the trend coefficient The product of the average rate of change of voltage of all cells; After triggering, the controller periodically... Intermittent equalization is activated, with a single activation duration of: in The pulse coefficient, 0 < <1, To balance the resistance value, To balance the maximum allowable balancing current of the branch; The interval between adjacent pulses is: .

3. The battery charging and discharging power conversion system with a supercapacitor according to claim 2, characterized in that: The bis-curve smoothing program divides the power command change process into seven stages: acceleration, deceleration, constant speed, acceleration-deceleration, deceleration, and deceleration-deceleration, making the first derivative of the power command continuous, the second derivative continuous, and the third derivative bounded. The outer power scheduling layer will smooth the power command Converted to inductor current setpoint according to the mapping relationship : Battery voltage, This is the voltage of the supercapacitor.

4. A battery charging and discharging power conversion system with a supercapacitor according to claim 3, characterized in that: The improved sliding mode control framework includes: Sliding surface constructed using the inductor current tracking error e and its integral term in, For the target inductor current, This is the actual inductor current. , These are the parameters of the sliding surface; And the improved exponential approach law: Among them, ε, , α and λ are positive constants. , , Boundary layer thickness and ; Saturation function The value is s / Φ when |s|≤Φ, and sgn(s) when |s|>Φ.

5. A battery charging and discharging power conversion system with a supercapacitor according to claim 4, characterized in that: The inner current control layer is also equipped with two cascaded extended state observers, including: First-level extended state observer, configuring the first observer bandwidth For observing slowly changing low-frequency disturbances, the state equation is: in, This is a first-order current observation value. This is a Level 1 disturbance observation. , ; For the input voltage of the converter, Where is the output voltage of the converter, D is the current duty cycle, and L is the inductance value of the power inductor. Second-level extended state observer, configuring the second observer bandwidth and Estimating residuals using first-order current As input to observe high-frequency disturbances, its state equation is: in, These are secondary current observations. These are second-order disturbance observations. , ; The total disturbance estimate is And a feedforward is introduced to correct the equivalent control duty cycle: in For the original equivalent control duty cycle, The equivalent control duty cycle after compensation.

6. The battery charging and discharging power conversion system with a supercapacitor according to claim 5, characterized in that: The inner current control layer is also equipped with a di / dt feedback damping vibration suppression element: Rate of change of inductor current High-frequency resonant components are extracted using a high-pass filter; Constructing a damping feedback duty cycle ,in The damping coefficient is... This represents the rate of change of the high-frequency current after high-pass filtering. Amplitude limiting constraint is applied to the damping feedback duty cycle. ; The compensated equivalent control duty cycle Switching control duty cycle With the damping feedback duty cycle Combined into the final PWM output duty cycle: 。 7. A battery charging and discharging power conversion system with a supercapacitor according to claim 6, characterized in that: The system is configured with a shockless switching strategy between Buck mode and Boost mode, and the shockless switching strategy is executed in the following sequence: Zero-crossing current detection uses a Hall sensor to monitor the inductor current in real time. ,when The current is determined to be zero when it falls below a set threshold. Turn off the active switch in the current mode, allowing the inductor to enter freewheeling mode until the current decays naturally. Dead-time wait, ensuring that the turn-off time of all switching transistors is greater than the turn-off delay of the MOSFETs; The new mode soft start starts the PWM of the new mode with zero duty cycle and gradually increases the duty cycle to the target value according to the double S curve plan; The sliding surface is reset, and the integral history error of the sliding controller is cleared after the switching is completed.

8. A battery charging and discharging power conversion system with a supercapacitor according to claim 7, characterized in that: The system is also equipped with dual backflow prevention logic: The hardware anti-backflow layer utilizes the enable pin of the isolation driver chip, which is controlled by the current direction signal. When a reverse current trend is detected, the driver signal is blocked by hardware. The software anti-backflow layer verifies the consistency between the direction of the inductor current observed by the two-stage cascaded expansion state observer and the direction of the command current, and in conjunction with the hardware current zero-crossing detection output, allows mode switching to be performed only when the directions are consistent and the current has crossed zero.

9. A battery charging and discharging power conversion system with a supercapacitor according to claim 8, characterized in that: Each equalization branch of the equalization dissipation circuit has a small-capacity ceramic capacitor connected in parallel across its two ends to filter out high-frequency noise caused by the switching of the MOS transistor.

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