A phase-shifted full-bridge and synchronous rectification PWM module and signal output method

Abstract

This invention discloses a phase-shifted full-bridge and synchronous rectification PWM module and its signal output method. The phase-shifted full-bridge and synchronous rectification PWM module includes a dead-time generation unit and an edge detection and delay unit. The dead-time generation unit outputs a first PWM signal and a second PWM signal based on the PWM input signal. The first and second PWM signals are inversely complementary and have a dead time. The edge detection and delay unit delays the signal based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third, fourth, fifth, and sixth PWM signal. The technical solution of this invention enables the phase-shifted full-bridge and synchronous rectification PWM module to control the leading arm, lagging arm, and synchronous rectification switch of the phase-shifted full-bridge. The phase-shifted full-bridge and synchronous rectification PWM module only requires two input interfaces, which are simple, easy to integrate, and reduce costs.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and in particular to a phase-shifted full-bridge and synchronous rectification PWM module and a signal output method. Background Technology

[0002] The phase-shifted full-bridge converter is a highly efficient power electronic converter topology widely used in DC-DC conversion, inverters, high-frequency power supplies, and other fields. The phase-shifted full-bridge circuit achieves phase regulation of the output voltage and power transfer by controlling the on and off times of the switching devices in the full-bridge circuit. Its core lies in using the junction capacitance of the power devices and the leakage inductance of the transformer as resonant elements to enable the switching transistors to achieve zero-voltage switching (ZVS), thereby achieving soft switching and reducing switching losses.

[0003] In the prior art, some microcontroller units (MCUs) have a peripheral generic timer module (GTM) that can control the leading and lagging arms of the phase-shifted full-bridge using a dead-time modulator (DTM).

[0004] However, the above technical solutions cannot control the secondary synchronous rectifier switch using only GTM, and the cost of using chips that integrate GTM is relatively high. Summary of the Invention

[0005] This invention provides a phase-shifted full-bridge and synchronous rectification PWM module and signal output method, which enables the control of the leading arm, lagging arm and synchronous rectification switch of the phase-shifted full-bridge through the phase-shifted full-bridge and synchronous rectification PWM module, thereby reducing costs.

[0006] According to one aspect of the present invention, a phase-shifted full-bridge and synchronous rectification PWM module is provided, the phase-shifted full-bridge and synchronous rectification PWM module including a dead time generation unit and an edge detection and delay unit; The dead time generation unit is used to output a first PWM signal and a second PWM signal according to the PWM input signal; wherein, the first PWM signal and the second PWM signal are a pair of inversely complementary drive signals with dead time, the first PWM signal is used as the upper bridge drive signal of the advanced bridge arm, and the second PWM signal is used as the lower bridge drive signal of the advanced bridge arm. The edge detection and delay unit is used to delay based on the transition edge of the PWM input signal or the transition edge of the first current limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal. The effective level period of the fifth PWM signal overlaps with the first period, but does not overlap with the second period. The effective level period of the sixth PWM signal overlaps with the second period, but does not overlap with the first period. The first period is when both the first PWM signal and the fourth PWM signal are at effective levels, and the second period is when both the second PWM signal and the third PWM signal are at effective levels. The third PWM signal and the fourth PWM signal are a pair of inversely complementary drive signals with dead time. The third PWM signal serves as the upper bridge drive signal of the lagging bridge arm, and the fourth PWM signal serves as the lower bridge drive signal of the lagging bridge arm. The fifth PWM signal serves as the drive signal of the first rectifier switch, and the sixth PWM signal serves as the drive signal of the second rectifier switch.

[0007] Optionally, the edge detection and delay unit includes a first edge detection and delay subunit, a second edge detection and delay subunit, a third edge detection and delay subunit, and a fourth edge detection and delay subunit. The first edge detection and delay subunit is used to generate the rising or falling edge of the third PWM signal after delaying the detected edge event, and output the third PWM signal. The second edge detection and delay subunit is used to generate the rising or falling edge of the fourth PWM signal after delaying the detected edge event, and output the fourth PWM signal. The third edge detection and delay subunit is used to generate the rising or falling edge of the fifth PWM signal after delaying the detected edge event, and output the fifth PWM signal. The fourth edge detection and delay subunit is used to generate the rising or falling edge of the sixth PWM signal after delaying the detected edge event, and output the sixth PWM signal. The rising edge event is at least one of the four rising edge events from the PWM input signal and the first current limiting input signal; the rising edge and falling edge of the same PWM signal correspond to different rising edge events.

[0008] Optionally, when the edge-jumping event includes at least two of the four edge-jumping events from the PWM input signal and the first current-limiting input signal, an OR operation is performed on at least two edge-jumping events.

[0009] Optionally, the phase-shifted full-bridge and synchronous rectification PWM module in this embodiment of the invention further includes a blanking window unit; The blanking window unit receives the second current-limiting input signal. The blanking window unit is used to insert the first time window after detecting the rising edge event and falling edge event of the PWM input signal, respectively. Within the first time window, the state of the second current-limiting input signal remains the same as the previous moment of the first time window, thus obtaining the first current-limiting input signal.

[0010] According to another aspect of the present invention, a signal output method for a phase-shifted full-bridge and synchronous rectification PWM module is provided, applicable to any phase-shifted full-bridge and synchronous rectification PWM module of the present invention. The signal output method for the phase-shifted full-bridge and synchronous rectification PWM module of the present invention includes: The dead time generation unit outputs a first PWM signal and a second PWM signal according to the PWM input signal; wherein, the first PWM signal and the second PWM signal are a pair of inversely complementary drive signals with dead time, the first PWM signal is used as the upper bridge drive signal of the advanced bridge arm, and the second PWM signal is used as the lower bridge drive signal of the advanced bridge arm. The edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal. The effective level period of the fifth PWM signal overlaps with the first time period, but does not overlap with the second time period. The effective level period of the sixth PWM signal overlaps with the second time period, but does not overlap with the first time period. The first time period is when both the first and fourth PWM signals are at effective levels, and the second time period is when both the second and third PWM signals are at effective levels. The third and fourth PWM signals are a pair of inversely complementary drive signals with dead time. The third PWM signal serves as the upper bridge drive signal for the lagging bridge arm, and the fourth PWM signal serves as the lower bridge drive signal for the lagging bridge arm. The fifth PWM signal serves as the drive signal for the first rectifier switch, and the sixth PWM signal serves as the drive signal for the second rectifier switch.

[0011] Optionally, the edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal, including: The first edge detection and delay subunit generates the rising edge or falling edge of the third PWM signal after delaying the detected edge event, and outputs the third PWM signal. The second edge detection and delay subunit generates the rising or falling edge of the fourth PWM signal after delaying the detected edge event, and outputs the fourth PWM signal. The third edge detection and delay subunit generates the rising or falling edge of the fifth PWM signal after delaying the detected edge event, and outputs the fifth PWM signal. The fourth edge detection and delay subunit generates the rising or falling edge of the sixth PWM signal after delaying the detected edge event, and outputs the sixth PWM signal. The rising edge event is at least one of the four rising edge events from the PWM input signal and the first current limiting input signal; the rising edge and falling edge of the same PWM signal correspond to different rising edge events.

[0012] Optionally, the dead-time generation unit outputs a first PWM signal and a second PWM signal based on the PWM input signal, including: The rising edge of the first PWM signal is triggered after a delay time is inserted after the rising edge event of the PWM input signal is detected, and the falling edge of the first PWM signal is triggered after the falling edge event of the PWM input signal is detected. The rising edge of the second PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected, and the falling edge of the second PWM signal is triggered after the rising edge event of the PWM input signal is detected.

[0013] Optionally, the edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal, including: The rising edge of the third PWM signal is triggered after a delay time is inserted after the rising edge event of the first current limiting input signal is detected; or, the rising edge of the third PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected. The rising edge of the fourth PWM signal is triggered after a delay time is inserted after the falling edge event of the first current limiting input signal is detected; or, the rising edge of the fourth PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected. The falling edge of the fourth PWM signal is triggered after a delay time is inserted after the falling edge event of the first current limiting input signal is detected; or, the falling edge of the fourth PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected. The rising edge of the fifth PWM signal is triggered after a delay time is inserted after the rising edge event of the first current limiting input signal is detected; or the falling edge of the fifth PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected. The rising edge of the sixth PWM signal is triggered after a delay time is inserted after the falling edge event of the detected PWM input signal; the falling edge of the sixth PWM signal is triggered after a delay time is inserted after the falling edge event of the detected first current limiting input signal; or, the falling edge of the sixth PWM signal is triggered after a delay time is inserted after the rising edge event of the detected PWM input signal.

[0014] Optionally, before the edge detection and delay unit delays the output of the third, fourth, fifth, and sixth PWM signals based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, the following method is further included: After detecting the rising edge and falling edge events of the PWM input signal, the blanking window unit inserts the first time window. Within the first time window, the state of the second current-limiting input signal remains the same as the previous moment of the first time window, thus obtaining the first current-limiting input signal.

[0015] The technical solution of this invention involves a dead-time generation unit that outputs a first PWM signal and a second PWM signal based on the PWM input signal. The first PWM signal P1 and the second PWM signal are inversely complementary and have a dead time. An edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal. The third PWM signal and the fourth PWM signal are inversely complementary and have a dead time. The effective level period of the fifth PWM signal overlaps with the first time period, and the effective level period of the sixth PWM signal overlaps with the second time period. The first time period is when both the first PWM signal and the fourth PWM signal are at effective levels, and the second time period is when both the second PWM signal and the third PWM signal are at effective levels. Therefore, the technical solution of the present invention realizes the control of the phase-shifted full-bridge leading arm, lagging arm and synchronous rectifier switch by the phase-shifted full-bridge and synchronous rectifier PWM module through the dead time generation unit and the edge detection and delay unit. The phase-shifted full-bridge and synchronous rectifier PWM module only needs to be configured with 2 input interfaces. The input interfaces are simple and easy to integrate into the chip timer module. Compared with the prior art, the chip does not need to integrate the GTM module, which reduces the cost.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention; Figure 2 A structural topology diagram of a phase-shifted full-bridge circuit provided in an embodiment of the present invention; Figure 3 This is a waveform diagram of the PWM signal output by a phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention; Figure 5 A flowchart illustrating a signal output method for a phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention; Figure 6 A flowchart illustrating another method for signal output from a phase-shifted full-bridge and synchronous rectified PWM module provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the driving system of a phase-shifted full-bridge circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a schematic diagram of a phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention. Figure 2 This invention provides a structural topology diagram of a phase-shifted full-bridge circuit. This invention is applicable to scenarios where a pulse width modulation (PWM) signal with a certain timing is output. For example, the output PWM signal can be used for... Figure 2 The phase-shifted full-bridge circuit shown is not specifically limited in this invention. The phase-shifted full-bridge and synchronous rectification PWM module provided in this embodiment of the invention can be implemented by digital circuits. The phase-shifted full-bridge and synchronous rectification PWM module 1 in this embodiment of the invention includes a dead-time generation unit 10 and an edge detection and delay unit 20; The dead time generation unit 10 outputs a first PWM signal P1 and a second PWM signal P2 according to the PWM input signal A; wherein, the first PWM signal P1 and the second PWM signal P2 are a pair of inversely complementary drive signals with dead time, the first PWM signal P1 serves as the upper bridge drive signal of the advanced bridge arm, and the second PWM signal P2 serves as the lower bridge drive signal of the advanced bridge arm. The edge detection and delay unit 20 is used to delay based on the transition edge of the PWM input signal A or the transition edge of the first current-limiting input signal B, and outputs the third PWM signal P3, the fourth PWM signal P4, the fifth PWM signal P5, and the sixth PWM signal P6; the effective level period of the fifth PWM signal P5 overlaps with the first time period T1, but does not overlap with the second time period T2; the effective level period of the sixth PWM signal P6 overlaps with the second time period T2, but does not overlap with the first time period T1; the first time period T1... The first time period is the period when both the first PWM signal P1 and the fourth PWM signal P4 are at an active level. The second time period is the period when both the second PWM signal P2 and the third PWM signal P3 are at an active level. The third PWM signal P3 and the fourth PWM signal P4 are a pair of inversely complementary drive signals with dead time. The third PWM signal P3 serves as the upper bridge drive signal for the lagging bridge arm, and the fourth PWM signal P4 serves as the lower bridge drive signal for the lagging bridge arm. The fifth PWM signal P5 serves as the drive signal for the first rectifier switch, and the sixth PWM signal P6 serves as the drive signal for the second rectifier switch.

[0022] Figure 3 This is a waveform diagram of the PWM signal output by a phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention. (Refer to...) Figure 1 , Figure 2 and Figure 3 In this embodiment of the invention, after the dead time generation unit 10 detects the rising edge and falling edge events of the PWM input signal A, it inserts a delay time and outputs a first PWM signal P1 and a second PWM signal P2. The first PWM signal P1 is used to drive the upper bridge switch Q1 of the leading bridge arm, and the second PWM signal P2 is used to drive the lower bridge switch Q2 of the leading bridge arm. Since the first PWM signal P1 and the second PWM signal P2 are mutually complementary and have a dead time, the conduction states of the upper bridge switch Q1 and the lower bridge switch Q2 of the leading bridge arm are opposite and there will be no shoot-through. That is, the upper bridge switch Q1 and the lower bridge switch Q2 of the leading bridge arm will not be turned on at the same time.

[0023] For example, after detecting the rising edge event of the PWM input signal A, the dead time generation unit 10 inserts a first delay time DT0 to trigger the rising edge of the first PWM signal P1, and after detecting the falling edge event of the PWM input signal A, it triggers the falling edge of the first PWM signal P1. Simultaneously, after detecting the falling edge event of the PWM input signal A, the dead time generation unit 10 inserts a second delay time DT1 to trigger the rising edge of the second PWM signal P2, and after detecting the rising edge event of the PWM input signal A, it triggers the falling edge of the second PWM signal P2. The first delay time DT0 and the second delay time DT1 can be the same or different; this embodiment of the invention does not impose any limitation on this. During the first delay time DT0, the upper bridge switch Q1 of the leading bridge arm discharges to a voltage of 0 through the junction capacitance. After the first delay time DT0 ends, the high level of the first PWM signal P1 can drive the upper bridge switch Q1 of the leading bridge arm to achieve zero-voltage switching (ZVS) conduction. Similarly, during the second delay time DT1, the lower bridge switch Q2 of the leading bridge arm discharges to a voltage of 0 through the junction capacitance. When the second delay time DT1 ends, the high level of the second PWM signal P2 can drive the lower bridge switch Q2 of the leading bridge arm to achieve ZVS conduction.

[0024] The first current-limiting input signal B is used to set the upper limit of the primary-side current of the phase-shifted full-bridge circuit. When the primary-side current exceeds the upper limit threshold, the transition edge of the first current-limiting input signal B flips. The edge detection and delay unit 20 can trigger a delayed output of the third PWM signal P3 and the fourth PWM signal P4 after detecting the transition edge event of the first current-limiting input signal B, or the edge detection and delay unit 20 can trigger a delayed output of the third PWM signal P3 and the fourth PWM signal P4 after detecting the transition edge event of the PWM input signal A. The third PWM signal P3 is used to drive the upper bridge switch Q3 of the lagging bridge arm, and the fourth PWM signal P4 is used to drive the lower bridge switch Q4 of the lagging bridge arm. Since the third PWM signal P3 and the fourth PWM signal P4 are mutually complementary and have a dead time, the conduction states of the upper bridge switch Q3 and the lower bridge switch Q4 of the lagging bridge arm are opposite and there will be no shoot-through. That is, the upper bridge switch Q3 and the lower bridge switch Q4 of the lagging bridge arm will not be turned on at the same time.

[0025] The first time period T1 refers to the overlapping period between the effective level of the first PWM signal P1 and the effective level of the fourth PWM signal P4. The second time period T2 refers to the overlapping period between the effective level of the second PWM signal P2 and the effective level of the third PWM signal P3. When the first time period T1 starts, the rising edge of the fifth PWM signal P5 is triggered or delayed. When the first time period T1 ends, the falling edge of the fifth PWM signal P5 is triggered or delayed. The high level corresponding to the fifth PWM signal P5 is used to drive the first rectifier switch Q5 to conduct, transferring energy from the primary side to the secondary side of the phase-shifted full-bridge circuit. When the second time period T2 starts, the rising edge of the sixth PWM signal P6 is triggered or delayed. When the second time period T2 ends, the falling edge of the sixth PWM signal P6 is triggered or delayed. The high level corresponding to the sixth PWM signal P6 is used to drive the second rectifier switch Q6 to conduct, transferring energy from the primary side to the secondary side of the phase-shifted full-bridge circuit. The rising edge of the PWM input signal A determines the turn-on time of the first time period T1 and the second time period T2, and also determines the latest turn-off time of the first time period T1 and the second time period T2. The rising edge of the first current limiting input signal B determines the earliest turn-off time of the first time period T1 and the second time period T2. The earlier the turn-off time of the first time period T1 and the second time period T2, the smaller the output voltage or primary current of the phase-shifted full-bridge rectifier circuit.

[0026] It is understood that the effective level period of the first PWM signal P1 is the period during which the upper bridge switch Q1 driving the leading bridge arm is turned on, and the invalid level period of the first PWM signal P1 is the period during which the upper bridge switch Q1 driving the leading bridge arm is turned off; the effective level period of the second PWM signal P2 is the period during which the lower bridge switch Q2 driving the leading bridge arm is turned on, and the invalid level period of the second PWM signal P2 is the period during which the lower bridge switch Q2 driving the leading bridge arm is turned off; the effective level periods of the third PWM signal P3, the fourth PWM signal P4, the fifth PWM signal P5, and the sixth PWM signal P6 are all periods during which the driving signal turns on the corresponding switch, and the invalid level periods are all periods during which the driving signal turns off the corresponding switch. These details will not be elaborated further here.

[0027] Specifically, the PWM input signal A can be adjusted by changing its duty cycle to control the on and off times of the first time period T1 and the second time period T2, thereby regulating the output voltage of the phase-shifted full-bridge circuit. For example, if the output voltage is too high, the duty cycle of the PWM input signal A is decreased; if the output voltage is too low, the duty cycle of the PWM input signal A is increased. When the load is overloaded or short-circuited, in peak current control mode, if the primary-side current exceeds the upper limit threshold, the first current-limiting input signal B can trigger a transition edge to control the early turn-off of the first time period T1 and the second time period T2, thereby regulating the magnitude of the primary-side current output of the phase-shifted full-bridge circuit.

[0028] It should be noted that in this embodiment, the dead time generation unit 10 and the edge detection and delay unit 20 can be implemented using digital circuits or integrated modules with relevant technologies. This embodiment does not specifically limit the internal circuit structure of the two.

[0029] According to the technical solution of this embodiment of the invention, a dead-time generation unit outputs a first PWM signal and a second PWM signal based on the PWM input signal. The first PWM signal P1 and the second PWM signal are inversely complementary and have a dead time. An edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal. The third PWM signal and the fourth PWM signal are inversely complementary and have a dead time. The effective level period of the fifth PWM signal overlaps with the first period, and the effective level period of the sixth PWM signal overlaps with the second period. The first period is the period when both the first PWM signal and the fourth PWM signal are at an effective level, and the second period is the period when both the second PWM signal and the third PWM signal are at an effective level. Therefore, the technical solution of the present invention realizes the control of the phase-shifted full-bridge leading arm, lagging arm and synchronous rectifier switch by the phase-shifted full-bridge and synchronous rectifier PWM module through the dead time generation unit and the edge detection and delay unit. The phase-shifted full-bridge and synchronous rectifier PWM module only needs to be configured with 2 input interfaces. The input interfaces are simple and easy to integrate into the chip timer module. Compared with the prior art, the chip does not need to integrate the GTM module, which reduces the cost.

[0030] Figure 4 This is a schematic diagram of another phase-shifted full-bridge and synchronous rectification PWM module provided in an embodiment of the present invention, as shown below. Figure 4 As shown, in some embodiments, the edge detection and delay unit 20 includes a first edge detection and delay subunit 21, a second edge detection and delay subunit 22, a third edge detection and delay subunit 23, and a fourth edge detection and delay subunit 24. The first edge detection and delay subunit 21 is used to generate the rising edge or falling edge of the third PWM signal P3 after a delay based on the detected edge-jumping event, and output the third PWM signal P3; the second edge detection and delay subunit 22 is used to generate the rising edge or falling edge of the fourth PWM signal P4 after a delay based on the detected edge-jumping event, and output the fourth PWM signal P4; the third edge detection and delay subunit 23 is used to generate the rising edge or falling edge of the fifth PWM signal P5 after a delay based on the detected edge-jumping event, and output the fifth PWM signal P5; the fourth edge detection and delay subunit 24 is used to generate the rising edge or falling edge of the sixth PWM signal P6 after a delay based on the detected edge-jumping event, and output the sixth PWM signal P6; the edge-jumping event is at least one of the four edge-jumping events from the PWM input signal A and the first current-limiting input signal B; the rising edge and falling edge of the same PWM signal correspond to different edge-jumping events.

[0031] Each edge detection and delay subunit can delay triggering the rising or falling edge of the PWM signal after detecting at least one of the four edge events of the PWM input signal A and the first current limiting input signal B. In practical applications, it can be configured according to specific needs, and the embodiments of the present invention do not limit it.

[0032] Optionally, when the edge-jumping event includes at least two of the four edge-jumping events from the PWM input signal and the first current-limiting input signal, an OR operation is performed on at least two edge-jumping events.

[0033] For example, the first edge detection and delay subunit 21 may trigger the rising edge of the third PWM signal P3 after a delay time is inserted following the detection of the rising edge event of the first current-limiting input signal B, or after a delay time is inserted following the detection of the falling edge event of the PWM input signal A; or after a delay time is inserted following the detection of the falling edge event of the first current-limiting input signal B, or after a delay time is inserted following the detection of the rising edge event of the PWM input signal A. The second edge detection and delay subunit 22 may trigger the rising edge of the fourth PWM signal P4 after a delay time is inserted following the detection of the falling edge event of the first current-limiting input signal B, or after a delay time is inserted following the detection of the rising edge event of the PWM input signal A; or after a delay time is inserted following the detection of the rising edge event of the first current-limiting input signal B, or after a delay time is inserted following the detection of the falling edge event of the PWM input signal A. The third edge detection and delay subunit 23 triggers the rising edge of the fifth PWM signal P5 after inserting a delay time following the detection of the rising edge event of the PWM input signal A; it also triggers the falling edge of the fifth PWM signal P5 after inserting a delay time following the detection of the rising edge event of the first current-limiting input signal B, or after inserting a delay time following the detection of the falling edge event of the PWM input signal A. The fourth edge detection and delay subunit 24 triggers the rising edge of the sixth PWM signal P6 after inserting a delay time following the detection of the falling edge event of the PWM input signal A; it also triggers the falling edge of the sixth PWM signal P6 after inserting a delay time following the detection of the falling edge event of the first current-limiting input signal B, or after inserting a delay time following the detection of the rising edge event of the PWM input signal A.

[0034] The first edge detection and delay subunit 21 and the second edge detection and delay subunit 22 can output the third PWM signal P3 and the fourth PWM signal P4 after a delay based on the detection of the opposite edge of the first current limiting input signal B, or output the third PWM signal P3 and the fourth PWM signal P4 after a delay based on the detection of the opposite edge of the PWM input signal A, so that the third PWM signal P3 and the fourth PWM signal P4 are drive signals with dead time and inversely complementary.

[0035] refer to Figure 3For example, when the first current-limiting input signal B is present, the first edge detection and delay subunit 21 can insert a third delay time D00 to trigger the rising edge of the third PWM signal P3 after detecting the rising edge event of the first current-limiting input signal B, and insert a fourth delay time D01 to trigger the falling edge of the third PWM signal P3 after detecting the falling edge event of the first current-limiting input signal B; when the first current-limiting input signal B is not present, the first edge detection and delay subunit 21 can insert a third delay time D00 to trigger the rising edge of the third PWM signal P3 after detecting the falling edge event of the PWM input signal A, and insert a fourth delay time D01 to trigger the falling edge of the third PWM signal P3 after detecting the rising edge event of the PWM input signal A. The upper bridge switch Q3 of the lagging bridge arm and the lower bridge switch Q2 of the leading bridge arm are a pair of diagonal switches. Since the dead time generation unit 10 is based on the second PWM signal P2 output by the PWM input signal A to drive the lower bridge switch Q2 of the leading bridge arm, the start time of the second time period T2 of the second PWM signal P2 and the third PWM signal P3 is determined by the edge event of the PWM input signal A. When the primary current is within the upper limit threshold range, the end time of the second time period T2 is determined by the edge event of the PWM input signal A. When the primary current exceeds the upper limit threshold, the end time of the second time period T2 is determined by the edge event of the first current limiting input signal B.

[0036] When the first current-limiting input signal B is present, the second edge detection and delay subunit 22, after detecting the falling edge event of the first current-limiting input signal B, inserts a fifth delay time D10 to trigger the rising edge of the fourth PWM signal P4, and after detecting the rising edge event of the first current-limiting input signal B, inserts a sixth delay time D11 to trigger the falling edge of the fourth PWM signal P4. When the first current-limiting input signal B is not present, the second edge detection and delay subunit 22, after detecting the rising edge event of the PWM input signal A, inserts a fifth delay time D10 to trigger the rising edge of the fourth PWM signal P4, and after detecting the falling edge event of the PWM input signal A, inserts a sixth delay time D11 to trigger the falling edge of the fourth PWM signal P4. The lower bridge switch Q4 of the lagging bridge arm and the upper bridge switch Q1 of the leading bridge arm are a pair of diagonal switches. Since the dead time generation unit 10 is based on the first PWM signal P1 output by the PWM input signal A to drive the upper bridge switch Q1 of the leading bridge arm, the start time of the first time period T1 is determined by the rising edge of the PWM input signal A. When the primary current is within the upper limit threshold range, the end time of the first time period T1 is determined by the rising edge of the PWM input signal A. When the primary current exceeds the upper limit threshold, the end time of the first time period T1 is determined by the rising edge of the first current limiting input signal B.

[0037] It is understandable that the third delay time D00, the fourth delay time D01, the fifth delay time D10, and the sixth delay time D11 can be configured. For example, the fourth delay time D01 is less than the fifth delay time D10, the sixth delay time D11 is less than the third delay time D00, the third delay time D00 and the fifth delay time D10 can be equal, the fourth delay time D01 and the sixth delay time D11 can be equal, and the fourth delay time D01 and the sixth delay time D11 can be 0. This allows the upper bridge switch Q3 of the lagging bridge arm to be turned off and, after a certain delay time, the lower bridge switch Q4 of the lagging bridge arm to be turned on. The lower bridge switch Q4 of the lagging bridge arm to be turned off and, after a certain delay time, the upper bridge switch Q3 of the lagging bridge arm to be turned on. During the third delay time D00, the upper bridge switch Q3 of the lagging bridge arm discharges to 0 through its junction capacitance. After the third delay time D00 ends, the high level of the third PWM signal P3 can drive the upper bridge switch Q3 of the lagging bridge arm to achieve ZVS conduction. Similarly, during the fifth delay time D10, the lower bridge switch Q4 of the lagging bridge arm discharges to 0 through its junction capacitance. After the fifth delay time D10 ends, the high level of the fourth PWM signal P4 can drive the lower bridge switch Q4 of the lagging bridge arm to achieve ZVS conduction.

[0038] When the first current-limiting input signal B is present, the third edge detection and delay subunit 23, after detecting the rising edge event of the PWM input signal A, inserts a seventh delay time D30 to trigger the rising edge of the fifth PWM signal P5, and after detecting the rising edge event of the first current-limiting input signal B, inserts an eighth delay time D31 to trigger the falling edge of the fifth PWM signal P5. When the first current-limiting input signal B is not present, the third edge detection and delay subunit 23, after detecting the rising edge event of the PWM input signal A, inserts a seventh delay time D30 to trigger the rising edge of the fifth PWM signal P5, and after detecting the falling edge event of the PWM input signal A, inserts an eighth delay time D31 to trigger the falling edge of the fifth PWM signal P5.

[0039] When the first current-limiting input signal B is present, the fourth edge detection and delay subunit 24, after detecting the falling edge event of the PWM input signal A and inserting a ninth delay time D20, triggers the rising edge of the sixth PWM signal P6. After detecting the falling edge event of the first current-limiting input signal B, it inserts a tenth delay time D21 and triggers the falling edge of the sixth PWM signal P6. When the first current-limiting input signal B is not present, the fourth edge detection and delay subunit 23, after detecting the falling edge event of the PWM input signal A and inserting a ninth delay time D20, triggers the rising edge of the sixth PWM signal P6. After detecting the rising edge event of the PWM input signal A and inserting a tenth delay time D21, it triggers the falling edge of the sixth PWM signal P6.

[0040] It is understandable that the seventh delay time D30, the eighth delay time D31, the ninth delay time D20, and the tenth delay time D21 can be configured. For example, the eighth delay time D31 is less than the ninth delay time D20, and the tenth delay time D21 is less than the seventh delay time D30. The seventh delay time D30 and the ninth delay time D20 can be equal, and the eighth delay time D31 and the tenth delay time D21 can be equal. When the first current-limiting input signal B is present, the conduction duration of the first rectifier switch Q5 is equal to the first time period T1, and the conduction duration of the second rectifier switch Q6 is equal to the second time period T2.

[0041] Continue to refer to Figure 3 and Figure 4 Optionally, the phase-shifted full-bridge and synchronous rectification PWM module in this embodiment of the invention further includes a blanking window unit 30; The blanking window unit 30 receives the second current limiting input signal C. After detecting the rising edge event and falling edge event of the PWM input signal A, the blanking window unit 30 inserts the first time window BLK respectively. Within the first time window BLK, the state of the second current limiting input signal C remains the same as the previous moment of the first time window BLK, thus obtaining the first current limiting input signal B.

[0042] The second current-limiting input signal C can be generated based on the reference current and the primary-side current. After the rising edge of the PWM input signal A flips, the narrow and high current spike generated by the reverse recovery current of the body diode of the switching transistor can easily be misinterpreted as the primary-side signal exceeding the upper limit threshold, causing the rising edge of the second current-limiting input signal C to change. By outputting the blanking window signal BL through the blanking window module 30, it is equivalent to inserting the first time window BLK after the rising and falling edges of the PWM input signal A are triggered. The duration of the first time window BLK is greater than the first delay time DT0 and the second delay time DT1. Therefore, within the first time window BLK, the rising edge of the second current-limiting input signal C does not flip, thus obtaining a stable first current-limiting input signal B.

[0043] Figure 5 This is a flowchart illustrating a signal output method for a phase-shifted full-bridge and synchronous rectification PWM module according to an embodiment of the present invention. This method is applicable to any embodiment of the phase-shifted full-bridge and synchronous rectification PWM module of the present invention. Figure 5 As shown, the phase-shifted full-bridge and synchronous rectification PWM module signal output method of this invention includes: S101, the dead time generation unit outputs the first PWM signal and the second PWM signal according to the PWM input signal.

[0044] Among them, the first PWM signal and the second PWM signal are a pair of inversely complementary drive signals with dead time. The first PWM signal serves as the upper bridge drive signal of the advanced bridge arm, and the second PWM signal serves as the lower bridge drive signal of the advanced bridge arm. S102, the edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal and the sixth PWM signal.

[0045] In this process, the effective level period of the fifth PWM signal overlaps with the first period, but does not overlap with the second period; the effective level period of the sixth PWM signal overlaps with the second period, but does not overlap with the first period; the first period is when both the first and fourth PWM signals are at effective levels, and the second period is when both the second and third PWM signals are at effective levels; the third and fourth PWM signals are a pair of inversely complementary drive signals with dead time, with the third PWM signal serving as the upper bridge drive signal for the lagging bridge arm and the fourth PWM signal serving as the lower bridge drive signal for the lagging bridge arm; the fifth PWM signal serves as the drive signal for the first rectifier switch, and the sixth PWM signal serves as the drive signal for the second rectifier switch.

[0046] Optionally, S102, the edge detection and delay unit, performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal, including: The first edge detection and delay subunit generates the rising or falling edge of the third PWM signal after delaying the detected edge event, and outputs the third PWM signal. The second edge detection and delay subunit generates the rising or falling edge of the fourth PWM signal after delaying the detected edge event, and outputs the fourth PWM signal. The third edge detection and delay subunit generates the rising or falling edge of the fifth PWM signal after delaying the detected edge event, and outputs the fifth PWM signal. The fourth edge detection and delay subunit generates the rising or falling edge of the sixth PWM signal after delaying the detected edge event, and outputs the sixth PWM signal. The rising edge event is at least one of the four rising edge events from the PWM input signal and the first current limiting input signal; the rising edge and falling edge of the same PWM signal correspond to different rising edge events.

[0047] Optionally, before S102, the edge detection and delay unit delays the signal based on the transition edge of the PWM input signal or the transition edge of the first current limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal, the following method is further included: After detecting the rising edge and falling edge events of the PWM input signal, the blanking window unit inserts the first time window. Within the first time window, the state of the second current-limiting input signal remains the same as the previous moment of the first time window, thus obtaining the first current-limiting input signal.

[0048] Optionally, the first time window is greater than the first delay time and the second delay time.

[0049] Figure 6 A flowchart of another phase-shifted full-bridge and synchronous rectification PWM module signal output method provided by an embodiment of the present invention is shown below. Figure 6 As shown, the signal output method of the phase-shifted full-bridge and synchronous rectification PWM module is as follows: S201. After inserting a delay time after detecting the rising edge event of the PWM input signal, the rising edge of the first PWM signal is triggered, and the falling edge of the first PWM signal is triggered after detecting the falling edge event of the PWM input signal. S202. After inserting a delay time after detecting the falling edge event of the PWM input signal, the rising edge of the second PWM signal is triggered, and the falling edge of the second PWM signal is triggered after detecting the rising edge event of the PWM input signal.

[0050] S203. Trigger the rising edge of the third PWM signal after a delay time is inserted after detecting the rising edge event of the first current limiting input signal, or trigger the rising edge of the third PWM signal after a delay time is inserted after detecting the falling edge event of the PWM input signal; trigger the falling edge of the third PWM signal after a delay time is inserted after detecting the falling edge event of the first current limiting input signal, or trigger the falling edge of the third PWM signal after a delay time is inserted after detecting the rising edge event of the PWM input signal.

[0051] S204. Trigger the rising edge of the fourth PWM signal after a delay time is inserted after the falling edge event of the first current limiting input signal is detected, or trigger the rising edge of the fourth PWM signal after a delay time is inserted after the falling edge event of the PWM input signal is detected; trigger the falling edge of the fourth PWM signal after a delay time is inserted after the falling edge event of the first current limiting input signal is detected, or trigger the falling edge of the fourth PWM signal after a delay time is inserted after the falling edge event of the PWM input signal is detected.

[0052] S205. Trigger the rising edge of the fifth PWM signal after inserting a delay time after detecting the rising edge event of the PWM input signal; trigger the falling edge of the fifth PWM signal after inserting a delay time after detecting the rising edge event of the first current limiting input signal; or trigger the falling edge of the fifth PWM signal after inserting a delay time after detecting the falling edge event of the PWM input signal.

[0053] S206. Trigger the rising edge of the sixth PWM signal after a delay time is inserted after the falling edge event of the detected PWM input signal is detected; trigger the falling edge of the sixth PWM signal after a delay time is inserted after the falling edge event of the detected first current limiting input signal is detected; or trigger the falling edge of the sixth PWM signal after a delay time is inserted after the rising edge event of the detected PWM input signal is detected.

[0054] Based on any of the above embodiments, Figure 7 This is a schematic diagram of the structure of a driving system for a phase-shifted full-bridge circuit provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the driving system of the phase-shifted full-bridge circuit in this embodiment of the invention includes a phase-shifted full-bridge and synchronous rectification PWM module 1 according to any embodiment of the invention. The driving system of the phase-shifted full-bridge circuit also includes a PWM module 2, a comparator module 3, an analog-to-digital converter module 4, and a voltage loop controller module 5; PWM module 2 is used to output PWM input signal A to phase-shifted full-bridge and synchronous rectification PWM module 1; analog-to-digital conversion module 4 is used to perform analog-to-digital conversion based on the voltage of phase-shifted full-bridge circuit 6 and output the first voltage data D; voltage loop controller module 5 is used to output reference current F based on reference voltage E and the first voltage data D; comparison module 3 is used to output the second current limiting input signal C to phase-shifted full-bridge and synchronous rectification PWM module based on reference current F and primary current G of phase-shifted full-bridge circuit, and the first current limiting input signal B is generated based on the second current limiting input signal C.

[0055] In this embodiment of the invention, PWM module 2 can output a PWM input signal A with a target frequency and 50% duty cycle to phase-shifted full-bridge and synchronous rectification PWM module 1. Analog-to-digital conversion module 4 can acquire the voltage signal of phase-shifted full-bridge circuit 6 and convert it into first voltage data D that can be recognized by voltage loop controller module 5. The first voltage data D can represent the actual output voltage of the current phase-shifted full-bridge circuit 6. The reference voltage E can be a pre-set output voltage value of phase-shifted full-bridge circuit 6. Voltage loop controller module 5 generates a reference current F based on the magnitude of reference voltage E and first voltage data D. Comparison module 3 outputs a second current-limiting input signal C based on the relationship between the reference current F and the primary current G. The second current-limiting input signal C is passed through the blanking window unit of phase-shifted full-bridge and synchronous rectification PWM module 1 and outputs a first current-limiting input signal B. Phase-shifted full-bridge and synchronous rectification PWM module 1 outputs a first PWM signal P1, a second PWM signal P2, a third PWM signal P3 and a fourth PWM signal P4 for driving the leading and lagging bridge arms, and a fifth PWM signal P5 and a sixth PWM signal P6 for driving the synchronous rectification switch.

[0056] Optionally, the dead time generation unit 10, the edge detection and delay unit 20, and the blanking window unit 30 can be integrated and configured with input / output interfaces so that the phase-shifted full-bridge and synchronous rectification PWM module can be easily applied to the driving system of the phase-shifted full-bridge circuit.

[0057] According to the technical solution of the present invention, a phase-shifted full-bridge and synchronous rectification PWM module outputs PWM input signals through a PWM module, an analog-to-digital conversion module performs analog-to-digital conversion based on the voltage of the phase-shifted full-bridge circuit, and outputs first voltage data. A voltage loop controller module outputs a reference current based on a reference voltage and the first voltage data. A comparison module collects the primary current of the phase-shifted full-bridge circuit and outputs a second current-limiting input signal to the phase-shifted full-bridge and synchronous rectification PWM module based on the reference current and the primary current. This enables the phase-shifted full-bridge and synchronous rectification PWM module to output a first PWM signal, a second PWM signal, a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal, thereby realizing the control of the leading arm, lagging arm, and synchronous rectification switch of the phase-shifted full-bridge.

[0058] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0059] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A phase-shifted full-bridge and synchronous rectification PWM module, characterized in that, Includes a dead-time generation unit and an edge detection and delay unit; The dead time generation unit is used to output a first PWM signal and a second PWM signal according to the PWM input signal; wherein, the first PWM signal and the second PWM signal are a pair of inversely complementary drive signals with dead time, the first PWM signal is used as the upper bridge drive signal of the advanced bridge arm, and the second PWM signal is used as the lower bridge drive signal of the advanced bridge arm. The edge detection and delay unit is used to delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal. The effective level period of the fifth PWM signal overlaps with the first period, but does not overlap with the second period. The effective level period of the sixth PWM signal overlaps with the second period, but does not overlap with the first period. The first period is when both the first PWM signal and the fourth PWM signal are at effective levels, and the second period is when both the second PWM signal and the third PWM signal are at effective levels. The third PWM signal and the fourth PWM signal are a pair of inversely complementary drive signals with dead time. The third PWM signal serves as the upper bridge drive signal of the lagging bridge arm, and the fourth PWM signal serves as the lower bridge drive signal of the lagging bridge arm. The fifth PWM signal serves as the drive signal of the first rectifier switch, and the sixth PWM signal serves as the drive signal of the second rectifier switch.

2. The phase-shifted full-bridge and synchronous rectification PWM module according to claim 1, characterized in that, The edge detection and delay unit includes a first edge detection and delay subunit, a second edge detection and delay subunit, a third edge detection and delay subunit, and a fourth edge detection and delay subunit; The first edge detection and delay subunit is used to generate the rising edge or falling edge of the third PWM signal after delaying the detected edge event, and output the third PWM signal. The second edge detection and delay subunit is used to generate the rising edge or falling edge of the fourth PWM signal after delaying the detected edge event, and output the fourth PWM signal. The third edge detection and delay subunit is used to generate the rising edge or falling edge of the fifth PWM signal after delaying the detected edge event, and output the fifth PWM signal. The fourth edge detection and delay subunit is used to generate the rising edge or falling edge of the sixth PWM signal after delaying the detected edge event, and output the sixth PWM signal. The rising edge event is at least one of the four rising edge events of the PWM input signal and the first current limiting input signal; the rising edge and falling edge of the same PWM signal correspond to different rising edge events.

3. The phase-shifted full-bridge and synchronous rectification PWM module according to claim 1, characterized in that, The transition edge event includes at least two of the four transition edge events from the PWM input signal and the first current limiting input signal, and an OR operation is performed on at least two of the transition edge events.

4. The phase-shifted full-bridge and synchronous rectification PWM module according to claim 1, characterized in that, It also includes a blanking window unit; The blanking window unit receives a second current-limiting input signal. After detecting the rising edge event and falling edge event of the PWM input signal, the blanking window unit inserts a first time window respectively. Within the first time window, the state of the second current-limiting input signal remains the same as the previous moment of the first time window, thus obtaining the first current-limiting input signal.

5. A method for signal output from a phase-shifted full-bridge and synchronous rectified PWM module, characterized in that, The phase-shifted full-bridge and synchronous rectification PWM module according to any one of claims 1-4 includes: The dead time generation unit outputs a first PWM signal and a second PWM signal according to the PWM input signal; wherein, the first PWM signal and the second PWM signal are a pair of inversely complementary drive signals with dead time, the first PWM signal serves as the upper bridge drive signal of the advanced bridge arm, and the second PWM signal serves as the lower bridge drive signal of the advanced bridge arm. The edge detection and delay unit delays the signal based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal. The effective level period of the fifth PWM signal overlaps with the first time period, but does not overlap with the second time period. The effective level period of the sixth PWM signal overlaps with the second time period, but does not overlap with the first time period. The first time period is when both the first PWM signal and the fourth PWM signal are at effective levels, and the second time period is when both the second PWM signal and the third PWM signal are at effective levels. The third PWM signal and the fourth PWM signal are a pair of inversely complementary drive signals with dead time. The third PWM signal serves as the upper bridge drive signal for the lagging bridge arm, and the fourth PWM signal serves as the lower bridge drive signal for the lagging bridge arm. The fifth PWM signal serves as the drive signal for the first rectifier switch, and the sixth PWM signal serves as the drive signal for the second rectifier switch.

6. The signal output method of the phase-shifted full-bridge and synchronous rectification PWM module according to claim 5, characterized in that, The edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal, including: The first edge detection and delay subunit generates the rising edge or falling edge of the third PWM signal after delaying the detected edge event, and outputs the third PWM signal. The second edge detection and delay subunit generates the rising edge or falling edge of the fourth PWM signal after delaying the detected edge event, and outputs the fourth PWM signal. The third edge detection and delay subunit generates the rising edge or falling edge of the fifth PWM signal after delaying the detected edge event, and outputs the fifth PWM signal. The fourth edge detection and delay subunit generates the rising edge or falling edge of the sixth PWM signal after delaying the detected edge event, and outputs the sixth PWM signal. The rising edge event is at least one of the four rising edge events of the PWM input signal and the first current limiting input signal; the rising edge and falling edge of the same PWM signal correspond to different rising edge events.

7. The signal output method of the phase-shifted full-bridge and synchronous rectification PWM module according to claim 5, characterized in that, The dead-time generation unit outputs a first PWM signal and a second PWM signal based on the PWM input signal, including: The rising edge of the first PWM signal is triggered after a delay time is inserted after the rising edge event of the PWM input signal is detected, and the falling edge of the first PWM signal is triggered after the falling edge event of the PWM input signal is detected. The rising edge of the second PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected, and the falling edge of the second PWM signal is triggered after the rising edge event of the PWM input signal is detected.

8. The signal output method of the phase-shifted full-bridge and synchronous rectification PWM module according to claim 5, characterized in that, The edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current-limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal, including: The rising edge of the third PWM signal is triggered after a delay time is inserted after the rising edge event of the first current limiting input signal is detected; or, the rising edge of the third PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected. The rising edge of the fourth PWM signal is triggered after a delay time is inserted after the falling edge event of the first current limiting input signal is detected; or, the rising edge of the fourth PWM signal is triggered after a delay time is inserted after the falling edge event of the PWM input signal is detected. The rising edge of the fifth PWM signal is triggered after a delay time is inserted to detect the rising edge event of the PWM input signal; the falling edge of the fifth PWM signal is triggered after a delay time is inserted to detect the rising edge event of the first current limiting input signal; or, the falling edge of the fifth PWM signal is triggered after a delay time is inserted to detect the falling edge event of the PWM input signal. The rising edge of the sixth PWM signal is triggered after a delay time is inserted to detect the falling edge event of the PWM input signal; the falling edge of the sixth PWM signal is triggered after a delay time is inserted to detect the falling edge event of the first current limiting input signal; or, the falling edge of the sixth PWM signal is triggered after a delay time is inserted to detect the rising edge event of the PWM input signal.

9. The signal output method of the phase-shifted full-bridge and synchronous rectification PWM module according to claim 5, characterized in that, Before the edge detection and delay unit performs a delay based on the transition edge of the PWM input signal or the transition edge of the first current limiting input signal, and outputs the third PWM signal, the fourth PWM signal, the fifth PWM signal, and the sixth PWM signal, the following method is further included: After detecting the rising edge and falling edge events of the PWM input signal, the blanking window unit inserts a first time window. Within the first time window, the state of the second current-limiting input signal remains the same as the state before the first time window, thus obtaining the first current-limiting input signal.

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