A dual-mode clllc resonant converter control method and system based on fixed resonant frequency pulse sequence modulation

Abstract

This invention discloses a control method and system for a dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation, belonging to the field of power electronic conversion technology. This invention maintains a constant switching frequency and duty cycle of the converter, and achieves precise regulation of the CLLLC resonant converter's output voltage and bidirectional power flow by dynamically adjusting the duty cycle and control period of a pulse sequence consisting of continuous operating pulse groups and complete sleep intervals. This control strategy effectively overcomes the shortcomings of traditional frequency conversion or phase shift control, such as reduced efficiency under light load, slow dynamic response, and insufficient control loop gain, which exist in a wide input voltage and load range. This invention maintains soft-switching characteristics under both light and heavy load conditions, significantly reducing switching losses and circulating energy, while balancing high power conversion efficiency and fast dynamic response. It is particularly suitable for high-voltage, high-power applications such as on-board chargers and energy storage systems for new energy vehicles.

Description

Technical Field

[0001] This invention relates to CLLLC circuit technology in the field of power electronics, and in particular to a control method and system for a dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation, which features wide input voltage, wide output power, high power conversion efficiency, and fast dynamic response. Background Technology

[0002] The CLLLC resonant converter is an isolated DC-DC converter topology widely used in on-board chargers and energy storage conversion systems for new energy vehicles. This converter introduces resonant inductors and capacitors on both the primary and secondary sides, achieving electrical isolation and energy transfer through a high-frequency transformer. It exhibits symmetrical voltage gain characteristics during forward and reverse power flow, enabling bidirectional energy transfer. Due to its soft-switching capability, it boasts advantages such as low switching losses, low electromagnetic interference, and high power density, making it a key power conversion unit in bidirectional on-board charging systems.

[0003] As on-board chargers evolve towards wider battery voltage ranges, wider power ranges, and higher efficiency, CLLLC resonant converters need to maintain stable operation under light, medium, and heavy load conditions, while also ensuring high efficiency and fast dynamic response. Under different input voltage and load conditions, the operating state of the resonant cavity changes, exhibiting near-resonance, inductive, or capacitive characteristics. Different operating regions correspond to different voltage gains and soft-switching characteristics. Therefore, the converter's performance largely depends on the choice of control strategy.

[0004] Currently, CLLLC resonant converters typically employ frequency conversion control or phase modulation control for voltage regulation, including pulse frequency modulation (PFM), phase shift modulation (PSM), and hybrid frequency and phase modulation methods. These control methods adjust the switching frequency or bridge arm phase relationship to change the equivalent impedance of the resonant cavity, thereby achieving output voltage regulation. They are widely used because they can achieve high efficiency and soft-switching operation near the rated load. However, when the converter operates over a wide input voltage and load range, relying solely on the above control strategies makes it difficult to maintain consistent performance across all operating ranges: at low gain or light load operation, the switching frequency needs to be significantly increased to maintain output regulation capability, leading to increased switching losses and reduced efficiency; when the operating frequency is far from the resonant point, the voltage gain becomes less sensitive to frequency changes, resulting in a decrease in the effective gain of the control loop, thus limiting the closed-loop bandwidth and reducing dynamic response speed; continuous high-frequency switching also generates additional cycling energy and magnetization losses, which are detrimental to light-load efficiency improvement; therefore, it is difficult to simultaneously meet the requirements for efficiency, output voltage ripple, and dynamic response performance over a wide input voltage and power range.

[0005] Therefore, achieving wide-range voltage regulation, improving light-load efficiency, and considering dynamic response performance while keeping the resonant converter close to its optimal operating state has become an important research direction in CLLLC resonant converter control technology. Currently, similar research and patents on dual-mode CLLLC resonant converter control methods and systems based on fixed-resonant-frequency pulse sequence modulation, targeting wide input voltage, wide output power, high power conversion efficiency, and fast dynamic response, are as follows:

[0006] Reference 1, "Bidirectional Current-Fed CLLC Resonant Converter Employing Asymmetric PWM" (IEEE Transactions on Energy Conversion, vol. 36, no. 4, pp. 3167-3177, Dec. 2021), proposes a bidirectional current-feed CLLC resonant converter based on asymmetric pulse width modulation (APWM). By adjusting the switching duty cycle to adapt to input voltage fluctuations, it achieves a wide voltage gain range and bidirectional power conversion. With an input voltage Vin = 12~16.8V and an output power of 20W, this method achieves a forward conversion efficiency of 92.3% and a reverse conversion efficiency of 89.7%. However, this method cannot solve the problem of significantly reduced circuit conversion efficiency under light load conditions, and its applicable voltage and power range is limited to low-voltage, low-power scenarios, making it difficult to meet the application requirements of high-voltage, high-power fields such as on-board chargers for new energy vehicles and energy storage conversion systems. In comparison, this invention maintains a constant switching frequency and duty cycle, and adjusts the output voltage of the CLLLC resonant converter by regulating the duty cycle and control period of a pulse sequence consisting of continuous working pulse groups and complete sleep intervals, thereby achieving a wider voltage gain range and bidirectional power conversion. In the forward charging mode with an input voltage of 390~450V and an output power of 4.6KW~5.6KW, this method achieves a forward conversion efficiency exceeding 92.7% under heavy load conditions and exceeding 92.2% under light load conditions. In the discharge mode with an input voltage of 260~300V and an output power of 2.1KW~3.1KW, this method achieves a reverse conversion efficiency exceeding 93.3% under heavy load conditions and exceeding 91.2% under light load conditions. It achieves high-efficiency output across the entire power range under high voltage and high power conditions, while simultaneously addressing the technical pain point of reduced efficiency under light load in Reference 1.

[0007] Reference 2, "A Boost CLLC Converter Controlled by PWM and PFM Hybrid Modulation for Photovoltaic Power Generation" (IEEE Access, vol. 8, pp. 112015-112026, June 2020), proposes a PWM-PFM hybrid modulation method. By controlling the duty cycle and switching frequency of the main MOSFET, the converter can track the photovoltaic maximum power point and stabilize the output voltage, thereby maximizing the utilization of photovoltaic energy and improving conversion efficiency. In low-voltage medium-power applications with input voltage Vin=20~80V and output power Po=50~500W, this method achieves a circuit conversion efficiency greater than 95%. However, this method cannot solve the problem of reduced circuit conversion efficiency under heavy load conditions, and its application is limited to low-voltage medium-power unidirectional transmission. In comparison, this invention maintains a constant switching frequency and duty cycle, and adjusts the duty cycle and control period of a pulse sequence consisting of continuous operating pulse groups and complete sleep intervals to regulate the output voltage of the CLLLC resonant converter, thereby achieving a wider voltage gain range and bidirectional power conversion. In forward charging mode with an input voltage of 390~450V and an output power of 4.6KW~5.6KW, this method achieves a forward conversion efficiency exceeding 92.7% under heavy load conditions and exceeding 92.2% under light load conditions. In discharge mode with an input voltage of 260~300V and an output power of 2.1KW~3.1KW, this method achieves a reverse conversion efficiency exceeding 93.3% under heavy load conditions and exceeding 91.2% under light load conditions. This invention, through an innovative pulse sequence modulation strategy, not only solves the core technical pain point of reduced efficiency under heavy load in Reference 2, but also breaks through its application limitations of low voltage, medium power, and unidirectional transmission, achieving high-efficiency output across the full power range under light and heavy loads in high voltage and high power scenarios, as well as flexible bidirectional energy conversion.

[0008] Reference 3, "A Novel Phase-Shift Pulsewidth Modulation Method for Light-Load Bidirectional CLLC Resonant Converter" (IEEE Transactions on Power Electronics, vol. 38, no. 3, pp. 3257-3267, March 2023), addresses the voltage gain imbalance and low energy transfer efficiency issues in bidirectional full-bridge CLLC resonant converters under light load conditions in PFM control mode. It proposes a novel PS-PWM control method, which flexibly adjusts the voltage gain by regulating the duty cycle Ds and the primary-side phase shift angle, while simultaneously achieving zero-voltage switching (ZVS) for both primary and secondary switches. This solves the duty cycle limitation problem imposed by soft switching in PWM control. Furthermore, the switching current stress of PS-PWM control is lower than that of APWM control, reducing switching losses and improving the converter's energy transfer efficiency. Under light load conditions (input voltage Vin=200V, output power Po=32.4W), this method achieves a circuit conversion efficiency of nearly 80%; under heavy load conditions (input voltage Vin=200V, output power Po=640~800W), it achieves a circuit conversion efficiency of nearly 95%. However, this method still relies on continuous modulation of the duty cycle and phase shift angle to achieve output regulation, resulting in numerous control variables. Furthermore, the switching frequency is not fixed at the optimal resonant point, making it difficult to simultaneously achieve high efficiency and fast dynamic response under wide input voltage and power range conditions. In contrast, this invention proposes a dual-mode CLLLC resonant converter control method based on fixed resonant frequency pulse sequence modulation. By fixing the switching frequency at the optimal resonant point and adjusting the duty cycle and control period of a pulse sequence consisting of continuous operating pulse groups and complete sleep intervals, the output voltage of the CLLLC resonant converter is adjusted, thereby achieving a wider voltage gain range and bidirectional power conversion. In the forward charging mode with an input voltage of 390~450V and an output power of 4.6KW~5.6KW, this method achieves a forward conversion efficiency of over 92.7% under heavy load conditions and over 92.2% under light load conditions. In the discharge mode with an input voltage of 260~300V and an output power of 2.1KW~3.1KW, this method achieves a reverse conversion efficiency of over 93.3% under heavy load conditions and over 91.2% under light load conditions. Under high voltage and high power conditions, this method achieves both high efficiency and fast dynamic response across the entire power range, including both light and heavy loads.

[0009] Texas Instruments has announced a bidirectional CLLLC resonant dual active bridge (DAB) reference design for HEV / EV on-board chargers—TIDM-02002. This design employs a pulse frequency modulation (PFM)-based split-loop control algorithm. In constant current mode, the current loop adjusts the switching frequency based on the error between the actual and reference values ​​of the output current to stabilize the output current. In constant voltage mode, the voltage loop adjusts the switching frequency based on the error between the actual and reference values ​​of the output voltage to stabilize the output voltage. With this control strategy, the solution achieves a peak conversion efficiency of 98% under operating conditions of 380V~600V input voltage, 280V~450V output voltage, and a maximum output power of 6.6kW, effectively improving the system's peak performance and power density. However, this method has a slow dynamic response speed at high frequencies and cannot achieve rapid output voltage adjustment under sudden load changes or wide voltage input scenarios. In comparison, this invention maintains a constant switching frequency and duty cycle, and adjusts the output voltage of the CLLLC resonant converter by regulating the duty cycle and control period of a pulse sequence consisting of continuous operating pulse groups and complete sleep intervals, thereby achieving a wider voltage gain range and bidirectional power conversion. In the forward charging mode with an input voltage of 390~450V and an output power of 4.6KW~5.6KW, this method achieves a forward conversion efficiency exceeding 92.7% under heavy load conditions and exceeding 92.2% under light load conditions. In the discharge mode with an input voltage of 260~300V and an output power of 2.1KW~3.1KW, this method achieves a reverse conversion efficiency exceeding 93.3% under heavy load conditions and exceeding 91.2% under light load conditions. This invention fundamentally solves the technical pain points of modulation lag and dynamic performance degradation in the TIDM-02002 reference design under high-frequency conditions by removing the high-frequency regulation stage. While ensuring high-voltage and high-power bidirectional conversion capability, it achieves high-efficiency output and better dynamic response characteristics across the entire power range.

[0010] Texas Instruments has announced a bidirectional on-board charger reference design—TIDM-02013. This design consists of an interleaved bridgeless totem-pole PFC power stage and a CLLLC DC power stage. The subsequent bidirectional full-bridge CLLLC resonant DC / DC converter employs a hybrid frequency and phase modulation strategy. Based on a nominal switching frequency of 500kHz with an adjustable range of 200kHz–800kHz, phase adjustment is combined to adapt to a wide output voltage range of 250–450V. Simultaneously, active synchronous rectification and soft-switching designs with primary-side zero-voltage switching (ZVS) and secondary-side zero-current switching (ZCS) / ZVS achieve efficient bidirectional power conversion. The CLLLC stage uses frequency and phase modulation to regulate the output over a wide voltage range, achieving high peak efficiency and high power density across the entire input voltage range. With this control strategy, the solution achieves a peak conversion efficiency of 98% under operating conditions of 400V input voltage, 250V~450V output voltage, and a maximum output power of 7.4kW, effectively improving the system's peak performance and power density. However, this method cannot solve the problem of reduced circuit conversion efficiency under light load conditions, and modulation lag easily occurs in the high-frequency band when the output voltage or load changes abruptly, making it impossible to lock the optimal operating point in time, resulting in poor dynamic response performance. In contrast, this invention keeps the switching frequency and duty cycle constant, and adjusts the duty cycle and control period of the pulse sequence consisting of continuous working pulse groups and complete sleep intervals to adjust the output voltage of the CLLLC resonant converter, achieving a wider voltage gain range and bidirectional power conversion. In the forward charging mode with an input voltage of 390~450V and an output power of 4.6KW~5.6KW, this method achieves a forward conversion efficiency of over 92.7% under heavy load conditions and over 92.2% under light load conditions; in the discharge mode with an input voltage of 260~300V and an output power of 2.1KW~3.1KW, this method achieves a reverse conversion efficiency of over 93.3% under heavy load conditions and over 91.2% under light load conditions. This invention fundamentally solves the technical pain points of reduced efficiency and lag in dynamic response of TIDM-02013 under light load, and achieves efficient and stable operation under all working conditions in high-voltage and high-power scenarios.

[0011] Chinese patent CN119787827A discloses a modulation and control method for a bridge-arm multiplexed FSBB-CLLLC bidirectional converter. This method divides the main circuit topology into different bridge arms, combines modulation methods and soft-switching conditions to solve the relationship between the converter's inductor current and phase shift angle, and establishes a three-dimensional table. Simultaneously, based on different input and output voltage requirements, it determines the duty cycle and optimal phase shift angle, solving the problems of unclear modulation methods, ambiguous working principles, and reduced efficiency due to complex soft-switching implementation in bridge-arm multiplexed FSBB-CLLLC converters. However, this method requires precise matching of the relationship between the phase shift angle α, duty cycle D, and inductor current i_L, and can only be implemented in the calibrated Modef2, Modef5, Modeb2, and Modeb5 operating modes. Once the input voltage or output power exceeds the design range, the inductor current waveform deviates from the theoretically calculated value, the soft-switching boundary conditions are broken, directly leading to increased switching losses and a significant decrease in efficiency. Furthermore, it does not explicitly mention the applicable range of input voltage and output power, nor the specific peak conversion efficiency indicators. In comparison, this invention maintains a constant switching frequency and duty cycle, and adjusts the output voltage of the CLLLC resonant converter by regulating the duty cycle and control period of a pulse sequence consisting of continuous operating pulse groups and complete sleep intervals, thereby achieving a wider voltage gain range and bidirectional power conversion. In the forward charging mode with an input voltage of 390~450V and an output power of 4.6KW~5.6KW, this method achieves a forward conversion efficiency exceeding 92.7% under heavy load conditions and exceeding 92.2% under light load conditions. In the discharge mode with an input voltage of 260~300V and an output power of 2.1KW~3.1KW, this method achieves a reverse conversion efficiency exceeding 93.3% under heavy load conditions and exceeding 91.2% under light load conditions, realizing stable and efficient bidirectional energy conversion within the specified operating range.

[0012] Chinese patent CN119787832A discloses an adaptive synchronous rectification control method for CLLLC resonant converters. Based on the circuit characteristics and operating process of CLLLC converters, this method analyzes the influence of the synchronous rectification drive signal on the output frequency when the converter achieves a stable output signal. It derives an equation relating the change in the synchronous rectification signal to the change in the operating frequency near the ideal synchronous rectification signal, and utilizes this equation to achieve the synchronous rectification function of the CLLLC converter. In the rectification control, a certain disturbance signal is applied to the synchronous rectification signal, and the change in the operating frequency before and after the converter reaches a stable output signal is used to gradually bring the synchronous rectification signal closer to the ideal synchronous rectification state, solving the problem of the complex theoretical calculation process for synchronous rectification in CLLLC resonant converters. However, this method requires dynamic adjustment of the operating frequency to achieve synchronous rectification optimization, making it difficult for the converter to operate at a fixed optimal resonant point. Furthermore, it does not explicitly mention the applicable range of input voltage and the coverage range of output power, nor the specific peak conversion efficiency indicators achieved. In comparison, this invention maintains a constant switching frequency and duty cycle, and adjusts the output voltage of the CLLLC resonant converter by regulating the duty cycle and control period of a pulse sequence consisting of continuous operating pulse groups and complete sleep intervals, thereby achieving a wider voltage gain range and bidirectional power conversion. In the forward charging mode with an input voltage of 390~450V and an output power of 4.6kW~5.6kW, this method achieves a forward conversion efficiency exceeding 92.7% under heavy load conditions and exceeding 92.2% under light load conditions. In the discharge mode with an input voltage of 260~300V and an output power of 2.1kW~3.1kW, this method achieves a reverse conversion efficiency exceeding 93.3% under heavy load conditions and exceeding 91.2% under light load conditions. These data demonstrate that this invention achieves more stable and efficient bidirectional energy conversion within a specified wide operating range.

[0013] In summary, while several CLLLC resonant converters and corresponding control methods achieving high conversion efficiency and fast dynamic response have emerged in recent years, none of these inventions relate to the dual-mode CLLLC resonant converter control method and system based on fixed resonant frequency pulse sequence modulation as described in this invention. Furthermore, existing literature and patents do not yet reveal a dual-mode CLLLC resonant converter control method and system based on fixed resonant frequency pulse sequence modulation as described in this invention, nor do they show a design that can achieve high conversion efficiency and fast dynamic response across a wide input voltage range and a wide output power operating range. Summary of the Invention

[0014] The purpose of this invention is to provide a control method and system for a dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation. Under conditions of wide input voltage and wide output power, the circuit achieves fast dynamic response and high peak efficiency. To achieve this goal, the invention employs the following innovative technologies: (1) The switching frequency is strictly fixed at the optimal resonant point. By adjusting the duty cycle of the pulse sequence consisting of a continuous working pulse group and a complete sleep interval, the output voltage of the CLLLC resonant converter is adjusted, achieving wide voltage regulation and high peak efficiency, thus solving the problem of reduced dynamic response speed in the low-gain stage of the traditional PFM control method; (2) Based on the control pulse sequence duty cycle, output voltage, and output power, the control period of the pulse sequence is automatically adjusted to achieve a trade-off between dynamic response, peak efficiency, and output voltage ripple; (3) In light load and low-gain modes, the sleep period can be significantly increased to drastically reduce losses, achieving high peak efficiency. The specific technical solutions are as follows:

[0015] The aforementioned control method and system for a dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation consists of two parts: a CLLLC resonant converter and a dual-mode control circuit based on fixed-frequency pulse sequence modulation.

[0016] The dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation includes a bus capacitor Cbus, CLLLC switches S1-S8, resonant inductors Lr1 and Lr2, resonant capacitors Cr1 and Cr2, a magnetizing inductor Lm, a transformer T1, and an output capacitor Co. The two ends of the bus capacitor Cbus are connected to the positive and negative terminals of the input voltage V1, respectively. The drains of switches S1 and S3 are connected to one end of the bus capacitor Cbus. The other end of the bus capacitor Cbus is connected to the source of switches S2 and S4. The source of switch S1 and the drain of switch S2 are connected to one end of the resonant inductor L1. The other end of the resonant inductor L1 is connected to one end of the primary winding of transformer T1. The other end of the primary winding of transformer T1 is connected to the resonant capacitor Cr1. One end is connected; the other end of the resonant capacitor Cr1 is connected to the source of switch S3 and the drain of switch S4; the magnetizing inductor Lm is connected in parallel across the primary side of transformer T1; one end of the secondary side of transformer T1 is connected to one end of the resonant inductor Lr2; the other end of the resonant inductor Lr2 is connected to the source of S5 and the drain of S6; the drains of switch S5 and S7 are connected to one end of the output capacitor Co; the other end of the output capacitor Co is connected to the source of S6 and S8; the source of switch S7 and the drain of switch S8 are connected to one end of the resonant capacitor Cr2; the other end of the resonant capacitor Cr2 is connected to the other end of the secondary side of transformer T1; the sources of switch S2, switch S4, switch S6, and switch S8, one end of bus capacitor Cbus, and one end of output capacitor Co are connected to ground.

[0017] The dual-mode control circuit based on fixed-frequency pulse sequence modulation includes a first analog-to-digital converter (ADC1), a second analog-to-digital converter (ADC2), a variable control period module, a pulse sequence duty cycle control module, and a PWM modulation module. The first ADC1 and the second ADC2 sample the forward and reverse output voltages of the CLLLC resonant circuit, respectively. The outputs of the first ADC1 and the second ADC2 are connected to the inputs of the variable control period module and the pulse sequence duty cycle control module, respectively, generating control signals for the forward charging and reverse discharging modes. The output of the pulse sequence duty cycle control module is connected to the input of the variable control period module, automatically adjusting the control period of the pulse sequence based on the control pulse sequence duty cycle, output voltage, and output power. The outputs of the variable control period module and the pulse sequence duty cycle control module are connected to the input of the PWM modulation module, generating drive signals for the switching transistors S1-S8.

[0018] Furthermore, the method for calculating the control cycle range under different operating modes by the variable control cycle module is characterized by automatically adjusting the control cycle range of the pulse sequence by controlling the duty cycle of the pulse sequence, the output voltage, and the output power. The specific calculation method for the control cycle range is as follows:

[0019] To enable a CLLLC resonant converter to achieve a fast dynamic response, the bandwidth of the control system must be fast enough to track load changes. The control cycle of the voltage loop should be 5 to 10 times the closed-loop bandwidth of the system.

[0020] Assume the required closed-loop bandwidth of the system is fbw (for an onboard charger, fbw is in the range of 100Hz-1kHz). According to the sampling theorem, the control period Tseq should satisfy:

[0021]

[0022] Where Ks is the oversampling coefficient, typically taken as 5~10. Converting the control period Tseq to the number of control periods, and assuming the switching period is Tsw, the maximum value of the number of control periods, Ntotal_max1, should satisfy:

[0023]

[0024] Where floor represents rounding down, which is the upper limit of the number of cycles set to ensure dynamic response.

[0025] When the load is light, efficiency can be improved by significantly increasing the sleep time M, but it is necessary to ensure that each working pulse group N can complete at least one complete resonant energy transfer process and maintain the soft switching function.

[0026] To achieve zero-voltage switching (ZVS) and ensure stable and reliable resonance, the value of parameter N must meet certain constraints. In practical engineering, the minimum number of operating pulses, Nmin, is typically 2 to 4. Nmin=2 ensures at least one complete positive and negative voltage cycle, while Nmin=4 makes the circuit more stable and facilitates the establishment of magnetizing current. At the target light load point, the controller calculates the duty cycle Dseq_light of the pulse sequence consisting of continuous operating pulse groups and complete sleep intervals based on the error between the target output voltage and the actual voltage. According to the relevant definition of duty cycle:

[0027]

[0028] Where N is the number of working cycles, and Ntotal is the number of control cycles. Under light load conditions, to ensure... Then the minimum number of control cycles, Ntotal_min, should satisfy:

[0029]

[0030] Here, ceil represents rounding up, which is a lower limit for the number of cycles set to ensure efficiency under light loads and soft switching. The lighter the load, the smaller Dseq_light, and the larger the required Ntotal_min. By increasing the sleep cycle time, switching losses are reduced, and the circuit's peak efficiency is achieved.

[0031] Output voltage ripple The ripple is primarily determined by the charge Qpulse injected by the working pulse group and the output capacitance Cout, therefore the ripple must be limited to its maximum value. Inside.

[0032] The total charge transferred to the output in every N working cycles Where Pout is the output power and Vout is the output voltage. The output capacitor Cout discharges every M sleep cycles, and its voltage drops. ,That Dseq is the duty cycle of a pulse sequence consisting of a continuous working pulse group and a complete sleep interval. Therefore, the ripple can also be expressed as:

[0033]

[0034] make ,get ,because Where Pmax is the maximum input power

[0035] The efficiency is η, where η is the circuit conversion efficiency. Therefore, under light load, Dseq is very small, (1-Dseq)≈1, and the formula can be simplified to:

[0036]

[0037] Then the maximum value of the number of control cycles, Ntotal_max1, should satisfy:

[0038]

[0039] This is another maximum cycle count set to ensure that the output voltage ripple does not exceed the upper limit. In actual engineering, It is typically 0.5% to 1% of the actual output voltage Vout.

[0040] Combining formulas (2), (4), and (7), we can obtain that Ntotal must satisfy... .

[0041] To balance dynamic response, peak efficiency, and output voltage ripple, the optimal number of control cycles Ntotal should satisfy the following:

[0042]

[0043] Furthermore, the method for calculating the pulse sequence duty cycle under different gains and output power conditions by the pulse sequence duty cycle control module is characterized by automatically adjusting the pulse sequence duty cycle based on the error between the target voltage and the actual output voltage, thereby achieving fast dynamic response and wide voltage regulation. The specific implementation principle is as follows:

[0044] When the switching frequency is fixed at the first resonant frequency fr, where fr = Lr and Cr correspond to the values ​​of the resonant inductance and resonant capacitance, respectively, according to the relevant expressions for the gain M and the switching frequency fs:

[0045]

[0046] in , , , , We can obtain the circuit gain M=1 at this time, that is, when the circuit is in the continuous working pulse period, the gain M=1. When the circuit is in complete sleep mode, since the input voltage of the resonant cavity is 0, it means that no energy transfer occurs, that is, the gain M=0 when the circuit is in complete sleep mode.

[0047] According to the relevant definition of duty cycle (3), the relevant expression of gain M and duty cycle Dseq during the control period can be calculated:

[0048]

[0049] Combination Figure 5 As shown in (a) and (b), under PFM control, the circuit gain changes less at high frequencies, indicating a longer dynamic response time at high frequencies, i.e., a longer dynamic response time in low-gain mode. In contrast, under the control method adopted in this invention, the circuit gains change more rapidly by adjusting the duty cycle of the pulse sequence consisting of continuous working pulse groups and complete sleep intervals, thus achieving fast dynamic response and wide voltage regulation.

[0050] Furthermore, the control method for the dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation includes the following steps:

[0051] (1) Initialization of the control circuit of the CLLLC resonant converter and the dual-mode CLLLC resonant converter based on fixed frequency pulse sequence modulation;

[0052] (2) The control circuit of the dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation fixes the switching frequency fs at the first resonant frequency fr, where fr = Lr and Cr correspond to the values ​​of resonant inductance and resonant capacitance, respectively;

[0053] (3) The control circuit of the dual-mode CLLLC resonant converter based on fixed frequency pulse sequence modulation defines a pulse sequence control cycle as N+M consecutive switching cycles, where N and M are both positive numbers, and are used to define the alternating working period and the sleep period, respectively.

[0054] (4) During the working period, the switching transistors of the CLLLC resonant converter are controlled to perform full-bridge switching at the first resonant frequency fr; during the sleep period, all switching transistors are controlled to turn off.

[0055] (5) The control circuit of the dual-mode CLLLC resonant converter based on fixed frequency pulse sequence modulation adjusts the duty cycle Dseq of the pulse sequence consisting of continuous working pulse group and complete sleep interval according to the error between the target output voltage Vref and the current output voltage Vout.

[0056] (6) The control circuit of the dual-mode CLLLC resonant converter based on fixed frequency pulse sequence modulation determines the optimal number of control cycles Ntotal according to formula (8) based on the duty cycle Dseq of the control pulse sequence, the output voltage Vout and the output power Pout, taking into account the dynamic response, peak efficiency and output voltage ripple performance.

[0057] (7) When the output voltage reaches the target voltage value and can remain stable, the above steps are terminated.

[0058] Compared with the prior art, the outstanding technical effect of the present invention is as follows:

[0059] 1. The present invention provides a method for calculating the control cycle range under different operating modes using a variable control cycle module. The method is characterized by automatically adjusting the control cycle range of the pulse sequence by controlling the duty cycle of the pulse sequence, the output voltage, and the output power, thereby achieving rapid dynamic response, high peak efficiency, and low ripple output voltage.

[0060] 2. The method for calculating the pulse sequence duty cycle under different gain and output power conditions by the pulse sequence duty cycle control module of the present invention is characterized by automatically adjusting the pulse sequence duty cycle according to the error between the target voltage and the actual output voltage, thereby achieving fast dynamic response and wide voltage regulation.

[0061] 3. Under light load and low gain modes, conduction losses can be reduced by significantly increasing the sleep cycle, thus achieving high peak efficiency. Attached Figure Description

[0062] Figure 1This is a block diagram of a dual-mode CLLLC resonant converter circuit and control method based on fixed-frequency pulse sequence modulation as described in this invention.

[0063] Figure 2 This is a flowchart of the control method for a dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation as described in this invention.

[0064] Figure 3 The diagram shows the control block diagram of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation of the present invention.

[0065] Figure 4 This diagram shows the timing state of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation in the forward charging mode with an input voltage of 400Vdc and an output power of 4.8 KW.

[0066] Figures 5 to 7 This is a comparison chart of the dynamic response performance of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention.

[0067] Figures 8 to 9 The figure shows the forward conversion efficiency and loss performance of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention.

[0068] Figures 10 to 11 The diagram shows the reverse conversion efficiency and loss performance of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention. Detailed Implementation

[0069] The following is in conjunction with the appendix Figure 1-11 This application will be described in further detail.

[0070] To make the objectives, technical solutions, and advantages of this invention clearer, the following embodiments will be used in conjunction with the accompanying drawings to further illustrate the method of this invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the principles of the circuit structure and method of this invention should be included within the scope of protection of this invention.

[0071] See Figure 1The dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation includes a bus capacitor Cbus, CLLLC switches S1-S8, resonant inductors Lr1 and Lr2, resonant capacitors Cr1 and Cr2, a magnetizing inductor Lm, a transformer T1, and an output capacitor Co. The two ends of the bus capacitor Cbus are connected to the positive and negative terminals of the input voltage V1, respectively. The drains of switches S1 and S3 are connected to one end of the bus capacitor Cbus. The other end of the bus capacitor Cbus is connected to the source of switches S2 and S4. The source of switch S1 and the drain of switch S2 are connected to one end of the resonant inductor L1. The other end of the resonant inductor L1 is connected to one end of the primary winding of transformer T1. The other end of the primary winding of transformer T1 is connected to the resonant capacitor Cr1. One end of the resonant capacitor Cr1 is connected to the source of the switch S3 and the drain of the switch S4; the magnetizing inductor Lm is connected in parallel across the primary side of the transformer T1; one end of the secondary side of the transformer T1 is connected to one end of the resonant inductor Lr2; the other end of the resonant inductor Lr2 is connected to the source of S5 and the drain of S6; the drains of the switches S5 and S7 are connected to one end of the output capacitor Co; the other end of the output capacitor Co is connected to the source of S6 and S8; the source of the switches S7 and S8 is connected to one end of the resonant capacitor Cr2; the other end of the resonant capacitor Cr2 is connected to the other end of the secondary side of the transformer T1; the sources of the switches S2, S4, S6, and S8, one end of the bus capacitor Cbus, and one end of the output capacitor Co are connected to ground.

[0072] See Figure 1 The control circuit based on fixed-frequency pulse sequence modulation includes a first analog-to-digital converter (ADC1), a second analog-to-digital converter (ADC2), a variable control period module, a pulse sequence duty cycle control module, and a PWM modulation module. The first ADC1 and the second ADC2 sample the forward and reverse output voltages of the CLLLC resonant circuit, respectively. The outputs of the first ADC1 and the second ADC2 are connected to the inputs of the variable control period module and the pulse sequence duty cycle control module, respectively, generating control signals for the forward charging and reverse discharging modes. The output of the pulse sequence duty cycle control module is connected to the input of the variable control period module, automatically adjusting the control period of the pulse sequence based on the control pulse sequence duty cycle, output voltage, and output power. The outputs of the variable control period module and the pulse sequence duty cycle control module are connected to the input of the PWM modulation module, generating drive signals for the switching transistors S1-S8.

[0073] See Figure 2This is an embodiment of the dual-mode CLLLC resonant converter control method based on fixed-frequency pulse sequence modulation described in this invention, and its steps are as follows:

[0074] Z1, initialization of the control circuit for the CLLLC resonant converter and the dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation;

[0075] Z2. The control circuit of the dual-mode CLLLC resonant converter based on fixed-frequency pulse sequence modulation fixes the switching frequency at the first resonant frequency fr, where fr = Lr and Cr correspond to the values ​​of resonant inductance and resonant capacitance, respectively;

[0076] Z3. The control circuit of the dual-mode CLLLC resonant converter based on fixed frequency pulse sequence modulation defines a pulse sequence control cycle as N+M consecutive switching cycles, where N and M are both positive integers, used to define the alternating working period and the sleep period, respectively.

[0077] Z4. During the working period, control the switching transistors of the CLLLC resonant converter to perform full-bridge switching at the first resonant frequency fr; during the sleep period, control all switching transistors to turn off.

[0078] Z5. A dual-mode CLLLC resonant converter control circuit based on fixed-frequency pulse sequence modulation adjusts the duty cycle Dseq of a pulse sequence consisting of a continuous working pulse group and a complete sleep interval according to the error between the target output voltage Vref and the current output voltage Vout.

[0079] Z6. The control circuit of the dual-mode CLLLC resonant converter based on fixed frequency pulse sequence modulation determines the optimal number of control cycles Ntotal according to formula (8), which takes into account dynamic response, peak efficiency and output voltage ripple performance, based on the duty cycle Dseq of the control pulse sequence, the output voltage Vout and the output power Pout.

[0080] Z7. When the output voltage reaches the target voltage value and can remain stable, the above steps end.

[0081] Figure 3 This is a control block diagram of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention. Figure 3V1 and V2 represent the output voltage values ​​in forward charging mode and reverse discharging mode, respectively. V1 or V2 is compared with the corresponding output voltage reference value Vref to obtain a voltage error value Verror. The voltage error value Verror is input to the PI controller, and after adjustment, it outputs the duty cycle Dseq of a pulse sequence consisting of a continuous working pulse group and a complete sleep interval. The pulse sequence duty cycle Dseq is transmitted to PWM module 1, which generates a first PWM signal based on Dseq, with an output duty cycle of Dseq. The output period of PWM module 1 depends on the variable control period module, and its period value Tseq satisfies: Ntotal is calculated by formula (8), and fr is the first resonant frequency of the CLLLC resonant converter. Simultaneously, the PWM signal output by PWM module 2 has a duty cycle of 50% and a frequency equal to the first resonant frequency fr. The two PWM signals output by PWM module 1 and PWM module 2 are logically operated through a logic gate, and then driven by a drive circuit to obtain the drive signals for switches S1~S4 in the forward charging mode and the drive signals for switches S5~S8 in the reverse discharging mode, respectively. Through the above control structure, while maintaining the switching frequency fixed at the first resonant frequency fr and the bridge arm drive duty cycle at 50%, a wide range of output voltage adjustment can be achieved by simply adjusting the pulse sequence duty cycle Dseq and the control period Ntotal, while also considering dynamic response performance, light-load efficiency, and output voltage ripple performance.

[0082] Figure 4 This diagram illustrates the timing of a dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation, operating under a 400Vdc input voltage and 4.8 kW output power forward charging mode. When the CLLLC resonant converter is in its operating phase, switches S1-S4 maintain a 50% duty cycle, with the switching frequency equal to the first resonant frequency fr. The drive signals of switches S3 and S4 lag behind the drive signals of S1 and S2 by 180°, respectively, thus forming a symmetrical full-bridge drive waveform on the primary side. In this operating state, the input voltage Vab of the primary resonant cavity is a square wave signal with an amplitude equal to the input voltage V1; the primary resonant current Ilr1 is approximately a sine wave signal with a frequency equal to the first resonant frequency fr. When the CLLLC resonant converter is in its sleep phase, the control system forcibly shuts down switches S1-S4, causing the primary bridge arm to stop working. At this time, both the input voltage Vab and the primary resonant current Ilr1 are equal to 0, achieving zero energy transfer and thus reducing switching losses under light load conditions. According to formula (8), the number of control switching cycles Ntotal is 13 under steady-state operation. By adjusting the control system, a comprehensive optimization and balance can be achieved between dynamic response performance, light-load operation efficiency, and output voltage ripple performance.

[0083] Figures 5 to 7 This is a comparison chart of the dynamic response performance of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention. Figure 5 The graph shows the relationship between the gain M and the switching frequency fn of CLLLC resonant converters with different output powers under traditional PFM control conditions. Figure 6 This is a graph showing the relationship between the gain M and duty cycle Dseq of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention. (Comparison) Figure 5 and Figure 6 It can be observed that, at high frequencies, the gain change of the CLLLC resonant converter controlled by PFM is relatively slow, resulting in poor dynamic response performance and a limited adjustable voltage range. In contrast, the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation of this invention fixes the switching frequency to the first resonant frequency fr. The output voltage is adjusted by regulating the duty cycle Dseq of the pulse sequence consisting of a continuous working pulse group and a complete sleep interval. The gain changes rapidly across the entire duty cycle range, enabling fast dynamic response and wide output voltage adjustment. Figure 7 The graphs showing the output voltage Vout versus time t under the control algorithm used in this invention and the traditional PFM control demonstrate that the control algorithm used in this invention achieves faster output voltage stabilization and better dynamic response performance compared to the traditional PFM algorithm. These experimental results verify the theoretical analysis described above.

[0084] Figures 8 to 9 The figure shows the forward conversion efficiency and loss performance of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention. Figure 8 The diagram shows the circuit conversion efficiency under forward charging mode with an input voltage of 400Vdc and an output power of 4.6KW~5.6KW. Under heavy load conditions, the forward conversion efficiency exceeds 92.7%, which is better than the circuit conversion efficiency performance of Reference 1 and close to that of Reference 2. Under light load conditions, the forward conversion efficiency exceeds 92.2%, which is better than the circuit conversion efficiency performance of Reference 1 but lower than that of Reference 2. However, Reference 1 cannot solve the problem of significantly reduced circuit conversion efficiency under light load conditions, and its applicable voltage and power range is limited to low-voltage, low-power scenarios. Reference 2 shows a more significant drop in circuit conversion efficiency under heavy load conditions, failing to guarantee high-efficiency and stable operation of the CLLLC resonant converter across the entire power range. Furthermore, it only supports unidirectional power transmission under low voltage and medium power conditions, and cannot achieve stable bidirectional transmission of the CLLLC resonant converter under high-voltage, high-power scenarios, thus limiting its application scope. Figure 9The diagram shows the main component losses of the circuit in forward charging mode with an input voltage of 400Vdc and an output power of 4.6KW~5.6KW. The main losses of the converter are concentrated in the conduction and turn-off losses of the secondary rectifier switch. The control strategy adopted in this invention fixes the switching frequency at the resonant frequency, fundamentally avoiding the additional increase in switching losses caused by frequency adjustment; at the same time, through dynamic adjustment of the sleep cycle, the switching losses of the switch under light load conditions are significantly reduced, so that the primary switch losses are always kept at a low level, ultimately achieving high-efficiency and stable operation of the converter across the entire power range.

[0085] Figures 10 to 11 The diagram shows the reverse conversion efficiency and loss performance of the dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation according to the present invention. Figure 10 The circuit conversion efficiency diagram shows a circuit with a 260Vdc input voltage and an output power of 2.1KW~3.1KW in reverse discharge mode. The circuit achieves a reverse conversion efficiency exceeding 93.3% under heavy load and over 91.2% under light load, outperforming the circuit conversion efficiency performance of Reference 1. However, Reference 1 only achieves a maximum circuit conversion efficiency of 89.7% in reverse discharge mode and cannot address the significant decrease in efficiency under light load conditions. Its applicable voltage and power range is limited to low-voltage, low-power scenarios, failing to meet the application requirements of medium-high voltage and medium-high power applications. Reference 2 only achieves unidirectional energy transfer and does not provide a circuit conversion efficiency diagram in reverse discharge mode. Figure 11 The diagram shows the main component losses of the circuit under reverse discharge mode with an input voltage of 260Vdc and an output power of 2.1KW~3.1KW. The main losses of the converter are concentrated in the conduction and turn-off losses of the switching transistors. The control strategy adopted in this invention fixes the switching frequency at the resonant frequency, fundamentally avoiding the additional increase in switching losses caused by frequency adjustment; at the same time, through dynamic adjustment of the sleep cycle, the switching losses of the switching transistors under light load conditions are significantly reduced, so that the switching losses of the switching transistors are always kept at a low level, ultimately achieving high-efficiency and stable operation of the converter across the entire power range.

[0086] This invention proposes a control method and system for a dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation. Addressing the problems of decreased efficiency under light load, slower dynamic response, and increased high-frequency modulation losses associated with traditional PFM, PSM, and hybrid modulation strategies under wide input voltage and load ranges, this invention strictly fixes the switching frequency at the optimal resonant frequency point. By constructing a pulse sequence control mode consisting of continuous operating pulses and complete sleep states, a wide range of output voltage adjustment is achieved simply by adjusting the pulse sequence duty cycle and control period. Furthermore, a control period optimization method that balances dynamic response, peak efficiency, and output voltage ripple is proposed, achieving a comprehensive trade-off between control bandwidth, efficiency, and stability. This method operates stably in both forward charging and reverse discharging modes, achieving high-efficiency output across the entire power range under both light and heavy loads within a high-voltage, high-power range, while significantly reducing switching losses under light loads and improving dynamic response speed. This embodiment supports dual operating modes of active and passive periods. In the forward charging mode (input voltage 390~450V, output power 4.6kW~5.6kW), the method achieves a forward conversion efficiency exceeding 92.7% under heavy load and exceeding 92.2% under light load. In the discharge mode (input voltage 260~300V, output power 2.1kW~3.1kW), the method achieves a reverse conversion efficiency exceeding 93.3% under heavy load and exceeding 91.2% under light load. No design of a variable control period pulse sequence control mode consisting of a continuous operating pulse group and a complete passive interval has been found in existing literature and patents to date, thus achieving a CLLLC resonant converter and method with high power conversion efficiency and fast dynamic response over a wide input voltage and output power operating range.

[0087] The above embodiments are merely preferred embodiments of the present invention and should not be considered as limiting the scope of the present invention. All equivalent variations and improvements made within the scope of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A control method for a dual-mode CLLLC resonant converter based on fixed resonant frequency pulse sequence modulation, characterized in that, The method includes the following steps: Z1. Frequency Locking: Locking the switching frequency f of the CLLC resonant converter. s Strictly fixed at the first resonant frequency f r ; Z2. Define the pulse sequence period: A pulse sequence control period is defined as N+M consecutive switching cycles, where N is the number of working pulses used to define the working period, and M is the number of sleep cycles used to define the sleep period. The control process is divided into a pulse sequence control period consisting of alternating working and sleep periods. During the working period, the switching transistors of the CLLLC resonant converter are controlled to perform full-bridge switching at the first resonant frequency. During the sleep period, all switching transistors are turned off. Z3. Dual-mode switching control: During the operating period, the converter switching transistors are controlled to perform full-bridge switching at the first resonant frequency fr; during the sleep period, all switching transistors are forcibly turned off to stop energy transmission. Z4. Duty Cycle Adjustment: Based on the target output voltage V ref With the current output voltage V out To mitigate the error, adjust the duty cycle D of the pulse sequence consisting of the working period and the sleep period. seq ; Z5. Optimal control cycle calculation: Based on the pulse sequence duty cycle Dseq, the current output voltage Vout, and the output power Pout, the optimal control cycle number Ntotal is automatically calculated and updated to balance dynamic response, peak efficiency, and output voltage ripple.

2. The control method according to claim 1, characterized in that, The optimal control cycle number N total The calculation method is as follows: The upper limit N is determined by combining the system closed-loop bandwidth. total_max1 The upper limit value N determined by the output voltage ripple limit total_max2 And to ensure the lower limit N of light-load efficiency and soft switching total_min A comprehensive value is obtained. The optimal control cycle number N is... total The calculation formula is:

3. The control method according to claim 2, characterized in that, The lower limit value of the number of cycles N total_min The calculation formula is: Where, N min This is the preset minimum number of operating pulses, used to ensure the completion of the full resonant energy transfer process and maintain the soft-switching function.

4. The control method according to claim 2, characterized in that, The upper limit N of the number of cycles is determined based on the system closed-loop bandwidth. total_max1 satisfy: Among them, f bw K is the closed-loop bandwidth of the system. s This is the oversampling coefficient, with a value ranging from 5 to 10.

5. The control method according to claim 2, characterized in that, The upper limit value of the number of cycles N total_max2 Based on the upper limit of output voltage ripple ΔV max It is confirmed that the calculation formula is as follows: Among them, C out For the output capacitor, T sw The switching cycle.

6. The control method according to claim 1, characterized in that, The generation logic of the pulse sequence duty cycle Dseq is as follows: V out With V ref Error value V error The input is fed into a PI controller, and after adjustment, the output D is obtained. seq And in conjunction with the period value T generated by the variable control period module seq They work together in the PWM modulation module.

7. The control method according to claim 1, characterized in that, The drive signal configuration for the working period is as follows: the duty cycle of the primary side bridge arm drive signal is 50%, and the drive signal of the corresponding bridge arm (such as S3, S4) is lagging behind the other group of bridge arms (such as S1, S2) by 180° phase, forming a symmetrical full-bridge drive.

8. The control method according to claim 1, characterized in that, The method supports bidirectional energy transfer, including a forward charging mode and a reverse discharging mode, which is achieved by sampling the forward and reverse output voltages respectively and generating corresponding drive signals.

9. The control method according to claim 3, characterized in that, The minimum number of working pulses N min The value can be between 2 and 4, where 2 ensures a complete positive and negative voltage cycle, and 4 is used to stabilize the circuit and facilitates the establishment of magnetizing current.

10. The control method according to claim 4, characterized in that, The upper limit of voltage ripple ΔV max Set to the actual output voltage V out 0.5% to 1%.

11. A dual-mode CLLLC resonant converter control system implementing the method of any one of claims 1 to 10, characterized in that, include: (1) CLLLC resonant circuit section, including switching transistors S1-S8, resonant elements and transformer; (2) The control circuit section includes an analog-to-digital converter (ADC), a variable control cycle module, a pulse sequence duty cycle control module, and a PWM modulation module. The pulse sequence duty cycle control module is used to control the output voltage V based on the target output voltage. ref With the current output voltage V out The error is used to generate a pulse sequence with duty cycle D consisting of working and sleeping periods. seq The variable control cycle module is used to automatically calculate and update the optimal number of control cycles Ntotal based on the pulse sequence duty cycle Dseq, the current output voltage Vout, and the output power Pout.

Images