A three-level inverter PWM frequency dynamic adjustment method

Abstract

This invention relates to a dynamic adjustment method for the PWM frequency of a three-level inverter, the execution steps of which include: S1, master station condition determination: the master controller monitors the motor operating status in real time and determines whether the frequency or mode switching conditions are met; S2, communication delay prediction: calculate the next common point time and the latest transmission time; S3, instruction transmission decision; S4, slave station reception confirmation: the slave controller receives the switching instruction frame, verifies it, extracts the target common point information, and prepares to synchronously update the PWM parameters at the common point time; S5, synchronous execution of switching: at the specified common point time, the slave station synchronously updates the PWM frequency, sampling period, and modulation mode; the master station synchronously performs one-time angle compensation and current loop PI regulator blocking; S6, stable operation recovery: the signal is reset, the current loop PI regulator resumes normal operation, and the system operates stably with the new frequency and new mode.

Description

Technical Field

[0001] This invention belongs to the field of three-level inverter topology technology, and relates to PWM pulse width modulation control, especially a method for dynamic adjustment of PWM frequency in a three-level inverter. Background Technology

[0002] With the widespread application of power electronics technology in rail transit, new energy power generation, and high-performance motor drives, three-level inverters have become the mainstream topology due to their advantages such as low output voltage harmonics and low switching losses. In actual operation, in order to balance system efficiency and control performance, it is often necessary to dynamically adjust the PWM switching frequency according to the load conditions (for example, reducing the frequency to reduce losses under light loads and increasing the frequency under heavy loads or high dynamic response). However, dynamic adjustment of the PWM frequency is not a simple parameter modification; it involves several complex issues such as sampling synchronization, delay compensation, and hardware coordination.

[0003] However, existing PWM frequency switching technologies have the following main problems: Delay caused by physical separation: Existing technologies mostly focus on "centralized control", while actual engineering often adopts a distributed architecture of "separation of main control (DSP / MCU) and driver (FPGA)". The two communicate through fiber optic / differential signals, which has an inherent delay of 7~9μs. If there is no predictive forced switching, it will lead to voltage surges and inrush currents.

[0004] Mismatch between sampling and control: If the sampling periods are not synchronized during frequency switching, it will lead to spectrum leakage; if the delay compensation parameters of the control loop are not updated, it will lead to system oscillation.

[0005] Voltage and current surges: Three-level inverters have multiple modulation modes (Mode 0 / Mode 1). If frequency or mode switching occurs at a non-specific point (non-common peak / valley) of the carrier wave, a voltage surge will occur, resulting in a huge current surge that can damage power devices (such as IGCTs).

[0006] The following is a brief analysis of the aforementioned technical issues: Existing PWM frequency switching technologies are mostly concentrated in centralized distributed control architectures, failing to fully consider the communication latency challenges brought about by such distributed hardware architectures. In distributed architectures, the control algorithm and PWM generation are usually located on different hardware boards (such as the master CPU and the slave FPGA), connected by high-speed communication. This physical separation leads to unavoidable signal transmission delays. When frequency switching occurs, if the sampling period cannot switch synchronously to maintain whole-cycle sampling, it will lead to spectrum leakage and decreased control accuracy. At the same time, changes in switching frequency will change the system's equivalent sampling delay. If the delay compensation in the control closed loop does not switch accordingly, it can easily cause system oscillations or even instability. That is, frequency coordination commands depend on communication transmission, and delays will lead to asynchronous frequency modulation and conflicting switching, causing communication delays and packet loss. This can result in harmonic superposition or, in severe cases, triggering overcurrent and shutdown.

[0007] Furthermore, three-level inverters have multiple modulation modes (such as Mode 0 and Mode 1), and mode switching is accompanied by changes in sampling and delay parameters. More critically, if frequency or mode switching does not occur at a specific point on the carrier (such as a common peak / valley point), it will cause voltage surges leading to current surges and damaging power devices. In distributed systems, due to communication lag, if the master station sends a switching command close to the common point, the slave station may not be able to synchronize in time. When the master station issues a frequency switching command, the slave station often receives it after missing the optimal carrier synchronization point. If a forced switch is performed at this time, it will cause voltage surges and inrush currents; if the next natural synchronization point is waited for, the waiting time may be too long, affecting the dynamic response. This leads to severe zero-sequence circulating current, common-mode interference, power imbalance, and a sharp drop in system efficiency and reliability.

[0008] In existing technologies, multiple distributed converters are typically connected in parallel to address the random accumulation of high-frequency harmonics at the PCC point, and fast global synchronization modulation is proposed to force multi-machine carrier / frequency coordination. However, a coordination mechanism that comprehensively considers communication delay, sampling synchronization, delay compensation, and carrier alignment is lacking, making it difficult to simultaneously achieve zero current inrush and minimum handover delay during multi-frequency handover from 125Hz to 1000Hz. Therefore, a dynamic adjustment method that can compensate for communication delay and achieve precise carrier alignment is urgently needed to solve the handover challenges under the aforementioned distributed architecture.

[0009] A search revealed several patent documents addressing similar technical issues, including: Chinese patent with publication number CN113765424A provides a method and apparatus for synchronous carrier modulation of a three-level inverter. This method is a centralized control method with no DSP+FPGA distributed master-slave architecture, which is significantly different from the technical solution of this invention application. Chinese patent CN121395955A discloses a three-phase three-wire three-level hybrid modulation switching method, device and medium, which realizes continuous / discontinuous space vector modulation switching. It reduces algorithm complexity and improves reliability through a unified PWM strategy. However, its technical means belongs to software parameter switching under a centralized control architecture. It directly generates the target modulation wave by changing the unified coefficient, without limiting the specific time of switching execution, and does not address the timing misalignment control inside the FPGA and the voltage loss problem during the mode switching process.

[0010] In summary, existing technologies lack a collaborative mechanism that can comprehensively consider communication delay prediction, carrier common point alignment, sampling period synchronization, delay compensation update, and mode switching timing control. This makes it difficult to achieve zero current impact and minimize switching delay when switching between multiple frequency points from 125Hz to 1000Hz and modulation modes in a distributed architecture. Summary of the Invention

[0011] This invention addresses the technical problems of multi-machine carrier / frequency asynchrony, communication delay, and packet loss by providing a dynamic PWM frequency adjustment method for three-level inverters that can compensate for communication delay, achieve precise carrier alignment, and accommodate multi-mode switching. It is applicable to distributed hardware systems with separate main control and drive, and aims to achieve smooth and shock-free switching of three-level inverters between different switching frequencies and modulation modes.

[0012] The present invention adopts the following technical solution to achieve the above objectives: A method for dynamically adjusting the PWM frequency of a three-level inverter, the method being based on a distributed communication architecture, which includes a master controller and multiple slave controllers, forming two physically separate processing units, master and slave. The execution steps are as follows: S1, Master station condition determination: The main controller monitors the motor's operating status in real time and determines whether the frequency or mode switching conditions are met. S2, Communication Delay Prediction: The main controller queries the current communication status and obtains the measured delay. Calculate the time of the next common point. and latest sending time ; S3, Instruction Sending Decision: If the current time... Latest sending time Immediately assemble the switching instruction frame, which includes the new frequency, new mode, and target common point information; if the previous time... Set a waiting flag, recalculate and send at the next common point period; S4, Slave station receives confirmation: The slave controller receives the switching instruction frame, verifies it, extracts the target common point information, loads it into the carrier counter and comparison register of the slave controller, and prepares to synchronously update the PWM parameters at the common point. S5, Synchronous execution switching: At the specified common point time, the slave station synchronously updates the PWM frequency, sampling period and modulation mode; the master station synchronously performs one-time angle compensation and current loop PI regulator blocking to achieve strict time and space alignment of the master and slave station actions. The state before the system switching is stored in the latched signal in the interval that avoids the impact of the sampling switching after the switching. The latched signal is set at the time of switching and maintains the blocking time after the switching. S6, Stable Recovery Operation: After the blocking time is completed, the latch signal is reset, the current loop PI regulator resumes normal operation, and the system operates stably in the new frequency and mode.

[0013] Furthermore, the main controller is responsible for executing the field orientation control algorithm, frequency switching decision, communication delay prediction, and angle compensation calculation; the slave controller is responsible for PWM waveform generation, sampling trigger pulse output, carrier counting management, and modulation mode logic implementation. The slave controller is connected to the power drive board through optical fiber or differential signal line to realize the switching control of power devices. The high-speed communication interface between the main controller and the slave controller adopts the 50Mbps optical fiber communication protocol.

[0014] Furthermore, in S1, the main controller is equipped with a sampling period and frequency synchronization mechanism, i.e., the sampling period is calculated... ,in The sampling period is This refers to the PWM switching frequency; for a frequency of 125Hz, 0.008s; for a frequency of 1kHz, 0.001s, After the frequency or modulation mode switching command is issued, the main controller synchronously updates the control equivalent delay compensation parameters in the control closed loop. The calculation basis for the control equivalent delay compensation amount dtc is as follows: This compensation amount is used to correct the phase lag introduced by the average value sampling and PWM carrier comparison.

[0015] Furthermore, in S2, a switching time determination mechanism based on communication delay prediction is set up to calculate the common point of carrier signals of different PWM frequencies and set it as the safe time for allowing switching. For any two switching frequencies... and ,set up Calculate its greatest common divisor gcd ( , The period of occurrence of its carrier common point is: Calculation of the latest sending time The main controller monitors the relative position of the current moment and the next common point in real time. If the current moment... < If so, immediately send a switching command; if > If so, you will be forced to wait until the next public point.

[0016] Furthermore, in S5, during the process of synchronously updating the PWM frequency, sampling period, and modulation mode by the slave station, carrier modulation constraints are set: Define the triangular carrier slope signal CB, where CB=1 during the rising phase and CB=0 during the falling phase.

[0017] To prevent multi-pulse phenomena during mode switching, the direction of PWM output level transitions is constrained: When CB=0, only the PWM output level is allowed to change from -1 to 0 or from 0 to 1; When CB=1, only the PWM output level is allowed to change from 0 to -1 or from 1 to 0. The carrier modulation constraint is implemented through combinational logic within the controller. During modulation mode switching, a timing misalignment update mechanism is set for the mode switching signal AF and the carrier slope signal CB. The AF signal is updated in the nth clock cycle, and the CB signal is updated in the n+kth clock cycle, where k is an integer from 2 to 10. This ensures that the update time of the CB signal lags behind that of the AF signal, avoiding voltage loss caused by synchronous updates. During modulation mode switching, the synchronization mechanism of frequency switching is reused to support mode switching accompanied by carrier frequency switching, and level jumps that violate the rules are prohibited.

[0018] Furthermore, in S5, the master station synchronously performs one-time angle compensation and PI blocking to achieve spatiotemporal alignment of the actions of the master and slave stations. The spatiotemporal alignment is ensured by the synchronization signal to ensure that the average current / voltage sampling value used by the magnetic field orientation module is strictly aligned with the PWM update time before and after the switch. The completion time of the last set of average value sampling before the switch and the start time of the first set of average value sampling after the switch both coincide with the common point time, eliminating the time misalignment of the sampling data.

[0019] Furthermore, the compensation mechanism for the one-time compensation of the synchronous execution angle is as follows: Based on the old sampling period before switching The average angle calculated after switching based on the new sampling period The average calculated angle has an inherent bias, which stems from changes in the sampling window length. This bias requires a one-time numerical compensation at the moment of switching. Angle compensation amount ,in This is the magnetic field orientation angle compensation amount, used to compensate for the magnetic field orientation angle deviation caused by sampling period switching. The angle output by the magnetic field orientation module. dt is the angular velocity of the motor (rad / s) and dt is the equivalent time deviation.

[0020] Furthermore, the blocking mechanism of the PI block is as follows: The system needs to avoid the period affected by the sampling switch. This time depends on the PWM switching frequency after the switch. The latch signal, i.e., the Lock signal, is used to latch the system's state before the switch, thus ensuring that the system avoids the period affected by the sampling switch after the switch. The Lock signal is set at the time of the switch and remains active for a certain duration after the switch. Normal vector control can only be resumed after the system stabilizes. Set to a complete sampling cycle after the switch, before the Lock signal switches the sampling, the motor field vector orientation module and the current loop PI regulator are blocked: the input signal of the PI regulator is forced to switch to zero, and the output value remains in the state before the switch to prevent integral saturation or sudden change. After the Lock signal switches the sampling, the PI regulator resumes normal operation with the maintained output value as the initial value.

[0021] Furthermore, the main controller employs a high-performance microprocessor or digital signal processor.

[0022] Furthermore, the slave controller employs an application-specific integrated circuit or a field-programmable gate array.

[0023] Compared with the prior art, the present invention has the following beneficial effects: 1. The dynamic frequency adjustment method for three-level inverter PWM based on distributed communication architecture provided by this invention completely eliminates the sudden changes in given voltage and current surges during frequency / mode switching through the carrier common point switching alignment mechanism, thus protecting power devices.

[0024] 2. The dynamic adjustment method for PWM frequency of three-level inverter provided by the present invention is based on a distributed communication architecture. It innovatively considers the communication delay between boards and solves the problem of master-slave station synchronization lag through a prediction mechanism, thereby improving the engineering practicality of the system.

[0025] 3. The dynamic adjustment method for PWM frequency of a three-level inverter based on a distributed communication architecture provided by this invention synchronously switches the sampling period and delay compensation parameters in the deployment of the sampling period and frequency synchronization mechanism, avoiding control loop oscillation caused by model mismatch and achieving high control stability.

[0026] 4. The dynamic adjustment method for PWM frequency of a three-level inverter based on a distributed communication architecture provided by this invention has a fast dynamic response: It minimizes PI blocking time and switching waiting time while ensuring safety. Under the graded switching strategy, the switching time in the full range of 125Hz-1000Hz does not exceed 0.008s, realizing a fast and smooth transition for online PWM frequency switching. At the same time, through timing misalignment control and mechanism reuse, it realizes seamless switching between mode 0 and mode 1, avoiding voltage loss. Attached Figure Description

[0027] Figure 1 This is a logical block diagram of the distributed communication architecture involved in this invention; Figure 2 This invention relates to two modulation modes of a three-level topology, wherein: Figure 2 (a) is the carrier comparison method for modulation mode 0; Figure 2 (b) is the carrier comparison method for modulation mode 1; Figure 3 This is a logic block diagram showing the correspondence between the PWM switching frequency and the sampling period during the sampling period and frequency synchronization mechanism of the present invention. Figure 4 This is a logic block diagram of the latest handover command transmission time in the handover time determination process based on carrier alignment of the present invention; Figure 5 This is a logic block diagram of the control closed-loop disturbance suppression strategy of the present invention; Figure 6 This is a system blocking logic block diagram of the switching delay avoidance process of the present invention; Figure 7 This is a logic block diagram of modulation mode switching in the modulation mode switching coordination process of the present invention. Figure 8 This is a logic block diagram of the timing misalignment control of the present invention, wherein: Figure 8 (a) is a sequence diagram of the problematic timing. Figure 8 (b) is a logic block diagram of the timing misalignment control of the present invention; Figure 9 These are comparison waveforms of frequency switching under conventional frequency regulation and the three-level inverter PWM frequency dynamic regulation method provided by this invention, wherein: Figure 9 (a) is a waveform diagram of conventional frequency switching. Figure 9 (b) is a waveform diagram of frequency switching according to the present invention; Figure 10The waveform diagrams are obtained from the switching test under the three-level inverter PWM frequency dynamic adjustment method provided by this invention, where: Figure 10 (a) is a waveform diagram of the 250Hz to 500Hz frequency switching test. Figure 10 (b) is the waveform diagram of the 500Hz to 250Hz frequency switching test. Figure 10 (c) is the waveform diagram of the 500Hz to 1000Hz frequency switching test. Figure 10 (d) is the waveform diagram of the 1000Hz to 500Hz frequency switching test; Figure 11 The waveforms for switching different modulation modes are shown in the test waveform diagrams for the three-level inverter PWM frequency dynamic adjustment method provided by this invention. Figure 11 (a) is the waveform of the modulation mode switching test from 0 to 1. Figure 11 (b) is the waveform of the modulation mode switching test from 1 to 0. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0029] This invention proposes a dynamic frequency adjustment method for a three-level inverter PWM, based on a distributed communication architecture, and mainly includes the following: 1. Distributed system architecture setup: Figure 1 The distributed control system architecture employed in this invention is demonstrated. The system comprises two physically separate processing units: a master controller and a slave controller, which are connected via a high-speed communication interface.

[0030] The main controller employs a digital signal processor (DSP) or a high-performance microprocessor (MCU) to execute the field-oriented control (FOC) algorithm, frequency switching decisions, communication delay prediction, and angle compensation calculations. The main controller is equipped with an analog-to-digital converter interface for acquiring motor current, voltage, and speed signals.

[0031] The controller, employing a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), is responsible for PWM waveform generation, sampling trigger pulse output, carrier count management, and modulation mode logic implementation. The controller connects to the power driver board via fiber optic cable or differential signal lines to control the switching of power devices.

[0032] The high-speed communication interface uses a 50Mbps fiber optic communication protocol, and the measured one-way transmission delay is [missing information]. Typical values ​​are 7~9 μs (0.000007s~0.000009s), and the bidirectional confirmation period does not exceed 20 μs (0.00002s).

[0033] Based on this architecture, the set of switchable PWM switching frequencies is defined as {125Hz, 250Hz, 500Hz, 1000Hz}, with corresponding sampling periods of {0.008s, 0.004s, 0.002s, 0.001s}. The three-level modulation modes are defined as Mode 0 (overlapping carrier, used for low modulation ratio conditions) and Mode 1 (layered carrier, used for high modulation ratio conditions). Figure 2 (a) shows the carrier comparison method for modulation mode 0, which uses a standard three-phase sinusoidal modulated wave to compare with an overlapping triangular carrier. Figure 2 (b) shows the carrier comparison method of modulation mode 1, which uses a standard three-phase sinusoidal modulated wave to compare with a stacked triangular carrier.

[0034] 2. Sampling period and frequency synchronization mechanism: Figure 3 This invention demonstrates the mapping relationship between PWM switching frequency and sampling period. It establishes a strict frequency-period correspondence table to ensure that the sampling period changes synchronously during frequency switching, maintaining whole-cycle sampling to avoid spectral leakage.

[0035] Sampling period calculation ,in The sampling period is expressed in seconds (s), and 1 represents the sampling time. This refers to the PWM switching frequency (in Hz, i.e., cycles / second). For a frequency of 125Hz, 0.008s; for a frequency of 1kHz, 0.001s.

[0036] After a frequency or modulation mode switching command is issued, the main controller synchronously updates the control equivalent delay compensation parameters in the control closed loop to compensate for the phase lag caused by frequency changes. The control equivalent delay compensation parameters are shown in the table below: Table 1 Switching Frequency and Equivalent Control Delay 125Hz 0.006s 250Hz 0.003s 500Hz 0.0015s 1000Hz 0.00075s

[0037] The calculation basis for the equivalent delay compensation amount dtc is as follows: This compensation amount is used to correct the phase lag introduced by the comparison between the average value sampling and the PWM carrier, ensuring the stability of the control loop. Synchronously switching the sampling period and delay compensation parameters avoids control loop oscillations caused by model mismatch.

[0038] 3. Handover timing determination based on carrier alignment: Figure 4 This invention demonstrates a switching timing determination mechanism based on communication delay prediction. It calculates the common point of carrier signals at different PWM frequencies and sets this point as the safe switching moment to ensure voltage vector continuity during switching and achieve zero current surge.

[0039] For any two switching frequencies and (set up The period of occurrence of its carrier common point is: , where gcd represents the greatest common divisor operation. For example, the common point period of 125Hz and 250Hz is 0.008s, and the common point period of 250Hz and 1000Hz is 0.004s.

[0040] Latest transmission time calculation ,in This is the time for the public point switching in this round. To reduce communication delay, the main controller monitors the relative position of the current moment and the next common point in real time. If the current moment... < If so, immediately send a switching command; if > If the slave station fails to receive and synchronize instructions, it will be forced to wait until the next public point.

[0041] 4. Control closed-loop disturbance suppression strategy: Figure 5 A block diagram illustrating the control closed-loop disturbance suppression strategy of the present invention is shown in the figure. and These are instantaneous sampled values ​​of three-phase current and three-phase voltage; The synchronization signal is emitted at the common point of different PWM frequency carrier signals (rising edge valid), realizing the synchronous switching of PWM switching frequency and sampling period.

[0042] Average and The average value is the average current and voltage corresponding to the current PWM frequency, with a sampling period of 0.001s to 0.008s. A moving average filtering method is used to reduce the impact of sampling noise. Lock is a latching signal used to latch the state of the system before switching, so as to avoid the influence of sampling switching after switching.

[0043] This is the magnetic field orientation angle compensation amount, used to compensate for the magnetic field orientation angle deviation caused by the switching of the sampling period.

[0044] dtc is the sampling equivalent delay compensation amount, which compensates for the control deviation caused by the average value sampling.

[0045] The angle output by the magnetic field orientation module; The observed values ​​are the dq-axis current components calculated using the Park transform. The given value is the dq-axis current component set by the system; The displayed value is the dq axis current component used for display; This strategy includes the following specific mechanisms: ① Precise Time Alignment: The synchronization signal ensures that the average current / voltage samples used by the field-oriented module are strictly aligned with the PWM update time before and after the switch. The completion time of the last set of average sampling before the switch and the start time of the first set of average sampling after the switch both coincide with the common point time, eliminating time misalignment of the sampling data.

[0046] ② Switching delay avoidance: Figure 6 The timing relationship of the system's blocking logic is illustrated. The system needs to avoid the interval affected by the sampling switch, and this time depends on the PWM switching frequency after the switch. The Lock signal is set during the switch and remains active for a certain duration after the switch. Normal vector control can only be resumed after the system stabilizes. Set to a complete sampling period after the switch, for example, the PWM frequency after the switch is 1kHz. =0.001s; the PWM frequency after switching is 125Hz. =0.008s.

[0047] ③ PI Regulator Lockout: During Lock=1, the motor field vector orientation module and the current loop PI regulator are locked out: the input signal of the PI regulator is forcibly switched to zero, and the output value remains in the state before the switch to prevent integral saturation or sudden changes. After the Lock signal becomes 0, the PI regulator resumes normal operation with the maintained output value as the initial value.

[0048] ④ One-time compensation mechanism for magnetic field orientation angle: Due to the magnetic field orientation angle It is obtained through continuous integration, based on the old sampling period before the switch. The average angle calculated after switching based on the new sampling period The average angle calculation has an inherent bias, which comes from the change in the sampling window length. It needs to be compensated numerically once at the moment of switching.

[0049] Angle compensation amount ,in Let dt be the motor angular velocity (rad / s) and dt be the equivalent time deviation. The compensation time dt for different PWM frequency switching processes is shown in the table below: Table 2 Frequency Switching and Compensation Time 125Hz->250Hz +0.002s 250Hz->125Hz -0.002s 250Hz->500Hz +0.001s 500Hz->250Hz -0.001s 500Hz->1kHz +0.0005s 1kHz->500Hz -0.0005s

[0050] Compensation amount The process is executed once at the moment of switching and superimposed on the current angle value. After the switch is complete, the system continues integration based on the new sampling period, without the need for subsequent continuous compensation.

[0051] 5. Modulation mode switching coordination: Figure 7 The constraints and timing control for modulation mode switching are illustrated. Modulation mode switching in a three-level inverter involves changes to the carrier comparison logic and must be executed in conjunction with frequency switching.

[0052] ① Carrier modulation constraints: Define the triangular carrier slope signal CB, where CB=1 during the rising phase and CB=0 during the falling phase.

[0053] To prevent multi-pulse phenomena during mode switching, the direction of PWM output level transitions is constrained: When CB=0, only the PWM output level is allowed to change from -1 to 0 or from 0 to 1; When CB=1, only the PWM output level is allowed to change from 0 to -1 or from 1 to 0. This constraint is implemented through combinational logic within the FPGA. During modulation mode switching, a timing misalignment update mechanism is set for the mode switching signal AF and the carrier slope signal CB. The AF signal is updated in the nth clock cycle, and the CB signal is updated in the (n+k)th clock cycle, where k is an integer from 2 to 10. This ensures that the update time of the CB signal lags behind that of the AF signal, avoiding voltage loss caused by synchronous updates. The frequency switching synchronization mechanism is reused during modulation mode switching, supporting simultaneous mode switching and carrier frequency switching. Level transitions that violate the rules are prohibited.

[0054] ② Timing misalignment control: Figure 8 (a) shows the timing of the problem: the mode switching signal AF and the carrier slope signal CB are updated synchronously, causing voltage loss at certain times (such as the inability of the 0 level to transition normally).

[0055] Appendix Figure 8(b) Demonstrates the timing misalignment control of the present invention: the program is designed to delay the CB signal by a preset clock period compared to the AF signal. Specifically, the AF signal is updated in the nth clock period, and the CB signal is updated in the n+2th clock period (delayed by 2 clock cycles, corresponding to a counting frequency of 50ns@40MHz).

[0056] The timing misalignment ensures that when AF changes first, CB remains in its original state, allowing the output level to change normally; subsequently, CB is updated to the new state, and the system resumes normal carrier comparison logic, thereby avoiding voltage loss and current surges.

[0057] ③ Mode switching coordination: When switching between three-level modulation modes (mode 0 / 1), the following mechanism for frequency switching is reused: Sampling period synchronous switching (mode switching may be accompanied by carrier frequency switching); Update the sampling equivalent delay compensation amount dtc; One-time compensation for magnetic field orientation angle; PI regulator blocking and Lock signal management; Mechanism reuse ensures that modulation mode switching does not cause additional system fluctuations. Timing misalignment control and mechanism reuse enable a smooth transition between mode 0 and mode 1, avoiding voltage loss.

[0058] 6. Distributed synchronous execution process: Based on the mechanisms and deployments described in 1-5 above, the distributed synchronous execution process of this invention is as follows: Step S1 Master station condition determination: The main controller monitors the motor operating status in real time and determines whether the frequency or mode switching conditions are met (such as load torque change, speed command change, efficiency optimization requirements).

[0059] In this embodiment, the main controller uses a TI TMS320F28346 single-core DSP with a clock frequency of 300MHz and a built-in floating-point unit. The slave controller uses a Xilinx Artix-7 FPGA (model XC7A35T) with a clock frequency of 100MHz. The high-speed communication interface uses 50Mbps fiber optic communication with a clock frequency of 50MHz and a 32-bit data frame format (8-bit command + 10*16-bit data + 32-bit CRC). The measured one-way transmission delay is... The two-way confirmation cycle is approximately 7~9μs, and approximately 15~20μs.

[0060] The power topology is a three-level inverter with a DC bus voltage of 2500V. The power devices are IGCT modules with a switching frequency range of 125Hz~1000Hz. The output is connected to a synchronous motor.

[0061] Step S2 Communication Delay Prediction: The main controller queries the current communication status and obtains the measured delay. Calculate the time of the next common point. and latest sending time , , The common point between 125Hz and 250Hz occurs at the 0.008s period point, which is each valley point of the 125Hz carrier, corresponding to the second valley point of the 250Hz carrier.

[0062] Step S3 Instruction Sending Decision: If the current time < Immediately assemble the switching command frame (containing the new frequency, new mode, and target common point number) and send it through the 50M communication interface; if Set a waiting flag, recalculate and send at the next common point period.

[0063] In this embodiment,

[0064] The master controller must issue a switching command before the time base count reaches 0.007991s to ensure that the slave station can synchronize at the common point of 0.008s.

[0065] Step S4: Slave Receive Confirmation: Receive the switching instruction frame from the controller, verify the CRC integrity, extract the target common point sequence number, load it into the carrier counter comparison register, and prepare to synchronously update the PWM parameters at the common point.

[0066] In this embodiment, the PWM switching frequency during operation is 125Hz. , The motor speed is 150 rpm (electric angle 62.8 rad / s). Switching condition determination: If the carrier ratio is maintained at no less than 12, the PWM switching frequency is switched to 250Hz. Main controller in The switching condition is met at 0.006s. Since 0.006s < 0.007991s, the data is sent immediately. After receiving the instruction from the controller and passing the verification, the target parameters are loaded into the register, and the system waits for synchronization to be triggered.

[0067] At the common point time t=0.008s: The slave PWM counter period register is updated from 160000 (125Hz, clock 40MHz) to 80000 (250Hz), and the sampling trigger period is changed synchronously.

[0068] Main site: Execution angle compensation:

[0069] Magnetic field orientation angle Instantaneous superposition of +3.6° compensation. Simultaneously, the Lock signal is set, the PI regulator input is forced to zero, and the output retains the instantaneous value before the switch.

[0070] Step S5 Synchronous execution switching: At the specified common point time, the slave station synchronously updates the PWM frequency, sampling period and modulation mode; the master station synchronously performs one-time angle compensation and PI blocking to achieve strict spatiotemporal alignment of master and slave station actions.

[0071] See Figures 9 to 11 By comparing the test waveforms of different frequency switching methods, different switching frequencies, and two modulation mode switching tests, it can be found that the carrier common point switching alignment mechanism completely eliminates the given voltage surge and current surge during the frequency / mode switching process, thus protecting the power devices.

[0072] Figure 9 (a) is a waveform diagram of frequency switching using conventional frequency regulation. Figure 9 (b) is a waveform diagram of frequency switching under the dynamic adjustment method of PWM frequency for three-level inverters provided by the present invention. Figure 10 The waveform diagrams are obtained from the switching test under the three-level inverter PWM frequency dynamic adjustment method provided by this invention, where: Figure 10 (a) is a waveform diagram of the 250Hz to 500Hz frequency switching test. Figure 10 (b) is the waveform diagram of the 500Hz to 250Hz frequency switching test. Figure 10 (c) is the waveform diagram of the 500Hz to 1000Hz frequency switching test. Figure 10 (d) is the waveform diagram of the 1000Hz to 500Hz frequency switching test.

[0073] Figure 11 (a) is a waveform diagram of the modulation mode switching test under the dynamic adjustment method of PWM frequency of the three-level inverter provided by the present invention, showing the modulation mode switching test waveform. Figure 11 (b) is the waveform of the modulation mode switching test from 1 to 0.

[0074] Taking a PWM switching frequency of 250Hz as an example, when the PWM switching frequency is 250Hz, the corresponding =0.004s, therefore the Lock signal is maintained for 0.004s, during which: The current loop PI output remains constant; The speed loop is operating normally and generating current input. The magnetic field orientation module continues calculations with the compensated angle.

[0075] At t=0.012s, the Lock signal is reset, and the PI regulator resumes normal operation with the value held 0.004s prior as its initial value. The system operates stably at 250Hz. While ensuring safety, the PI lock-up time and switching wait time are minimized. Under the tiered switching strategy, the switching time does not exceed 0.008s across the entire range of 125Hz-1000Hz, achieving a fast and smooth transition for online PWM frequency switching.

[0076] Step S6: Stable recovery and operation: After After the lockout period, the Lock signal resets, the PI regulator resumes normal operation, and the system operates stably at the new frequency and in the new mode. The process is similar to the above, but in the opposite direction. The angle compensation is -7.2°. =0.008s, ensuring full stability.

[0077] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for dynamic adjustment of PWM frequency in a three-level inverter, based on a distributed communication architecture, wherein the distributed communication architecture includes a master controller and multiple slave controllers, forming two physically separated processing units, master and slave, characterized in that: The execution steps are as follows: S1, Master station condition determination: The main controller monitors the motor's operating status in real time and determines whether the frequency or mode switching conditions are met. S2, Communication Delay Prediction: The main controller queries the current communication status and obtains the measured delay, i.e. Calculate the next common point time and the latest transmission time, i.e. ; S3, Instruction Sending Decision: If at the current moment, i.e. < Immediately assemble the switching instruction frame, which includes the new frequency, new mode, and target common point information; if Set a waiting flag, recalculate and send at the next common point period; S4, Slave station receives confirmation: The slave controller receives the switching instruction frame, verifies it, extracts the target common point information, loads it into the carrier counter and comparison register of the slave controller, and prepares to synchronously update the PWM parameters at the common point. S5, Synchronous Switching: At the specified common point, the slave station synchronously updates the PWM frequency, sampling period, and modulation mode; The master station synchronously performs one-time angle compensation and current loop PI regulator blocking to achieve strict spatiotemporal alignment of master and slave station actions. The state before system switching is stored in the latched signal in the interval that avoids the impact of sampling switching after switching. The latched signal is set during switching and the blocking time is maintained after switching. S6, Stable recovery of operation: After the blocking time ends, the latch signal is reset, the current loop PI regulator resumes normal operation, and the system operates stably with a new frequency and a new mode.

2. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 1, characterized in that: The main controller is responsible for executing the field orientation control algorithm, frequency switching decision, communication delay prediction, and angle compensation calculation; the slave controller is responsible for PWM waveform generation, sampling trigger pulse output, carrier counting management, and modulation mode logic implementation. The slave controller is connected to the power drive board through optical fiber or differential signal line to realize the switching control of power devices. The high-speed communication interface between the main controller and the slave controller adopts the 50Mbps optical fiber communication protocol.

3. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 2, characterized in that: In S1, the main controller sets up a sampling period and frequency synchronization mechanism, and the sampling period is calculated. ,in The sampling period is For the PWM switching frequency, after the frequency or modulation mode switching command is issued, the main controller synchronously updates the control equivalent delay compensation parameters in the control closed loop. The calculation basis for the control equivalent delay compensation amount dtc is as follows: It is used to correct the phase lag introduced by the comparison between the average value sampling and the PWM carrier.

4. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 3, characterized in that: In S2, a switching time determination mechanism based on communication delay prediction is set up. The common point of carrier signals at different PWM frequencies is calculated and set as the safe switching time. For any two switching frequencies... and ,set up Calculate its greatest common divisor gcd ( , The period of occurrence of its carrier common point is: Calculation of the latest sending time The main controller monitors the relative position of the current moment and the next common point in real time. If the current moment... < If so, immediately send a switching command; if > If so, you will be forced to wait until the next public point.

5. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 4, characterized in that: In S5, during the process of synchronously updating the PWM frequency, sampling period, and modulation mode by the slave station, carrier modulation constraints are set: Define a triangular carrier slope signal CB, where CB=1 during the carrier rise phase and CB=0 during the carrier fall phase, to constrain the direction of the PWM output level transition: When CB=0, only the PWM output level is allowed to change from -1 to 0 or from 0 to 1; When CB=1, only the PWM output level is allowed to change from 0 to -1 or from 1 to 0. The carrier modulation constraint is implemented through combinational logic inside the controller. When the modulation mode is switched, a timing misalignment update mechanism is set between the mode switching signal AF and the carrier slope signal CB. The AF signal is updated in the nth clock cycle and the CB signal is updated in the n+kth clock cycle, where k is an integer from 2 to 10. This makes the update time of the CB signal lag behind that of the AF signal, thus avoiding voltage loss caused by synchronous updates. The synchronization mechanism of frequency switching is reused when the modulation mode is switched, so that the mode switching is accompanied by carrier frequency switching.

6. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 4, characterized in that: In S5, the master station synchronously performs one-time angle compensation and PI blocking to achieve spatiotemporal alignment of the actions of the master and slave stations. The spatiotemporal alignment is ensured by the synchronization signal to ensure that the average current / voltage sampling value used by the magnetic field orientation module is strictly aligned with the PWM update time before and after the switch. The completion time of the last set of average value sampling before the switch and the start time of the first set of average value sampling after the switch both coincide with the common point time, eliminating the time misalignment of the sampling data.

7. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 6, characterized in that: The compensation mechanism for the one-time compensation of the synchronous execution angle is as follows: Based on the old sampling period before switching The average angle calculated after switching based on the new sampling period The average calculated angle has an inherent bias, which originates from the variation in the sampling window length. This bias requires a one-time numerical compensation at the moment of switching. Angle one-time compensation amount ,in This is the magnetic field orientation angle compensation amount, used to compensate for the magnetic field orientation angle deviation caused by sampling period switching. The angle output by the magnetic field orientation module. dt is the angular velocity of the motor (rad / s) and dt is the equivalent time deviation.

8. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 6, characterized in that: The blocking mechanism of the PI block is as follows: The system needs to avoid the period affected by the sampling switch. This time depends on the PWM switching frequency after the switch. A latch signal, i.e., a Lock signal, is used to latch the system's state before the switch, thus ensuring that the system avoids the period affected by the sampling switch after the switch. The Lock signal is set at the time of the switch and remains active for a certain duration after the switch. Once the system stabilizes, normal vector control can be resumed. Set to a complete sampling cycle after the switch, before the Lock signal is switched, the motor field vector orientation module and the current loop PI regulator are blocked: the input signal of the PI regulator is forced to switch to zero, and the output value remains in the state before the switch. After the Lock signal is switched, the PI regulator resumes normal operation with the maintained output value as the initial value.

9. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 2, characterized in that: The main controller uses a high-performance microprocessor or digital signal processor.

10. The method for dynamic adjustment of PWM frequency in a three-level inverter according to claim 2, characterized in that: The controller is equipped with a dedicated integrated circuit or a field-programmable gate array.

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