A multi-rate distributed control system for a three-level inverter

Abstract

This invention discloses a multi-rate distributed control system for three-level inverters, belonging to the field of power electronic converter technology. It includes a master station, slave stations, a 50M fiber optic communication link, and three-level inverters. The master station communicates with multiple slave stations via the 50M fiber optic communication link, and each slave station communicates with one three-level inverter. Multiple three-level inverters are connected in parallel to drive a motor. The master station is responsible for calculating the average current value over the entire cycle. The slave stations are responsible for short-cycle current sampling and average value calculation, current loop PI regulation, PWM generation and driving. The master station and slave stations are clock-synchronized to achieve periodic communication. The overall technical solution of this system relies on algorithm optimization and hardware-software co-design to improve performance without adding expensive hardware equipment. It has low engineering implementation costs, is easy to promote, and achieves a unified dynamic fast response from slave stations and steady-state precise control from the master station.

Description

Technical Field

[0001] This invention belongs to the fields of power electronic converter technology and high-power motor drive technology, specifically relating to a three-level inverter multi-rate distributed control system. Background Technology

[0002] Medium- and high-voltage high-power three-level inverters are core drive components for heavy industrial equipment such as metallurgical rolling mills, mine hoists, and ship propulsion. With the continuous increase in power levels and the diversification of switching frequency requirements (pulse width modulation (PWM) frequency range of 125Hz to 1000Hz), traditional centralized control architectures, due to limited I / O resources and excessive algorithm computational load, struggle to meet the demands of fast-cycle, high-performance control. Therefore, distributed control systems with a master-slave architecture have become the mainstream trend in the industry. However, a natural contradiction exists between the low bandwidth requirements of the complex algorithms in the master control unit and the high dynamic response requirements of the slave power units in a distributed architecture, making multi-rate collaborative control a critical technical challenge that urgently needs to be addressed.

[0003] Regarding current control and sampling consistency, while existing technologies have attempted to optimize the response speed of a single controller, they struggle to address the multi-rate coupling problem in distributed systems. For example, CN 115395842 A proposes a method for extending the current loop bandwidth. This method achieves multiple PWM duty cycle updates within a single carrier cycle through "single sampling, multiple reconstruction," effectively reducing the digital delay within a single controller. However, traditional instantaneous value sampling suffers from poor anti-interference capabilities and is susceptible to switching spikes. Furthermore, this method primarily optimizes delays within a single machine and does not consider the difference in sampling periods between the master and slave stations in a distributed system. The master station directly uses the instantaneous sampled values ​​uploaded by the slave station without compensating for amplitude attenuation and phase lag between the integer cycle average and the short cycle average, leading to steady-state current ripple and decreased accuracy. Moreover, when the current loop period is inconsistent with the carrier period, the traditional single-rate PI parameter tuning method fails, lacking a quantitative design basis for multi-rate coupling effects, resulting in slow system dynamic response or deteriorated stability.

[0004] Regarding carrier synchronization, existing solutions largely rely on grid voltage feedback or dedicated hardware communication, which struggles to meet the high dynamic and flexible requirements of distributed internal control. For example, patent application CN 118100295 A discloses a carrier synchronization method for multiple inverters, which modulates the frequency and phase of a triangular carrier by sampling the grid voltage frequency and zero-crossing point. However, this method relies on the grid voltage zero-crossing point (50Hz power frequency) for phase adjustment, resulting in a synchronization period of 10ms to 20ms. For the distributed control system within a three-level inverter, this method cannot achieve instantaneous switching of the switching frequency and cannot correct phase drift within each control cycle. On the other hand, patent application CN 118826526 A proposes a PWM carrier synchronization method based on fiber optic communication. While this achieves multi-machine synchronization, it requires equal length fiber optic communication lines between the master controller and the power module controller, imposing strict hardware wiring constraints and high implementation costs. Furthermore, this method relies on a fixed communication frame structure to send synchronization and PWM signals, failing to address the multi-rate matching problem when the master station control cycle and the slave station carrier cycle are inconsistent, making it difficult to adapt to scenarios with dynamically changing switching frequencies.

[0005] In summary, existing technologies lack a control system capable of simultaneously compensating for multi-rate sampling differences, achieving high-precision and fast carrier synchronization, and adapting to distributed architectures. There is an urgent need to develop a novel multi-rate distributed control system for three-level inverters to address the accuracy loss caused by master-slave sampling period mismatch, as well as the problems of slow dynamic response, strong hardware dependence, and inability to support instantaneous frequency switching in existing synchronization methods. This would improve the steady-state accuracy and dynamic performance of high-power drive systems. Summary of the Invention

[0006] This invention aims to address the technical pain points in existing three-level inverter current loop control, such as the trade-off between speed and accuracy, master-slave timing phase mismatch, limited modulation method adaptability, and lack of targeted PI parameter tuning, and provides a multi-rate distributed control system for three-level inverters.

[0007] This technical solution is implemented in the following way: A three-level inverter multi-rate distributed control system includes a master station, slave stations, a 50M fiber optic communication link, and three-level inverters. The master station is connected to multiple slave stations via the 50M fiber optic communication link, and each slave station is connected to a three-level inverter. The multiple three-level inverters are connected in parallel to drive a motor. The master station and slave station use different sampling periods. The master station performs motor vector control and generates control commands based on whole-cycle sampling. The master station uses a DSP processor to calculate the average current value of the whole cycle, perform motor vector control, and issue commands. The slave station performs closed-loop control of the current loop based on short-cycle sampling and generates PWM drive signals; the slave station uses an FPGA processor, which is responsible for short-cycle current sampling and average value calculation, current loop PI regulation, PWM generation and driving; The master station and the slave station achieve multi-rate coordinated control through phase time difference compensation and amplitude deviation compensation. The master station and the slave station are clock synchronized to achieve periodic communication.

[0008] Furthermore, the algorithm execution steps of the system are as follows: Step 1: Sampling and Calculation of Average Current from Substation; Sampling is initiated at the substation, and multiple short-cycle instantaneous values ​​of the A, B, and C phase currents of the motor are sampled. The arithmetic mean of the multiple sampled values ​​for each phase is calculated to obtain the average short-cycle current. After sampling is completed, the sampling channel is closed. Step 2: Master-slave fiber optic communication interaction; the master station sends primary motor vector control parameters to the slave station via fiber optic cable, including the feedforward voltage. The slave station transmits the average short-cycle current to the master station via optical fiber. Step 3: Master station full-cycle sampling processing and vector control; The master station receives the short-cycle current average value, calculates the whole-cycle current average value, and calculates the motor vector control parameters, which are then sent to the slave station in the next communication interaction. Step 4: The slave station receives the average current value of the entire cycle from the master station, performs phase time difference compensation and amplitude deviation compensation, and obtains the compensated average current value of the entire cycle. Step 5: Slave-station multi-rate PI regulation; Based on the compensated average current over the entire cycle, calculate the intermediate value of the voltage setpoint after PI regulation. Combined with the feedforward voltage issued by the main station The final voltage setting is obtained. ; Step 6: Segmented PWM carrier generation at the slave station. The slave station performs carrier stacking calculation to generate a voltage triangular carrier corresponding to the entire cycle. Step 7: Slave PWM generation and voltage update, setting the final voltage to U ref The signal is compared with the voltage triangular carrier wave of the corresponding full cycle to generate the PWM drive signal of the three-level inverter, which is then sent to the power component for driving. Step 8: Repeat steps 1 to 7 to achieve accurate generation of PWM pulses.

[0009] Furthermore, in step 1, the A, B, and C phase currents of the motor are sampled at a short period of 0.5ms from the slave station, and the average of 500 1μs instantaneous values ​​is obtained to get the 0.5ms short-cycle current average value.

[0010] Furthermore, the master station's full-cycle sampling processing and vector control in step 3 include: The master station receives the 0.5ms short-cycle current average value uploaded by the slave station, stores it in the current average value storage array, and calculates the whole-cycle current average value with periods of 1ms, 2ms, 4ms and 8ms for magnetic field orientation calculation. The master station executes a field-oriented algorithm based on the average current over the entire cycle to calculate the motor vector control parameters, including the field-oriented angle. dq axis current given .

[0011] Furthermore, the phase time difference compensation in step 4 specifically involves the following steps: Because there is a time offset between the midpoint of the master station's whole-cycle sampling and the midpoint of the slave station's short-cycle sampling, a phase time difference is generated. The calculation formula is: Δt = 0.5Ts - 0.5Tc, where, It is the total sampling duration of the main station throughout the entire cycle. The short-cycle sampling time Δt is measured in milliseconds (ms) and changes automatically with the PWM switching frequency. After calculating the phase time difference, the compensation angle is obtained by combining it with the motor's electrical angular velocity ω. The phase compensation angle Δθ = ω × Δt is then calculated and superimposed on the original magnetic field orientation angle. The angle after compensation = + Δθ, corrects the vector rotation angle.

[0012] Furthermore, the amplitude deviation compensation adopts feedback compensation, and the specific steps are as follows: The system obtains two types of average current values ​​in real time: one is the short-cycle average current value calculated by the system itself (0.5ms). Second, the average current value of the entire cycle issued by the main station. Calculate the difference between the average values ​​of the two types of currents. The calculation formula is:

[0013] For the difference Low-pass filtering is performed to remove high-frequency interference, resulting in the filtered differential current. To avoid high-frequency interference affecting the compensation effect; Operating condition assessment and compensation execution: The slave station will and Add them together to obtain the compensated feedback current. The calculation formula is:

[0014] by The current loop feedback signal is used for closed-loop control to ensure the average current value over the entire cycle in steady state. When the current is equal to the given value, and the load changes abruptly, It plays a key role in ensuring dynamic response speed.

[0015] Furthermore, the amplitude deviation compensation employs a given outer loop correction, and the specific steps are as follows: The average short-cycle current of the slave station calculated by itself over 0.5ms. As the basic feedback signal, conventional current loop closed-loop control is performed to ensure the system's dynamic response speed; The slave station obtains the raw current command issued by the master station in real time. Compared with the average current of the whole cycle Calculate the difference between the two. The calculation formula is:

[0016] For the difference Perform low-pass filtering to obtain the filtered difference. Multiply it by the preset scaling factor To obtain the current given compensation amount The calculation formula is:

[0017] Working condition adaptation and compensation execution: Under dynamic working conditions, It changes in real time with sudden changes in load and current. Attach in real time The final current setting on the FPGA side is obtained from the above. The calculation formula is:

[0018] From the station Given, combined Implement closed-loop control for rapid response to changes in operating conditions; under steady-state conditions... Approaching zero, the magnitude of the value is related to the coefficient. Inversely proportional, Approaching a constant value, making and The difference narrows; under dynamic operating conditions, the slave station still... Based on feedback.

[0019] Furthermore, in step 5, the current loop PI regulation adopts a multi-rate PI parameter tuning method, the specific steps of which are: Establish an equivalent delay model: =0.5 +0.25 ,in, It is the equivalent delay time; The short-cycle sampling duration from the slave station is fixed at 0.5ms; This refers to the total sampling duration of the main station throughout the entire cycle; based on the equivalent delay model, the proportional coefficient of the PI controller is selected. With integration time When the PWM switching frequency changes, the master station updates the equivalent delay time. Re-adjust the proportional coefficient The data is then sent to the slave stations, enabling the system to adapt to different switching frequencies.

[0020] Furthermore, in step 6, the slave station performs carrier splicing calculation. Specifically, based on a short-cycle clock synchronized with the communication cycle, the long-cycle triangular carrier is decomposed into multiple short-cycle segments for segmented splicing calculation using a preset carrier base offset array to generate a triangular carrier corresponding to the whole cycle sampling duration, supporting smooth online switching of the switching frequency.

[0021] Furthermore, the specific steps for generating the slave station segmented PWM carrier in step 6 are as follows: Define the number of fundamental clocks N contained within a carrier period = / ,in The PWM switching frequency period, The short-cycle sampling duration is denoted as carrier(k), which is the carrier output value in the k-th base clock cycle. cnt is the base clock count value, ranging from 0 to Tc. base[k] is the carrier base offset corresponding to the k-th base clock cycle, which is pre-calculated and stored in the slave station. During the carrier rise phase, as the base clock counter k increments from 0 to (N / 2-1), the carrier value linearly rises from 0 to the peak value. The calculation formula is: carrier(k) = cnt + base[k]; During the carrier descent phase, when the base clock counter k reaches N / 2, the carrier value linearly decreases from the peak value to 0. The calculation formula is: carrier(k) = N×Tc - cnt - base[k].

[0022] Furthermore, in step 7, the system is compatible with the synchronous symmetrical lookup table PWM method. The virtual carrier period is set to be aligned with the 0.5ms short-cycle control period. The voltage setpoint is updated synchronously every 0.5ms short cycle. Specifically, the voltage setpoint is updated at the peak and valley points of the virtual carrier. The voltage setpoint is not updated at non-peak and valley points. However, the errors of multiple 0.5ms short-cycle sampling points within one carrier period are all integrated to achieve an equivalent oversampling smoothing effect.

[0023] Furthermore, step 8 specifically involves the slave station clearing the sampling register and the master station updating the cumulative count after completing a single 0.5ms control cycle, before entering the next 0.5ms control cycle.

[0024] This system is suitable for scenarios with high requirements for dynamic response speed, steady-state control accuracy, and anti-interference capability of motor control, such as medium-voltage frequency conversion, industrial servo drive, rail transit, and precision machine tool transmission. It is compatible with carrier comparison PWM method and synchronous symmetrical lookup table PWM method, and supports online switching of multiple switching frequencies.

[0025] Compared with the prior art, the present invention has the following beneficial effects: 1. This system employs a short-cycle multi-point average sampling combined with a dual-bias compensation strategy for amplitude and phase. This effectively suppresses sampling interference caused by switching spikes and dead-zone effects, eliminates amplitude attenuation and phase lag issues in multi-rate sampling between master and slave stations, and significantly improves the system's steady-state control accuracy and the precision of motor field orientation. (See appendix) Figure 11 The amplitude attenuation and compensation effects shown indicate that, compared with the uncompensated amplitude attenuation, the amplitude after compensation using this system shows no significant attenuation.

[0026] 2. This system utilizes the integral accumulation effect of the current loop to achieve the superposition effect of multiple oversampling and integral smoothing filtering, reducing the harmonic content of the system output voltage, improving the smoothness of the output voltage, and enhancing the stability of motor operation. (See attached document) Figure 12 As shown in the comparison of current fluctuations between the proposed solution and the conventional solution, the current fluctuations are significantly stabilized after adopting this system.

[0027] 3. This system enables short-cycle current loop closed-loop control at the slave station, significantly improving the system's dynamic response speed to load and current change. It supports seamless online switching of multiple PWM switching frequencies, with no phase jump or voltage surge during the switching process, and can quickly adapt to the dynamic requirements of different operating conditions. Figure 13 In a comparison of torque current response time, the response time using this system was improved from 5.5ms to 3ms using the conventional method, resulting in a significantly faster response speed.

[0028] 4. This system achieves periodic communication between master and slave stations through a clock synchronization protocol. The communication period is strictly aligned with the short-period sampling period to ensure timing consistency. It does not rely on mains voltage or equal-length fiber optic cabling, reducing hardware constraints while improving carrier synchronization. Combined with a multi-rate PI parameter tuning method, it ensures that the system has good stability across the entire switching frequency range with no steady-state error. Figure 14 The improved clock synchronization effect has increased the clock synchronization accuracy from 150ns to 44ns, resulting in a significant improvement in synchronization accuracy.

[0029] 5. This system, through a virtual carrier mechanism, can be compatible with both carrier comparison PWM method and synchronous symmetric lookup table PWM method without adding new hardware or modifying the underlying algorithm, enabling flexible switching between the two modulation methods and effectively broadening the system's application scenarios.

[0030] 6. The overall technical solution of this system relies on algorithm optimization and hardware-software co-design to improve performance without the need for additional expensive hardware equipment. It has low engineering implementation costs and is easy to promote. It achieves the unity of dynamic and rapid response of slave stations and steady-state and precise control of master stations, and takes into account the multiple performance requirements of high-power motor drive systems, thus having significant industrial application value. Attached Figure Description

[0031] Figure 1 Technical architecture logic diagram; Figure 2 System overall hardware architecture diagram; Figure 3 Schematic diagram of dual-timescale sampling timing; Figure 4 Schematic diagram of phase compensation principle; Figure 5 Inner loop feedback amplitude compensation scheme; Figure 6 Outer ring correction amplitude compensation scheme; Figure 7 Transmission line delay measurement methods; Figure 8 Schematic diagram of high-precision clock closed-loop control; Figure 9 Synchronous PWM virtual carrier and voltage update timing diagram; Figure 10 Integral effect and voltage update strategy; Figure 11 Amplitude attenuation and compensation effect; Figure 12 Comparison of current fluctuations between this solution and conventional solutions Figure 13 Torque-current response time comparison; (a) Control effect of conventional method at 500Hz; (b) Control effect of this embodiment at 500Hz; Figure 14 Improved clock synchronization effect; (a) Clock synchronization accuracy before improvement: 150ns; (b) Clock synchronization accuracy in this embodiment: 44ns. Detailed Implementation

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0033] The technical solution of this invention includes a system overall architecture, a dual time-scale sampling and compensation strategy, a multi-rate PI parameter tuning method, a segmented stacked PWM carrier generation method, a timing control and voltage update strategy, and each module is logically progressive and works in coordination.

[0034] See appendix Figure 1 As shown, the technical architecture of this application embodiment includes a hardware layer, a sampling layer, an algorithm layer, and an execution layer. At the hardware layer, the system adopts a master-slave distributed hardware architecture, including a master controller and multiple slave controllers. The master controller and slave controllers communicate with each other via a 50M fiber optic communication link with a period of 0.5ms to issue control commands and exchange sampled data. At the sampling layer, the master controller executes motor-level slow control algorithms such as vector control, model prediction, and field orientation calculation based on the full-cycle sampling data of 1~8ms. The slave controller, on the other hand, implements current loop closed-loop control and PWM signal generation based on the short-cycle sampling data of 0.5ms. This forms a dual-time-scale sampling and control mechanism between the master and slave stations. Under this mechanism, there is an inherent problem of difference between the two time scales: amplitude attenuation and phase lag.

[0035] At the algorithm layer, the system sets up a sampling difference compensation module and a multi-rate PI tuning module. Through collaborative design, the two modules compensate for the phase time difference and amplitude deviation of the master and slave sampling data, respectively, and complete the multi-rate PI parameter tuning based on the equivalent delay model and the second-order system optimal design method to eliminate the impact of multi-rate coupling on control performance. At the execution layer, the system uses a segmented carrier stacking module, employing short-cycle clock stacking, compatible synchronous lookup table PWM, and virtual carrier frequency technology to achieve precise reconstruction of the full-cycle long carrier. It works in conjunction with the timing control and voltage update modules through a synchronization mechanism. By strictly aligning the timing, continuously accumulating integrals, and using equivalent oversampling smoothing methods, the system ensures the synchronization of multi-unit drive and the continuity of voltage updates. Ultimately, this resolves the contradiction between control accuracy and dynamic response under multi-rate coupling, achieving efficient, high-precision, and stable operation of the medium- and high-voltage high-power three-level inverter.

[0036] See appendix Figure 2As shown, the hardware architecture of this system adopts a distributed hardware board architecture. The core consists of four parts: master station, slave station, communication link, and power stage. Each part has a clear division of labor and works in concert. The specific structure is as follows: (1) Main station: The DSP processor is used as the core control unit. It is mainly responsible for the execution of the motor vector control algorithm, including magnetic field orientation angle calculation, dq axis current calculation, speed loop control, feedforward voltage generation, and receiving and processing the average current value of the whole cycle. Based on the whole cycle sampling data, it realizes the precise control of the motor magnetic field orientation and ensures the steady-state performance of the system.

[0037] (2) Slave station: The FPGA processor is used as the core control unit. It is mainly responsible for high-speed current sampling, 0.5ms current average value calculation, current loop PI regulation, PWM pulse generation, and drive signal output. At the same time, it performs logic such as phase compensation, amplitude compensation, and segmented splicing carrier generation to quickly respond to the master station's instructions and ensure the dynamic performance of the system.

[0038] (3) Communication link: The master station and the slave station communicate point-to-point through a 50M optical fiber. The communication mode is periodic communication of 0.5ms. The communication delay is controlled at 6~9μs. It has the advantages of strong anti-interference ability, low transmission delay and stable data transmission, and realizes real-time interaction of information such as current setting, magnetic field orientation angle, feedforward voltage and sampling data between the master and slave stations.

[0039] (4) Power stage: It adopts a three-level inverter topology and supports online switching of four PWM switching frequencies of 125Hz, 250Hz, 500Hz and 1000Hz. The output terminal is connected to the motor and converts the PWM drive signal generated by the FPGA into a stable three-phase voltage to drive the motor to run normally.

[0040] Software architecture module The software architecture of this system is based on a layered hardware architecture design, consisting of a master station software module and a slave station software module. Each module is functionally independent yet works in synergy, as detailed below: (1) Main site software module: Integer sampling processing module: Receives the 0.5ms current average value uploaded by the slave station, calculates the current average value for the whole cycle (1ms / 2ms / 4ms / 8ms), and uses it for magnetic field orientation calculation.

[0041] PI parameter tuning module: Based on the equivalent delay model, it calculates and distributes PI parameters adapted to different switching frequencies.

[0042] Motor vector control module: Based on whole-cycle sampling data, it executes the field orientation algorithm, dq-axis current calculation, and speed loop adjustment to generate the field orientation angle, dq-axis current setpoint, and feedforward voltage.

[0043] Communication transmission module: According to the preset timing sequence, the magnetic field orientation angle, current setting, and feedforward voltage are sent to the slave station, and the sampling data uploaded by the slave station is received at the same time.

[0044] (2) Slave software module: Communication receiving module: Receives instructions and data from the master station and uploads sampled data and control status from the slave station.

[0045] Dual time-scale sampling module: performs 0.5ms short-cycle sampling, calculates the average value of 500 1μs instantaneous sampling points, and simultaneously receives the average value of the whole cycle current sent by the master station.

[0046] Deviation Compensation Module: Includes a phase compensation submodule and an amplitude compensation submodule, which perform phase angle correction and current amplitude deviation compensation.

[0047] Multi-rate PI regulation module: Based on the PI parameters issued by the master station, it performs current loop PI regulation and outputs a voltage command signal.

[0048] Segmented and stacked carrier generation module: Based on a synchronous clock, it generates triangular carriers of different periods, supports online switching of switching frequencies, and is compatible with two PWM modulation methods.

[0049] PWM Generation and Driving Module: Based on the carrier wave and voltage input, it generates a PWM driving signal to drive the three-level inverter and simultaneously executes the voltage input update logic.

[0050] See appendix Figure 3 The diagram shows a dual-time-scale sampling timing sequence. This system employs a dual-time-scale sampling mechanism, which is implemented as follows: (1) Master station sampling mechanism: The master station sampling period strictly corresponds to the PWM switching frequency period, that is, the switching frequency and the whole cycle sampling duration are exactly the same. The correspondence is as follows: 1000Hz corresponds to =1ms, 500Hz corresponds to =2ms, 250Hz corresponds to =4ms, 125Hz corresponds to =8ms. The master station does not directly sample the current, but instead receives the average current value uploaded by the slave station at 0.5ms. The average current value for the whole cycle is obtained through cumulative calculation. This average value is used for motor field orientation calculation, which can effectively eliminate current ripple interference, ensure the stable and ripple-free characteristics of field orientation, and improve the steady-state control accuracy of the system.

[0051] (2) Slave sampling mechanism: The slave station adopts short-cycle sampling, and the sampling duration is =0.5ms. Within each sampling period, 500 instantaneous values ​​of 1μs are sampled for the motor phase current. Then, the arithmetic mean of the 500 instantaneous values ​​is calculated to obtain the 0.5ms average current value. Compared with traditional single-point instantaneous value sampling, this sampling method can effectively suppress the interference caused by switching spikes and dead-time effects of power devices, and improve sampling accuracy. At the same time, the 0.5ms short-cycle sampling can quickly capture current changes, providing a basis for fast closed-loop control of the current loop and ensuring the dynamic response speed of the system.

[0052] (3) Sampling data interaction: After each 0.5ms sampling and average value calculation, the slave station uploads the 0.5ms current average value to the master station via fiber optic communication. After receiving the data, the master station accumulates multiple 0.5ms average values ​​(the number of accumulated values ​​corresponds to the whole cycle duration, such as 8 0.5ms average values ​​accumulated in a 4ms whole cycle), calculates the whole cycle current average value, and uses it for magnetic field orientation calculation. At the same time, the whole cycle current average value is sent down to the slave station for amplitude deviation compensation.

[0053] See Figure 4 As shown, phase compensation: Because the sampling periods of the master station's full-cycle sampling and the slave station's 0.5ms short-cycle sampling are different, there is an amplitude deviation in the average current value between the two. Simultaneously, the time difference at the sampling midpoint causes a phase deviation in the magnetic field orientation angle. Without compensation, this will affect the accuracy of the current loop control and the stability of motor operation. This system proposes a systematic dual-deviation compensation scheme, as follows: (1) Phase time difference compensation Phase time difference calculation: Define the total sampling duration of the master station as... The short-cycle sampling time from the station is (0.5ms) Due to the time shift between the midpoint of the master station's full-cycle sampling and the midpoint of the slave station's short-cycle sampling, a phase time difference is generated. The calculation formula is:

[0054] The unit of Δt is ms, and it changes automatically with the switching frequency of the PWM.

[0055] For example, when =4ms, = 0.5 × (4 - 0.5) = 1.75ms; when =2ms, = 0.5 × (2 - 0.5) = 0.75ms.

[0056] Phase compensation angle calculation: phase time difference This will cause a deviation in the rotation angle of the slave current loop vector, which needs to be eliminated through angle compensation. Phase compensation angle. Due to phase time difference With the electric angular velocity of the motor (Calculated by real-time data from the master station or based on motor speed from the slave station) The calculation formula is as follows:

[0057] in, The unit is rad. The unit is rad / s.

[0058] Compensation Implementation: Different pre-stored data in the slave FPGA corresponding Parameters are automatically matched when the PWM switching frequency is switched online. Simultaneously, the slave station receives the motor's electrical angular velocity from the master station in real time. Real-time calculation And superimpose it onto the original magnetic field orientation angle issued by the main station. The compensated vector rotation angle is obtained. The calculation formula is:

[0059] The slave station adopts Perform dq-axis vector rotation (coordinate transformation) of the current loop to completely eliminate control errors caused by phase deviation and ensure the accuracy of coordinate transformation.

[0060] Amplitude deviation compensation (two switchable schemes) This system provides two amplitude deviation compensation schemes, which can be flexibly switched according to the actual application scenario (such as selecting inner loop feedback compensation if steady-state accuracy requirements are prioritized, and selecting outer loop correction compensation if dynamic response requirements are prioritized). Neither scheme requires additional hardware; it is implemented solely through algorithm optimization, as detailed below: Option 1: Inner loop feedback compensation scheme (recommended, implemented internally by the FPGA), see Figure 5 Inner loop feedback amplitude compensation scheme. This scheme achieves consistency of the average current values ​​between the master and slave stations by compensating for the current loop feedback signal. It is suitable for scenarios with high steady-state accuracy requirements. Specific steps: The system obtains two types of average current values ​​in real time: one is the short-cycle average current value calculated by the system itself (0.5ms). (For dynamic closed-loop control); secondly, the average current value of the entire cycle issued by the master station. (Used for steady-state amplitude compensation).

[0061] Calculate the difference between the average values ​​of the two types of currents. The calculation formula is:

[0062] For the difference Low-pass filtering (using a first-order low-pass filtering algorithm) is performed to remove high-frequency interference, resulting in the filtered differential current. To avoid high-frequency interference affecting the compensation effect.

[0063] Operating condition assessment and compensation execution: The slave station will and Add them together to obtain the compensated feedback current. The calculation formula is:

[0064] by The current loop feedback signal is used for closed-loop control to ensure the average current value over the entire cycle in steady state. When the current is equal to the given value, and the load changes abruptly, It plays a key role in ensuring dynamic response speed.

[0065] Option 2: Given an outer loop correction scheme (which can be implemented by either the master station or the slave station), see [link / reference]. Figure 6 Outer loop correction amplitude compensation scheme. This scheme achieves a balance between dynamic response and steady-state accuracy by compensating for the current setpoint, making it suitable for scenarios with high requirements for both dynamic response and steady-state accuracy. Specific steps: The average short-cycle current of the slave station calculated by itself over 0.5ms. As the basic feedback signal, conventional current loop closed-loop control is performed to ensure the system's dynamic response speed.

[0066] The slave station obtains the raw current command issued by the master station in real time. Compared with the average current of the whole cycle Calculate the difference between the two. The calculation formula is:

[0067] For the difference Perform low-pass filtering to obtain the filtered difference. Multiply it by the preset scaling factor (Adaptively tuned according to motor parameters and control accuracy requirements) to obtain the current setpoint compensation amount. The calculation formula is:

[0068] Working condition adaptation and compensation execution: Under dynamic working conditions, It changes in real time with sudden changes in load and current. Attach in real time The final current setting on the FPGA side is obtained from the above. The calculation formula is:

[0069] From the station Given, combined Implement closed-loop control for rapid response to changes in operating conditions; under steady-state conditions... Approaching zero (numerical magnitude and coefficient) (inversely proportional) Approaching a constant value, making and The difference narrows. Under dynamic operating conditions, the slave station still... Based on feedback, ensure dynamic response speed.

[0070] Multi-rate PI parameter tuning method For the multi-rate characteristics of this system, where the master station samples with an integer cycle and the slave station samples with a short cycle of 0.5ms, existing PI parameter tuning methods are not suitable, leading to instability and poor control performance at different switching frequencies. This paper establishes an equivalent delay model specifically for multi-rate systems and proposes a PI parameter tuning method based on the optimal design of a second-order system, ensuring excellent control performance at different switching frequencies.

[0071] (1) Equivalent delay model The control delay of a multi-rate system mainly comes from the sampling delay and the PWM update delay. This system, combining the dual-time-scale sampling characteristics, proposes a dedicated equivalent delay time. The calculation formula accurately describes the system's delay characteristics, providing a foundation for PI parameter tuning. Equivalent delay time. The calculation formula is:

[0072] in: Equivalent delay time (unit: ms); : Slave station short-cycle sampling duration of 0.5ms (fixed at 0.5ms); : The sampling duration of the main station for the entire cycle (i.e., the PWM switching frequency cycle, 1ms / 2ms / 4ms / 8ms).

[0073] This model fully considers the average sampling delay of 0.5ms from the slave station (0.5ms). The delay between 0.25 and PWM update (0.25) This model can accurately reflect the dynamic characteristics of multi-rate systems, solving the problem that traditional models cannot adapt to multi-rate systems.

[0074] For example: when =4ms =0.5ms, = 0.5×0.5 + 0.25×4 = 1.25ms; when =2ms, =0.5ms, = 0.5×0.5 + 0.25×2 = 0.75ms.

[0075] (2) Optimal PI design for second-order systems Based on the above equivalent delay model The multi-rate system is simplified to a typical system of "first-order inertia + pure delay". The PI parameters are tuned using the optimal design criterion for Type I systems to ensure that the system has a fast dynamic response, small overshoot, and no steady-state error. The specific tuning process is as follows: Determine the open-loop transfer function of the system: Simplify the multi-rate system to ,in For system gain, The system's inertial time constant (determined by motor parameters) , ), This is the equivalent delay time.

[0076] Optimal parameter tuning for a second-order system: Based on the optimal design criteria for a second-order system, select the proportional gain of the PI controller. With integration time The specific calculation formula is as follows: Scale factor:

[0077] Points Time:

[0078] At this point, the equivalent time constant of the entire closed-loop system is: The step response overshoot is 4.3%, which well meets the requirements of fast response and low overshoot in the current loop; when the PWM switching frequency changes, the master station adjusts the response according to the new frequency. Reconfiguration The data is then sent to the slave stations to ensure that the system maintains optimal control performance at different switching frequencies.

[0079] Segmented PWM Carrier Generation Method This system proposes a segmented, stacked carrier generation method. Based on a master-slave synchronous clock, it achieves accurate generation of multi-cycle triangular carriers, supports smooth online switching of the switching frequency, and is compatible with both carrier comparison PWM and synchronous symmetrical lookup table PWM methods (without physical carriers). This solves the problems of poor synchronization and limited adaptability of traditional carrier generation methods, and is one of the core innovations of this system. The specific mechanism is as follows: (1) Clock synchronization basis: The master station and the slave station use an improved precision clock synchronization protocol to achieve strict synchronization between the slave station clock and the master station clock with a 0.5ms control cycle, ensuring the timing consistency between the master and slave stations and providing a basis for the synchronization of carrier generation.

[0080] See Figure 7 As shown, the improved precision clock synchronization method and transmission line delay measurement method are used. The communication between the master station and the slave station adopts 50MHz optical fiber communication with a communication cycle of 10µs / time.

[0081] During each communication, the master station uses its own clock to record the transmission time. and the moment of acceptance The slave station uses its own clock to record the receiving time. and the time of transmission ; This allows us to obtain the total delay for each transmission.

[0082] Calculate the average one-way delay of the fiber optic line for multiple communication transmissions.

[0083] After each transmission, the compensation amount for the clock errors between the master and slave stations should be: (where i = 1 ~ n) The above is the basic principle of transmission delay measurement. However, due to fluctuations in protocol parsing time, the time recorded by the slave station may vary. (Where i=1~n) will also fluctuate. High-precision synchronization requires filtering and compensating for random errors. The principle is as follows: See Figure 8 The high-precision clock closed-loop control principle diagram shown uses a 200MHz clock (5ns per unit time) for both the master station communication clock and the slave station communication clock. The clock increments by 8 values ​​every 5ns and cycles around the clock with a period of 0.5ms. The range of the values ​​is 0~800k.

[0084] First, the average fiber optic line delay of multiple communication transmissions is calculated.

[0085] Compensation amount for slave calibration after each transmission

[0086] (where i = 1 to n, and n is the number of transmissions) Yes (Average clock offset after integration) Use every 0.5ms The slave station's communication clock is calibrated. Since n takes a relatively large value, therefore... It can maintain numerical stability, making the fluctuation of the slave control clock very small.

[0087] Random errors are suppressed by using a proportional feedback closed-loop method, which is equivalent to introducing system damping to eliminate the impact on the system. The system oscillations caused by long-period integration.

[0088] right The compensation clock TC is obtained by performing large inertia filtering. Slave control clock TSC = Slave communication clock TS + Compensation clock TC. This clock is a high-precision, low-fluctuation synchronous clock.

[0089] (2) Core logic for carrier generation: The slave station uses the synchronized 0.5ms ramp clock as the basic unit to decompose the long-period triangular carrier into multiple 0.5ms short-period "segments". Through segmented stacking calculation, triangular carriers with different periods (1ms / 2ms / 4ms / 8ms) are generated. This method does not require complex hardware frequency multiplication or phase-locked loop (PLL) and can be implemented only through software algorithm. Moreover, the carrier is always aligned with the slave station's synchronization clock and there is no phase drift.

[0090] The general calculation formula for the above software algorithm is as follows: To achieve accurate generation of carriers with different periods, the following variables are defined: PWM switching frequency period (i.e. carrier period, unit: ms), with values ​​of 1ms, 2ms, 4ms, and 8ms; Slave station base clock cycle: 0.5ms (fixed at 0.5ms); The number of fundamental clock cycles contained within a carrier cycle. (like =4ms, =8; =2ms, =4); : Base clock count value, ranging from 0 to ; : No. Carrier output value within one basic clock cycle; : No. The carrier base offset corresponding to each base clock cycle (pre-calculated and stored in the FPGA to ensure the continuity and integrity of carrier segment stacking).

[0091] Based on the above variables, the general calculation formula for segmented and stacked carriers is as follows: Carrier rise phase: when the base clock counter Incrementing from 0 to ( When -1), the carrier value linearly increases from 0 to the peak value, and the calculation formula is:

[0092] Carrier fall-off phase: When the base clock counter k reaches Then, in the next 0.5ms cycle, the carrier value linearly decreases from its peak to 0, calculated as follows:

[0093] Using the above formula, the slave station can determine the current switching frequency based on the given frequency. Automatically call the corresponding and It achieves accurate generation of triangular carrier waves with different periods, and the carrier waves are strictly synchronized with the 0.5ms base clock.

[0094] Online switching frequency When switching frequencies online, the master station issues a new switching frequency command, and the slave station updates synchronously. , and The parameters, calculated using the general formula described above, regenerate the corresponding periodic triangular carrier wave to achieve seamless switching of the switching frequency. During the switching process, there are no phase jumps or voltage surges, ensuring system stability. Specific switching procedure: The master station issues new PWM switching frequency commands (125Hz / 250Hz / 500Hz / 1000Hz) according to the operating conditions. After receiving the instruction from the slave station, it automatically matches the corresponding... (8ms / 4ms / 2ms / 1ms), calculate ; The slave station calls the pre-stored corresponding The parameters are used to regenerate the triangular carrier according to the calculation formulas for the carrier rise and fall phases; During the switching process, the slave station maintains continuous operation of the current loop and integral circuit to ensure smooth voltage output without significant fluctuations.

[0095] Synchronous PWM compatibility To address the limitation of synchronous symmetrical lookup table PWM methods lacking a physical carrier, this system achieves compatibility between the current loop and the synchronous PWM modulation strategy by setting a virtual carrier period, without requiring modification to the lookup table logic. (See [link to relevant documentation]). Figure 9 The timing diagram for synchronous PWM virtual carrier and voltage update is as follows: (1) Virtual carrier setting: Set the virtual carrier period to 1kHz (corresponding to a period of 1ms), which is strictly aligned with the slave station's 0.5ms control period, that is, each virtual carrier period contains two 0.5ms control periods.

[0096] (2) Voltage setting update logic: The synchronous symmetrical lookup table PWM method does not have carrier peak and valley points. This system aligns the peak and valley points of the virtual carrier with the 0.5ms control cycle. The voltage setting is updated synchronously every 0.5ms, which is equivalent to updating the voltage setting at the peak and valley points of the virtual carrier, ensuring the synchronization of PWM modulation.

[0097] (3) Compatibility effect: Through the virtual carrier mechanism, the current loop control logic of this system can be directly adapted to the synchronous symmetrical lookup table PWM method without adding hardware or modifying the underlying lookup table algorithm, thus broadening the applicability of the system; at the same time, the 0.5ms voltage setpoint update frequency, combined with short-cycle average value sampling, solves the problem that instantaneous value sampling is easily interfered with, further improving the smoothness of the output voltage.

[0098] Timing control and voltage update strategy Strict timing design To ensure the real-time and synchronous nature of data exchange between the master and slave stations and to avoid timing deviations affecting control performance, this system is designed with a strict 0.5ms periodic communication timing, strictly aligned with the carrier period and sampling period. The specific timing is as follows: (1) Communication cycle: fixed at 0.5ms, consistent with the slave station sampling cycle and virtual carrier update cycle, to ensure the coordination of data interaction and control logic.

[0099] (2) Timing of data transmission: At 490μs in each communication cycle, the master station transmits instructions and data such as dq axis current setting, magnetic field orientation angle, feedforward voltage, and PI parameters (if the switching frequency is switched) to the slave station via optical fiber communication.

[0100] Upload timing: After receiving data from the master station, the slave station immediately uploads its own calculated 0.5ms average current value. The upload time is 496~499μs, and the communication time is strictly controlled within 6~9μs to ensure that the master station can receive and process the sampled data uploaded by the slave station before the 0.5ms communication cycle ends.

[0101] Timing alignment: The communication cycle is strictly aligned with the carrier cycle. For example, a 4ms carrier cycle (corresponding to a 250Hz switching frequency) contains eight 0.5ms communication cycles. The voltage update time of each communication cycle is aligned with the peak and trough of the carrier (or the virtual peak and trough of the carrier) to ensure the accuracy of PWM generation.

[0102] Voltage update strategy, see Figure 10 Regarding the integral effect and voltage update strategy, existing technologies traditionally consider that the voltage setting of the current loop is only effective at the peak and trough of the carrier wave. Calculating the current loop at non-peak and trough points is considered a "waste of resources" because the updated voltage setting cannot be immediately applied to PWM generation, leading to control logic redundancy. This system explores and utilizes the integral accumulation effect of the current loop to achieve efficient use of control resources, improve the system's anti-aliasing capability, and enhance output voltage smoothness.

[0103] Specifically as follows: (1) Voltage setting update rule: Regardless of whether the carrier comparison PWM method or the synchronous symmetrical lookup table PWM method is used, this system follows the rule that "the voltage setting is only updated at the peak and valley points of the carrier (or the virtual peak and valley points)" to ensure the accuracy of PWM pulse generation and avoid the misalignment of the scope caused by random voltage setting updates, which leads to PWM waveform distortion.

[0104] (2) Integral accumulation logic: At non-carrier peak and valley times, the voltage setting is not updated, but the current loop integration link continues to work. The integral value is accumulated in real time according to the current current deviation without interruption or reset.

[0105] (3) Core effect: Taking a 4ms carrier cycle (corresponding to 8 0.5ms communication cycles) as an example, within one carrier cycle, the slave station will complete 8 0.5ms samplings, 8 current loop calculations, and 8 integral accumulations. All 8 sampling points are 500μs average values. Compared with traditional single-point instantaneous value sampling, the anti-aliasing effect is significantly improved. At the same time, the current deviation of all 8 sampling points participates in the integration, which is equivalent to the effect of "8 times oversampling + integral smoothing filtering", making the output voltage smoother, the current waveform harmonics lower, and the motor running more smoothly.

[0106] Example 1 Using a 250Hz PWM switching frequency (corresponding to a carrier period of 4ms) as the core embodiment, and combining the actual parameters of an 11kW permanent magnet synchronous motor, this paper describes in detail the hardware construction, software implementation, and core algorithm execution steps of a three-level inverter multi-rate distributed control system. A variant implementation with a 1000Hz switching frequency is also provided to illustrate the adaptability of this invention across the entire switching frequency range. In this embodiment, the motor parameters are: stator... =0.2Ω, stator inductance =5mH, rated speed 1500r / min, rated phase voltage 220V, rated current 20A, electric angular velocity ω range 0~314rad / s.

[0107] (I) Example 1: 250Hz PWM switching frequency (carrier period Ts=4ms) 1. Hardware architecture setup The hardware of this system consists of a master station, slave stations, a 50M fiber optic communication link, and a three-level inverter power section. The specific hardware selection and connection are as follows: Main station: The TI TMS320F28377 DSP is selected as the core processor, which is responsible for executing the motor vector control algorithm; Slave: The ALTERA EP4CE75 FPGA is selected as the core processor, with an external 16-bit high-precision current sampling module, fiber optic receiver module, and PWM drive module, which are responsible for high-speed sampling, current loop PI regulation, and PWM generation. Communication link: A 50M fiber optic cable is used to realize point-to-point communication between master and slave stations. The communication protocol is a custom periodic protocol with a communication period of 0.5ms and a communication latency controlled within 6~9μs. Power stage: It adopts the NPC three-level inverter topology, and the power device is IGBT (model FF100R12RT4). It supports four switching frequencies of 125Hz / 250Hz / 500Hz / 1000Hz. The output is connected to an 11kW permanent magnet synchronous motor.

[0108] 2. Software Module Deployment The master station software module is developed using C language based on DSP, while the slave station software module is developed using Verilog HDL based on FPGA. The master and slave station software modules operate collaboratively with a control cycle of 0.5ms. The module initialization and operation process is as follows: (1) Initialization of main station software modules Full-cycle sampling processing module: Configure the accumulation coefficient to 8 (the average value of 8 short cycles of 0.5ms needs to be accumulated for a 4ms full cycle), and initialize the current average value storage array; PI parameter tuning module: Input motor parameters =0.2Ω =5mH, calculate the system's inertial time constant. = / =25ms, system gain =1 / =1 / 0.2=5; calculated according to the equivalent delay model. =0.5×0.5+0.25×4=1.25ms, and then tune the PI parameter: proportional coefficient. =0.5× / ( × = 0.5 × 25 / (5 × 1.25) = 2, integration time = =25ms; Communication transmission module: Configure fiber optic transmission timing, and set 490μs as the command issuance time.

[0109] (2) Initialization of slave software module Communication receiving module: Configure fiber optic receiving timing, and set 499μs as the sampling data upload time; Dual time-scale sampling module: configured with a sampling frequency of 1MHz (1μs / point), collecting 500 instantaneous current values ​​every 0.5ms period, and initializing the average value calculation register; Deviation compensation module: pre-stores the phase time difference Δt=1.75ms corresponding to Ts=4ms, configures the first-order low-pass filter time to 20ms, and sets the amplitude compensation ratio coefficient K=1; Multi-rate PI control module: Receives data from the master station. =2、 =25ms, initialize the PI integration register; Segmented Carrier Generation Module: Calculation = 4 / 0.5 = 8, pre-store the base[k] values ​​corresponding to 8 basic clock cycles, which are [0,0.5,1.0,1.5,2.0,2.5,3.0,3.5] (unit: ms), and configure the synchronization clock to 200MHz; PWM Generation and Drive Module: Configures the dead time of the PWM drive signal of the three-level inverter to be 2μs, and aligns the voltage setpoint update time with the peak and valley points of the carrier wave.

[0110] 3. Core algorithm execution steps (0.5ms control cycle, single cycle execution) This system uses a basic control period of 0.5ms, and executes the same control steps 8 times within a 4ms carrier period. The specific steps are as follows: Step 1: High-speed sampling and average value calculation from the station The slave FPGA initiates 1MHz sampling, taking 500 1μs instantaneous values ​​of the three-phase current of motor A, B, and C. The arithmetic mean of the 500 samples for each phase is calculated to obtain the 0.5ms short-cycle current average. After sampling is completed, the sampling channel is closed to avoid interference.

[0111] Step 2: Master-slave fiber optic communication interaction At 490μs: The master station DSP transmits the magnetic field orientation angle to the slave station via optical fiber. dq axis current given Feedforward voltage PI parameters; At 499μs: The slave FPGA transmits the average three-phase 0.5ms short-cycle current to the master station via optical fiber. The communication time is 8μs, which meets the 0.5ms period requirement.

[0112] Step 3: Master Station Integer Sampling Processing and Vector Control The main site receives data uploaded by the slave site. Store it in the current average value storage array, for 8 The average current over a 4ms cycle is obtained by averaging. ; The main site is based on Execute the field orientation algorithm, calculate the dq-axis current, adjust the speed loop, and update the field orientation angle. dq axis current given And calculate the feedforward voltage. In preparation for the next communication.

[0113] Step 4: Slave station deviation compensation (phase + amplitude) Phase compensation: The slave station receives the electrical angular velocity ω (ω=314 rad / s) from the master station, and calculates the phase compensation angle Δθ=ω×Δt=314×0.00175=0.5495 rad; Δθ is then superimposed on the original magnetic field orientation angle. The angle after compensation = + 0.5495 rad, used for subsequent dq axis coordinate transformation; Amplitude compensation: An inner-loop feedback compensation scheme (recommended) is adopted, where the slave station receives signals from the master station. Calculate the amplitude difference Δ ; for Δ Perform a first-order low-pass filter with a time constant of 20ms to obtain Δ ; will Δ and Add them together to obtain the compensated feedback current. =Δ + , which serves as the feedback signal for the closed-loop control of the current loop.

[0114] Step 5: Slave station multi-rate PI regulation The slave station is based on the compensated feedback current. With the current given by the main station Input the PI controller and perform PI calculation: = ×[1+ Obtain the intermediate value of the voltage setpoint after PI regulation. Combined with the feedforward voltage issued by the main station The final voltage setting is obtained. .

[0115] Step 6: Generation of segmented PWM carriers from the slave station The slave station performs carrier stacking calculations based on a 200MHz synchronization clock, N=8, and a pre-stored base[k]. When k=0~3 (carrier rise phase): carrier(k)=cnt+base[k], the carrier value rises linearly from 0 to 2.0ms (peak). When k=4~7 (carrier descent phase): carrier(k)=8×0.5-cnt-base[k], the carrier value decreases linearly from 2.0ms to 0; a triangular carrier with a period of 4ms is generated, which is strictly aligned with the synchronization clock and has no phase drift.

[0116] Step 7: Slave PWM Generation and Voltage Update The slave station compares the voltage reference Uref with the generated triangular carrier wave to generate the PWM drive signal for the three-level inverter. After adding a 2μs dead time, it sends the signal to the power unit to drive the IGBT. In this step, the voltage setting is not updated (non-carrier peak / valley point), but the PI integrator continues to work, and the integral value is accumulated in real time according to the current deviation.

[0117] Step 8: Execute repeatedly After completing a single 0.5ms control cycle, the slave station clears the sampling register, the master station updates the cumulative count, and enters the next 0.5ms control cycle, repeating steps 1 to 7. When k=8, a 4ms carrier cycle is completed, and the voltage setting is updated at the peak and valley points of the carrier, realizing the accurate generation of PWM pulses.

[0118] (II) Example 2: 1000Hz PWM switching frequency This embodiment is an adaptation implementation for a 1000Hz switching frequency. The motor parameters and hardware architecture are the same as in Embodiment 1, with adjustments only made to the core parameters, cumulative coefficient, PI parameters, and carrier generation parameters. The specific adjustments and key steps are as follows: Parameter adjustment: Cumulative coefficient for whole-cycle sampling: = 1 / 0.5 = 2; Phase time difference: Δt = 0.5 × (1 - 0.5) = 0.25 ms; Equivalent delay: =0.5×0.5+0.25×1=0.5ms; PI parameters: =0.5×25 / (5×0.5)=5, =25ms; Carrier generation base[k]: Values ​​are [0, 0.5] (unit: ms).

[0119] Step adjustments: Main station whole-cycle sampling: Accumulate two 0.5ms averages to obtain a 1ms whole-cycle average. ; Phase compensation: Δθ=ω×0.00025, with a smaller compensation angle and higher phase accuracy; Carrier generation: k=0~1, representing the rising and falling phases respectively, generating a 1ms periodic triangular carrier. Voltage update: Two 0.5ms control cycles are executed within a 1ms carrier cycle, and the integral element accumulates two times. The voltage setpoint is updated at the peak and trough of the carrier.

[0120] See Figure 11 The amplitude attenuation and compensation effects shown indicate that, compared with the uncompensated amplitude attenuation, the amplitude after compensation using this system shows no significant attenuation.

[0121] See Figure 12 As shown in the comparison of current fluctuations between the proposed scheme and the conventional scheme, the current fluctuations are significantly more stable after adopting the proposed scheme.

[0122] See Figure 13 In a comparison of torque current response time, the response time using this system was improved from 5.5ms to 3ms using the conventional method, resulting in a significantly faster response speed.

[0123] See Figure 14 The improved clock synchronization effect has increased the clock synchronization accuracy from 150ns to 44ns, resulting in a significant improvement in synchronization accuracy.

[0124] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A three-level inverter multi-rate distributed control system, characterized by, It includes a master station, slave stations, a 50M fiber optic communication link, and three-level inverters. The master station communicates with multiple slave stations through the 50M fiber optic communication link, and each slave station communicates with a three-level inverter. Multiple three-level inverters are connected in parallel to drive the motor. The master station performs vector control based on whole-cycle sampling. The master station uses a DSP processor and is responsible for calculating the average current value of the whole cycle, motor vector control, and issuing commands. The slave station performs closed-loop control of the current loop based on short-cycle sampling and generates PWM drive signals, and achieves multi-rate coordination through phase time difference compensation and amplitude deviation compensation; the slave station uses an FPGA processor to be responsible for short-cycle current sampling and average value calculation, current loop PI regulation, PWM generation and driving; The master station and the slave station achieve multi-rate coordinated control through phase time difference compensation and amplitude deviation compensation. The master station and the slave station are clock synchronized to achieve periodic communication.

2. The three-level inverter multi-rate distributed control system according to claim 1, characterized in that, The system executes the following algorithm steps: Step 1: Sampling and Calculation of Average Current from Substation; Sampling is initiated at the substation, and multiple short-cycle instantaneous values ​​of the A, B, and C phase currents of the motor are sampled. The arithmetic mean of the multiple sampled values ​​for each phase is calculated to obtain the average short-cycle current. After sampling is completed, the sampling channel is closed. Step 2: master-slave station optical fiber communication interaction; the master station issues motor vector control parameters to the slave station through optical fiber once, and the parameters include feedforward voltage U ff ; the slave station uploads short-period current average to the master station through optical fiber; Step 3: Master station full-cycle sampling processing and vector control; The master station receives the short-cycle current average value, calculates the whole-cycle current average value, and calculates the motor vector control parameters, which are then sent to the slave station in the next communication interaction. Step 4: The slave station receives the average current value of the entire cycle from the master station, performs phase time difference compensation and amplitude deviation compensation, and obtains the compensated average current value of the entire cycle. Step 5: Slave station multi-rate PI regulation; Based on the compensated average current over the entire cycle, calculate the intermediate value U of the voltage setpoint after PI regulation. PI Combined with the feedforward voltage U issued by the main station ff The final voltage setting is obtained. ; Step 6: Segmented PWM carrier generation at the slave station. The slave station performs carrier stacking calculation to generate a voltage triangular carrier corresponding to the whole cycle. Step 7: From the station PWM generation and voltage update, the final voltage given U ref The PWM drive signal of the three-level inverter is generated by comparing with the corresponding voltage triangular carrier, and is sent to the motor for driving; Step 8: Repeat steps 1 to 7 to achieve accurate generation of PWM pulses.

3. The three-level inverter multi-rate distributed control system according to claim 2, characterized in that, In step 1, the A, B, and C phase currents of the motor are sampled at a short period of 0.5ms from the slave station, and the average of 500 1μs instantaneous values ​​is calculated to obtain the 0.5ms short-cycle current average value.

4. The three-level inverter multi-rate distributed control system according to claim 3, characterized in that, The main station's full-cycle sampling processing and vector control in step 3 include: The master station receives the 0.5ms short-cycle current average value uploaded by the slave station, stores it in the current average value storage array, and calculates the whole-cycle current average value with periods of 1ms, 2ms, 4ms and 8ms for magnetic field orientation calculation. The master station executes a field-oriented algorithm based on the average current over the entire cycle to calculate the motor vector control parameters, including the field-oriented angle. dq axis current given .

5. The three-level inverter multi-rate distributed control system according to claim 4, characterized in that, The phase time difference compensation in step 4 specifically involves the following steps: Because there is a time offset between the midpoint of the master station's whole-cycle sampling and the midpoint of the slave station's short-cycle sampling, a phase time difference is generated. The calculation formula is: ,in, It is the total sampling duration of the main station throughout the entire cycle. The short-cycle sampling time Δt is measured in milliseconds (ms) and changes automatically with the PWM switching frequency. After calculating the phase time difference, the compensation angle is obtained by combining it with the motor's electrical angular velocity ω. The phase compensation angle Δθ = ω × Δt is then calculated and superimposed on the original magnetic field orientation angle. The angle after compensation Correct the vector rotation angle.

6. The three-level inverter multi-rate distributed control system according to claim 5, characterized in that, The amplitude deviation compensation in step 4 adopts feedback compensation, and the specific steps are as follows: The system obtains two types of average current values ​​in real time: one is the short-cycle average current value calculated by the system itself (0.5ms). Second, the average current value of the entire cycle issued by the main station. Calculate the difference between the average values ​​of the two types of currents. The calculation formula is: ， For the difference Low-pass filtering is performed to remove high-frequency interference, resulting in the filtered differential current. To avoid high-frequency interference affecting the compensation effect; Operating condition assessment and compensation execution: The slave station will and Add them together to obtain the compensated feedback current. The calculation formula is: ， by The current loop feedback signal is used for closed-loop control to ensure the average current value over the entire cycle in steady state. When the current is equal to the given value, and the load changes abruptly, It plays a key role in ensuring dynamic response speed.

7. The three-level inverter multi-rate distributed control system according to claim 5, characterized in that, The amplitude deviation compensation in step 4 uses a given outer loop correction. The specific steps are as follows: The average short-cycle current of the slave station calculated by itself over 0.5ms. As the basic feedback signal, conventional current loop closed-loop control is performed to ensure the system's dynamic response speed; The slave station obtains the raw current command issued by the master station in real time. Compared with the average current of the whole cycle Calculate the difference between the two. The calculation formula is: ， For the difference Perform low-pass filtering to obtain the filtered difference. Multiply it by the preset scaling factor The current compensation amount is obtained. The calculation formula is: ， Working condition adaptation and compensation execution: Under dynamic working conditions, It changes in real time with sudden changes in load and current. Attach in real time The final current setting on the FPGA side is obtained from the above. The calculation formula is: ， From the station Given, combined Implement closed-loop control for rapid response to changes in operating conditions; under steady-state conditions... Approaching zero, the magnitude of the value is related to the coefficient. Inversely proportional, Approaching a constant value, making and The difference narrows; under dynamic operating conditions, the slave station still... Based on feedback.

8. The three-level inverter multi-rate distributed control system according to claim 4, characterized in that, In step 5, the current loop PI regulation adopts a multi-rate PI parameter tuning method, and the specific steps are as follows: Establish an equivalent delay model: =0.5 +0.25 ,in, It is the equivalent delay time; The short-cycle sampling duration from the slave station is fixed at 0.5ms; This refers to the total sampling duration of the main station throughout the entire cycle; based on the equivalent delay model, the proportional coefficient of the PI controller is selected. With integration time When the PWM switching frequency changes, the master station updates the equivalent delay time. Re-adjust the proportional coefficient The data is then sent to the slave stations, enabling the system to adapt to different switching frequencies.

9. The three-level inverter multi-rate distributed control system according to claim 4, characterized in that, The specific method for generating the slave station segmented PWM carrier in step 6 is as follows: Define the number of fundamental clocks N contained within a carrier period = / ,in The PWM switching frequency period, The short-cycle sampling duration is denoted as carrier(k), which is the carrier output value in the k-th base clock cycle. cnt is the base clock count value, ranging from 0 to Tc. base[k] is the carrier base offset corresponding to the k-th base clock cycle, which is pre-calculated and stored in the slave station. During the carrier rise phase, as the base clock counter k increments from 0 to (N / 2-1), the carrier value linearly rises from 0 to the peak value. The calculation formula is: carrier(k) = cnt + base[k]; During the carrier descent phase, when the base clock counter k reaches N / 2, the carrier value linearly decreases from the peak value to 0. The calculation formula is: carrier(k) = N×Tc - cnt - base[k].

10. The three-level inverter multi-rate distributed control system according to claim 4, characterized in that, In step 7, the system is compatible with the synchronous symmetrical lookup table PWM method. The virtual carrier period is set to be aligned with the 0.5ms short-cycle control period. The voltage setpoint is updated synchronously every 0.5ms short cycle. Specifically, the voltage setpoint is updated at the peak and valley points of the virtual carrier. The voltage setpoint is not updated at non-peak and valley points. However, the errors of multiple 0.5ms short-cycle sampling points within one carrier period are all integrated to achieve an equivalent oversampling smoothing effect.

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