Methods, apparatus and systems for multiband hybrid inductor-capacitor voltage-controlled oscillators

Abstract

This disclosure relates to methods, apparatus, and systems for multi-band hybrid inductor-capacitor voltage-controlled oscillators. An example apparatus includes an inverter (306) having a first terminal and a second terminal coupled to an enable terminal (352). The apparatus includes a first transistor (312) having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the inverter (306), the first terminal being coupled to a power supply terminal (348). The apparatus includes a second transistor (314) having a control terminal, a first terminal, and a second terminal, the first terminal being coupled to the second terminal of the first transistor (312). The apparatus includes an inductor (322) having a first terminal coupled to the second terminal of the second transistor (314) and a second terminal coupled to the control terminal of the second transistor (314).

Description

Technical Field

[0001] This specification generally relates to oscillators, and more specifically to methods, apparatus, and systems for multi-band hybrid inductor-capacitor voltage-controlled oscillators. Background Technology

[0002] Electronic oscillators generate periodic, oscillating, or alternating current (AC) signals. For example, electronic oscillators, or more generally oscillators, generate signals such as sine waves, square waves, or triangle waves. Oscillators are used in a variety of applications, such as receivers, transmitters, computers, peripherals, mobile devices, and televisions. Summary of the Invention

[0003] For methods, apparatus, and systems for multi-band hybrid inductor-capacitor voltage-controlled oscillators, an example apparatus includes an inverter having a first terminal and a second terminal coupled to an enable terminal. The apparatus includes a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the inverter, and the first terminal being coupled to a power supply terminal. The apparatus includes a second transistor having a control terminal, a first terminal, and a second terminal, the first terminal being coupled to the second terminal of the first transistor. The apparatus includes an inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor. The apparatus includes a capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor. The apparatus includes a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the inductor and the first terminal of the capacitor, and the second terminal being coupled to the second terminal of the inductor and the second terminal of the capacitor. The device includes a fourth transistor having a control terminal coupled to the enable terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the third transistor. Other examples are described.

[0004] For methods, apparatus, and systems for multi-band hybrid inductor-capacitor voltage-controlled oscillators, an example inductor-capacitor (LC) oscillator includes a first inverter having a first terminal and a second terminal coupled to an enable terminal. The LC oscillator includes a first core comprising: a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first inverter, the first terminal coupled to a power supply terminal; a first LC resonant circuit including a first inductor and a first capacitor, the first LC resonant circuit having a first terminal and a second terminal, a clock signal being measured across the first terminal and the second terminal; and a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the enable terminal, the first terminal coupled to a ground terminal. The LC oscillator includes a second inverter having a first terminal and a second terminal coupled to a tuning terminal. The LC oscillator includes a second core comprising: a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the second inverter, the first terminal being coupled to the power supply terminal; a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the first LC resonant circuit, the first terminal being coupled to the second terminal of the third transistor; a second LC resonant circuit including a second inductor and a second capacitor, the second LC resonant circuit having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the fourth transistor; and a fifth transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the second terminal of the first LC resonant circuit, the second terminal being coupled to the second terminal of the second LC resonant circuit; and a sixth transistor having a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the fifth transistor, the first inductor being coupled to the second inductor via mutual inductance. Other examples are described.

[0005] For methods, apparatus, and systems for multi-band hybrid inductor-capacitor voltage-controlled oscillators, an example phase-locked loop (PLL) oscillator includes a phase comparator circuit having terminals. The PLL oscillator includes a filter circuit having a first terminal and a second terminal coupled to the terminals of the phase comparator circuit. The PLL oscillator comprises an inductor-capacitor (LC) voltage-controlled oscillator (VCO) including: an inverter having a first terminal and a second terminal coupled to the first terminal of the filter circuit; a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inverter, the first terminal coupled to a power supply terminal; a second transistor having a control terminal, a first terminal, and a second terminal, the first terminal coupled to the second terminal of the first transistor; an inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the second transistor; a capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor; a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inductor and the first terminal of the capacitor, the second terminal coupled to the second terminal of the inductor and the second terminal of the capacitor; and a fourth transistor having a control terminal coupled to the first terminal of the filter circuit, a first terminal coupled to a ground terminal, and a second terminal coupled to the first terminal of the third transistor. Other examples are described. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an example inductor-capacitor (LC) voltage-controlled oscillator (VCO).

[0007] Figure 2 It is a description Figure 1 A first example graph and depiction of the oscillation signal at the first and second terminals of the LC resonant circuit. Figure 1 A graphical illustration of the second example of the differential output signal of an LC resonant circuit.

[0008] Figure 3 This is a schematic diagram of a sample LC VCO, which includes a sample main core and sample peripheral cores.

[0009] Figure 4A yes Figure 3 A schematic diagram of an LC VCO, in which the second inductor of the outer core is physically nested within the first inductor of the main core.

[0010] Figure 4B This is a top view of the first inductor in the main core and the second inductor in the peripheral core.

[0011] Figure 4C This is a cross-sectional side view of the first inductor in the main core and the second inductor in the peripheral core.

[0012] Figure 5 It is a description Figure 3 A graphical illustration of an example of the operating frequency variation of an LC VCO in response to the value of the tuning signal and the coupling factor K between the first and second inductors.

[0013] Figure 6 It is a graphic illustration depicting a first example oscillation signal and a second example oscillation signal in an LC resonant circuit when the tuning signal has a value of zero, and a second example oscillation signal in an LC resonant circuit when the tuning signal has a value of one.

[0014] Figure 7A and 7B (Collectively referred to as Figure 7) is a schematic diagram of an example LC VCO containing an example main core and N example peripheral cores.

[0015] Figure 8A and 8B (Collectively referred to as Figure 8) is a schematic diagram of the LC VCO in Figure 7, wherein there are two peripheral cores, and the third inductor of the peripheral core is physically nested in the second inductor of the peripheral core, and the second inductor of the peripheral core is physically nested in the first inductor of the main core.

[0016] Figure 9 This is a block diagram of an example phase-locked loop (PLL) oscillator that includes an example VCO implemented in conjunction with the examples described herein.

[0017] Figure 10 It is a block diagram of an example vehicle that includes an example Advanced Driver Assistance System (ADAS) system and an example In-vehicle Infotainment (IVI) system.

[0018] Figure 11 It includes a sample ADAS hub, a sample peripheral module, and a sample display. Figure 10 A block diagram of an example ADAS system, wherein the ADAS hub further includes an example deserializer circuit system, and the peripheral module further includes an example serializer circuit system.

[0019] Figure 12 It is a block diagram of an example IVI system including an example IVI driver circuit system, an example display driver, and an example display. The IVI driver circuit system includes an example serializer circuit system, and the display driver includes an example deserializer circuit system.

[0020] Figure 13 It includes Figure 11 and 12 Examples of serializer circuit systems and Figure 11 and 12 The block diagram of an example serial deserializer (SerDes) system is provided, which further includes a retimer circuit system.

[0021] The accompanying drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to the same or similar features or parts (in terms of at least one of their function or structure). Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be unobservable, mixed, or irregular. Detailed Implementation

[0022] Oscillators can be implemented as linear or nonlinear oscillators. In some instances, linear oscillators are called resonant oscillators, and nonlinear oscillators are called relaxation oscillators. One type of linear oscillator is the inductor-capacitor (LC) oscillator. One type of LC oscillator includes a tuning circuit with an inductor coupled to a capacitor, which is called an LC resonant circuit. In an LC oscillator, the LC resonant circuit acts as a resonator, allowing charge to flow back and forth between the plates of the capacitor via the inductor. Therefore, an LC resonant circuit can store electrical energy oscillating at the resonant frequency of the LC resonant circuit.

[0023] In some instances, the resonant frequency of an LC resonant circuit and the frequency of the oscillation signal (sometimes called the clock signal) generated by the LC oscillator can be tuned. For example, the resonant frequency of an LC resonant circuit can be tuned by adjusting the capacitance of the LC resonant circuit using coarse-grained or fine-grained control, thereby achieving [tuning / adjusting / resonance]. A proportional tuning range. Furthermore, the frequency tuning of an LC resonant circuit can be achieved by tuning the inductor of the LC resonant circuit. To tune the inductor of an LC resonant circuit, two or more inductors are coupled to a capacitor in the LC resonant circuit, and a switch is placed in series with each of the two or more inductors in the LC resonant circuit. The switch is used to selectively connect the inductors to the LC resonant circuit, thereby tuning the LC resonant circuit. Including a switch in series with two or more inductors affects the quality factor (Q) of the LC resonant circuit.

[0024] Oscillators can also be controlled by an input voltage signal. For example, the frequency generated by a voltage-controlled oscillator (VCO) can vary within a range defined by the VCO's architecture in response to the input voltage signal. An LC VCO is an LC oscillator controlled by an input voltage signal that tunes the LC oscillator frequency. The tuning range of an LC VCO is limited. For example, the tuning range of a single LC VCO can be between 1 and 1.5 GHz. Modern applications may require oscillators that support an operating frequency range between 4 GHz and 8 GHz.

[0025] Therefore, multiple LC VCOs may be needed to support a wider operating frequency range than a single LC VCO can tune. Implementing multiple LC VCOs requires a significant amount of on-chip area and consumes substantial power. For example, implementing multiple LC VCOs requires a large area on the chip to ensure that the LC VCOs remain physically isolated from each other. Furthermore, high-speed multiplexers may be needed to switch between different clock signals generated by multiple LC VCOs, which can lead to clock distortion, clock jitter, routing complexity, and increased power consumption.

[0026] Some LC VCOs are designed with complementary metal-oxide-semiconductor (MOS) transistors. For example, an LC VCO is designed with two positive-channel (p-channel) MOS (PMOS) transistors and two negative-channel (n-channel) MOS (NMOS) transistors coupled in parallel with the LC resonant circuit. Thus, because four MOS transistors are coupled in parallel with the LC resonant circuit, a large parasitic capacitance is formed in the LC VCO.

[0027] The increase in parasitic capacitance necessitates a reduction in the inductance of the LC resonant circuit to achieve the target resonant frequency. Consequently, the characteristic impedance of the LC resonant circuit is also reduced. For example, because each MOS transistor has a finite output impedance. Therefore, the impedance of the LC resonant circuit is reduced. Consequently, due to the reduced impedance of the LC resonant circuit, increased power is required to start the LC VCO and maintain the amplitude of the clock signal generated by the LC VCO. Furthermore, the efficiency of the LC VCO is also reduced due to the parasitic capacitance generated within the LC VCO.

[0028] The examples described herein include a single-ended LC VCO stage containing a differential output with reduced parasitic impedance and increased LC resonant circuit impedance relative to other LC VCOs described herein. The examples also include one or more mirror stages (sometimes referred to as one or more peripheral stages) that can be coupled to a single-ended LC-VCO stage (sometimes referred to as the main stage) to provide in-phase and out-of-phase current injection. For example, current can be injected into one or more LC resonant circuits in one or more peripheral stages, wherein one or more LC resonant circuits are coupled to the LC resonant circuit of the main stage via at least one of mutual inductance or mutual capacitance. Therefore, the inductance of the LC VCO can be tuned by changing the polarity of the injected current. Accordingly, the tuning capability of the LC VCO is extended to both the tuning inductance and capacitance.

[0029] In the examples described herein, the LC resonant circuit does not contain any switches connected in series with the inductor of the LC resonant circuit. Therefore, the examples described herein do not affect the quality factor of the LC resonant circuit. Moreover, because the example LCVCO described herein contains a single differential output, multiplexing is not required at the output of the described LC VCO. Therefore, the performance of the clock signal generated by the example LC VCO described herein is improved, at least in terms of reducing duty cycle distortion and reducing jitter associated with power supply noise.

[0030] Figure 1 This is a schematic diagram of an example inductor-capacitor (LC) voltage-controlled oscillator (VCO) 100. Figure 1 In this example, the LC VCO 100 includes an example inverter 102, a first example transistor 104, a second example transistor 106, an example inductor-capacitor (LC) resonant circuit 108, a third example transistor 110, a fourth example transistor 112, and an example buffer 114. Furthermore, the example LC resonant circuit 108 includes an example inductor 116 and an example capacitor 118. Figure 1 In this example, the LC VCO 100 also includes an example power supply terminal 120, an example ground terminal 122, an example enable terminal 124, and an example clock terminal 126. In some examples, the power supply terminal 120 is referred to as V... DD Or at least one of the voltage terminals, and ground terminal 122 is referred to as GND or at least one of the voltage terminals.

[0031] exist Figure 1 In the example shown, inverter 102 has inputs and outputs. Figure 1In examples, each of transistors 104, 106, 110, and 112 has a control terminal, a first terminal, and a second terminal. In some examples, the control terminal, first terminal, and second terminal of the transistor are referred to as the gate terminal, source terminal, and drain terminal of the transistor, respectively. Furthermore, each of the LC resonant circuit 108, inductor 116, and capacitor 118 has a first terminal and a second terminal. Figure 1 In this example, buffer 114 has a first input, a second input, and an output.

[0032] exist Figure 1 In the example shown, inverter 102 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In this example, the input of inverter 102 is coupled to enable terminal 124. Furthermore, the output of inverter 102 is coupled to the control terminal of transistor 104.

[0033] exist Figure 1 In the example shown, transistor 104 is implemented using a PMOS transistor. Figure 1 In this example, the control terminal of transistor 104 is coupled to the output of inverter 102, the first terminal of transistor 104 is coupled to power supply terminal 120, and the second terminal of transistor 104 is coupled to the first terminal of transistor 106. Furthermore, in Figure 1 In this example, transistor 106 is implemented using a PMOS transistor. Figure 1 In one example, the control terminal of transistor 106 is coupled to the second terminal of LC resonant circuit 108, the first terminal of transistor 106 is coupled to the second terminal of transistor 104, and the second terminal of transistor 106 is coupled to the first terminal of LC resonant circuit 108.

[0034] exist Figure 1 In the example shown, the first terminal of the LC resonant circuit 108 is implemented by the first terminal of the inductor 116 and the first terminal of the capacitor 118. Furthermore, the second terminal of the LC resonant circuit 108 is implemented by the second terminal of the inductor 116 and the second terminal of the capacitor 118. Figure 1 In this example, the first terminal of the LC resonant circuit 108 is coupled to the second terminal of the transistor 106, the control terminal of the transistor 110, and the first input of the buffer 114. Furthermore, the second terminal of the LC resonant circuit 108 is coupled to the control terminal of the transistor 106, the second terminal of the transistor 110, and the second input of the buffer 114.

[0035] exist Figure 1In the example shown, the first terminal of inductor 116 is coupled to the second terminal of transistor 106, the control terminal of transistor 110, the first input of buffer 114, and the first terminal of capacitor 118. Furthermore, the second terminal of inductor 116 is coupled to the control terminal of transistor 106, the second terminal of transistor 110, the second input of buffer 114, and the second terminal of capacitor 118. Figure 1 In this example, capacitor 118 is a tunable capacitor. To tune the capacitance of capacitor 118, two or more capacitors are coupled in parallel to implement capacitor 118, and a switch is placed in series with each of the two or more capacitors.

[0036] Therefore, one or more of the switches can be turned on or off to increase or decrease the capacitance of capacitor 118. Figure 1 In this example, the first terminal of capacitor 118 is coupled to the second terminal of transistor 106, the control terminal of transistor 110, the first input of buffer 114, and the first terminal of inductor 116. Furthermore, the second terminal of capacitor 118 is coupled to the control terminal of transistor 106, the second terminal of transistor 110, the second input of buffer 114, and the second terminal of inductor 116.

[0037] exist Figure 1 In the example shown, transistor 110 is implemented using an NMOS transistor. Figure 1 In this example, the control terminal of transistor 110 is coupled to the first terminal of LC resonant circuit 108, the first terminal of transistor 110 is coupled to the second terminal of transistor 112, and the second terminal of transistor 110 is coupled to the second terminal of LC resonant circuit 108. Furthermore, in Figure 1 In this example, transistor 112 is implemented using an NMOS transistor. Figure 1 In the example, the control terminal of transistor 112 is coupled to the enable terminal 124, the first terminal of transistor 112 is coupled to the ground terminal 122, and the second terminal of transistor 112 is coupled to the first terminal of transistor 110.

[0038] exist Figure 1 In the example shown, buffer 114 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In this example, the first input of buffer 114 is coupled to the first terminal of LC resonant circuit 108, and the second input of buffer 114 is coupled to the second terminal of LC resonant circuit 108. Furthermore, the output of buffer 114 is coupled to clock terminal 126.

[0039] In example operation, the LC VCO 100 operates in response to an enable signal at enable terminal 124. For example, the LC resonant circuit 108 generates or is about to generate an oscillation signal in response to the enable signal at enable terminal 124. Figure 1 In this example, the enable signal is a binary signal. In response to a logic value of one at enable terminal 124, LC VCO 100 is enabled, and LC VCO 100 generates a clock signal at clock terminal 126. Furthermore, in response to a logic value of zero at enable terminal 124, LC VCO 100 is disabled, and LC VCO 100 does not generate a clock signal at clock terminal 126. In some examples, a logic value of one refers to at least one of the value "1", a logic high value, or a 5-volt (V) signal. Furthermore, in some examples, a logic value of zero refers to at least one of the value "0", a logic low value, or a 0V signal.

[0040] exist Figure 1 In the example shown, when the LC VCO 100 is enabled, the LC resonant circuit 108 generates a differential output signal V. OUT It oscillates at the resonant frequency of the LC resonant circuit 108. For example, the differential output signal V OUT At the first terminal of the LC resonant circuit 108 (also known as V) OUT+ ) and the second terminal (also known as V) of the LC resonant circuit 108 OUT- ) measured between ) . In Figure 1 In this example, buffer 114 buffers the differential output signal V from LC resonant circuit 108. OUT And in response to the differential output signal V OUT A clock signal is provided at clock terminal 126. For example, the clock signal generated at clock terminal 126 has a differential output signal V from LC resonant circuit 108. OUT Same frequency.

[0041] exist Figure 1 In the example shown, LC VCO 100 is a low-overhead LC VCO compared to other LC VCOs. For example, LCVCO 100 contains fewer components than other LC VCOs. Figure 1 In this example, the LC VCO 100 includes two transistors cross-coupled to the LC resonant circuit 108. For example, transistors 106 and 110 are cross-coupled to the LC resonant circuit 108. Furthermore, the terminals of transistors 106 and 110 that are cross-coupled to the LC resonant circuit 108 serve as the differential output of the LC resonant circuit 108. Therefore, compared to other LC VCOs, the LC VCO 100 provides improved common-mode noise suppression.

[0042] exist Figure 1In the example shown, compared to other LC VCOs, by reducing the number of transistors coupled across the LC resonant circuit, for example from four to two, the parasitic capacitance generated in LC VCO 100 is reduced by half compared to other LC VCOs. Therefore, inductor 116 can have a larger inductance compared to other LC VCOs, while achieving the target resonant frequency of LC resonant circuit 108. This also increases the characteristic impedance of LC resonant circuit 108. As a result, compared to other LC VCOs, the amount of power required to start up the LC VCO 100 and maintain the amplitude of the clock signal generated by the LC VCO 100, or the current required to maintain a constant supply voltage, is reduced. Furthermore, the efficiency of the LC VCO 100 is also improved due to the reduction in parasitic capacitance generated within the LC VCO 100.

[0043] exist Figure 1 In the example shown, transistors 104 and 106 are p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 104 and 106 can be p-channel field-effect transistors (FETs), p-channel insulated-gate bipolar transistors (IGBTs), p-channel junction field-effect transistors (JFETs), positive-negative-positive (PNP) bipolar junction transistors (BJTs), or slightly modified n-type equivalents. Figure 1 In the example, transistors 110 and 112 are n-channel MOSFETs. Alternatively, transistors 110 and 112 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Transistors 104, 106, 110, and 112 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 104, 106, 110, and 112 can be implemented in or on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0044] Figure 2 It is a description Figure 1 The first example oscillation signal 204 (also known as V) at the first terminal of the LC resonant circuit 108 OUT+ ) and the second example oscillation signal 206 at the second terminal (also known as V) OUT- The first example figure 202 and the depiction from Figure 1 Example differential output signal 210 (also known as V) of LC resonant circuit 108 OUT The second example figure 208 is a graphical description. Figure 2In the example, Figure 202 depicts voltage V in volts. OUT+ and V OUT- The relationship with time measured in nanoseconds (ns). Additionally, in Figure 2 In this example, Figure 208 depicts the voltage V from the LC resonant circuit 108 in volts. OUT The relationship with time measured in nanoseconds.

[0045] Figure 3 This is a schematic diagram of a sample LC VCO 300, including a sample main core 302 and a sample peripheral core 304. Figure 3 In this example, the LC VCO 300 also includes a first example inverter 306, a second example inverter 308, and an example buffer 310. Figure 3 In this example, the main core 302 (also referred to as the first core) includes a first example transistor 312, a second example transistor 314, a first example inductor-capacitor (LC) resonant circuit 316, a third example transistor 318, and a fourth example transistor 320. Furthermore, the example LC resonant circuit 316 includes a first example inductor 322 and a first example capacitor 324.

[0046] exist Figure 3 In the example shown, the peripheral core 304 (also referred to as the second core) includes a fifth example transistor 326, a sixth example transistor 328, a second example LC resonant circuit 330, a seventh example transistor 332, an eighth example transistor 334, a ninth example transistor 336, a tenth example transistor 338, an eleventh example transistor 340, and a twelfth example transistor 342. Figure 3 In one example, the example LC resonant circuit 330 includes a second example inductor 344 and a second example capacitor 346. Furthermore, in Figure 3 In this example, the LC VCO 300 includes an example power supply terminal 348, an example ground terminal 350, an example enable terminal 352, an example clock terminal 354, and an example tuning terminal 356. In some examples, the power supply terminal 348 is referred to as V... DD Or at least one of the voltage terminals, and ground terminal 350 is referred to as GND or at least one of the voltage terminals.

[0047] exist Figure 3 In the example shown, the main core 302 has a first voltage terminal, a second voltage terminal, a first control terminal, a second control terminal, a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. Figure 3 In this example, the peripheral core 304 has a first voltage terminal, a second voltage terminal, a first control terminal, a second control terminal, a first input, a second input, a third input, and a fourth input. Furthermore, in... Figure 3 In the example, each of inverters 306 and 308 has an input and an output.

[0048] exist Figure 3 In the examples shown, each of transistors 312, 314, 318, 320, 326, 328, 332, 334, 336, 338, 340, and 342 has a control terminal, a first terminal, and a second terminal. In some examples, the control terminal, first terminal, and second terminal of the transistor are referred to as the gate terminal, source terminal, and drain terminal of the transistor, respectively. Furthermore, each of the LC resonant circuit 316, inductor 322, capacitor 324, LC resonant circuit 330, inductor 344, and capacitor 346 has a first terminal and a second terminal. Figure 3 In this example, buffer 310 has a first input, a second input, and an output.

[0049] exist Figure 3 In the example shown, the first terminal of transistor 312 serves as the first voltage terminal of the main core 302, and the first terminal of transistor 320 serves as the second voltage terminal of the main core 302. Furthermore, the control terminal of transistor 312 serves as the first control terminal of the main core 302, and the control terminal of transistor 320 serves as the second control terminal of the main core 302. Figure 3 In the example, the first terminal of the LC resonant circuit 316 is used as the first output, fourth output and sixth output of the main core 302, and the second terminal of the LC resonant circuit 316 is used as the second output, third output and fifth output of the main core 302.

[0050] exist Figure 3 In the example shown, the first terminals of transistor 326 and transistor 336 serve as the first voltage terminals of the peripheral core 304. Figure 3 In this example, the first terminal of transistor 334 and the first terminal of transistor 342 serve as the second voltage terminals of the peripheral core 304. Furthermore, the control terminals of transistor 326 and transistor 342 serve as the first control terminals of the peripheral core 304.

[0051] exist Figure 3 In the example shown, the control terminals of transistor 334 and transistor 336 serve as second control terminals for the peripheral core 304. Figure 3In this example, the control terminal of transistor 338 is used as the first input of peripheral core 304, and the control terminal of transistor 328 is used as the second input of peripheral core 304. Furthermore, the control terminal of transistor 332 is used as the third input of peripheral core 304, and the control terminal of transistor 340 is used as the fourth input of peripheral core 304.

[0052] exist Figure 3 In the example shown, the first voltage terminal of the main core 302 and the first voltage terminal of the peripheral core 304 are coupled to the power supply terminal 348. Figure 3 In this example, the second voltage terminal of the main core 302 and the second voltage terminal of the peripheral core 304 are coupled to the ground terminal 350. Furthermore, the first control terminal of the main core 302 is coupled to the output of the inverter 306, and the second control terminal of the main core 302 is coupled to the enable terminal 352.

[0053] exist Figure 3 In the example shown, the first control terminal of the peripheral core 304 is coupled to the output of the inverter 308, and the second control terminal of the peripheral core 304 is coupled to the tuning terminal 356. Figure 3 In this example, the first output of the main core 302 is coupled to the first input of the buffer 310, and the second output of the main core 302 is coupled to the second input of the buffer 310. Furthermore, the third output of the main core 302 is coupled to the first input of the peripheral core 304, the fourth output of the main core 302 is coupled to the second input of the peripheral core 304, the fifth output of the main core 302 is coupled to the third input of the peripheral core 304, and the sixth output of the main core 302 is coupled to the fourth input of the peripheral core 304.

[0054] exist Figure 3 In the example shown, inverter 306, buffer 310, transistor 312, transistor 314, LC resonant circuit 316 including inductor 322 and capacitor 324, transistor 318, transistor 320, power supply terminal 348, ground terminal 350, enable terminal 352 and clock terminal 354 are connected to... Figure 1 The components of the LC VCO 100 are implemented and coupled in a similar manner, unless otherwise stated. Figure 3 In this example, inverter 308 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 3 In this example, the input of inverter 308 is coupled to tuning terminal 356, and the output of inverter 308 is coupled to the control terminals of transistor 326 and transistor 342.

[0055] exist Figure 3 In the example shown, transistor 326 is implemented using a PMOS transistor. Figure 3In this example, the control terminal of transistor 326 is coupled to the output of inverter 308, the first terminal of transistor 326 is coupled to power supply terminal 348, and the second terminal of transistor 326 is coupled to the first terminal of transistor 328. Furthermore, in Figure 3 In this example, transistor 328 is implemented using a PMOS transistor. Figure 3 In one example, the control terminal of transistor 328 is coupled to the first terminal of LC resonant circuit 316, the first terminal of transistor 328 is coupled to the second terminal of transistor 326, and the second terminal of transistor 328 is coupled to the first terminal of LC resonant circuit 330.

[0056] exist Figure 3 In the example shown, transistor 336 is implemented using a PMOS transistor. Figure 3 In this example, the control terminal of transistor 336 is coupled to the tuning terminal 356, the first terminal of transistor 336 is coupled to the power supply terminal 348, and the second terminal of transistor 336 is coupled to the first terminal of transistor 338. Furthermore, in Figure 3 In this example, transistor 338 is implemented using a PMOS transistor. Figure 3 In one example, the control terminal of transistor 338 is coupled to the second terminal of LC resonant circuit 316, the first terminal of transistor 338 is coupled to the second terminal of transistor 336, and the second terminal of transistor 338 is coupled to the first terminal of LC resonant circuit 330.

[0057] exist Figure 3 In the example shown, the first terminal of the LC resonant circuit 330 is implemented by the first terminal of the inductor 344 and the first terminal of the capacitor 346. Furthermore, the second terminal of the LC resonant circuit 330 is implemented by the second terminal of the inductor 344 and the second terminal of the capacitor 346. Figure 3 In this example, the first terminal of the LC resonant circuit 330 is coupled to the second terminals of transistors 328 and 338. Furthermore, the second terminal of the LC resonant circuit 330 is coupled to the second terminals of transistors 332 and 340.

[0058] exist Figure 3 In the example shown, the first terminal of inductor 344 is coupled to the second terminals of transistor 328, transistor 338, and capacitor 346. Furthermore, the second terminal of inductor 344 is coupled to the second terminals of transistor 332, transistor 340, and capacitor 346. Figure 3In this example, capacitor 346 is a tunable capacitor. To tune the capacitance of capacitor 346, two or more capacitors are coupled in parallel to implement capacitor 346, and a switch is placed in series with each of the two or more capacitors.

[0059] Therefore, one or more of the switches can be turned on or off to increase or decrease the capacitance of capacitor 346. Figure 3 In this example, the first terminal of capacitor 346 is coupled to the second terminal of transistor 328, the second terminal of transistor 338, and the first terminal of inductor 344. Furthermore, the second terminal of capacitor 346 is coupled to the second terminal of transistor 332, the second terminal of transistor 340, and the second terminal of inductor 344.

[0060] exist Figure 3 In the example shown, transistor 332 is implemented using an NMOS transistor. Figure 3 In this example, the control terminal of transistor 332 is coupled to the second terminal of LC resonant circuit 316, the first terminal of transistor 332 is coupled to the second terminal of transistor 334, and the second terminal of transistor 332 is coupled to the second terminal of LC resonant circuit 330. Furthermore, in Figure 3 In this example, transistor 334 is implemented using an NMOS transistor. Figure 3 In this example, the control terminal of transistor 334 is coupled to the tuning terminal 356, the first terminal of transistor 334 is coupled to the ground terminal 350, and the second terminal of transistor 334 is coupled to the first terminal of transistor 332.

[0061] exist Figure 3 In the example shown, transistor 340 is implemented using an NMOS transistor. Figure 3 In this example, the control terminal of transistor 340 is coupled to the first terminal of LC resonant circuit 316, the first terminal of transistor 340 is coupled to the second terminal of transistor 342, and the second terminal of transistor 340 is coupled to the second terminal of LC resonant circuit 330. Furthermore, in Figure 3 In this example, transistor 342 is implemented using an NMOS transistor. Figure 3 In this example, the control terminal of transistor 342 is coupled to the output of inverter 308, the first terminal of transistor 342 is coupled to ground terminal 350, and the second terminal of transistor 342 is coupled to the first terminal of transistor 340.

[0062] In example operation, the LC VCO 300 operates in response to an enable signal at enable terminal 352 and a tuning signal at tuning terminal 356. For example, the LC resonant circuit 316 generates or is about to generate an oscillation signal in response to the enable signal at enable terminal 352. Figure 3In this example, the enable signal is a binary signal. In response to a logic value of one at enable terminal 352, LC VCO 300 is enabled, and LC VCO 300 generates a clock signal at clock terminal 354. Furthermore, in response to a logic value of zero at enable terminal 352, LC VCO 300 is disabled, and LC VCO 300 does not generate a clock signal at clock terminal 354. In some examples, a logic value of one refers to at least one of the value "1", a logic high value, or a 5-volt (V) signal. Furthermore, in some examples, a logic value of zero refers to at least one of the value "0", a logic low value, or a 0V signal.

[0063] exist Figure 3 In the example shown, inductor 322 is coupled to inductor 344 via mutual inductance. For example, the magnetic field generated by the current flowing through inductor 344 induces a voltage across inductor 322, and vice versa. Figure 3 In this example, the mutual inductance between inductor 322 and inductor 344 is based on the coupling factor K. For example, the larger the coupling factor K, the greater the influence of the current flowing through inductor 344 on the current flowing through inductor 322. The mutual inductance M between inductor 322 and inductor 344 can be calculated as the product of the following two items: (a) the coupling factor K and (b) the square root of the product of the inductance L1 of inductor 322 and the inductance L2 of inductor 344. .

[0064] As described herein, the LC VCO 300 operates in response to an enable signal at enable terminal 352 and a tuning signal at tuning terminal 356. For example, the LC resonant circuit 330 generates or is about to generate an oscillation signal in response to the tuning signal (also referred to as a control signal) at tuning terminal 356. Figure 3 In this example, the tuning signal is a binary signal. In response to a logic value of one at tuning terminal 356, transistor 326 is enabled, transistor 336 is disabled, transistor 334 is enabled, and transistor 342 is disabled. For example, the transistor is enabled when it conducts current, and disabled when it does not conduct current.

[0065] Therefore, in response to the differential output signal V from the LC resonant circuit 316 OUT The current in the peripheral core 304 flows from the power supply terminal 348 to the ground terminal 350 through transistors 326, 328, LC resonant circuit 330, 332, and 334. For example... Figure 3 As shown, the control terminal of transistor 314 is coupled to the second terminal of LC resonant circuit 316, and the control terminal of transistor 328 is coupled to the first terminal of LC resonant circuit 316. Furthermore, as... Figure 3As shown, the control terminal of transistor 318 is coupled to the first terminal of LC resonant circuit 316, and the control terminal of transistor 332 is coupled to the second terminal of LC resonant circuit 316.

[0066] Because the control terminals of transistors 328 and 332 are coupled to the LC resonant circuit 316 in the opposite manner to those of transistors 314 and 318, the peripheral core 304 injects current into the LC resonant circuit 330 at a different time than the main core 302 injects current into the LC resonant circuit 316. Therefore, when the tuning signal at tuning terminal 356 has a logic value of one, the LC resonant circuit 330 generates an oscillation signal (e.g., current) that is out of phase with the oscillation signal (e.g., current) generated by the LC resonant circuit 316. Consequently, the total inductance of the LC VCO 300 is reduced due to the negative mutual inductance between inductor 344 and inductor 322.

[0067] exist Figure 3 In the example shown, in response to a logic value of zero at tuning terminal 356, transistor 326 is disabled, transistor 336 is enabled, transistor 334 is disabled, and transistor 342 is enabled. Therefore, in response to the differential output signal V from the LC resonant circuit 316... OUT The current in the peripheral core 304 flows from the power supply terminal 348 to the ground terminal 350 through transistors 336, 338, LC resonant circuit 330, 340, and 342. For example... Figure 3 As shown, the control terminal of transistor 314 is coupled to the second terminal of LC resonant circuit 316, and the control terminal of transistor 338 is also coupled to the second terminal of LC resonant circuit 316. Furthermore, as... Figure 3 As shown, the control terminal of transistor 318 is coupled to the first terminal of LC resonant circuit 316, and the control terminal of transistor 340 is coupled to the first terminal of LC resonant circuit 316.

[0068] Because the control terminals of transistors 338 and 340 are coupled to the LC resonant circuit 316 in the same manner as the control terminals of transistors 314 and 318, the peripheral core 304 injects current into the LC resonant circuit 330 at a similar time as the main core 302 injects current into the LC resonant circuit 316. Therefore, when the tuning signal at tuning terminal 356 has a logic value of zero, the LC resonant circuit 330 generates an oscillating signal (e.g., current) in phase with the oscillating signal (e.g., current) generated by the LC resonant circuit 316. Consequently, the total inductance of the LC VCO 300 increases due to the positive mutual inductance between inductor 344 and inductor 322.

[0069] like Figure 3As shown, the inductance of the LC VCO 300 can be tuned without utilizing the switches in the LC resonant circuits 316 and 330. Instead, the inductance of the LC VCO 300 is tuned using phase control switches external to the LC resonant circuits 316 and 330, such as transistors 326, 334, 336, and 342. This allows for tuning not only the capacitance of the LC VCO 300 but also its inductance without affecting the quality factor of the LC resonant circuits 316 and 330. Therefore, compared to other LC VCOs, the operating frequency range of the LC VCO 300 can be increased while reducing its area and power consumption.

[0070] exist Figure 3 In the example shown, transistors 312, 314, 326, 328, 336, and 338 are p-channel MOSFETs. Alternatively, transistors 312, 314, 326, 328, 336, and 338 can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified n-type equivalents. Figure 3 In the examples, transistors 318, 320, 332, 334, 340, and 342 are n-channel MOSFETs. Alternatively, transistors 318, 320, 332, 334, 340, and 342 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Transistors 312, 314, 318, 320, 326, 328, 332, 334, 336, 338, 340, and 342 can be depletion-mode devices, extended-drain devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 312, 314, 318, 320, 326, 328, 332, 334, 336, 338, 340, and 342 can be implemented in or on a Si substrate, a SiC substrate, a GaN substrate, or a GaAs substrate.

[0071] Figure 4A yes Figure 3 A schematic diagram of the LC VCO 300, wherein the inductor 344 of the peripheral core 304 is physically nested within the inductor 322 of the main core 302. Figure 4AIn this example, inductor 344 is located within the coverage area of ​​inductor 322. For instance, inductor 344 is located within the internal region of inductor 322. Figure 4A In this example, inductor 344 is physically nested within inductor 322 to satisfy the target coupling coefficient K. By satisfying the target coupling coefficient K, the LC VCO 300 satisfies the target operating frequency range and the target spacing between frequency bands within the target operating frequency range.

[0072] Furthermore, by physically nesting inductor 344 within inductor 322, LC VCO 300 occupies a smaller area on the chip compared to other LC VCOs, while achieving a wide operating frequency range. For example, by physically nesting inductor 344 within inductor 322, LC VCO 300 occupies approximately the same amount of area on the chip as a single LC VCO, while providing an operating frequency range comparable to that of two LC VCOs containing multiplexed outputs. In this way, the examples described herein include single-stage multi-band hybrid LC VCOs tunable in response to polarity-controlled phase injection.

[0073] Figure 4B This is a top view of the inductor 322 of the main core 302 and the inductor 344 of the peripheral core 304. Figure 4C This is a cross-sectional side view of the inductor 322 of the main core 302 and the inductor 344 of the peripheral core 304. Figure 4B Top view and Figure 4C The cross-sectional side view shows how inductors 322 and 344 are implemented in the substrate. (See diagram below.) Figure 4C As shown, inductors 322 and 344 are at least one of the following: residing in, located in, or disposed in an example metal layer 402 of the substrate. For example, metal layer 402 may be made of a metal comprising at least one of copper or aluminum. Furthermore, as... Figure 4C As shown, metal layer 402 is located beneath example capping layer 404. For example, capping layer 404 may be made of a metal comprising at least one of tungsten, titanium, titanium nitride, cobalt, platinum, gold, nickel, aluminum, copper, or ruthenium.

[0074] Figure 5 It is a description Figure 3 A graphical illustration of 500 showing the operating frequency variation of the LC VCO 300 in response to the value of the tuning signal and the coupling factor K between inductors 322 and 344. Figure 5 In the example, Figure 500 depicts the differential output voltage signal V in gigahertz (GHz) units. OUT The relationship between the oscillation frequency and the value of the tuning signal (e.g., between zero and one). Figure 5 In the example, graphic 500 corresponds to Figure 3The LC VCO 300 includes an inductor 322 with an inductance of 500 picohens (pH), a capacitor 324 with a capacitance of one picofarad (pF), and an LC resonant circuit 316 with a capacitance of 350 milliohms. The resistor 344 has an inductance of 300 pH, the capacitor 346 has a capacitance of 2 pF, and the LC resonant circuit 330 has a capacitance of 230 pF. The resistance.

[0075] exist Figure 5 In the example shown, graph 500 includes a first example curve 502, which corresponds to an LC VCO 300 with a zero coupling factor K (K = 0.00) between inductor 322 and inductor 344. Figure 5 In this example, by switching the tuning signal between zero and one, the user of the LC VCO 300 can switch the frequency of the clock signal generated by the LC VCO 300 between lower and higher values, respectively. Therefore, the frequency of the oscillation signal generated by the LC resonant circuit 316 is adjusted based on the coupling factor K between inductors 322 and 344 and the value of the tuning signal at tuning terminal 356. In the example of curve 502, the frequency of the clock signal generated by the LC VCO 300 is 6.4 GHz, and it does not change when the tuning signal is switched between zero and one because the coupling factor K is zero.

[0076] exist Figure 5 In the example shown, graph 500 includes a second example curve 504, which corresponds to an LC VCO 300 with a coupling factor K of 0.15 (K = 0.15) between inductors 322 and 344. In the example of curve 504, the frequency of the clock signal generated by the LC VCO 300 varies between 5.93 GHz and 6.97 GHz when the tuning signal switches between zero and one. Therefore, based on the coupling factor K between inductors 322 and 344, when the value of the tuning signal at tuning terminal 356 is one, the oscillation signal generated by LC resonant circuit 330 increases the frequency of the oscillation signal generated by LC resonant circuit 316. Furthermore, based on the coupling factor K between inductors 322 and 344, when the value of the tuning signal at tuning terminal 356 is zero, the oscillation signal generated by LC resonant circuit 330 decreases the frequency of the oscillation signal generated by LC resonant circuit 316.

[0077] exist Figure 5In the example shown, graph 500 includes a third example curve 506, which corresponds to an LC VCO 300 with a coupling factor K of 0.20 (K = 0.20) between inductors 322 and 344. In the example of curve 506, the frequency of the clock signal generated by the LC VCO 300 varies between 5.8 GHz and 7.2 GHz when the tuning signal switches between zero and one. Figure 5 In the example, Figure 500 includes a fourth example curve 508, which corresponds to an LC VCO 300 having a coupling factor K of 0.25 (K = 0.25) between inductors 322 and 344. In the example of curve 508, the frequency of the clock signal generated by the LC VCO 300 varies between 5.7 GHz and 7.4 GHz as the tuning signal switches between zero and one.

[0078] exist Figure 5 In the example shown, graph 500 includes a fifth example curve 510, which corresponds to an LC VCO 300 with a coupling factor K of 0.30 (K = 0.30) between inductors 322 and 344. In the example of curve 510, the frequency of the clock signal generated by the LC VCO 300 varies between 5.6 GHz and 7.7 GHz when the tuning signal switches between zero and one. Figure 5 In the example, Figure 500 includes a sixth example curve 512, which corresponds to an LC VCO 300 having a coupling factor K of 0.35 (K = 0.35) between inductors 322 and 344. In the example of curve 512, the frequency of the clock signal generated by the LC VCO 300 varies between 5.47 GHz and 7.95 GHz as the tuning signal switches between zero and one.

[0079] exist Figure 5 In the example shown, graph 500 includes a seventh example curve 514, which corresponds to an LC VCO 300 with a coupling factor K of 0.40 (K = 0.40) between inductors 322 and 344. In the example of curve 514, the frequency of the clock signal generated by the LC VCO 300 varies between 5.4 GHz and 8.3 GHz as the tuning signal switches between zero and one. Figure 5 As shown, when the coupling factor K between inductor 322 and inductor 344 increases, the tuning range of LC VCO 300 increases.

[0080] exist Figure 5In the example shown, by setting the tuning signal to zero, the user can set the frequency of the clock signal generated by the LC VCO 300 to the lower limit of the tuning range. Furthermore, by setting the tuning signal to one, the user can set the frequency of the clock signal generated by the LC VCO 300 to the upper limit of the tuning range. Once the user has set the frequency of the clock signal generated by the LC VCO 300 via inductor tuning, the user can further tune the frequency of the clock signal by tuning one or more of the capacitors 324 or 346.

[0081] Figure 6 This is a graphic illustration depicting a first example graph 602 showing a first example oscillation signal 604 in LC resonant circuit 316 and a second example oscillation signal 606 in LC resonant circuit 330 when the tuning signal has a value of zero, and a second example graph 608 showing an oscillation signal 604 in LC resonant circuit 316 and an oscillation signal 606 in LC resonant circuit 330 when the tuning signal has a value of one. Figure 6 In the examples, Figures 602 and 608 depict the relationship between voltage in volts and time in nanoseconds (ns). Figure 6 As shown, when the value of the tuning signal is zero, the oscillation signal 606 is in phase with the oscillation signal 604, and when the value of the tuning signal is one, the oscillation signal 606 is out of phase with the oscillation signal 604. In other words, when the tuning signal has a value of zero, the LC resonant circuit 330 generates an oscillation signal in phase with the oscillation signal generated by the LC resonant circuit 316, and when the tuning signal has a value of one, the LC resonant circuit 330 generates an oscillation signal out of phase with the oscillation signal generated by the LC resonant circuit 316. Furthermore, as... Figure 6 As shown, when the value of the tuning signal is zero, the frequency V of the differential output signal is... OUT The frequency V of the differential output signal is 5.76 GHz, and when the value of the tuning signal is one, the frequency V of the differential output signal is... OUT It is 7.097 GHz.

[0082] Figure 7 shows a diagram containing the example main core 702 and N example peripheral cores 7041-704. N A schematic diagram of an example LC VCO 700 is shown in Figure 7. In the example of Figure 7, the LC VCO 700 also includes a first example inverter 706, a second example inverter 708, a third example inverter 710, and an example buffer 712. In the example of Figure 7, the main core 702 (also referred to as the first core) includes a first example transistor 714, a second example transistor 716, a first example inductor-capacitor (LC) resonant circuit 718, a third example transistor 720, and a fourth example transistor 722. Furthermore, the example LC resonant circuit 718 includes a first example inductor 724 and a first example capacitor 726.

[0083] In the example shown in Figure 7, the peripheral core 7041 (also referred to as the second core) includes a fifth example transistor 728, a sixth example transistor 730, a second example LC resonant circuit 732, a seventh example transistor 734, an eighth example transistor 736, a ninth example transistor 738, a tenth example transistor 740, an eleventh example transistor 742, and a twelfth example transistor 744. In the example of Figure 7, the example LC resonant circuit 732 includes a second example inductor 746 and a second example capacitor 748. Furthermore, the peripheral core 704... N Also known as the N+1th core, it includes a thirteenth example transistor 750, a fourteenth example transistor 752, a third example LC resonant circuit 754, a fifteenth example transistor 756, a sixteenth example transistor 758, a seventeenth example transistor 760, an eighteenth example transistor 762, a nineteenth example transistor 764, and a twentieth example transistor 766. In the example of Figure 7, the example LC resonant circuit 754 includes a third example inductor 768 and a third example capacitor 770.

[0084] In the example shown in Figure 7, the LC VCO 700 includes an example power terminal 772, an example ground terminal 774, an example enable terminal 776, an example clock terminal 778, and N example tuning terminals 7801-780. N In some instances, power terminal 772 is referred to as V. DD Or at least one of the voltage terminals, and ground terminal 774 is referred to as GND or at least one of the voltage terminals. In the example of FIG7, the main core 702 has a first voltage terminal, a second voltage terminal, a first control terminal, a second control terminal, a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. In the example of FIG7, the peripheral core 7041 has a first voltage terminal, a second voltage terminal, a first control terminal, a second control terminal, a first input, a second input, a third input, a fourth input, a first output, a second output, a third output, and a fourth output. In addition, peripheral core 704 N It has a first voltage terminal, a second voltage terminal, a first control terminal, a second control terminal, a first input, a second input, a third input, and a fourth input.

[0085] In the example shown in Figure 7, each of inverters 706, 708, and 710 has an input and an output. In the example of Figure 7, each of transistors 714, 716, 720, 722, 728, 730, 734, 736, 738, 740, 742, 744, 750, 752, 756, 758, 760, 762, 764, and 766 has a control terminal, a first terminal, and a second terminal. In some examples, the control terminal, first terminal, and second terminal of a transistor are referred to as the gate terminal, source terminal, and drain terminal of the transistor, respectively. Furthermore, each of LC resonant circuits 718, 724, 726, 732, 746, 748, 754, 768, and 770 has a first terminal and a second terminal. In the example of Figure 7, buffer 712 has a first input, a second input, and an output.

[0086] In the example shown in Figure 7, the first terminal of transistor 714 serves as the first voltage terminal of the main core 702, and the first terminal of transistor 722 serves as the second voltage terminal of the main core 702. Furthermore, the control terminal of transistor 714 serves as the first control terminal of the main core 702, and the control terminal of transistor 722 serves as the second control terminal of the main core 702. In the example of Figure 7, the first terminal of LC resonant circuit 718 serves as the first, fourth, and sixth outputs of the main core 702, and the second terminal of LC resonant circuit 718 serves as the second, third, and fifth outputs of the main core 702.

[0087] In the example shown in Figure 7, the first terminals of transistors 728 and 738 serve as the first voltage terminals of the peripheral core 7041. In the example of Figure 7, the first terminals of transistors 736 and 744 serve as the second voltage terminals of the peripheral core 7041. Furthermore, the control terminals of transistors 728 and 744 serve as the first control terminals of the peripheral core 7041. In the example of Figure 7, the control terminals of transistors 736 and 738 serve as the second control terminals of the peripheral core 7041.

[0088] In the example shown in Figure 7, the control terminal of transistor 740 serves as the first input and first output of peripheral core 7041. In the example of Figure 7, the control terminal of transistor 730 serves as the second input and second output of peripheral core 7041. Furthermore, the control terminal of transistor 734 serves as the third input and third output of peripheral core 7041. In the example of Figure 7, the control terminal of transistor 742 serves as the fourth input and fourth output of peripheral core 7041.

[0089] In the example shown in Figure 7, the first terminals of transistor 750 and transistor 760 serve as the peripheral core 704. N The first voltage terminal. In the example of Figure 7, the first terminals of transistor 758 and transistor 766 are used as the peripheral core 704. N The second voltage terminal. Furthermore, the control terminals of transistor 750 and transistor 766 serve as the peripheral core 704. N The first control terminal. In the example of Figure 7, the control terminals of transistor 758 and transistor 760 are used as peripheral core 704. N The second control terminal.

[0090] In the example shown in Figure 7, the control terminal of transistor 762 is used as the peripheral core 704. N The first input. In the example of Figure 7, the control terminal of transistor 752 is used as the peripheral core 704. N The second input. Furthermore, the control terminal of transistor 756 serves as the peripheral core 704. N The third input. In the example of Figure 7, the control terminal of transistor 764 is used as the peripheral core 704. N The fourth input.

[0091] In the example shown in Figure 7, the first voltage terminal of the main core 702, the first voltage terminal of the peripheral core 7041, and the peripheral core 704 N The first voltage terminal is coupled to the power supply terminal 772. In the example of Figure 7, the second voltage terminal of the main core 702, the second voltage terminal of the peripheral core 7041, and the peripheral core 704... N The second voltage terminal is coupled to the ground terminal 774. In addition, the first control terminal of the main core 702 is coupled to the output of the inverter 706, and the second control terminal of the main core 702 is coupled to the enable terminal 776.

[0092] In the example shown in Figure 7, the first control terminal of the peripheral core 7041 is coupled to the output of the inverter 708, and the second control terminal of the peripheral core 7041 is coupled to the tuning terminal 7801. In the example of Figure 7, the first output of the main core 702 is coupled to the first input of the buffer 712, and the second output of the main core 702 is coupled to the second input of the buffer 712. Furthermore, the third output of the main core 702 is coupled to the first input of the peripheral core 7041, the fourth output of the main core 702 is coupled to the second input of the peripheral core 7041, the fifth output of the main core 702 is coupled to the third input of the peripheral core 7041, and the sixth output of the main core 702 is coupled to the fourth input of the peripheral core 7041.

[0093] In the example shown in Figure 7, the outer core 704 N The first control terminal is coupled to the output of inverter 710, and the peripheral core 704 N The second control terminal is coupled to the tuning terminal 780. N In the example of Figure 7, the first output of peripheral core 7041 is coupled to peripheral core 704. N The first input, and the second output of the peripheral core 7041 is coupled to the peripheral core 704. N The second input. Furthermore, the third output of peripheral core 7041 is coupled to peripheral core 704. N The third input, and the fourth output of the peripheral core 7041 is coupled to the peripheral core 704. N The fourth input.

[0094] In the example shown in Figure 7, inverter 706, inverter 708, buffer 712, transistor 714, transistor 716, LC resonant circuit 718 including inductor 724 and capacitor 726, transistor 720, transistor 722, transistor 728, transistor 730, LC resonant circuit 732 including inductor 746 and capacitor 748, transistor 734, transistor 736, transistor 738, transistor 740, transistor 742, transistor 744, power supply terminal 772, ground terminal 774, enable terminal 776, clock terminal 778, and tuning terminal 7801 are connected to... Figure 3 The components of the LC VCO 300 are implemented and coupled in a similar manner, unless otherwise stated. In the example of Figure 7, the inverter 710 is implemented by at least one of an analog or digital circuit system. In the example of Figure 7, the input of the inverter 710 is coupled to the tuning terminal 780. N Furthermore, the output of inverter 710 is coupled to the control terminals of transistor 750 and transistor 766.

[0095] In the example shown in Figure 7, transistor 750 is implemented as a PMOS transistor. In this example, the control terminal of transistor 750 is coupled to the output of inverter 710, the first terminal of transistor 750 is coupled to power supply terminal 772, and the second terminal of transistor 750 is coupled to the first terminal of transistor 752. Furthermore, in this example, transistor 752 is implemented as a PMOS transistor. In this example, the control terminal of transistor 752 is coupled to the control terminal of transistor 730, the control terminal of transistor 730 is coupled to the first terminal of LC resonant circuit 718, the first terminal of transistor 752 is coupled to the second terminal of transistor 750, and the second terminal of transistor 752 is coupled to the first terminal of LC resonant circuit 754.

[0096] In the example shown in Figure 7, transistor 760 is implemented using a PMOS transistor. In the example of Figure 7, the control terminal of transistor 760 is coupled to the tuning terminal 780. N The first terminal of transistor 760 is coupled to power supply terminal 772, and the second terminal of transistor 760 is coupled to the first terminal of transistor 762. Furthermore, in the example of FIG. 7, transistor 762 is implemented as a PMOS transistor. In the example of FIG. 7, the control terminal of transistor 762 is coupled to the control terminal of transistor 740, the control terminal of transistor 740 is coupled to the second terminal of LC resonant circuit 718, the first terminal of transistor 762 is coupled to the second terminal of transistor 760, and the second terminal of transistor 762 is coupled to the first terminal of LC resonant circuit 754.

[0097] In the example shown in Figure 7, the first terminal of the LC resonant circuit 754 is implemented by the first terminal of the inductor 768 and the first terminal of the capacitor 770. Furthermore, the second terminal of the LC resonant circuit 754 is implemented by the second terminal of the inductor 768 and the second terminal of the capacitor 770. In the example of Figure 7, the first terminal of the LC resonant circuit 754 is coupled to the second terminals of transistors 752 and 762. Furthermore, the second terminal of the LC resonant circuit 754 is coupled to the second terminals of transistors 756 and 764.

[0098] In the example shown in Figure 7, the first terminal of inductor 768 is coupled to the second terminal of transistor 752, the second terminal of transistor 762, and the first terminal of capacitor 770. Furthermore, the second terminal of inductor 768 is coupled to the second terminals of transistor 756, transistor 764, and the second terminal of capacitor 770. In the example of Figure 7, capacitor 770 is a tunable capacitor. To tune the capacitance of capacitor 770, two or more capacitors are coupled in parallel to implement capacitor 770, and a switch is placed in series with each of the two or more capacitors.

[0099] Therefore, one or more of the switches can be switched on or off to increase or decrease the capacitance of capacitor 770. In the example of FIG. 7, the first terminal of capacitor 770 is coupled to the second terminal of transistor 752, the second terminal of transistor 762, and the first terminal of inductor 768. Furthermore, the second terminal of capacitor 770 is coupled to the second terminal of transistor 756, the second terminal of transistor 764, and the second terminal of inductor 768.

[0100] In the example shown in Figure 7, transistor 756 is implemented using an NMOS transistor. In this example, the control terminal of transistor 756 is coupled to the control terminal of transistor 734, the control terminal of transistor 734 is coupled to the second terminal of the LC resonant circuit 718, the first terminal of transistor 756 is coupled to the second terminal of transistor 758, and the second terminal of transistor 756 is coupled to the second terminal of the LC resonant circuit 754. Furthermore, in the example of Figure 7, transistor 758 is implemented using an NMOS transistor. In this example, the control terminal of transistor 758 is coupled to the tuning terminal 780. N The first terminal of transistor 758 is coupled to ground terminal 774, and the second terminal of transistor 758 is coupled to the first terminal of transistor 756.

[0101] In the example shown in Figure 7, transistor 764 is implemented as an NMOS transistor. In this example, the control terminal of transistor 764 is coupled to the control terminal of transistor 742, the control terminal of transistor 742 is coupled to the first terminal of LC resonant circuit 718, the first terminal of transistor 764 is coupled to the second terminal of transistor 766, and the second terminal of transistor 764 is coupled to the second terminal of LC resonant circuit 754. Furthermore, in the example of Figure 7, transistor 766 is implemented as an NMOS transistor. In this example, the control terminal of transistor 766 is coupled to the output of inverter 710, the first terminal of transistor 766 is coupled to ground terminal 774, and the second terminal of transistor 766 is coupled to the first terminal of transistor 764.

[0102] In the example operation, the LC VCO 700 responds to the enable signal at enable terminal 776 and tuning terminals 7801-780. N It operates based on N tuning signals at a given location. For example, the LC VCO 700 and... Figure 3 The LC VCO 300 operates similarly, but has N peripheral cores 7041-704. N Each outer core inductor has a corresponding coupling factor K1-K with the preceding core. N Therefore, by switching tuning terminals 7801-780... NThe tuning signal at the location allows the inductance of the LC VCO 700 to be tuned without utilizing the switches in the LC resonant circuit 718, LC resonant circuit 732, or LC resonant circuit 754.

[0103] In the example shown in Figure 7, transistors 714, 716, 728, 730, 738, 740, 750, 752, 760, and 762 are p-channel MOSFETs. Alternatively, transistors 714, 716, 728, 730, 738, 740, 750, 752, 760, and 762 can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified n-type equivalent devices. In the example of Figure 7, transistors 720, 722, 734, 736, 742, 744, 756, 758, 764, and 766 are n-channel MOSFETs. Alternatively, transistors 720, 722, 734, 736, 742, 744, 756, 758, 764, and 766 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Transistors 714, 716, 720, 722, 728, 730, 734, 736, 738, 740, 742, 744, 750, 752, 756, 758, 760, 762, 764, and 766 can be depletion-mode devices, extended-drain devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 714, 716, 720, 722, 728, 730, 734, 736, 738, 740, 742, 744, 750, 752, 756, 758, 760, 762, 764, and 766 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0104] Figure 8 is a schematic diagram of the LC VCO 700 shown in Figure 7, where there are two outer cores, and the outer cores are 704. NInductor 768 is physically nested within inductor 746 of peripheral core 7041, and inductor 746 of peripheral core 7041 is physically nested within inductor 724 of main core 702. In the example of FIG8, each of inductors 768, 746, and 724 is implemented by a high-layer multilayer inductor, such as by three or more layers of inductors. Other inductor configurations can be used to implement one or more of inductors 768, 746, or 724. For example, one or more of inductors 768, 746, or 724 can be implemented by a multi-turn inductor.

[0105] In the example shown in Figure 8, inductor 768 is physically nested within inductor 746, and inductor 746 is physically nested within inductor 724 to satisfy target coupling coefficients K1 and K2. By satisfying the target coupling coefficients K1 and K2, the LC VCO 700 satisfies the target operating frequency range and the target spacing between frequency bands within the target operating frequency range. Furthermore, by physically nesting inductor 768 within inductor 746 and inductor 746 within inductor 724, the LC VCO 700 occupies a smaller area on the chip compared to other LCVCOs, while achieving a wide operating frequency range. For example, by physically nesting inductor 768 within inductor 746 and inductor 746 within inductor 724, the LC VCO 700 occupies approximately the same amount of area on the chip as a single LC VCO, while providing an operating frequency range comparable to that of three LC VCOs containing multiplexed outputs. In this manner, the examples described herein include single-stage multi-band hybrid LC VCOs that are tunable in response to polarity-controlled phase injection.

[0106] Figure 9 This is a block diagram of an example phase-locked loop (PLL) oscillator 900 that includes an example VCO 902 implemented in conjunction with the examples described herein. Figure 9 In the example, the PLL oscillator 900 includes an example phase comparator circuit 904, an example filter circuit 906, an example input 908, an example tuning terminal 910, and an example output 912. Furthermore, each of the VCO 902 and the phase comparator circuit 904 has a first input, a second input, and an output. In some examples, the VCO 902 has an additional input. Figure 9 In this example, the filter circuit 906 has both inputs and outputs.

[0107] exist Figure 9 In the example shown, VCO 902 is combined Figure 1 LC VCO 100 Figure 3 and 4AThe LC VCO 300 or the LC VCO 700 shown in Figures 7 and 8 are implemented. Figure 9 In one example, the first input of VCO 902 is coupled to the output of filter circuit 906, and the second input of VCO 902 is coupled to tuning terminal 910. In some examples, VCO 902 has an additional input coupled to an additional tuning terminal. Furthermore, the output of VCO 902 is coupled to the second input of phase comparator circuit 904 and to output 912.

[0108] exist Figure 9 In the example shown, the phase comparator circuit 904 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 9 In this example, the first input of the phase comparator circuit system 904 is coupled to input 908, the second input of the phase comparator circuit 904 is coupled to the output of VCO 902, and the output of the phase comparator circuit 904 is coupled to the input of the filter circuit 906. Furthermore, in Figure 9 In this example, the filter circuit 906 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 9 In this example, the input of filter circuit 906 is coupled to the output of phase comparator circuit 904, and the output of filter circuit 906 is coupled to the first input of VCO 902.

[0109] exist Figure 9 In the example shown, VCO 902 generates a periodic signal, also known as V OUT Its frequency is proportional to the voltage applied at the first input. Figure 9 In this example, the phase comparator circuit 904 compares the phase of the signal provided by VCO 902 with the phase of the periodic input reference signal (also known as V) at input 908. IN The phase of the signal at output 912 is compared with that of the signal at input 908. Based on the comparison, phase comparator circuit 904 provides a voltage (which is filtered by filter circuit 906) to adjust the frequency of VCO 902 so that the phase of the signal at output 912 matches the phase of the signal at input 908. In some instances, the user can adjust the operating frequency range of VCO 902 via a tuning signal applied at tuning terminal 910, as described herein.

[0110] Figure 10 This is a block diagram of an example vehicle 1000 that includes an example Advanced Driver Assistance System (ADAS) 1005 and an example In-vehicle Infotainment (IVI) system 1010. Figure 10The example ADAS system 1005 includes an example ADAS hub 1015, a first example peripheral module 1020, a second example peripheral module 1025, a third example peripheral module 1030, a fourth example peripheral module 1035, and an example display 1040. Figure 10 The example IVI system 1010 includes an example media source 1045, an example IVI driver circuitry system 1050, a first example display driver 1055, a first example display 1060, a second example display 1065, a second example display driver 1070, and a third example display 1075.

[0111] Vehicle 1000 illustrates an example implementation of a flat panel display (FPD) link system for displaying media such as images and multimedia content. The example FPD link system includes ADAS system 1005 and IVI system 1010. Figure 10 Example vehicle 1000 includes ADAS system 1005 and IVI system 1010. In some instances, vehicle 1000 may include one or more instances of ADAS system 1005 or IVI system 1010. For example, vehicle 1000 may include one or more instances of ADAS system 1005 without IVI system 1010. In another instance, vehicle 1000 may include one or more instances of IVI system 1010 without ADAS system 1005. In yet another instance, vehicle 1000 may include one or more instances of ADAS system 1005 and one or more instances of IVI system 1010. Figure 10 In the example, vehicle 1000 is shown as a system for traversing distances, such as a car, truck, etc. Alternatively, vehicle 1000 may be replaced, shown, or described as an alternative distributed display system, such as a ship, aircraft, spacecraft, workstation, control panel, etc.

[0112] ADAS system 1005 is an example type of FPD link system that utilizes serialized and deserialized media for driver assistance in vehicle 1000. ADAS system 1005 can utilize serialized and deserialized media in alternative implementations for processing, storing, or displaying data, such as safety systems, recording systems, etc. In some instances, ADAS system 1005 is an example camera system that facilitates at least one of the following: storing, processing, or displaying multimedia data (e.g., images, video, etc.) from one or more cameras. In other instances, ADAS system 1005 can facilitate at least one of the following: storing, processing, or displaying alternative types of data from one or more alternative types of sensors (e.g., lidar, radar, ultrasonic sensors, etc.). Figure 10In this example, ADAS system 1005 includes ADAS hub 1015, peripheral modules 1020, 1025, 1030, 1035, and display 1040. Alternatively, ADAS system 1005 may include any number of peripheral modules or displays. Figure 11 An example of ADAS system 1005 is further shown and described.

[0113] The IVI system 1010 is an example type of FPD link system that utilizes serialized and deserialized media for infotainment on one or more displays (e.g., displays 1060, 1065, 1075). In some instances, the IVI system 1010 is a dashboard with multiple displays for displaying content. In other instances, the IVI system 1010 is a different display system with multiple displays for displaying content, such as a studio, workstation, etc. Figure 10 In this example, the IVI system 1010 includes a media source 1045, an IVI driver circuitry 1050, display drivers 1055 and 1070, and displays 1060, 1065, and 1075. Alternatively, the IVI system 1010 may include any number of media sources, display drivers, or displays. Figure 12 An example of the IVI system 1010 is further shown and described.

[0114] ADAS hub 1015 is communicatively coupled to peripheral modules 1020, 1025, 1030, 1035 and display 1040. ADAS hub 1015 uses full-duplex communication to send and receive data from peripheral modules 1020, 1025, 1030, 1035. In some instances, ADAS hub 1015 uses low-voltage differential signaling (LVDS) to communicate with peripheral modules 1020, 1025, 1030, 1035. Alternatively, ADAS hub 1015 can use alternative types of signaling to communicate with peripheral modules 1020, 1025, 1030, 1035, such as Display Serial Interface (DSI), Embedded Display Port (eDP), etc. ADAS hub 1015 can store, process, or display data from peripheral modules 1020, 1025, 1030, 1035. Figure 10In this example, the ADAS hub 1015 uses a display 1040 to display data from one or more of the peripheral modules 1020, 1025, 1030, and 1035. The ADAS hub 1015 uses multi-channel signaling to display data on the display 1040. Furthermore, the ADAS hub 1015 can also store or process data from the peripheral modules 1020, 1025, 1030, and 1035 for use in other functions of the vehicle 1000, such as object recognition and time-of-flight calculation. Figure 11 An example of the ADAS hub 1015 is further shown and described.

[0115] Peripheral modules 1020, 1025, 1030, and 1035 are communicatively coupled to ADAS hub 1015. Peripheral modules 1020, 1025, 1030, and 1035 contain at least one sensor that acquires information about the surrounding environment, such as images, video, time-of-flight measurements, beamforming data, etc. Peripheral modules 1020, 1025, 1030, and 1035 transmit the acquired sensor data to ADAS hub 1015 using communication channels 1020A, 1025A, 1030A, and 1035A. In some instances, communication channels 1020A, 1025A, 1030A, and 1035A are coaxial connectors that couple ADAS hub 1015 to peripheral modules 1020, 1025, 1030, and 1035. In such an example, the ADAS hub 1015 supplies power to peripheral modules 1020, 1025, 1030, and 1035 via Power over Coaxial Cable (POC) across communication channels 1020A, 1025A, 1030A, and 1035A. Alternatively, communication channels 1020A, 1025A, 1030A, and 1035A can be formed using different types of connectors, such as standard twisted-pair (STP). Figure 11 Examples of peripheral modules 1020, 1025, 1030, and 1035 are further shown and described.

[0116] exist Figure 10In an example operation of the ADAS system 1005, peripheral modules 1020, 1025, 1030, and 1035 generate video streams of the environment surrounding the vehicle 1000. Peripheral modules 1020, 1025, 1030, and 1035 serialize the video stream data. Peripheral modules 1020, 1025, 1030, and 1035 use communication channels 1020A, 1025A, 1030A, and 1035A to send the serial data stream to the ADAS hub 1015. Simultaneously, the ADAS hub 1015 can use communication channels 1020A, 1025A, 1030A, and 1035A to send data to the peripheral modules 1020, 1025, 1030, and 1035. Communication between the ADAS hub 1015 and the peripheral modules 1020, 1025, 1030, and 1035 can occur simultaneously. This type of multi-directional communication across the same communication channel in communication channels 1020A, 1025A, 1030A, and 1035A is called full-duplex communication.

[0117] exist Figure 10 In this example operation of the ADAS system 1005, the ADAS hub 1015 receives serial data streams from peripheral modules 1020, 1025, 1030, and 1035. The ADAS hub 1015 deserializes the data streams to reconstruct the video streams captured by the peripheral modules 1020, 1025, 1030, and 1035. The ADAS hub 1015 performs at least one of the following: storing, processing, or displaying the video streams for driver assistance. For example, the ADAS hub 1015 displays the video stream of the peripheral module 1035 on a display 1040 in response to determining that a viewing angle corresponding to the peripheral module 1035 is required. In another example, the ADAS hub 1015 stores or processes the video streams of the peripheral modules 1020, 1025, 1030, and 1035 for detecting safety hazards in the vehicle 1000 environment.

[0118] Combination Figure 11 The example operation of ADAS system 1005 is further described. Advantageously, serializing and deserializing data from peripheral modules 1020, 1025, 1030, and 1035 reduces the number of connections that need to traverse a relatively large portion of vehicle 1000 to reach ADAS hub 1015. Advantageously, the serial data stream is able to accurately traverse relatively large distances across communication channels 1020A, 1025A, 1030A, and 1035A.

[0119] Turning to IVI system 1010, media source 1045 is coupled to IVI driver circuitry 1050. Media source 1045 supplies media to IVI driver circuitry 1050 for display on one or more of displays 1060, 1065, and 1075. In some instances, media source 1045 is integrated into vehicle 1000, such as a circuitry supporting data streaming or a memory storing media. In other instances, media source 1045 represents a connection to a device external to vehicle 1000, such as a wireless connection to a service hosting multimedia streaming.

[0120] The IVI driver circuitry 1050 is communicatively coupled to a media source 1045 and a display driver 1055. The IVI driver circuitry 1050 processes multimedia data from the media source 1045 for transmission to one or more of the display drivers 1055 and 1070. The IVI driver circuitry 1050 uses full-duplex communication to send and receive data from the display driver 1055. In some instances, the IVI driver circuitry 1050 uses LVDS to communicate with the display driver 1055. In such instances, the IVI driver circuitry 1050 communicates indirectly with the display driver 1070 via the display driver 1055. Figure 12 Further examples of this are shown and described. Alternatively, the IVI driver circuitry 1050 can communicate with the display driver 1055 using alternative types of signaling, such as DSI, eDP, etc. In conjunction with Figure 12 An example of the IVI driver circuit system 1050 is further shown and described.

[0121] Display driver 1055 is communicatively coupled to IVI driver circuitry 1050, displays 1060, 1065, and display driver 1070. Display driver 1055 receives and transmits data to IVI driver circuitry 1050 using a first communication channel 1055A and a second communication channel 1055B. Display driver 1055 receives and transmits data to display driver 1070 using a third communication channel 1055C and a fourth communication channel 1055D. Figure 10In one example, the first and second coaxial connectors form communication channels 1055A and 1055B between the IVI driver circuitry 1050 and the display driver 1055. Similarly, the third and fourth coaxial connectors form communication channels 1055C and 1055D between the display drivers 1055 and 1070. The display driver 1055 uses multichannel signaling to use the displays 1060 and 1065 to display media. In some instances, the display driver 1055 determines which of the displays 1060 and 1065 corresponds to the data in response to decoding additional data from the IVI driver circuitry 1050. Alternatively, the display driver 1055 can be coupled to any number of displays. Figure 12 An example of the display driver 1055 is further shown and described.

[0122] Display driver 1070 is communicatively coupled to display driver 1055 and display 1075. In some instances, display driver 1070 may be coupled to another instance of display driver 1070 (similar to communication channels 1055A, 1055B, 1055C, 1055D of display driver 1055). Display driver 1070 uses communication channels 1055C and 1055D to receive and send data to display driver 1055. Display driver 1070 uses multichannel signaling to display multimedia data using display 1075. Alternatively, display driver 1070 may be coupled to any number of displays.

[0123] exist Figure 10 In an example operation of the IVI system 1010, a media source 1045 supplies media for display on at least one of displays 1060, 1065, and 1075. An IVI driver circuitry system 1050 determines one or more of the displays 1060, 1065, and 1075 corresponding to the media from the media source 1045. The IVI driver circuitry system 1050 determines one or more display drivers 1055 and 1070 coupled to one or more of the displays 1060, 1065, and 1075. The IVI driver circuitry system 1050 generates identification data specifying one or more of the display drivers 1055 and 1070 or at least one of the displays 1060, 1065, and 1075. The IVI driver circuitry system 1050 combines the identification data with the media from the media source 1045. The IVI driver circuitry system 1050 serializes the combined data for transmission on at least one of communication channels 1055A and 1055B.

[0124] In this example operation of IVI system 1010, display driver 1055 receives a serial data stream representing media and identification data. Display driver 1055 deserializes the serial data stream from communication channels 1055A and 1055B. Display driver 1055 decodes the identification data to determine whether the media corresponds to either display 1060 or 1065. Display driver 1055 displays the media on one or more of display 1060 or 1065 in response to determining that the identification data designates one or more of the display 1060 or 1065. Display driver 1055 reserializes the combined media and identification data in response to determining that the identification data designates another display corresponding to the media. Display driver 1055 transmits serial data on at least one of communication channels 1055C and 1055D. Display driver 1070 receives a serial data stream representing media and identification data from display driver 1055. Display driver 1055 deserializes the serial data stream from communication channels 1055C and 1055D. Display driver 1070 decodes identification data to determine whether the media corresponds to display 1075. Display driver 1070 displays the media on display 1075 in response to determining that the identification data designates display 1075. In some instances, display drivers 1055 and 1070 transmit serial data to IVI driver circuitry 1050 along communication channels 1055A, 1055B, 1055C, and 1055D. In such instances, concurrent communication from display drivers 1055 and 1070 can confirm that media has been received or displayed on one or more of displays 1060, 1065, and 1075.

[0125] Combination Figure 12 The example operation of the IVI system 1010 is further described. Advantageously, the serialization and deserialization of media from media source 1045 reduces the number of connections that need to traverse a relatively large portion of vehicle 1000 to reach displays 1060, 1065, and 1075. Advantageously, the serial data stream is able to accurately traverse relatively large distances across communication channels 1055A, 1055B, 1055C, and 1055D.

[0126] Figure 11 yes Figure 10 A block diagram of an example of ADAS system 1005, which includes Figure 10 Examples of ADAS hub 1015 Figure 10 Examples of peripheral modules 1020 and 1035 and Figure 10 The monitor is 1040. Figure 11The example ADAS hub 1015 includes a first example power supply circuit system 1105, a first example deserializer circuit system 1110, a first example serializer circuit system 1115, a second example power supply circuit system 1120, a second example deserializer circuit system 1125, a second example serializer circuit system 1130, an example programmable circuit system 1135, and an example display interface circuit system 1140. Figure 11 The example peripheral module 1020 includes an example serializer circuit system 1145, an example power regulator circuit system 1150, and an example sensor 1155.

[0127] The power supply circuit system 1105 has outputs coupled to the communication channel 1020A and the deserializer circuit system 1110. In some instances, the power supply circuit system 1105 has inputs coupled to a power storage device or an electronic control unit (ECU) supplying power. In other instances, the power supply circuit system 1105 is located within the peripheral module 1020. In such instances, the power supply circuit system 1105 directly supplies power to the peripheral module 1020. Alternatively, different methods of powering the peripheral module 1020 can be used in conjunction with the circuit system described herein.

[0128] The deserializer circuit system 1110 has inputs and outputs. The inputs of the deserializer circuit system 1110 are coupled to the communication channel 1020A and the power supply circuit system 1105. The outputs of the deserializer circuit system 1110 are coupled to the serializer circuit system 1115 and the programmable circuit system 1135. In some instances, the deserializer circuit system 1110 uses a serial data stream to communicate with the peripheral module 1020 along the communication channel 1020A. Figure 13 Further examples of understanding the serializer circuit system 1110 are shown and described.

[0129] The serializer circuit system 1115 has inputs and outputs. The inputs of the serializer circuit system 1115 are coupled to the deserializer circuit system 1110 and the programmable circuit system 1135. The outputs of the serializer circuit system 1115 are configured to couple to an additional communication channel. In some instances, as shown by dashed lines, the ADAS hub 1015 may include the serializer circuit system 1115 to connect the ADAS system 1005 to an external circuit system. In such instances, the serializer circuit system 1115 can communicatively couple the ADAS system 1005 to another ADAS system, IVI system 1010, storage media, ECU, etc. In other instances, the serializer circuit system 1115 may be excluded from the ADAS hub 1015.

[0130] The power supply circuit system 1120 has outputs coupled to the communication channel 1035A and the deserializer circuit system 1125. In some instances, the power supply circuit system 1120 has inputs coupled to a power storage device or a power supply ECU. In other instances, the power supply circuit system 1120 is located within the peripheral module 1035. In such instances, the power supply circuit system 1120 directly supplies power to the peripheral module 1035. Alternatively, different methods of powering the peripheral module 1035 can be used in conjunction with the circuit system described herein.

[0131] The deserializer circuit system 1125 has inputs and outputs. The inputs of the deserializer circuit system 1125 are coupled to the communication channel 1035A and the power supply circuit system 1120. The outputs of the deserializer circuit system 1125 are coupled to the serializer circuit system 1130 and the programmable circuit system 1135. In some instances, the deserializer circuit system 1125 uses a serial data stream to communicate with the peripheral module 1035 along the communication channel 1035A. Figure 13 Examples of the serializer circuit system 1125 are further shown and described.

[0132] The serializer circuit system 1130 has inputs and outputs. The inputs of the serializer circuit system 1130 are coupled to the deserializer circuit system 1125 and the programmable circuit system 1135. The outputs of the serializer circuit system 1130 are configured to couple to an additional communication channel. In some instances, as shown by dashed lines, the ADAS hub 1015 may include the serializer circuit system 1130 to connect the ADAS system 1005 to an external circuit system. In such instances, the serializer circuit system 1130 can communicatively couple the ADAS system 1005 to another ADAS system, IVI system 1010, storage media, ECU, etc. In other instances, the serializer circuit system 1130 may be excluded from the ADAS hub 1015.

[0133] Programmable circuit system 1135 has a first input, a second input, and an output. The first input of programmable circuit system 1135 is coupled to deserializer circuit system 1110 and serializer circuit system 1115. The second input of programmable circuit system 1135 is coupled to deserializer circuit system 1125 and serializer circuit system 1130. The output of programmable circuit system 1135 is coupled to display interface circuit system 1140. In some instances, programmable circuit system 1135 is instantiated in response to the execution of machine-readable instructions. In such instances, programmable circuit system 1135 may be one of a central processing unit (CPU), graphics processing unit (GPU), multi-core processing unit (MCU), etc. Alternatively, programmable circuit system 1135 may be an application-specific integrated circuit (ASIC) configured to perform at least one of the following: storing, processing, or regulating data from deserializer circuit systems 1110, 1125.

[0134] The display interface circuitry 1140 has inputs and outputs. The inputs of the display interface circuitry 1140 are coupled to the programmable circuitry 1135. The outputs of the display interface circuitry 1140 are coupled to the display 1040. In some instances, the display interface circuitry 1140 represents a display driver that translates data from the programmable circuitry 1135 to drive the display 1040. In some such instances, the display interface circuitry 1140 may include ports and connectors dedicated to driving the display 1040, such as a display port, a High Definition Multimedia Interface (HDMI) port, etc.

[0135] The serializer circuit system 1145 has inputs and outputs. The input of the serializer circuit system 1145 is coupled to a sensor 1155. The output of the serializer circuit system 1145 is coupled to a communication channel 1020A and a power conditioner circuit system 1150. In some instances, the serializer circuit system 1145 communicates with an ADAS hub 1015 using a serial data stream along the communication channel 1020A. Figure 13 An example of the serializer circuit system 1145 is further shown and described.

[0136] exist Figure 11 In one example, the deserializer circuit system 1110 is communicatively coupled to the serializer circuit system 1145 via a full-duplex wired connection represented by the communication channel 1020A. In some examples, both the deserializer circuit system 1110 and the serializer circuit system 1145 can receive data from or transmit data on the communication channel 1020A. In such examples, the input of the deserializer circuit system 1110 can also represent the output, and the output of the serializer circuit system 1145 can also represent the input. Figure 13 Such instances are further described.

[0137] The power regulator circuit system 1150 has inputs and outputs. The input of the power regulator circuit system 1150 is coupled to the communication channel 1020A and the serializer circuit system 1145. The output of the power regulator circuit system 1150 is coupled to the sensor 1155. The power regulator circuit system 1150 receives power from the power supply circuit system 1105. In some instances, such as in… Figure 11 In this embodiment, the power regulator circuitry 1150 receives power via communication channel 1020A. In other embodiments, the power supply circuitry 1105 may be coupled to the power regulator circuitry 1150 via a separate connection, or may be located near the peripheral module 1020.

[0138] Sensor 1155 has an input and an output. The input of sensor 1155 is coupled to power regulator circuitry 1150. The output of sensor 1155 is coupled to serializer circuitry 1145. In some instances, sensor 1155 generates data representing the surrounding environment. For example, in... Figure 10 In this embodiment, sensor 1155 may be a camera positioned to capture a portion of the environment surrounding vehicle 1000. In another instance, sensor 1155 may be an alternative type of sensor used to represent characteristics (e.g., obstacles) of the environment surrounding vehicle 1000.

[0139] In example operation, power supply circuitry 1105 supplies power to power regulator circuitry 1150 via communication channel 1020A. In some instances, such as when communication channel 1020A is a coaxial connector, power supply circuitry 1105 and power regulator circuitry 1150 implement power on coaxial cable (POC). In such instances, power supply circuitry 1105 supplies power (power input), and power regulator circuitry 1150 receives power (power output). Power regulator circuitry 1150 supplies power to sensor 1155 in response to receiving power from power supply circuitry 1105, or more generally, to peripheral module 1020. Similarly, power supply circuitry 1120 may supply power to peripheral module 1035 via communication channel 1035A.

[0140] In example operation, sensor 1155 generates data representing the surrounding environment. In some instances, sensor 1155 is a camera that generates multimedia data representing the viewpoint of the surrounding environment. In another instance, sensor 1155 is a lidar device that generates time-of-flight data representing potential obstacles in the surrounding environment. In yet another instance, sensor 1155 is a radar that generates beamforming data representing the surrounding environment. Alternatively, sensor 1155 could be an alternative type of sensor that generates alternative types of data. In such example operation, sensor 1155 uses multiple parallel data paths (also called lines or channels) to generate sensor data. Serializer circuitry 1145 serializes the data from the multiple parallel data paths to generate a serial data stream, the data rate of which is greater than the data rate of the parallel data paths from sensor 1155. Serializer circuitry 1145 uses the forward channel of communication channel 1020A to send the serial data stream to deserializer circuitry 1110. This data of the serial data stream is referred to as forward channel data (DATA). FC_0 ).

[0141] In the example operation, the deserializer circuit system 1110 receives a serial data stream after traversing the communication channel 1020A. Simultaneously, the deserializer circuit system 1110 can use the reverse channel of the communication channel 1020A to send a serial data stream to the serializer circuit system 1145. This data is referred to as reverse channel data (DATA). BC_0 In such instances, the forward channel data has a higher data rate than the reverse channel data to reduce interference. This multidirectional communication along communication channel 1020A is referred to as full-duplex communication. The deserializer circuitry 1110 can use the reverse channel of communication channel 1020A to control the setup of sensor 1155 or verify the reception of data on the forward channel. Similarly, peripheral module 1035 and deserializer circuitry 1125 can utilize full-duplex communication along communication channel 1035A to exchange forward and reverse channel data (DATA). FC_N DATA BC_N ).

[0142] In example operation, deserializer circuitry 1110 deserializes the forward channel data to generate multiple parallel data paths. In some instances, deserializer circuitry 1110 may decode identification data from the forward channel data. In such instances, serializer circuitry 1115 may serialize and transmit the forward channel data to the external circuitry in response to deserializer circuitry 1110 decoding identification data corresponding to the external circuitry. Advantageously, serializer circuitry 1115 allows ADAS system 1005 to be coupled to another instance of ADAS system 1005, IVI system 1010, or an alternative type of data processing system.

[0143] In example operation, programmable circuit system 1135 performs at least one of the following: processes, stores, or modulates data from multiple parallel data paths of display 1040. In some instances, programmable circuit system 1135 combines data from peripheral modules 1020, 1035 before displaying it. For example, programmable circuit system 1135 may stitch together video streams from peripheral modules 1020, 1035 to display a larger portion of the surrounding environment. In such example operation, display interface circuit system 1140 constructs data from programmable circuit system 1135 to drive display 1040. In some instances, display interface circuit system 1140 is at least one of column and row pixel drivers. Display 1040 generates a perceptible representation of data from at least one of peripheral modules 1020, 1035 in response to display interface circuit system 1140.

[0144] Combination Figure 13 Example operation of the serializer and deserializer system of ADAS system 1005 is further described. Advantageously, serializing and deserializing data from peripheral modules 1020 and 1035 reduces the number of connections that need to traverse relatively large distances to reach ADAS hub 1015. Advantageously, the serial data stream can accurately traverse relatively large distances across communication channels 1020A and 1035A.

[0145] Figure 12 yes Figure 10 A block diagram of an instance of the IVI system 1010, which includes Figure 10 Media source 1045 Figure 10 Examples of IVI driver circuitry systems 1050 Figure 10 Examples of display drivers 1055 and 1070 and Figure 10 The monitors are 1060, 1065, and 1075. Figure 12 The example IVI driver circuit system 1050 includes an example programmable circuit system 1220 and an example serializer circuit system 1230. Figure 12 The example display driver 1055 includes an example deserializer circuit system 1240, an example decoder circuit system 1250, an example display interface circuit system 1260, and an example serializer circuit system 1270.

[0146] Programmable circuit system 1220 has inputs and outputs. The inputs of programmable circuit system 1220 are coupled to current source 1045. The outputs of programmable circuit system 1220 are coupled to serializer circuit system 1230. In some instances, programmable circuit system 1220 is instantiated in response to the execution of machine-readable instructions. In such instances, programmable circuit system 1220 may be one of a CPU, GPU, MCU, etc. Alternatively, programmable circuit system 1135 may be an ASIC configured to perform at least one of the following: storing, processing, or regulating data from media source 1045.

[0147] Serializer circuit system 1230 has an input, a first output, and a second output. The input of serializer circuit system 1230 is coupled to programmable circuit system 1220. The first output of serializer circuit system 1230 is coupled to communication channel 1055A. The second output of serializer circuit system 1230 is coupled to communication channel 1055B. In some instances, serializer circuit system 1230 uses a serial data stream to communicate with display driver 1055 along communication channels 1055A and 1055B. Figure 13 An example of the serializer circuit system 1230 is further shown and described. (With) Figure 11 Unlike serializer circuit system 1145, serializer circuit system 1230 uses multiple serial data streams to exchange data along communication channels 1055A, 1055B. In some instances, serializer circuit system 1230 can be shown and described as multiple instances of serializer circuit system 1230 supporting a single communication channel in communication channels 1055A, 1055B. For example, serializer circuit system 1230 can be divided into two instances of serializer circuit system 1230.

[0148] The deserializer circuit system 1240 has a first input, a second input, and an output. The first input of the deserializer circuit system 1240 is coupled to a communication channel 1055A. The second input of the deserializer circuit system 1240 is coupled to a communication channel 1055B. The output of the deserializer circuit system 1240 is coupled to a decoder circuit system 1250. In some instances, the deserializer circuit system 1240 communicates with the IVI driver circuit system 1050 using a serial data stream along communication channels 1055A and 1055B. Figure 13 Further examples of the serializer circuit system 1240 are shown and described. (With) Figure 11Unlike the deserializer circuit systems 1110 and 1125, deserializer circuit system 1240 uses multiple serial data streams to exchange data along communication channels 1055A and 1055B. In some instances, deserializer circuit system 1240 can be shown and described as multiple instances of deserializer circuit system 1240 supporting a single communication channel in communication channels 1055A and 1055B. For example, deserializer circuit system 1240 can be divided into two instances of deserializer circuit system 1240, for example... Figure 11 The deserializer circuit system 1110, 1125.

[0149] Decoder circuitry 1250 has an input, a first output, and a second output. The input of deserializer circuitry 1250 is coupled to deserializer circuitry 1240. The first output of decoder circuitry 1250 is coupled to display interface 1260. The second output of decoder circuitry 1250 is coupled to serializer circuitry 1270. In some instances, decoder circuitry 1250 is implemented using a programmable circuitry or an ASIC. In such instances, decoder circuitry 1250 is configured to route data from deserializer circuitry 1240 to at least one of display interface 1260 or serializer circuitry 1270 in response to decoding a portion of the data. Such a portion of the data from deserializer circuitry 1240 may be referred to as identification data, which designates one or more of displays 1060, 1065, and 1075 for displaying media thereon.

[0150] Display interface 1260 has an input, a first output, and a second output. The input of display interface 1260 is coupled to decoder circuitry 1250. The first output of display interface 1260 is coupled to display 1060. The second output of display interface 1260 is coupled to display 1065. In some instances, display interface 1260 drives one or more of displays 1060 and 1065 in response to data from decoder circuitry 1250. In some such instances, display interface 1260 may include ports and connectors dedicated to driving the displays, such as monitor ports, HDMI ports, etc. Figure 12 In this example, display interface 1260 drives displays 1060 and 1065. Alternatively, display driver 1055 may include any number of display interfaces 1260 for driving any number of displays (e.g., displays 1060 and 1065).

[0151] Serializer circuitry 1270 has an input, a first output, and a second output. The input of serializer circuitry 1270 is coupled to decoder circuitry 1250. The first output of serializer circuitry 1270 is coupled to communication channel 1055C. The second output of serializer circuitry 1270 is coupled to communication channel 1055D. In some instances, serializer circuitry 1270 communicates with display driver 1070 using a serial data stream along communication channels 1055C and 1055D. Figure 13 Further examples of the serializer circuit system 1270 are shown and described. Similar to the serializer circuit system 1230, the serializer circuit system 1270 uses multiple serial data streams to exchange data along communication channels 1055C, 1055D. In some instances, the serializer circuit system 1270 may be shown and described as multiple instances of the serializer circuit system 1270 supporting one of the communication channels 1055C, 1055D. For example, the serializer circuit system 1270 may be divided into two instances of the serializer circuit system 1270.

[0152] In the example operation, the programmable circuit system 1220 receives multimedia data from a media source 1045. In some instances, the media source 1045 is internal to the IVI system 1010, such as a memory storage device, ECU, media stream, etc. In other instances, the media source 1045 is external to the IVI system 1010, such as a wireless connection to a service hosting the multimedia stream. The programmable circuit system 1220 identifies which of the displays 1060, 1065, and 1075 corresponds to the data from the media source 1045. In some instances, the programmable circuit system 1220 encodes additional data corresponding to different conditions of the IVI system 1010 onto the data from the media source 1045. For example, the programmable circuit system 1220 adds identification data to a portion of the data from the media source 1045 to specify which of the displays 1060, 1065, and 1075 corresponds to the media. In such instances, the identification data may specify one or more of the displays 1060, 1065, and 1075. The programmable circuit system 1220 supplies data to the serializer circuit system 1230 for transmission to the display drivers 1055, 1070.

[0153] In the example operation, the serializer circuitry 1230 receives data from the programmable circuitry 1220 on multiple parallel data paths. The serializer circuitry 1230 serializes the data from the multiple parallel data paths to produce first and second serial data streams with data rates greater than the data rates of the parallel data paths from the programmable circuitry 1220. The serializer circuitry 1230 transmits the first serial data stream to the deserializer circuitry 1240 using the forward channel of communication channel 1055A. This data of the first serial data stream is referred to as first forward channel data (DATA). FC_0 The serializer circuit system 1230 uses the forward channel of communication channel 1055B to send the second serial data stream to the deserializer circuit system 1240. This data in the second serial data stream is called the second forward channel data (DATA). FC_1 Advantageously, increasing the number of communication channels between the serializer circuit system 1230 and the deserializer circuit system 1240 increases the possible number of displays that the IVI system 1010 can support at a given time.

[0154] In the example operation, the deserializer circuit system 1240 receives the first and second serial data streams after traversing communication channels 1055A and 1055B. Simultaneously, the deserializer circuit system 1240 can transmit the first serial data stream to the serializer circuit system 1230 using the reverse channel of communication channel 1055A. This data is referred to as the first reverse channel data (DATA). BC_0 Similarly, the deserializer circuit system 1240 can use the reverse channel of the communication channel 1055B to send a second serial data stream to the serializer circuit system 1230. This data is referred to as second reverse channel data (DATA). BC_1 In such an example, the first and second forward channel data have a higher data rate than the first and second reverse channel data to reduce interference. This multidirectional communication along communication channels 1055A and 1055B is called full-duplex communication. The deserializer circuit system 1240 can use the reverse channels of communication channels 1055A and 1055B to verify the reception of the first and second forward channel data, report errors to the programmable circuit system 1220, etc. Similarly, the display driver 1070 and the serializer circuit system 1270 can use full-duplex communication along communication channels 1055C and 1055D to exchange third and fourth forward channel data (DATA). FC_2 DATA FC_3 ) and third and fourth reverse channel data (DATA) BC_2 DATA BC_3 ).

[0155] In example operation, deserializer circuitry 1240 deserializes the first and second forward channel data to generate multiple parallel data paths. Decoder circuitry 1250 decodes the data from media source 1045 from additional data from programmable circuitry 1220. Decoder circuitry 1250 determines, in response to the decoded data, which of displays 1060, 1065, and 1075 corresponds to the data from media source 1045. In some instances, decoder circuitry 1250 provides multiple parallel data paths to serializer circuitry 1270 in response to determining that the media does not correspond to displays 1060 or 1065. In such an instance, serializer circuitry 1270 serializes the third and fourth forward channel data and sends it to display driver 1070. Advantageously, display driver 1070 can be coupled in series with another instance of display driver 1070 via additional communication channels, such as fifth and sixth communication channels.

[0156] In example operation, the decoder circuitry provides multiple parallel data paths to the display interface 1260 in response to determining that media from media source 1045 corresponds to at least one of displays 1060, 1065. In some instances, the display interface 1260 constructs data from the decoder circuitry 1250 to drive at least one of displays 1060, 1065. In some instances, the display interface 1260 is at least one of column and row pixel drivers. In such example operation, at least one of displays 1060, 1065 generates a perceptible representation of media from media source 1045 in response to the display interface 1260.

[0157] Combination Figure 13 The example operation of the serializer and deserializer system of the IVI system 1010 is further described. Advantageously, serializing and deserializing data from the media source 1045 reduces the number of connections that need to traverse relatively large distances to reach one or more of the displays 1060, 1065, and 1075. Advantageously, the serial data stream can accurately traverse relatively large distances across communication channels 1055A, 1055B, 1055C, and 1055D.

[0158] Figure 13 This is a block diagram of an example serial deserializer (SerDes) system 1300, which includes an example deserializer circuit system 1305 and an example serializer circuit system 1310. Figure 13 The example deserializer circuit system 1305 includes an example serializer circuit system 1315, an example transmitter circuit system 1320, an example receiver circuit system 1325, and an example clock and data recovery (CDR) circuit system 1330. Figure 13The example CDR circuit system 1330 includes the example retimer circuit system 1335 and the example deserializer circuit system 1340. Figure 13 The example serializer circuit system 1310 includes an example serializer circuit system 1345, an example transmitter circuit system 1350, an example receiver circuit system 1355, an example CDR circuit system 1360, and an example decoder circuit system 1365. Figure 13 The example CDR circuit system 1360 includes an example retimer circuit system 1370 and an example deserializer circuit system 1375.

[0159] SerDes system 1300 is Figure 10 and 11 ADAS system 1005 and Figure 10 and 12 An example interface between the deserializer circuit system 1305 and the serializer circuit system 1310 in the IVI system 1010. Figure 11 In the example of ADAS system 1005, deserializer circuit system 1305 represents deserializer circuit system 1110 in ADAS hub 1015, and serializer circuit system 1310 represents serializer circuit system 1145 in peripheral module 1020. Figure 12 In the example of IVI system 1010, deserializer circuit system 1305 represents deserializer circuit system 1240 in display driver 1055. Furthermore, in Figure 12 In the example of IVI system 1010, serializer circuit system 1310 refers to serializer circuit system 1230 in IVI driver circuit system 1050 or serializer circuit system 1270 in display driver 1055.

[0160] The deserializer circuit system 1305 is coupled to the serializer circuit system 1310 via the communication channel 1310A. The deserializer circuit system 1305 has an input (DATA_IN). BC ) and output (DATA_OUT) FC The inputs and outputs of the deserializer circuit system 1305 are configured to be coupled to... Figure 11 Programmable circuit system 1135 or Figure 12 This is one of the decoder circuit systems 1250. The input of the deserializer circuit system 1305 receives reverse channel data for transmission along the communication channel 1310A. The output of the deserializer circuit system 1305 provides forward channel data from the communication channel 1310A.

[0161] The serializer circuit system 1310 is coupled to the deserializer circuit system 1305 via a communication channel 1310A. The serializer circuit system 1310 has an input (DATA_IN). FC) and output (DATA_OUT) BC The inputs and outputs of the serializer circuit system 1310 are configured to be coupled to... Figure 11 Sensor 1155 or Figure 12 One of the programmable circuit systems 1220. The input of the serializer circuit system 1310 receives forward channel data for transmission along the communication channel 1310A. The output of the serializer circuit system 1310 provides reverse channel data from the communication channel 1310A.

[0162] The serializer 1315 has inputs and outputs. The input of the serializer circuit system 1315 is coupled to the input (DATA_IN) of the deserializer circuit system 1305. BC The output of the serializer circuit system 1315 is coupled to the transmitter circuit system 1320. In some instances, the serializer circuit system 1315 is referred to as a reverse channel serializer.

[0163] Transmitter circuit system 1320 has inputs and outputs. The input of transmitter circuit system 1320 is coupled to serializer circuit system 1315. The output of transmitter circuit system 1320 is coupled to communication channel 1310A and receiver circuit system 1325. In some instances, transmitter circuit system 1320 is referred to as a reverse channel transmitter.

[0164] Receiver circuitry 1325 has inputs and outputs. The inputs of receiver circuitry 1325 are coupled to communication channel 1310A and transmitter circuitry 1320. The outputs of receiver circuitry 1325 are coupled to CDR circuitry 1330. In some instances, receiver circuitry 1325 is referred to as a forward channel receiver.

[0165] The CDR circuit system 1330 has inputs and outputs. The input of the CDR circuit system 1330 is coupled to the receiver circuit system 1325. The output of the CDR circuit system 1330 is coupled to the output (DATA_OUT) of the deserializer circuit system 1305. FC In some instances, the CDR circuit system 1330 is referred to as the forward channel CDR circuit system.

[0166] The retimer circuit system 1335 has an input, a first output, and a second output. The input of the retimer circuit system 1335 is coupled to the receiver circuit system 1325. The first and second outputs of the retimer circuit system 1335 are coupled to the deserializer circuit system 1340. Figure 1 , 3 At least one of 4A, 7 or 8 shows and describes example operation of an LC VCO for implementing at least some of the retimer circuitry system 1335.

[0167] Deserializer 1340 has a first input, a second input, and an output. The first and second inputs of deserializer circuit system 1340 are coupled to retimer circuit system 1335. The output of deserializer circuit system 1340 is coupled to the output (DATA_OUT) of deserializer circuit system 1305. FC ).

[0168] The serializer 1345 has inputs and outputs. The input of the serializer circuit system 1345 is coupled to the input (DATA_IN) of the serializer circuit system 1310. FC The output of the serializer circuit system 1345 is coupled to the transmitter circuit system 1350. In some instances, the serializer is referred to as a forward channel serializer.

[0169] Transmitter circuit system 1350 has inputs and outputs. The input of transmitter circuit system 1350 is coupled to serializer circuit system 1345. The output of transmitter circuit system 1350 is coupled to communication channel 1310A and receiver circuit system 1355. In some instances, transmitter circuit system 1350 is referred to as a forward channel transmitter. Transmitter circuit systems 1320 and 1350 may include circuitry for impedance matching of communication channel 1310A to reduce reflections. Furthermore, transmitter circuit systems 1320 and 1350 may have different bandwidths.

[0170] Receiver circuitry 1355 has inputs and outputs. The inputs of receiver circuitry 1355 are coupled to communication channel 1310A and transmitter circuitry 1350. The outputs of receiver circuitry 1355 are coupled to CDR circuitry 1360. In some instances, receiver circuitry 1355 is referred to as a reverse channel receiver.

[0171] CDR circuit system 1360 has inputs and outputs. The input of CDR circuit system 1360 is coupled to receiver circuit system 1355. The output of CDR circuit system 1360 is coupled to decoder circuit system 1365. In some instances, CDR circuit system 1360 is referred to as reverse channel CDR circuit system.

[0172] The decoder circuit system 1365 has inputs and outputs. The input of the deserializer circuit system 1365 is coupled to the CDR circuit system 1360. The output of the decoder circuit system 1365 is coupled to the output (DATA_OUT) of the serializer circuit system 1310. BC In some instances, as shown by the dashed line, the output of the CDR circuit system 1360 is directly coupled to the output (DATA_OUT) of the serializer circuit system 1310. BC ).

[0173] The retimer circuit system 1370 has an input, a first output, and a second output. The input of the retimer circuit system 1370 is coupled to the receiver circuit system 1355. The first and second outputs of the retimer circuit system 1370 are coupled to the deserializer circuit system 1375. Figure 1 , 3 At least one of 4A, 7 or 8 shows and describes example operation of an LC VCO for implementing at least some of the retimer circuitry system 1370.

[0174] Deserializer 1375 has a first input, a second input, and an output. The first and second inputs of deserializer circuitry 1375 are coupled to timer circuitry 1370. The output of deserializer circuitry 1375 is coupled to decoder circuitry 1365. In some instances, as shown by the dashed line, the output of deserializer circuitry 1375 is directly coupled to the output (DATA_OUT) of serializer circuitry 1310. BC ).

[0175] In the example operation, the deserializer circuitry 1305 receives reverse channel data (DATA) from an external data source (e.g., programmable circuitry 1135 or decoder circuitry 1250) on multiple data paths. BC The serializer circuitry 1315 generates a reverse-channel serial data stream in response to the reverse-channel data. The transmitter circuitry 1320 transmits the reverse-channel data to the serializer circuitry 1310 on the communication channel 1310A. Similarly, the serializer circuitry 1310 receives forward-channel data (DATA) from external data sources (e.g., sensor 1155 or programmable circuitry 1220) on multiple data paths. FC The serializer circuitry 1345 generates a forward channel serial data stream in response to the forward channel data. The transmitter circuitry 1320 transmits the forward channel data to the deserializer circuitry 1305 on the communication channel 1310A. In this example operation, the data rates for the forward and reverse channel data transmissions are different to prevent interference. In some instances, the bandwidth of the transmitter circuitry 1320 transmitting the reverse channel data is modified to reduce the nonlinear gain contribution of the communication channel 1310A. Advantageously, the serializer circuitries 1315, 1345 and the transmitter circuitries 1320, 1350 support full-duplex data transmission along the communication channel 1310A.

[0176] In the example operation, in the forward channel data (DATA) FCAfter propagation along communication channel 1310A, deserializer circuitry 1305 receives the forward channel data. Receiver circuitry 1325 generates a serial data stream representing the forward channel data in response to a signal from communication channel 1310A. In some instances, receiver circuitry 1325 isolates communication channel 1310A from CDR circuitry 1330. Deserializer circuitry 1305 may include echo cancellation circuitry to reduce the contribution of reverse channel data from the signal received from transmitter circuitry 1320. Similarly, in the reverse channel data (DATA... BC After propagation along communication channel 1310A, serializer circuitry 1310 receives the reverse channel data. Receiver circuitry 1355 generates a serial data stream representing the reverse channel data in response to a signal from communication channel 1310A. In some instances, receiver circuitry 1325 isolates communication channel 1310A from CDR circuitry 1330. Serializer circuitry 1310 may include echo cancellation circuitry to reduce the contribution of forward channel data from signals received from transmitter circuitry 1350. Furthermore, receiver circuitry 1325 and 1355 terminate current in communication channel 1310A.

[0177] In the example operation, CDR circuitry 1330 receives forward channel data from receiver circuitry 1325. Retimer circuitry 1335 retimes the forward channel data to produce retimed forward channel data (RETIMED_DATA). Retimer circuitry 1335 generates a clock signal (CLK) representing the precise sampling time of the retimed forward channel data. Deserializer circuitry 1340 receives the retimed forward channel data and clock signal from retimer circuitry 1335. Deserializer circuitry 1340 generates multiple parallel data paths representing the forward channel data. The output of deserializer circuitry 1305 provides the forward channel data to external circuitry, such as programmable circuitry 1135 or decoder circuitry 1250. Similarly, CDR circuitry 1360 receives reverse channel data from receiver circuitry 1355. Retimer circuitry 1335 generates retimed reverse channel data and clock signal in response to retimed reverse channel data to a clock signal. The deserializer circuitry 1375 receives retimed reverse channel data and a clock signal from the retimer circuitry 1370. The deserializer circuitry 1375 generates multiple parallel data paths representing the reverse channel data. In some such example operations, the decoder circuitry 1365 decodes a portion of the reverse channel data before the output of the serializer circuitry 1310 provides the reverse channel data to an external circuitry (e.g., sensor 1155 or programmable circuitry 1220).

[0178] Combination Figure 1 , 3 At least one of 4A, 7, or 8 shows and describes example operation of an LC VCO for implementing at least some of the retimer circuit systems 1335, 1370. Advantageously, serializing and deserializing the forward and reverse channel data reduces the number of connections required to traverse the relatively large distance of communication channel 1310A. Advantageously, the serial data stream is able to accurately traverse the relatively large distance across communication channel 1310A.

[0179] Although Figure 1 The implementation is shown in the figure. Figure 1 The example method of LC VCO 100, in Figure 3 and 4A The implementation is shown in the figure. Figure 3 An example configuration of the LC VCO 300 is shown, and an example configuration of the LC VCO 700 implementing Figure 7 is shown in Figures 7 and 8, but... Figure 1 , 3 One or more of the elements, processes, or apparatuses shown in 4A, 7, and 8 may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, Figure 1 Example LC VCO 100 Figure 3 and 4A The example LC VCO300 and the example LC VCO 700 in Figures 7 and 8 can be implemented by hardware alone, or by a combination of hardware, software, and firmware. Thus, for example, Figure 1 Example LC VCO 100 Figure 3 and 4A Any of the example LC VCO 300 or the example LCVCO 700 of Figures 7 and 8 can be implemented by a programmable circuit system in conjunction with one or more machine-readable instructions, such as firmware or software, processor circuit systems, analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), or field-programmable logic devices (FPLDs) such as FPGAs. Furthermore, Figure 1 Example LC VCO 100 Figure 3 and 4A The example LCVCO 300 and the example LCVCO 700 in Figures 7 and 8 can include, in addition to Figure 1 , 3 One or more elements, processes or devices other than or in place of those shown in 4A, 7 and 8, or may include more than one of any or all of the elements, processes and devices shown.

[0180] "Including" and "comprising" (and all their forms and tenses) are used herein as open terms. Therefore, whenever a claim uses any form of "including" or "comprising" as a preamble or in any type of claim statement, additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or reference. Example forms of "include" and "comprise" include include, include, includes, includes, includes, comprising, having, etc. As used herein, when the phrase "at least" is used as a transitional term, for example, in a preamble of a claim, it is open in the same way as the terms "including" and "comprising" are open. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" means an embodiment comprising any one of: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0181] As used herein, a singular reference does not exclude multiple references. Examples of singular references include “a”, “an”, “first”, “second”, etc. As used herein, the term “a” or “an” refers to one or more of the objects mentioned. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Moreover, while individual features may be included in different instances or claims, these features may be combined, and inclusion in different instances or claims does not imply that the combination of features is not feasible and / or advantageous.

[0182] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. The first part is above the second part if at least one portion of the second part lies between the earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the earth than the second part. As mentioned above, the first part may be above or below the second part, having one or more of the following: having other parts between it, having no other parts between it, the first and second parts in contact, or the first and second parts not in direct contact with each other.

[0183] Notwithstanding the foregoing, when referring to at least one of a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, "above" does not refer to ground, but to the underlying substrate on which the relevant component is manufactured, assembled, mounted, supported, or otherwise provided. Therefore, as used herein and unless otherwise stated or implied from the context, for a substrate (e.g., a semiconductor wafer) on which two components are fabricated or otherwise provided, the first component within a semiconductor die (e.g., a transistor or other semiconductor device) is "above" the second component within the semiconductor die when the first component is further away from the substrate than the second component during fabrication / manufacturing. Similarly, unless the context otherwise indicates or implies, the first component within an IC package (e.g., a semiconductor die) is "above" the second component within the IC package during manufacturing, where the first component is further away from the printed circuit board (PCB) to which the IC package is to be mounted or attached. Semiconductor devices are typically used in an orientation different from their orientation during fabrication. Therefore, when referring to one or a combination of a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an integrated circuit (IC) package containing a semiconductor die during use, the definition of "above" in the preceding paragraph will likely be governed by the context of use. For example, the term "above" as defined in the preceding paragraph describes the relationship between two parts relative to the Earth.

[0184] As used in this patent, stating that any part (e.g., layer, film, region, area, or plate) is located on another part in any way (e.g., located on it, positioned on it, disposed on it, or formed on it, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0185] As used herein, unless otherwise indicated, a connection reference (e.g., fitting, coupling, connection, and joining) may include an intermediate member between elements referenced by at least one of the connection references or relative movements between those elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected or fixed to each other.

[0186] Unless otherwise specifically stated, descriptive terms such as “first,” “second,” and “third” are used herein without intending to or otherwise indicate priority, physical order, arrangement, or any sorting in the list, but are used only as markers or at least one of any name to distinguish elements in order to facilitate understanding of the described instance. In some instances, the descriptive term “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to in the technical solution by different descriptive terms such as “second” or “third.” In such cases, such descriptive terms are used only to clearly identify those elements within the context of the discussion (e.g., within the claims), where elements may otherwise share the same name.

[0187] As used herein, the phrase “communication” includes its variations, encompassing one or a combination of direct communication or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-off events. Furthermore, as used herein, the phrase “in response to” may be used interchangeably with the phrase “based on”.

[0188] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) configured to perform a particular operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits programmable by instructions to perform one or more particular functions or operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) capable of executing a first instruction to perform one or more operations or functions; a field-programmable gate array (FPGA) programmable with a second instruction to configure or structure at least one of the FPGAs, thereby instantiating one or more operations or functions corresponding to the first instruction; a graphics processing unit (GPU) capable of executing a first instruction to perform one or more operations or functions; a digital signal processor (DSP) capable of executing a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers capable of executing a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes various types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs)) that can assign computing tasks to any one or more types of programmable circuit systems that are suitable for and can be used to implement the computing tasks.

[0189] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0190] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0191] A device “configured” to perform a task or function may be configured (e.g., at least one of programming or hardwiring) to perform the function during manufacturing by the manufacturer, or may be configured (or reconfigurable) by the user after manufacturing to perform the function or at least one of other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the device’s hardware components and interconnects, or by a combination thereof.

[0192] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0193] In this specification and claims, the described "circuit system" may comprise one or more circuits. A circuit or device described herein as including certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as comprising one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., at least one of voltage or current sources) may alternatively comprise only a semiconductor element within a single physical device (e.g., at least one in a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled, at or after manufacturing time, for example by at least one of an end user or a third party, to at least some of the passive elements or sources to form the described structure.

[0194] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some elements in the described examples are included in the integrated circuit and others are outside the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as outside the integrated circuit may be included in the integrated circuit, and some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in / on the same printed circuit board.

[0195] The use of the phrase “ground” in the foregoing description includes at least one of chassis ground, earth, floating ground, virtual ground, digital ground, public ground, or any other form of ground connection applicable to or suitable for the teachings of this specification.

[0196] As used herein, “approximately,” “about,” and “substantially” modify their subject / value to identify the potential presence of variation in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0197] Within the scope of the claims, modifications may be made to the described examples, and other examples are also possible.

[0198] As can be understood from the foregoing, example systems, apparatuses, articles of manufacture, and methods for multi-band hybrid inductor-capacitor voltage-controlled oscillators have been described. As described herein, inductor tuning is performed via current mirroring from the main core (also known as the main LC resonant circuit) to one or more peripheral cores (also known as peripheral LC resonant circuits). The example peripheral cores are mutually coupled to the main core via mutual inductance coupling. Therefore, by mirroring in-phase and out-of-phase currents to one or more peripheral cores, the total inductance of the example LC VCO described herein is controlled, resulting in negative or positive mutual inductance, which also affects the oscillation frequency.

[0199] As described herein, the phase of the injected current is controlled by a tuning signal, also known as a control signal, which allows the user to change the sign of the resonance of the peripheral resonant circuit. Therefore, the inductance of the example LC VCO described herein can be increased or decreased by injecting a proportionally positive or negative phase current into the peripheral core via a tuning signal of one or zero, thereby resulting in an increase or decrease in the oscillation frequency, respectively. As a result of the single differential output structure of the example LC VCO described herein, clock multiplexing between multiple LC VCOs, which consume significant power, is avoided. Therefore, compared to other LC VCOs, the example LC VCO described herein reduces power consumption, clock distortion (e.g., duty cycle distortion), power supply noise, and wiring complexity.

[0200] Compared to other LC VCOs, the described systems, apparatuses, articles, and methods improve the efficiency of using computing devices by reducing the amount of on-chip area and the power consumed by the LC VCO. For example, the examples described herein include an LC VCO with a single differential clock having an ultra-wide frequency tuning range. Therefore, the example LC VCO described herein consumes approximately the same amount of on-chip area as a single LC VCO while providing an operating frequency range comparable to that of multiple LC VCOs containing multiplexed outputs. However, the example LC VCO described herein does not contain multiplexed outputs from multiple LC VCOs, and thus avoids routing complexity and the reallocation buffers used for such multiplexing. The described systems, apparatuses, articles, and methods also relate to one or more improvements in the operation of machines (e.g., computers or other electronic, electromechanical, or mechanical devices).

Claims

1. An apparatus comprising: An inverter having a first terminal and a second terminal coupled to an enable terminal; A first transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the inverter, and the first terminal being coupled to a power supply terminal; The second transistor has a control terminal, a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first transistor; An inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor; A capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor; A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first terminal of the inductor and the first terminal of the capacitor, and the second terminal is coupled to the second terminal of the inductor and the second terminal of the capacitor; as well as The fourth transistor has a control terminal coupled to the enable terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the third transistor.

2. The device of claim 1, wherein the inverter is a first inverter, the inductor is a first inductor, the capacitor is a first capacitor, and the device further comprises: The second inverter has a first terminal and a second terminal coupled to the tuning terminal; The fifth transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the second inverter, and the first terminal being coupled to the power supply terminal; The sixth transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the first inductor and the first terminal of the first capacitor, and the first terminal being coupled to the second terminal of the fifth transistor; A second inductor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the sixth transistor; The second capacitor has a first terminal coupled to the second terminal of the sixth transistor and the first terminal of the second inductor, and a second terminal coupled to the second terminal of the second inductor. A seventh transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the second terminal of the first inductor and the second terminal of the first capacitor, and the second terminal being coupled to the second terminal of the second inductor and the second terminal of the second capacitor; as well as The eighth transistor has a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the seventh transistor.

3. The device according to claim 2, wherein: The first inductor and the first capacitor are configured to serve as a first LC resonant circuit, which is configured to generate a first oscillation signal based on an enable signal at the enable terminal. and The second inductor and the second capacitor are configured to serve as a second LC resonant circuit, which is configured to generate a second oscillation signal based on a control signal at the tuning terminal. The second oscillation signal is used to adjust the frequency of the first oscillation signal based on the coupling factor between the first inductor and the second inductor.

4. The device according to claim 2, further comprising: A ninth transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the tuning terminal, and the first terminal being coupled to the power supply terminal; The tenth transistor has a control terminal coupled to the second terminal of the first inductor and the second terminal of the first capacitor, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the first terminal of the second inductor and the first terminal of the second capacitor. The eleventh transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first terminal of the first inductor and the first terminal of the first capacitor, and the second terminal is coupled to the second terminal of the second inductor and the second terminal of the second capacitor; as well as The twelfth transistor has a control terminal coupled to the first terminal of the second inverter, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the eleventh transistor.

5. The device according to claim 4, wherein: The first inductor and the first capacitor are configured to serve as a first LC resonant circuit, which is configured to generate a first oscillation signal when the enable signal at the enable terminal has a logic value of one. and The second inductor and the second capacitor are configured to function as a second LC resonant circuit, which is configured to: When the control signal at the tuning terminal has a logic value of one, a second oscillation signal out of phase with the first oscillation signal is generated. This second oscillation signal is used to increase the frequency of the first oscillation signal based on the coupling factor between the first inductor and the second inductor. When the control signal at the tuning terminal has a logic value of zero, a second oscillation signal in phase with the first oscillation signal is generated. The second oscillation signal is used to reduce the frequency of the first oscillation signal based on the coupling factor.

6. The device of claim 2, wherein the first inductor is coupled to the second inductor via mutual inductance.

7. The device of claim 2, wherein the second inductor is physically nested within the first inductor.

8. An inductor-capacitor LC oscillator, comprising: A first inverter has a first terminal and a second terminal coupled to an enable terminal; The first core, which includes: A first transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the first inverter, and the first terminal being coupled to a power supply terminal; A first LC resonant circuit includes a first inductor and a first capacitor. The first LC resonant circuit has a first terminal and a second terminal, and a clock signal is measured across the first terminal and the second terminal. and The second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the enable terminal, and the first terminal is coupled to the ground terminal. The second inverter has a first terminal and a second terminal coupled to the tuning terminal; as well as The second core includes: The third transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the second inverter, and the first terminal being coupled to the power supply terminal; A fourth transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the first LC resonant circuit, and the first terminal being coupled to the second terminal of the third transistor; The second LC resonant circuit includes a second inductor and a second capacitor. The second LC resonant circuit has a first terminal and a second terminal, the first terminal being coupled to the second terminal of the fourth transistor. and The fifth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the second terminal of the first LC resonant circuit, and the second terminal is coupled to the second terminal of the second LC resonant circuit. as well as The sixth transistor has a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the fifth transistor, wherein the first inductor is coupled to the second inductor via mutual inductance.

9. The LC oscillator according to claim 8, wherein: The first core is used to generate a first oscillation signal based on the enable signal at the enable terminal; and The second core is used to generate a second oscillation signal based on the control signal at the tuning terminal. The second oscillation signal is used to adjust the frequency of the first oscillation signal based on the coupling factor between the first inductor of the first LC resonant circuit and the second inductor of the second LC resonant circuit.

10. The LC oscillator according to claim 8, wherein: The first core is used to generate a first oscillation signal when the enable signal at the enable terminal has a logic value of one; and The second core is used for: When the control signal at the tuning terminal has a logic value of one, a second oscillation signal that is out of phase with the first oscillation signal is generated. The second oscillation signal is used to increase the frequency of the first oscillation signal based on the coupling factor between the first inductor of the first LC resonant circuit and the second inductor of the second LC resonant circuit. and When the control signal at the tuning terminal has a logic value of zero, a second oscillation signal in phase with the first oscillation signal is generated. The second oscillation signal is used to reduce the frequency of the first oscillation signal based on the coupling factor.

11. The LC oscillator of claim 8, further comprising a buffer having a first terminal coupled to a clock terminal, a second terminal coupled to the first terminal of the first LC resonant circuit, and a third terminal coupled to the second terminal of the first LC resonant circuit.

12. The LC oscillator of claim 8, wherein the second inductor is physically nested within the first inductor.

13. The LC oscillator of claim 8, wherein the inductance of the LC oscillator is adjustable based on a control signal at the tuning terminal.

14. A phase-locked loop (PLL) oscillator, comprising: A phase comparator circuit has terminals; A filter circuit having a first terminal and a second terminal coupled to the terminal of the phase comparator circuit; as well as An inductor-capacitor LC voltage-controlled oscillator (VCO) comprises: An inverter having a first terminal and a second terminal coupled to the first terminal of the filter circuit; A first transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the inverter, and the first terminal being coupled to a power supply terminal; The second transistor has a control terminal, a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first transistor; An inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the second transistor; A capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor; A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first terminal of the inductor and the first terminal of the capacitor, and the second terminal is coupled to the second terminal of the inductor and the second terminal of the capacitor; as well as The fourth transistor has a control terminal coupled to the first terminal of the filter circuit, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the third transistor.

15. The PLL oscillator of claim 14, wherein the PLL oscillator includes a tuning terminal, the inverter is a first inverter, the inductor is a first inductor, the capacitor is a first capacitor, and the LC VCO further comprises: A second inverter has a first terminal and a second terminal coupled to the tuning terminal of the PLL oscillator; The fifth transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the second inverter, and the first terminal being coupled to the power supply terminal; The sixth transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the first terminal of the first inductor and the first terminal of the first capacitor, and the first terminal being coupled to the second terminal of the fifth transistor; A second inductor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the sixth transistor; The second capacitor has a first terminal coupled to the second terminal of the sixth transistor and the first terminal of the second inductor, and a second terminal coupled to the second terminal of the second inductor. A seventh transistor has a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the second terminal of the first inductor and the second terminal of the first capacitor, and the second terminal being coupled to the second terminal of the second inductor and the second terminal of the second capacitor; as well as The eighth transistor has a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the seventh transistor.

16. The PLL oscillator according to claim 15, wherein: The first inductor and the first capacitor are configured to serve as a first LC resonant circuit, which is configured to generate a first oscillation signal based on the signal at the first terminal of the filter circuit. and The second inductor and the second capacitor are configured to serve as a second LC resonant circuit, which is configured to generate a second oscillation signal based on a control signal at the tuning terminal. The second oscillation signal is used to adjust the frequency of the first oscillation signal based on the coupling factor between the first inductor and the second inductor.

17. The PLL oscillator of claim 15, further comprising: A ninth transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the tuning terminal, and the first terminal being coupled to the power supply terminal; The tenth transistor has a control terminal coupled to the second terminal of the first inductor and the second terminal of the first capacitor, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the first terminal of the second inductor and the first terminal of the second capacitor. The eleventh transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first terminal of the first inductor and the first terminal of the first capacitor, and the second terminal is coupled to the second terminal of the second inductor and the second terminal of the second capacitor; as well as The twelfth transistor has a control terminal coupled to the first terminal of the second inverter, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the eleventh transistor.

18. The PLL oscillator according to claim 17, wherein: The first inductor and the first capacitor are configured to serve as a first LC resonant circuit, which is configured to generate a first oscillation signal when the output signal at the first terminal of the filter circuit has a logic value of one. and The second inductor and the second capacitor are configured to function as a second LC resonant circuit, which is configured to: When the control signal at the tuning terminal has a logic value of one, a second oscillation signal out of phase with the first oscillation signal is generated. This second oscillation signal is used to increase the frequency of the first oscillation signal based on the coupling factor between the first inductor and the second inductor. When the control signal at the tuning terminal has a logic value of zero, a second oscillation signal in phase with the first oscillation signal is generated. The second oscillation signal is used to reduce the frequency of the first oscillation signal based on the coupling factor.

19. The PLL oscillator of claim 15, wherein the first inductor is coupled to the second inductor via mutual inductance.

20. The PLL oscillator of claim 15, wherein the second inductor is physically nested within the first inductor.

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