Programmable start-up point DC cancellation circuit for transimpedance amplifiers in optical communication

Abstract

This invention relates to a programmable start-up point DC cancellation circuit for transimpedance amplifiers used in optical communication, belonging to the fields of integrated circuits and optical communication technology. The invention addresses the problem of abnormal operating point and signal distortion in existing transimpedance amplifiers under strong ambient light or high dark current conditions due to excessive input DC components. The invention comprises a transimpedance amplifier core unit, a DC component detection unit, a start-up threshold setting unit, and a compensation current generation unit. The DC component detection unit is connected to the input and output terminals of the transimpedance amplifier core unit, used to compare the DC potential relationship between the two terminals and generate a comparison signal. The start-up threshold setting unit injects a set current into the DC component detection unit to adjust the flip threshold of the comparison signal. The compensation current generation unit, controlled by the comparison signal, generates two compensation currents, one output to the input terminal to extract the DC component and the other output to the DC component detection unit to adjust its comparison reference, thereby restoring the static operating point of the transimpedance amplifier core unit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and optical communication technology, and specifically relates to a programmable start-up point DC cancellation circuit and method for use in optical communication transimpedance amplifiers. Background Technology

[0002] Optical communication is a communication method that uses light as the information carrier and optical fiber as the transmission medium, involving multiple technical fields such as optical networks, optoelectronic devices, and integrated circuits. At the receiver end of an optical communication module (ROSA), the preamplifier typically uses a transimpedance amplifier (TIA) chip, working in conjunction with a photodiode (PD or APD) to convert the optical signal into an electrical signal. Specifically, the photodiode converts the weak optical signal into a current signal, and the transimpedance amplifier then converts this current signal into a voltage signal for subsequent network equipment to receive and process.

[0003] However, the following problems exist in practical applications. First, photodiodes exhibit non-ideal effects, such as dark current generated by reverse bias and the influence of ambient light, causing the current signal received by the transimpedance amplifier to typically be an AC signal containing a DC component, in which the AC signal carries various commands and data. Second, if the DC current signal is too large, the voltage drop across the feedback resistor Rf will be too large, preventing the transistors inside the transimpedance amplifier from operating normally, resulting in AC signal distortion and data failure.

[0004] While existing DC cancellation solutions address the aforementioned issues, they often suffer from the following shortcomings: First, the DC cancellation trigger point is fixed, making it impossible to flexibly adjust according to different application scenarios (such as changes in ambient light intensity or differences in dark current among different photodiode models); second, the circuit structure is complex and has low integration, hindering its implementation in optical communication receiver chips; and third, the accuracy and stability of the compensation current are insufficient, affecting the DC cancellation effect. Therefore, a DC cancellation solution with programmable control over the trigger point and a simple and reliable circuit structure is urgently needed. Summary of the Invention

[0005] To address the problem of abnormal operating point and signal distortion caused by excessive input DC component in existing transimpedance amplifiers under strong ambient light or high dark current conditions, this invention provides a programmable start-up point DC cancellation circuit for use in optical communication transimpedance amplifiers.

[0006] In a first aspect, the programmable start-up point DC cancellation circuit applied to an optical communication transimpedance amplifier according to the present invention includes:

[0007] The transimpedance amplifier core unit receives an input current signal containing a DC component and converts the input current signal into an output voltage signal;

[0008] A DC component detection unit is connected to the input and output terminals of the transimpedance amplification core unit. It is used to compare the DC potential relationship between the input and output terminals of the transimpedance amplification core unit and generate a comparison signal.

[0009] A threshold setting unit is connected to the DC component detection unit and is used to programmatically set the threshold for the DC elimination function.

[0010] The compensation current generation unit, controlled by the comparison signal, generates a first compensation current and a second compensation current. The first compensation current is output to the input terminal of the transimpedance amplification core unit to extract the DC component, and the second compensation current is output to the DC component detection unit, thereby restoring the static operating point of the transimpedance amplification core unit.

[0011] Preferably, the DC component detection unit includes:

[0012] A reference potential generation subunit is connected to the output terminal of the transimpedance amplification core unit. The reference potential generation subunit includes a resistor R2, which is used to generate a first potential V1 through the resistor R2.

[0013] The input potential extraction subunit is connected to the input terminal of the transimpedance amplification core unit and is used to extract the DC potential of the input terminal of the transimpedance amplification core unit and output it as the second potential V2.

[0014] The comparison subunit is implemented using comparator AMP1. The non-inverting input of AMP1 is connected to the second potential V2, and the inverting input of AMP1 is connected to the first potential V1. It is used to compare the magnitudes of the two and output the comparison signal.

[0015] Preferably, the input potential extraction subunit includes a low-pass filter network, which includes a resistor R3 and a capacitor C1. One end of the resistor R3 is connected to the input of the transimpedance amplification core unit, and the other end is connected to one end of the capacitor C1 and outputs the second potential V2. The other end of the capacitor C1 is grounded.

[0016] Preferably, the start-up threshold setting unit includes:

[0017] The reference current generation subunit is used to generate a reference current;

[0018] A programmable current mirroring subunit, connected to the reference current generating subunit, is used to replicate the reference current at a programmable mirroring ratio to generate a programmable set current.

[0019] The programmable current is injected into the first potential V1 node of the DC component detection unit to adjust the flip threshold of the comparison signal.

[0020] Preferably, the compensation current generating unit includes:

[0021] An error conversion subunit, in response to the comparison signal, is used to generate an error current;

[0022] A current replication and distribution subunit, which is connected to the error conversion subunit, is used to replicate the error current;

[0023] A current direction conversion unit, which is connected to the current replication and distribution subunit, is used to convert the replicated current from the NMOS domain to the PMOS domain.

[0024] A common-source, common-gate output stage is connected to the current direction conversion unit to improve the accuracy of the output current and the output impedance;

[0025] A bias generation circuit, connected to the common-source cascode output stage, is used to provide a bias voltage;

[0026] The compensation current generation unit outputs a first compensation current to the input terminal of the transimpedance amplification core unit to extract a DC component from the input terminal, and outputs a second compensation current to the first potential V1 node of the DC component detection unit to pull down the first potential V1.

[0027] Preferably, the startup threshold set by the startup threshold setting unit satisfies the following relationship:

[0028]

[0029] in:

[0030] The input current threshold for triggering DC cancellation;

[0031] The feedback resistor value of the transimpedance amplifier core unit;

[0032] Let R2 be the resistance value.

[0033] The programmable set current value is output by the start-up threshold setting unit.

[0034] Preferably, the start-up threshold setting unit specifically includes:

[0035] The reference current generation subunit includes a current source I2;

[0036] Programmable current mirror subunit, including MOSFET M14 and n programmable mirror MOSFETs. and n switches ;

[0037] The gate and drain of the MOS transistor M14 are shorted and connected to the positive terminal of the current source I2, while the source is connected to the power supply voltage; the n programmable mirror MOS transistors The gates of all switches are connected to the gate of the MOS transistor M14, and the sources of all switches are connected to the power supply voltage; the n switches One end of each switch is connected to the drain of a programmable mirror MOS transistor, and the other ends of all switches are connected to the first potential node V1.

[0038] By controlling the number of times the switch is closed, the magnitude of the current injected into the first potential V1 node is adjusted, that is, the programmable current is adjusted. .

[0039] Preferably, the compensation current generation unit specifically includes:

[0040] The error conversion subunit includes an NMOS transistor M1 and a resistor R4. The gate of the NMOS transistor M1 receives the comparison signal, the source of the NMOS transistor M1 is grounded through the resistor R4, and the drain of the NMOS transistor M1 outputs the error current.

[0041] The current replication and distribution subunit includes a PMOS current mirror and an NMOS current mirror. The PMOS current mirror includes PMOS transistors M2 and M3. The gate and drain of PMOS transistor M2 are shorted and connected to the drain of NMOS transistor M1. The source of PMOS transistor M2 is connected to the power supply voltage VDD. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M2, and the source of PMOS transistor M3 is connected to the power supply voltage VDD. The NMOS current mirror includes NMOS transistors M4, M5, and M6. The gate and drain of NMOS transistor M4 are shorted and connected to the drain of PMOS transistor M3. The source of NMOS transistor M4 is grounded. The gate of NMOS transistor M5 is connected to the gate of NMOS transistor M4. The source of NMOS transistor M5 is grounded. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M4. The source of NMOS transistor M6 is grounded. The drain of NMOS transistor M6 is connected to the input terminal of the transimpedance amplifier core unit, which is used to draw DC current from the input terminal of the transimpedance amplifier core unit as the first compensation current.

[0042] A current direction conversion unit includes a PMOS transistor M7 and a PMOS transistor M8. The gate and drain of the PMOS transistor M7 are shorted and connected to the drain of the NMOS transistor M5, and are used to receive the NMOS domain current output by the NMOS transistor M5. The source of the PMOS transistor M7 is connected to the power supply voltage VDD. The gate of the PMOS transistor M8 is connected to the gate of the PMOS transistor M7, and the source of the PMOS transistor M8 is connected to the power supply voltage VDD, and are used to convert the NMOS domain current output by the NMOS transistor M5 into a PMOS domain current and output it.

[0043] The common-source common-gate output stage includes NMOS transistors M9, M10, M12, and M13. The gate and drain of NMOS transistor M9 are shorted and connected to the drain of PMOS transistor M8 to receive the PMOS domain current output by PMOS transistor M8. The source of NMOS transistor M9 is connected to the drain of PMOS transistor M12. The gate of NMOS transistor M10 is connected to the gate of NMOS transistor M9. The source of NMOS transistor M10 is connected to the drain of NMOS transistor M13. The drain of NMOS transistor M10 is connected to the first potential node V1 to pull down current from the first potential node V1 as the second compensation current. The source of PMOS transistor M12 is connected to the power supply voltage VDD, and the gate of PMOS transistor M12 is connected to the bias voltage. The source of NMOS transistor M13 is grounded, and the gate of NMOS transistor M13 is connected to the bias voltage.

[0044] The bias generation circuit includes a current source I3 and an NMOS transistor M11. The positive terminal of the current source I3 is connected to the power supply voltage VDD, and the negative terminal of the current source I3 is connected to the gate and drain of the NMOS transistor M11. The source of the NMOS transistor M11 is grounded, and the gate of the NMOS transistor M11 is also connected to the gate of the PMOS transistor M12 and the gate of the NMOS transistor M13, which is used to provide a bias voltage for the common source common gate output stage.

[0045] Preferably, the transimpedance amplification core unit includes:

[0046] Transistor Q1 has its base connected to the input terminal of the transimpedance amplifier core unit, its emitter grounded, and its collector connected to the power supply voltage VDD through resistor R1.

[0047] Transistor Q2 has its base connected to the collector of transistor Q1, the collector connected to the power supply voltage VDD, and its emitter serving as the output terminal.

[0048] The feedback resistor Rf is connected across the input terminal and the output terminal of the transimpedance amplifier core unit;

[0049] The current source I1 has its positive terminal connected to the emitter of the transistor Q2, and its negative terminal grounded.

[0050] Secondly, the programmable startup point DC elimination method for optical communication transimpedance amplifiers according to the present invention includes the following steps:

[0051] Detection steps: Detect the DC potential relationship between the input and output terminals of the transimpedance amplifier core unit and generate a comparison signal;

[0052] Threshold setting step: Inject a programmable current into the DC potential comparison node between the input and output terminals in a programmable manner to set the activation threshold of the DC cancellation function;

[0053] Compensation generation step: In response to the comparison signal, a first compensation current and a second compensation current are generated;

[0054] Compensation execution steps: Inject the first compensation current into the input terminal of the transimpedance amplifier core unit to extract the DC component, and inject the second compensation current into the comparator node to pull down the potential.

[0055] The beneficial effects of this invention are:

[0056] 1. This invention extracts the DC component from the input of the transimpedance amplifier core unit through a compensation current generation unit, effectively restoring the static operating conditions of the transimpedance amplifier and ensuring normal data communication. This solves the problem of conventional transimpedance amplifiers failing to operate normally under strong ambient light or high dark current conditions. Simultaneously, by controlling the number of programmable mirror transistors through the switch in the start-up threshold setting unit, the starting current value for DC cancellation can be programmed and controlled, flexibly adapting to the needs of different application scenarios. Users can set an appropriate start-up threshold digitally based on the actual ambient light intensity or dark current magnitude.

[0057] 2. This invention uses a comparator to detect the relationship between the input DC potential and the output reference potential. When they are equal, DC cancellation is automatically initiated, forming a negative feedback closed-loop control, which has the advantages of fast response speed and high stability. Simultaneously, the use of a common-source, common-gate output stage structure improves the output accuracy and output impedance of the compensation current, ensuring the accuracy and consistency of the DC cancellation effect.

[0058] 3. The circuit structure of this invention is simple and reliable. All components can be integrated into standard CMOS technology, making it easy to implement in the transimpedance amplifier chip of the optical communication receiver without adding extra peripheral components, which helps to improve integration and reduce system cost. Furthermore, this invention also provides a corresponding programmable start-point DC elimination method. Through four steps—detection, threshold setting, compensation generation, and compensation execution—it achieves automatic elimination of the input DC component. The method steps are clear and easy to implement in engineering. Attached Figure Description

[0059] Figure 1 This is a circuit diagram of the programmable start-up point DC cancellation circuit applied to the transimpedance amplifier of optical communication as described in this invention;

[0060] Figure 2 This is a simulation image of the conduction current of MOS transistor M6 in the compensation current generation unit when the input DC current changes according to the present invention.

[0061] Figure 3 This is a simulation image of the first potential V1 and the second potential V2 in the DC component detection unit when the input DC current changes according to the present invention;

[0062] Figure 4 This is a simulated image of the current through resistor R2 in the DC component detection unit when the input DC current changes according to the present invention. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0065] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0066] In optical communication receivers, photodiodes (PDs or APDs) convert weak optical signals into current signals, which are then converted into voltage signals by a transimpedance amplifier (TIA). However, due to non-ideal effects of photodiodes (such as dark current generated by reverse bias) or the influence of ambient light, the current signal received by the transimpedance amplifier typically contains a DC component. If the DC current signal is too large, the voltage drop across the feedback resistor Rf will prevent the internal transistors of the transimpedance amplifier from operating normally, resulting in AC signal distortion and data loss. This invention provides a solution to this problem.

[0067] Specific Implementation Method 1: The following is combined with... Figures 1 to 4 This embodiment describes a programmable start-point DC elimination circuit applied to an optical communication transimpedance amplifier, which mainly includes four parts: a transimpedance amplification core unit, a DC component detection unit, a start-up threshold setting unit, and a compensation current generation unit.

[0068] The transimpedance amplifier core unit receives an input current signal containing a DC component and converts it into an output voltage signal. A DC component detection unit is connected to both the input and output terminals of the transimpedance amplifier core unit, comparing the DC potential relationship between the input and output terminals and generating a comparison signal. A start-up threshold setting unit is connected to the DC component detection unit and programmably sets the start-up threshold for the DC cancellation function. A compensation current generation unit, controlled by the comparison signal, generates a first compensation current and a second compensation current. The first compensation current is output to the input terminal of the transimpedance amplifier core unit to extract the DC component, and the second compensation current is output to the DC component detection unit, thereby restoring the static operating point of the transimpedance amplifier core unit. The specific circuit structures of these four units are described in detail below.

[0069] First, let's introduce the specific implementation of the transimpedance amplifier core unit. The transimpedance amplifier core unit includes transistors Q1 and Q2, a feedback resistor Rf, a resistor R1, and a current source I1. The base of transistor Q1 is connected to the input terminal TZIN, its emitter is grounded, and its collector is connected to the power supply voltage VDD through resistor R1. The base of transistor Q2 is connected to the collector of transistor Q1, and its collector is connected to the power supply voltage VDD. Its emitter serves as the output terminal VOUT. The feedback resistor Rf is connected between the input terminal TZIN and the output terminal VOUT, and is used to determine the transimpedance gain. The positive terminal of the current source I1 is connected to the emitter of transistor Q2, and its negative terminal is grounded, used to provide bias current to transistor Q2.

[0070] The specific circuit of the DC component detection unit is described below. The DC component detection unit further includes three parts: a reference potential generation subunit, an input potential extraction subunit, and a comparison subunit.

[0071] The reference potential generation subunit is connected to the output of the transimpedance amplifier core unit and is used to generate a first potential V1 as a comparison reference. Specifically, the reference potential generation subunit includes a resistor R2, one end of which is connected to the output VOUT of the transimpedance amplifier core unit, and the other end generates the first potential V1, which is connected to the inverting input of the comparison subunit.

[0072] The input potential extraction subunit is connected to the input terminal of the transimpedance amplifier core unit and is used to extract the DC potential of the input terminal and output it as the second potential V2. Specifically, the input potential extraction subunit includes a resistor R3 and a capacitor C1, which together form a low-pass filter network. One end of the resistor R3 is connected to the input terminal TZIN of the transimpedance amplifier core unit, and the other end is connected to one end of the capacitor C1 to generate the second potential V2. The other end of the capacitor C1 is grounded. This low-pass filter network is used to filter out the AC component of the input terminal TZIN and extract its DC potential as the second potential V2. The second potential V2 is connected to the non-inverting input terminal of the comparator subunit.

[0073] The comparator subunit is used to compare the magnitudes of a first potential V1 and a second potential V2 and output a comparison signal. Specifically, the comparator subunit includes a comparator AMP1. The non-inverting input of comparator AMP1 is connected to the second potential V2, the inverting input is connected to the first potential V1, and the output is a comparison signal. When the first potential V1 is greater than the second potential V2, comparator AMP1 outputs a low level; when the first potential V1 is less than the second potential V2, comparator AMP1 outputs a high level; when the first potential V1 is equal to the second potential V2, the output of comparator AMP1 is at the flip-flop threshold.

[0074] The specific circuit of the startup threshold setting unit is described below. The startup threshold setting unit further includes two parts: a reference current generation subunit and a programmable current mirror subunit.

[0075] The reference current generation subunit is used to generate a reference current. Specifically, the reference current generation subunit includes a current source I2, the positive terminal of which is connected to the programmable current mirror subunit, and the negative terminal of which is grounded.

[0076] The programmable current mirror subunit is connected to the reference current generation subunit and is used to replicate the reference current at a programmable mirror ratio to generate a programmable set current. Specifically, the programmable current mirror subunit includes a MOSFET M14, n programmable mirror MOSFETs, and n switches. The gate and drain of MOSFET M14 are shorted and connected to the positive terminal of the current source I2. The source of MOSFET M14 is connected to the power supply voltage VDD, and its gate and drain are shorted to form a diode connection. The n programmable mirror MOSFETs are denoted as... The gates of these MOSFETs are all connected to the gate of MOSFET M14, and their sources are all connected to the power supply voltage VDD. Each programmable mirror MOSFET has a switch connected in series at its drain; that is, one end of switch S1 is connected to... The drain of the switch S2 is connected to one end. The drain of the switch Sn is connected to the drain of the switch Sn, and so on. The drain of the switch. The other end of all switches is connected to the first potential node V1.

[0077] By controlling the switch The number of closed connections allows adjustment of the programmable current injected into the first potential V1 node. The size. Due to the programmable current setting. The flow of current through resistor R2 changes the value of the first potential V1, thereby adjusting the toggling threshold of the comparator AMP1 output comparison signal. Therefore, the start-up threshold setting unit of this invention can programmatically set the start-up threshold of the DC cancellation function. Specifically, the more switches closed, the more programmable current is injected. The larger the threshold, the higher the start-up threshold. The higher the threshold, the fewer the number of closed switches, and the lower the activation threshold. The lower.

[0078] The specific circuit of the compensation current generation unit will be described in more detail. The compensation current generation unit further includes five parts: an error conversion subunit, a current replication and distribution subunit, a current direction conversion unit, a common source cascode output stage, and a bias generation circuit.

[0079] The error conversion subunit includes an NMOS transistor M1 and a resistor R4. The gate of NMOS transistor M1 receives the comparison signal output from comparator AMP1, the source of NMOS transistor M1 is grounded through resistor R4, and the drain of NMOS transistor M1 outputs the error current. Resistor R4 provides source negative feedback for NMOS transistor M1 to improve the linearity range of the error conversion.

[0080] The current replication and distribution subunit includes a PMOS current mirror and an NMOS current mirror. The PMOS current mirror is composed of PMOS transistors M2 and M3. The gate and drain of PMOS transistor M2 are shorted and connected to the drain of NMOS transistor M1. The source of PMOS transistor M2 is connected to the power supply voltage VDD. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M2, and the source of PMOS transistor M3 is also connected to the power supply voltage VDD. This PMOS current mirror is used to replicate the error current. The NMOS current mirror is composed of NMOS transistors M4, M5, and M6. The gate and drain of NMOS transistor M4 are shorted and connected to the drain of PMOS transistor M3. The source of NMOS transistor M4 is grounded. The gates of NMOS transistors M5 and M6 are both connected to the gate of NMOS transistor M4, and the sources of NMOS transistors M5 and M6 are both grounded. This NMOS current mirror is used to distribute the replicated current to at least two branches. The drain of NMOS transistor M6 is connected to the input terminal TZIN of the transimpedance amplifier core unit and one end of resistor R3, used to draw DC current from the input terminal TZIN as the first compensation current. It should be noted that the TZIN node, the drain of M6, and one end of R3 are connected together to form the same node.

[0081] The current direction conversion unit includes PMOS transistors M7 and M8. The gate and drain of PMOS transistor M7 are shorted and connected to the drain of NMOS transistor M5, used to receive the NMOS domain current output from NMOS transistor M5. The source of PMOS transistor M7 is connected to the power supply voltage VDD. The gate of PMOS transistor M8 is connected to the gate of PMOS transistor M7, and the source of PMOS transistor M8 is connected to the power supply voltage VDD, used to convert the NMOS domain current output from NMOS transistor M5 into a PMOS domain current and output it.

[0082] The common-source, common-gate output stage includes NMOS transistors M9, M10, M12, and M13. The gate and drain of NMOS transistor M9 are shorted and connected to the drain of PMOS transistor M8 to receive the PMOS domain current output from PMOS transistor M8. The source of NMOS transistor M9 is connected to the drain of PMOS transistor M12. The gate of NMOS transistor M10 is connected to the gate of NMOS transistor M9, and the source of NMOS transistor M10 is connected to the drain of NMOS transistor M13. The drain of NMOS transistor M10 is connected to a first potential node V1 to pull down current from the first potential node V1 as a second compensation current. The source of PMOS transistor M12 is connected to the power supply voltage VDD, and its gate is connected to the bias voltage. The source of NMOS transistor M13 is grounded, and its gate is connected to the bias voltage. This common-source, common-gate output stage is used to improve the accuracy of the output current and the output impedance.

[0083] The bias generation circuit includes a current source I3 and an NMOS transistor M11. The positive terminal of the current source I3 is connected to the power supply voltage VDD, and the negative terminal is connected to the gate and drain of the NMOS transistor M11. The source of the NMOS transistor M11 is grounded. The gate of the NMOS transistor M11 is also connected to the gate of the PMOS transistor M12 and the gate of the NMOS transistor M13, which is used to provide bias voltage for the common-source common-gate output stage.

[0084] The specific structure of the circuit of the present invention has been described in detail above. Its working principle will be explained below with reference to the accompanying drawings.

[0085] When there is no current at the input terminal TZIN or the current is sufficiently small, the programmable mirror MOS transistor in the programmable current mirror subunit... The programmable current generated by the current mirror The current flows through resistor R2 to the output terminal VOUT. At this time, the first potential V1 is greater than the second potential V2. The comparator AMP1 outputs a low level, the NMOS transistor M1 is in the off state, and the compensation current generation unit does not work.

[0086] As the DC current I input to the TZIN terminal gradually increases, this DC current generates a voltage drop across the feedback resistor Rf, causing the output VOUT to decrease, which in turn lowers the first potential V1. Simultaneously, the DC potential at the TZIN terminal is also reflected in the second potential V2 through a low-pass filter network composed of resistor R3 and capacitor C1. When the input DC current reaches a point that satisfies the following relationship:

[0087]

[0088] in:

[0089] The input current threshold for triggering DC cancellation;

[0090] The feedback resistor value of the transimpedance amplifier core unit;

[0091] Let R2 be the resistance value.

[0092] The programmable set current value is output by the start-up threshold setting unit.

[0093] When the first potential V1 equals the second potential V2, the output of comparator AMP1 begins to increase, and NMOS transistor M1 transitions from the off state to the on state. After passing through the current replication and distribution subunit, the current direction conversion unit, and the common-source common-gate output stage, the error current draws DC current from the input terminal TZIN through NMOS transistor M6 as the first compensation current, and pulls down current from the first potential V1 node through NMOS transistor M10 as the second compensation current, thus forming a negative feedback loop. This eliminates the DC component at the input terminal TZIN and restores the static operating point of the transimpedance amplifier core unit.

[0094] Figures 2 to 4 Simulation results of the present invention are presented. The simulation conditions are: the resistance value of the feedback resistor Rf... Choose 320Ω or 3021Ω, switch The initial current flowing through the controlled current mirror to resistor R2 is 27 μA. According to the above formula, when... =320Ω When the resistance is 3021Ω, the activation threshold is reached. The theoretical value is 255 μA. Figure 2 The simulation curve of the NMOS transistor M6 conduction current as a function of the input DC current is shown. Figure 3 Simulated curves showing the variation of the first potential V1 and the second potential V2 with the input DC current are displayed. Figure 4 The simulation curve of the current across resistor R2 as a function of the input DC current is displayed. The simulation results show that the actual start-up threshold is 258 μA, which differs from the theoretical value by only 3 μA, verifying the effectiveness of the invention.

[0095] Compared with existing technologies, this invention has the following advantages: First, by extracting the DC component from the input terminal through the compensation current generation unit, the static operating conditions of the transimpedance amplifier can be restored, ensuring normal data communication and solving the problem that conventional transimpedance amplifiers cannot operate normally under strong ambient light or high dark current conditions. Second, by controlling the number of mirror transistors through the switch in the threshold setting unit, the starting current value of DC cancellation can be programmed and controlled, flexibly adapting to the needs of different application scenarios. Third, the circuit structure of this invention is simple and reliable, and easy to integrate into the transimpedance amplifier chip of the optical communication receiver.

[0096] Specific Implementation Method Two: The present invention also provides a programmable start-up point DC elimination method for optical communication transimpedance amplifiers. This method can be implemented based on the circuit described in Specific Implementation Method One above, but is not limited to this circuit structure.

[0097] The method includes the following steps.

[0098] Detection steps: Detect the DC potential relationship between the input and output terminals of the transimpedance amplifier core unit and generate a comparison signal. Specifically, the voltage signal at the output terminal is extracted by the reference potential generation subunit to generate a first potential V1, and the DC potential at the input terminal is extracted by the input potential extraction subunit to generate a second potential V2. The comparison subunit compares the magnitudes of the first potential V1 and the second potential V2 to generate a comparison signal. When the first potential V1 is greater than the second potential V2, the comparison signal is low; when the first potential V1 is less than the second potential V2, the comparison signal is high; when the first potential V1 is equal to the second potential V2, the comparison signal is at the flip-flop threshold.

[0099] Threshold setting steps: A programmable current is injected into the DC potential comparison node between the input and output terminals in a programmable manner to set the activation threshold of the DC cancellation function. Specifically, a reference current is generated by a reference current generation subunit, and the reference current is replicated by a programmable current mirroring subunit at a programmable mirror ratio to generate the programmable set current. By controlling the number of closed switches in the programmable current mirror subunit, the programmable set current injected into the first potential V1 node is adjusted. The size of the programmable current setting. The current flows through resistor R2, changing the value of the first potential V1, thereby adjusting the toggling threshold of the comparison signal. The more switches are closed, the more programmable current is injected. The larger the threshold, the higher the start-up threshold. The higher the threshold, the fewer the number of closed switches, and the lower the activation threshold. The lower.

[0100] Compensation generation steps: In response to the comparison signal, a first compensation current and a second compensation current are generated. Specifically, when the comparison signal is high, the error conversion subunit generates an error current in response to the comparison signal. The current replication and distribution subunit, the current direction conversion unit, and the cascode output stage replicate, convert, and distribute this error current to generate the first compensation current and the second compensation current. The first compensation current is used to extract the DC component from the input terminal, and the second compensation current is used to pull down the potential of the DC potential comparison node.

[0101] The compensation process involves injecting a first compensation current into the input terminal of the transimpedance amplifier core unit to extract the DC component, and injecting a second compensation current into the comparator node at a pull-down potential. Specifically, the first compensation current draws DC current from the input terminal TZIN through NMOS transistor M6, and this current flows to ground; the second compensation current pulls down the current from the first potential V1 node through NMOS transistor M10, and this current also flows to ground. The two compensation currents work together to form a negative feedback loop, eliminating the DC component at the input terminal TZIN and restoring the static operating point of the transimpedance amplifier core unit.

[0102] The above detection steps, threshold setting steps, compensation generation steps, and compensation execution steps are executed consecutively. When the input DC current exceeds the start-up threshold set by the programmable current setting, the circuit automatically starts the DC cancellation function to eliminate the DC component in the input terminal, so that the transimpedance amplifier core unit returns to normal working state.

[0103] Using the above method, the DC cancellation activation threshold can be flexibly set according to actual application requirements. When the ambient light is strong or the dark current is large, the activation threshold can be increased to improve anti-interference capability; when a more sensitive DC cancellation response is required, the activation threshold can be decreased. This method works in conjunction with the circuit structure in Specific Implementation Method 1 to jointly realize the programmable activation point DC cancellation function.

[0104] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A programmable start point DC cancellation circuit applied to a transimpedance amplifier of optical communication, characterized in that, include: The transimpedance amplifier core unit receives an input current signal containing a DC component and converts the input current signal into an output voltage signal; A DC component detection unit is connected to the input and output terminals of the transimpedance amplification core unit. It is used to compare the DC potential relationship between the input and output terminals of the transimpedance amplification core unit and generate a comparison signal. A threshold setting unit is connected to the DC component detection unit and is used to programmatically set the threshold for the DC elimination function. The compensation current generation unit, controlled by the comparison signal, generates a first compensation current and a second compensation current. The first compensation current is output to the input terminal of the transimpedance amplification core unit to extract the DC component, and the second compensation current is output to the DC component detection unit, thereby restoring the static operating point of the transimpedance amplification core unit.

2. The programmable start point DC cancellation circuit applied to the transimpedance amplifier of optical communication according to claim 1, characterized in that, The DC component detection unit includes: A reference potential generation subunit is connected to the output terminal of the transimpedance amplification core unit. The reference potential generation subunit includes a resistor R2, which is used to generate a first potential V1 through the resistor R2. The input potential extraction subunit is connected to the input terminal of the transimpedance amplification core unit and is used to extract the DC potential of the input terminal of the transimpedance amplification core unit and output it as the second potential V2. The comparison subunit is implemented using comparator AMP1. The non-inverting input of AMP1 is connected to the second potential V2, and the inverting input of AMP1 is connected to the first potential V1. It is used to compare the magnitudes of the two and output the comparison signal.

3. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 2, characterized in that, The input potential extraction subunit includes a low-pass filter network, which includes a resistor R3 and a capacitor C1. One end of the resistor R3 is connected to the input of the transimpedance amplification core unit, and the other end is connected to one end of the capacitor C1 and outputs the second potential V2. The other end of the capacitor C1 is grounded.

4. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 2, characterized in that, The start-up threshold setting unit includes: The reference current generation subunit is used to generate a reference current; A programmable current mirroring subunit, connected to the reference current generating subunit, is used to replicate the reference current at a programmable mirroring ratio to generate a programmable set current. The programmable current is injected into the first potential V1 node of the DC component detection unit to adjust the flip threshold of the comparison signal.

5. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 1, characterized in that, The compensation current generation unit includes: An error conversion subunit, in response to the comparison signal, is used to generate an error current; A current replication and distribution subunit, which is connected to the error conversion subunit, is used to replicate the error current; A current direction conversion unit, which is connected to the current replication and distribution subunit, is used to convert the replicated current from the NMOS domain to the PMOS domain. A common-source, common-gate output stage is connected to the current direction conversion unit to improve the accuracy of the output current and the output impedance; A bias generation circuit, connected to the common-source cascode output stage, is used to provide a bias voltage; The compensation current generation unit outputs a first compensation current to the input terminal of the transimpedance amplification core unit to extract a DC component from the input terminal, and outputs a second compensation current to the first potential V1 node of the DC component detection unit to pull down the first potential V1.

6. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 4, characterized in that, The startup threshold set by the startup threshold setting unit satisfies the following relationship: in: The input current threshold for triggering DC cancellation; The feedback resistor value of the transimpedance amplifier core unit; Let R2 be the resistance value. The programmable set current value is output by the start-up threshold setting unit.

7. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 6, characterized in that, The startup threshold setting unit specifically includes: The reference current generation subunit includes a current source I2; Programmable current mirror subunit, including MOSFET M14 and n programmable mirror MOSFETs. and n switches ; The gate and drain of the MOS transistor M14 are shorted and connected to the positive terminal of the current source I2, while the source is connected to the power supply voltage; the n programmable mirror MOS transistors The gates of all switches are connected to the gate of the MOS transistor M14, and the sources of all switches are connected to the power supply voltage; the n switches One end of each switch is connected to the drain of a programmable mirror MOS transistor, and the other ends of all switches are connected to the first potential node V1. By controlling the number of times the switch is closed, the magnitude of the current injected into the first potential V1 node is adjusted, that is, the programmable current is adjusted. .

8. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 5, characterized in that, The compensation current generation unit specifically includes: The error conversion subunit includes an NMOS transistor M1 and a resistor R4. The gate of the NMOS transistor M1 receives the comparison signal, the source of the NMOS transistor M1 is grounded through the resistor R4, and the drain of the NMOS transistor M1 outputs the error current. The current replication and distribution subunit includes a PMOS current mirror and an NMOS current mirror. The PMOS current mirror includes PMOS transistors M2 and M3. The gate and drain of PMOS transistor M2 are shorted and connected to the drain of NMOS transistor M1. The source of PMOS transistor M2 is connected to the power supply voltage VDD. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M2, and the source of PMOS transistor M3 is connected to the power supply voltage VDD. The NMOS current mirror includes NMOS transistors M4, M5, and M6. The gate and drain of NMOS transistor M4 are shorted and connected to the drain of PMOS transistor M3. The source of NMOS transistor M4 is grounded. The gate of NMOS transistor M5 is connected to the gate of NMOS transistor M4. The source of NMOS transistor M5 is grounded. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M4. The source of NMOS transistor M6 is grounded. The drain of NMOS transistor M6 is connected to the input terminal of the transimpedance amplifier core unit, which is used to draw DC current from the input terminal of the transimpedance amplifier core unit as the first compensation current. A current direction conversion unit includes a PMOS transistor M7 and a PMOS transistor M8. The gate and drain of the PMOS transistor M7 are shorted and connected to the drain of the NMOS transistor M5, and are used to receive the NMOS domain current output by the NMOS transistor M5. The source of the PMOS transistor M7 is connected to the power supply voltage VDD. The gate of the PMOS transistor M8 is connected to the gate of the PMOS transistor M7, and the source of the PMOS transistor M8 is connected to the power supply voltage VDD, and are used to convert the NMOS domain current output by the NMOS transistor M5 into a PMOS domain current and output it. The common-source common-gate output stage includes NMOS transistors M9, M10, M12, and M13. The gate and drain of NMOS transistor M9 are shorted and connected to the drain of PMOS transistor M8 to receive the PMOS domain current output by PMOS transistor M8. The source of NMOS transistor M9 is connected to the drain of PMOS transistor M12. The gate of NMOS transistor M10 is connected to the gate of NMOS transistor M9. The source of NMOS transistor M10 is connected to the drain of NMOS transistor M13. The drain of NMOS transistor M10 is connected to the first potential node V1 to pull down current from the first potential node V1 as the second compensation current. The source of PMOS transistor M12 is connected to the power supply voltage VDD, and the gate of PMOS transistor M12 is connected to the bias voltage. The source of NMOS transistor M13 is grounded, and the gate of NMOS transistor M13 is connected to the bias voltage. The bias generation circuit includes a current source I3 and an NMOS transistor M11. The positive terminal of the current source I3 is connected to the power supply voltage VDD, and the negative terminal of the current source I3 is connected to the gate and drain of the NMOS transistor M11. The source of the NMOS transistor M11 is grounded, and the gate of the NMOS transistor M11 is also connected to the gate of the PMOS transistor M12 and the gate of the NMOS transistor M13, which is used to provide a bias voltage for the common source common gate output stage.

9. The programmable start-up point DC cancellation circuit for an optical communication transimpedance amplifier according to claim 1, characterized in that, The transimpedance amplification core unit includes: Transistor Q1 has its base connected to the input terminal of the transimpedance amplifier core unit, its emitter grounded, and its collector connected to the power supply voltage VDD through resistor R1. Transistor Q2 has its base connected to the collector of transistor Q1, the collector connected to the power supply voltage VDD, and its emitter serving as the output terminal. The feedback resistor Rf is connected across the input terminal and the output terminal of the transimpedance amplifier core unit; The current source I1 has its positive terminal connected to the emitter of the transistor Q2, and its negative terminal grounded.

10. A programmable start-up point DC elimination method applied to transimpedance amplifiers in optical communication, characterized in that, Includes the following steps: Detection steps: Detect the DC potential relationship between the input and output terminals of the transimpedance amplifier core unit and generate a comparison signal; Threshold setting step: Inject a programmable current into the DC potential comparison node between the input and output terminals in a programmable manner to set the activation threshold of the DC cancellation function; Compensation generation step: In response to the comparison signal, a first compensation current and a second compensation current are generated; Compensation execution steps: Inject the first compensation current into the input terminal of the transimpedance amplifier core unit to extract the DC component, and inject the second compensation current into the comparator node to pull down the potential.

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