A base current cancellation circuit

Abstract

This application provides a base current elimination circuit. Applied to the field of semiconductor integrated circuit design, it includes: a differential input module comprising: a first transistor and a second transistor, wherein the first transistor is an inverting input transistor and the second transistor is a non-inverting input transistor; a base current compensation module comprising: a third transistor and a fourth transistor, wherein the third and second transistors are identical transistors, and the fourth transistor and the first transistor are identical transistors; a voltage clamping module for limiting the collector-emitter junction voltage drop of the third and fourth transistors; and a current replication module comprising: a first current mirror structure and a second current mirror structure, wherein the first current mirror structure replicates the base current of the third transistor, and the second current mirror structure replicates the base current of the fourth transistor. This application achieves higher precision base current elimination while ensuring that other amplifier performance is not affected.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit design, and in particular to a base current elimination circuit. Background Technology

[0002] As an indispensable part of most circuits, the performance of amplifiers largely determines the performance of the entire circuit or even the system. With the development of electronic technology, photoelectric detection, sensors, and medical electronic equipment are increasingly widely used. In the processing of weak signals, if the input bias current is too high, it will generate a large voltage drop for high source impedance devices, severely attenuating the useful signal, or even submerging the useful signal in error. Furthermore, with the development of modern precision electronic systems, the required signal accuracy is increasing, placing more stringent demands on the amplifier's input bias current and other performance indicators. For amplifiers using bipolar transistor inputs, the input bias current generally consists of the base current and is closely related to the collector current. To achieve ultra-low input bias current, methods to reduce the input bias current must be employed, typically using a base current cancellation structure.

[0003] Existing base current elimination methods typically employ a standard NPN transistor to generate a compensation current equal in magnitude but opposite in direction to the base current source of the input stage tail current source. This compensation current is then injected into each input stage to reduce the input bias current. However, due to the relatively small current amplification factor (β) of a standard NPN transistor, it is insufficient to significantly reduce the base current amplitude initially. Furthermore, using only a single NPN transistor makes it difficult to precisely control the compensation current in each path, failing to eliminate the increased input offset current caused by other circuit mismatches. In addition, existing base current elimination structures do not utilize current mirrors for precise current control, and their own input stages and the externally added compensation NPN transistor may introduce additional mismatches, negatively impacting the amplifier's input bias current and input offset current. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a base current elimination circuit, comprising:

[0005] A differential input module, comprising: a first transistor and a second transistor, wherein the first transistor is an inverting input transistor and the second transistor is a non-inverting input transistor;

[0006] A base current compensation module, comprising: a third transistor and a fourth transistor, wherein the third transistor and the second transistor are identical transistors, and the fourth transistor and the first transistor are identical transistors;

[0007] A voltage clamping module, comprising a fifth transistor, a sixth transistor, and a seventh transistor, wherein the voltage clamping module is used to limit the collector-emitter junction voltage drop of the third transistor and the fourth transistor;

[0008] A current replication module includes a first current mirror structure and a second current mirror structure, wherein the first current mirror structure is used to replicate the base current of the third transistor, and the second current mirror structure is used to replicate the base current of the fourth transistor.

[0009] Optionally, the base current elimination circuit further includes a third current source, wherein the emitter of the first transistor and the emitter of the second transistor are connected to the third current source.

[0010] Optionally, the first transistor and the second transistor are NPN transistors.

[0011] Optionally, the base current elimination circuit further includes a first current source and a second current source, the collector of the third transistor and the collector of the fourth transistor are connected, the emitter of the third transistor is connected to the first current source, and the emitter of the fourth transistor is connected to the second current source.

[0012] Optionally, the first current mirror structure includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, and the second current mirror structure includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor.

[0013] Optionally, the input terminal of the first current mirror structure is connected to the base of the third transistor, the output terminal of the first current mirror structure is connected to the base of the second transistor, the input terminal of the second current mirror structure is connected to the base of the fourth transistor, and the output terminal of the second current mirror structure is connected to the base of the first transistor.

[0014] Optionally, the emitter of the fifth transistor is connected to the emitter of the sixth transistor, the collector of the fifth transistor is connected to the base of the fifth transistor, the base of the sixth transistor is connected to the emitter of the third transistor, the collector of the sixth transistor is connected to a negative power supply, the emitter of the seventh transistor is connected to the emitter of the sixth transistor, the base of the seventh transistor is connected to the emitter of the fourth transistor, and the collector of the seventh transistor is connected to a negative power supply.

[0015] Optionally, the base of the eighth transistor is connected to the base of the eleventh transistor, the emitter of the eighth transistor is connected to the collector of the ninth transistor, the collector of the eighth transistor is connected to the base of the second transistor, the base and collector of the ninth transistor are connected, the emitter of the ninth transistor is connected to a positive power supply, the emitter of the tenth transistor is connected to the emitter of the ninth transistor, the base of the tenth transistor is connected to the base of the tenth transistor, the collector of the tenth transistor is connected to the emitter of the eleventh transistor, the base and collector of the eleventh transistor are connected, and the collector of the eleventh transistor is connected to the base of the third transistor.

[0016] Optionally, the base of the twelfth transistor is connected to the base of the fifteenth transistor, the emitter of the twelfth transistor is connected to the collector of the thirteenth transistor, the collector of the twelfth transistor is connected to the base of the first transistor, the base and collector of the thirteenth transistor are connected, the emitter of the thirteenth transistor is connected to the emitter of the tenth transistor, the emitter of the fourteenth transistor is connected to the emitter of the thirteenth transistor, the base of the fourteenth transistor is connected to the base of the thirteenth transistor, the collector of the fourteenth transistor is connected to the emitter of the fifteenth transistor, the base and collector of the fifteenth transistor are connected, and the collector of the fifteenth transistor is connected to the base of the fourth transistor.

[0017] This application provides a base current elimination circuit, including: a differential input module, a base current compensation module, a voltage clamping module, and a current replication module. The differential input module includes a first transistor and a second transistor, where the first transistor is an inverting input and the second transistor is a non-inverting input. The base current compensation module includes a third transistor and a fourth transistor, where the third and second transistors are identical, and the fourth transistor and the first transistor are identical. The voltage clamping module includes a fifth transistor, a sixth transistor, and a seventh transistor, used to limit the collector-emitter junction voltage drop of the third and fourth transistors. The current replication module includes a first current mirror structure and a second current mirror structure, where the first current mirror structure replicates the base current of the third transistor, and the second current mirror structure replicates the base current of the fourth transistor. This invention, while maintaining other amplifier specifications unaffected, requires only a small number of transistors, resulting in a simple circuit structure. It can reduce the amplifier's input bias current and input offset current to the pA level and can independently adjust the current at the non-inverting or inverting input terminals, reducing the impact of various errors on the input bias current. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram of a base current elimination circuit provided in an embodiment of this application.

[0020] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0023] In this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of a base current elimination circuit provided in an embodiment of this application. Figure 1As shown, this embodiment provides a base current elimination circuit, including: a differential input module 1, a base current compensation module 2, a voltage clamping module 3, and a current replication module 4.

[0026] Specifically, the differential input module 1 includes: a first transistor Q1 and a second transistor Q2, wherein the first transistor Q1 is an inverting input transistor and the second transistor Q2 is a non-inverting input transistor, and both the first transistor Q1 and the second transistor Q2 are NPN transistors.

[0027] The base current compensation module 2 includes a third transistor Q34 and a fourth transistor Q35. The third transistor Q34 and the second transistor Q2 are identical transistors, and the fourth transistor Q35 and the first transistor Q1 are identical transistors.

[0028] The voltage clamping module 3 includes a fifth transistor Q41, a sixth transistor Q43, and a seventh transistor Q44. The voltage clamping module 3 is used to limit the collector-emitter junction voltage drop of the third transistor Q34 and the fourth transistor Q35.

[0029] In an optional embodiment, the emitter of the fifth transistor Q41 is connected to the emitter of the sixth transistor Q43, the collector of the fifth transistor Q41 is connected to the base of the sixth transistor Q43, the base of the sixth transistor Q43 is connected to the emitter of the third transistor Q34, and the collector of the sixth transistor Q43 is connected to the negative power supply V. EE The emitter of the seventh transistor Q44 is connected to the emitter of the sixth transistor Q43, the base of the seventh transistor Q44 is connected to the emitter of the fourth transistor Q35, and the collector of the seventh transistor Q44 is connected to the negative power supply V. EE .

[0030] The current replication module 4 includes a first current mirror structure and a second current mirror structure. The first current mirror structure is used to replicate the base current of the third transistor Q34, and the second current mirror structure is used to replicate the base current of the fourth transistor Q35.

[0031] In an optional embodiment, the first current mirror structure includes: an eighth transistor Q45, a ninth transistor Q47, a tenth transistor Q50, and an eleventh transistor Q52, and the second current mirror structure includes: a twelfth transistor Q46, a thirteenth transistor Q48, a fourteenth transistor Q51, and a fifteenth transistor Q53.

[0032] The input terminal of the first current mirror structure is connected to the base of the third transistor Q34, and the output terminal of the first current mirror structure is connected to the base of the second transistor Q2. Specifically, the base of the eighth transistor Q45 is connected to the base of the eleventh transistor Q52, the emitter of the eighth transistor Q45 is connected to the collector of the ninth transistor Q47, the collector of the eighth transistor Q45 is connected to the base of the second transistor Q2, the base and collector of the ninth transistor Q47 are connected, and the emitter of the ninth transistor Q47 is connected to the positive power supply V. CC The emitter of the tenth transistor Q50 is connected to the emitter of the ninth transistor Q47, the base of the tenth transistor Q50 is connected to the base of the tenth transistor Q50, the collector of the tenth transistor Q50 is connected to the emitter of the eleventh transistor Q52, the base of the eleventh transistor Q52 is connected to the collector of the eleventh transistor, and the collector of the eleventh transistor Q52 is connected to the base of the third transistor Q34.

[0033] The input terminal of the second current mirror structure is connected to the base of the fourth transistor Q35, and the output terminal of the second current mirror structure is connected to the base of the first transistor Q1. Specifically, the base of the twelfth transistor Q46 is connected to the base of the fifteenth transistor Q53, the emitter of the twelfth transistor Q46 is connected to the collector of the thirteenth transistor Q48, the collector of the twelfth transistor Q46 is connected to the base of the first transistor Q1, the base and collector of the thirteenth transistor Q48 are connected, the emitter of the thirteenth transistor Q48 is connected to the emitter of the tenth transistor Q50, the emitter of the fourteenth transistor Q51 is connected to the emitter of the thirteenth transistor Q48, the base of the fourteenth transistor Q51 is connected to the base of the thirteenth transistor Q48, the collector of the fourteenth transistor Q51 is connected to the emitter of the fifteenth transistor Q53, the base and collector of the fifteenth transistor Q53 are connected, and the collector of the fifteenth transistor Q53 is connected to the base of the fourth transistor Q35.

[0034] Furthermore, the base current elimination circuit also includes a third current source I3, with the emitter of the first transistor Q1 and the emitter of the second transistor Q2 connected to the third current source I3.

[0035] Furthermore, the base current elimination circuit also includes a first current source I1 and a second current source I2, the collector of the third transistor Q34 and the collector of the fourth transistor Q35 are connected, the emitter of the third transistor Q34 is connected to the first current source I1, and the emitter of the fourth transistor Q35 is connected to the second current source I2.

[0036] The working principle of this invention is as follows:

[0037] The input structure of the base current elimination section is a differential pair composed of NPN transistors Q1 and Q2. Q34 and Q35 are identical to the differential input pair Q1 and Q2. Two independent high-precision current mirrors are used: one current mirror is composed of Q47, Q50, Q45, and Q52, and the other current mirror is composed of Q48, Q51, Q46, and Q53. Q2 is one of the NPN differential input transistors, and its collector-emitter junction voltage drop is limited by external circuitry. For the base current at the non-inverting input terminal, Q34 is an NPN transistor with the exact same operating state as input transistor Q2. The voltage of Q2 is limited by a voltage clamping module composed of Q41, Q43, and Q44 to ensure that the collector-emitter junction voltage drops of Q34 and Q2 are the same. By adjusting the first current source I1, the second current source I2, and the third current source I3, I3 = 2I, and I1 = I2 = I, to ensure that the base current and collector current of Q34 and Q2 are exactly the same. If Q2 is a standard NPN transistor, its collector current is I. C If the current amplification factor is β, then the base current of Q2 is 1 / β times I. C , that is I B_Q2 =1 / β I C The base current I of Q34 B Also 1 / β I C Furthermore, this current is replicated through a current mirror composed of Q45, Q47, Q50, and Q52, and then enters the non-inverting input terminal through Q45, interacting with the base current I of Q2. B_Q2 They cancel each other out. Ideally, the current flowing through Q45 to the non-inverting input cancels out the base current I of Q2. B_Q2 The currents are the same in magnitude but opposite in direction, completely canceling each other out. Externally, the current I seen at the non-inverting input terminal is... B+ =0. Similarly, Q35 functions similarly to Q34, and the current mirror composed of Q48, Q51, Q46, and Q53 is similar to the current mirror composed of Q47, Q50, Q45, and Q52. Externally, the current I at the inverting input terminal is observed to be 0. B- =0. The final input bias current depends on the dimensions of Q34, Q35 and Q2, Q1, the current amplification factor β, the operating current, the matching degree of the collector-emitter junction voltage drop, and the matching degree of the current mirror.

[0038] Furthermore, when the non-inverting input transistor Q1 and the inverting input transistor Q2 are super-β NPN transistors, the base current I of Q1 and Q2... B_Q2 =1 / β S I C , where β S I is the current amplification factor of the super-β NPN transistor. CThe collector current is given by a current amplification factor of β. S At this time, β S >>β, therefore I B_Q2 It will decrease significantly.

[0039] If the β of a standard NPN transistor is 200, then the β of a super-β NPN transistor is... S The value is 2000. Under normal operation, the collector current I of input transistors Q1 and Q2 is... C I C =100μA. When using a common NPN transistor, taking the non-inverting input terminal as an example, I B_Q2 =1 / β I C Then the base current I of Q2 B_Q2 The input bias current of the simulated amplifier can be reduced to within 5nA by adding the aforementioned base current cancellation structure, resulting in a current of 500nA. Furthermore, compared to a standard NPN transistor, if a super-β NPN transistor is used, again taking the non-inverting input as an example, I... B_Q2 =1 / β I C Then the base current I of Q2 B_Q2 The base current I is 50nA. B_Q2 This directly reduces the current by a factor of 10. Combined with the aforementioned base current elimination structure, and by replacing Q34 and Q35 with the same super-β NPN transistors as Q1 and Q2, simulation results show that the input bias current can be reduced to below 500pA, achieving the goal of reducing the input bias current to the pA level.

[0040] Furthermore, Q34 is an NPN transistor identical to Q2 at the non-inverting input terminal, and its base current is eliminated by a current mirror composed of Q45, Q47, Q50, and Q52. Q35 is an NPN transistor identical to Q1 at the non-inverting input terminal, and its base current is eliminated by a current mirror composed of Q48, Q51, Q46, and Q53. The base current elimination at the non-inverting and inverting input terminals is completely independent and does not interfere with each other. This allows for individual adjustment of one of the inputs, corrected based on simulation or actual measured values ​​from the finished product. When the amplifier itself is asymmetrical or there are manufacturing deviations leading to transistor mismatch, it will not affect the current at the other input terminal, thus halving the impact on the overall amplifier bias current.

[0041] The base current elimination circuit proposed in this application includes: a differential input module, a base current compensation module, a voltage clamping module, and a current replication module. The differential input module includes a first transistor and a second transistor, where the first transistor is the inverting input and the second transistor is the non-inverting input. The base current compensation module includes a third transistor and a fourth transistor, where the third and second transistors are identical, and the fourth transistor and the first transistor are identical. The voltage clamping module includes a fifth transistor, a sixth transistor, and a seventh transistor, used to limit the collector-emitter junction voltage drop of the third and fourth transistors. The current replication module includes a first current mirror structure and a second current mirror structure, where the first current mirror structure replicates the base current of the third transistor, and the second current mirror structure replicates the base current of the fourth transistor. This invention, while maintaining other amplifier specifications unaffected, requires only a small number of transistors, resulting in a simple circuit structure. It can reduce the amplifier's input bias current and input offset current to the pA level and can independently adjust the current at the non-inverting or inverting input, reducing the impact of various errors on the input bias current.

[0042] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0043] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A base current elimination circuit, characterized in that, include: A differential input module, comprising: a first transistor and a second transistor, wherein the first transistor is an inverting input transistor and the second transistor is a non-inverting input transistor; A base current compensation module, comprising: a third transistor and a fourth transistor, wherein the third transistor and the second transistor are identical transistors, and the fourth transistor and the first transistor are identical transistors; A voltage clamping module, comprising a fifth transistor, a sixth transistor, and a seventh transistor, wherein the voltage clamping module is used to limit the collector-emitter junction voltage drop of the third transistor and the fourth transistor; A current replication module includes a first current mirror structure and a second current mirror structure, wherein the first current mirror structure is used to replicate the base current of the third transistor, and the second current mirror structure is used to replicate the base current of the fourth transistor.

2. The base current elimination circuit according to claim 1, characterized in that, The base current elimination circuit further includes a third current source, and the emitters of the first transistor and the second transistor are connected to the third current source.

3. The base current elimination circuit according to claim 1, characterized in that, The first transistor and the second transistor are NPN transistors.

4. The base current elimination circuit according to claim 1, characterized in that, The base current elimination circuit further includes a first current source and a second current source. The collector of the third transistor and the collector of the fourth transistor are connected. The emitter of the third transistor is connected to the first current source, and the emitter of the fourth transistor is connected to the second current source.

5. The base current elimination circuit according to claim 1, characterized in that, The first current mirror structure includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, and the second current mirror structure includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor.

6. The base current elimination circuit according to claim 1, characterized in that, The input terminal of the first current mirror structure is connected to the base of the third transistor, the output terminal of the first current mirror structure is connected to the base of the second transistor, the input terminal of the second current mirror structure is connected to the base of the fourth transistor, and the output terminal of the second current mirror structure is connected to the base of the first transistor.

7. The base current elimination circuit according to claim 1, characterized in that, The emitter of the fifth transistor is connected to the emitter of the sixth transistor, the collector of the fifth transistor is connected to the base of the fifth transistor, the base of the sixth transistor is connected to the emitter of the third transistor, the collector of the sixth transistor is connected to a negative power supply, the emitter of the seventh transistor is connected to the emitter of the sixth transistor, the base of the seventh transistor is connected to the emitter of the fourth transistor, and the collector of the seventh transistor is connected to a negative power supply.

8. The base current elimination circuit according to claim 1, characterized in that, The base of the eighth transistor is connected to the base of the eleventh transistor, the emitter of the eighth transistor is connected to the collector of the ninth transistor, the collector of the eighth transistor is connected to the base of the second transistor, the base and collector of the ninth transistor are connected, the emitter of the ninth transistor is connected to a positive power supply, the emitter of the tenth transistor is connected to the emitter of the ninth transistor, the base of the tenth transistor is connected to the base of the tenth transistor, the collector of the tenth transistor is connected to the emitter of the eleventh transistor, the base and collector of the eleventh transistor are connected, and the collector of the eleventh transistor is connected to the base of the third transistor.

9. A base current elimination circuit according to claim 1, characterized in that, The base of the twelfth transistor is connected to the base of the fifteenth transistor, the emitter of the twelfth transistor is connected to the collector of the thirteenth transistor, the collector of the twelfth transistor is connected to the base of the first transistor, the base and collector of the thirteenth transistor are connected, the emitter of the thirteenth transistor is connected to the emitter of the tenth transistor, the emitter of the fourteenth transistor is connected to the emitter of the thirteenth transistor, the base of the fourteenth transistor is connected to the base of the thirteenth transistor, the collector of the fourteenth transistor is connected to the emitter of the fifteenth transistor, the base and collector of the fifteenth transistor are connected, and the collector of the fifteenth transistor is connected to the base of the fourth transistor.

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