Circuit for txldo overshoot suppression and radio frequency transceiver

Abstract

This application relates to the field of integrated circuit design technology, and discloses a circuit and RF transceiver for TXLDO overshoot suppression. The circuit for TXLDO overshoot suppression includes: a timing-linked detection module configured to detect the load current of the TXLDO, determine the rate of change of the load current, compare the rate of change of the current with a preset threshold, and output a comparison signal; the preset threshold is dynamically determined according to the operating timing of the TXLDO; a drive adjustment module configured to dynamically output a drive signal for the amplifier of the TXLDO based on the comparison signal, so as to adjust the drive capability of the amplifier; and a noise isolation module configured to block noise coupling of the drive signal to the TXLDO. This application can achieve TXLDO overshoot suppression while ensuring system response speed.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, for example to a circuit and radio frequency transceiver for TXLDO overshoot suppression. Background Technology

[0002] Currently, in the transmitting circuit of RF transceivers, the TXLDO (Transmitter Low-Dropout Regulator) is a core power module providing stable power to key RF components such as power amplifiers, mixers, and RF oscillators. The operating characteristics of the transmitting circuit dictate that its load current exhibits typical features of wide range, high frequency, and rapid abrupt changes. Furthermore, these abrupt changes occur periodically with the frame structure of the communication protocol, thus placing extremely high demands on the dynamic response capability of the TXLDO. When the load current of the transmitting circuit abruptly changes from low to high, the power transistor of the TXLDO needs to quickly turn on to compensate for the large current. If the error amplifier's driving capability is insufficient, it will cause a lag in the adjustment of the power transistor's gate voltage, leading to output voltage overshoot.

[0003] In related technologies, overshoot suppression of TXLDOs is achieved by increasing the phase margin, such as by adding compensation capacitors or optimizing the compensation network.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: The relevant technologies will significantly extend the system stabilization time and improve the system response speed.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a circuit and radio frequency transceiver for TXLDO overshoot suppression, so as to achieve overshoot suppression of TXLDO while ensuring system response speed.

[0008] In some embodiments, the circuit for TXLDO overshoot suppression includes: a timing-linked detection module configured to detect the load current of the TXLDO, determine the rate of change of the load current, compare the rate of change of the current with a preset threshold, and output a comparison signal; the preset threshold is dynamically determined according to the operating timing of the TXLDO; a drive adjustment module configured to dynamically output a drive signal for the amplifier of the TXLDO according to the comparison signal, so as to adjust the drive capability of the amplifier; and a noise isolation module configured to block noise from the drive signal from coupling to the TXLDO.

[0009] Optionally, the timing-linked detection module includes: a current detection unit configured to detect the load current of the TXLDO and generate a detection current; a current change rate calculation unit configured to calculate the current change rate of the detection current; and a timing-linked threshold comparison unit configured to dynamically determine a preset threshold based on the working timing of the TXLDO, compare the current change rate with the preset threshold, and output a comparison signal.

[0010] Optionally, the current detection unit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the current change rate calculation unit includes a first resistor, a first capacitor, and a second resistor; the timing-linked threshold comparison unit includes a comparator and a multiplexer; wherein: the gate of the first PMOS transistor is connected to the gate of the TXLDO power MOS transistor, the source is connected to the power supply, and the drain is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor; the source of the first NMOS transistor is grounded; the drain of the second NMOS transistor is connected to the first terminal of the first resistor and the first terminal of the first capacitor. The first capacitor is connected to the first terminal of the second resistor and grounded; the second terminal of the first capacitor is connected to the first terminal of the second resistor and the first input terminal of the comparator; the second terminal of the second resistor is grounded; the second input terminal of the comparator is connected to the output terminal of the multiplexer, and the output terminal of the comparator outputs a comparison signal; the operating timing of the TXLDO acts on the control terminal of the multiplexer; the operating timing includes an enable signal, when the enable signal is valid, the multiplexer outputs a first preset threshold; when the enable signal is invalid, the multiplexer outputs a second preset threshold; the first preset threshold is less than the second preset threshold.

[0011] Optionally, the first preset threshold includes a first preset value and a second preset value; when the enable signal is valid and the TXLDO is in the light load section, the multiplexer outputs the first preset value; when the enable signal is valid and the TXLDO is in the heavy load section, the multiplexer outputs the second preset value; the first preset value is less than the second preset value.

[0012] Optionally, the drive adjustment module includes: multiple drive adjustment units, each drive adjustment unit connected in series, the first drive adjustment unit receives a comparison signal, outputs the drive signal corresponding to the drive adjustment unit after a preset delay, and applies the drive signal to the next drive adjustment unit so that the next drive adjustment unit has the corresponding drive signal after a preset delay.

[0013] Optionally, the drive adjustment unit includes a current source, a third NMOS transistor, a second capacitor, and a first inverter; wherein: the input terminal of the current source is connected to the power supply, and the output terminal is connected to the drain of the third NMOS transistor, the first terminal of the second capacitor, and the input terminal of the first inverter; the gate of the third NMOS transistor receives a comparison signal or a drive signal from the previous drive adjustment unit, and the source is grounded; the second terminal of the second capacitor is grounded; and the output terminal of the first inverter outputs a drive signal.

[0014] Optionally, the amplifier of the TXLDO includes a reference unit and multiple enhancement units connected in parallel; each drive adjustment unit outputs a drive signal corresponding to an enhancement unit; when an enhancement unit receives a drive signal, the enhancement unit is turned on or off according to the drive signal to adjust the total transconductance of the amplifier.

[0015] Optionally, the noise isolation module includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a second inverter, a second PMOS transistor, and a third PMOS transistor; wherein: the gate of the fourth NMOS transistor and the input terminal of the second inverter receive the drive signal output by the drive adjustment module; the output terminal of the second inverter is connected to the gate of the fifth NMOS transistor; the sources of the fourth and fifth NMOS transistors are both grounded; the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor; the sixth... The gates of the NMOS transistor and the seventh NMOS transistor are both connected to the bias voltage; the drain of the sixth NMOS transistor is connected to the drain and gate of the second PMOS transistor and the gate of the third PMOS transistor, and serves as the first output terminal of the noise isolation module; the drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor, and serves as the second output terminal of the noise isolation module; the sources of the second PMOS transistor and the third PMOS transistor are connected to the power supply; the first and second output terminals of the noise isolation module are connected in parallel to output the drive signal after noise isolation, and act on the enhancement unit of the TXLDO amplifier.

[0016] Optionally, the grounding terminal of the timing linkage detection module, the drive adjustment module, and the noise isolation module is the first grounding terminal; the grounding terminal of the TXLDO is the second grounding terminal.

[0017] In some embodiments, the radio frequency transceiver includes the circuitry described above for TXLDO overshoot suppression.

[0018] The circuit and RF transceiver for TXLDO overshoot suppression provided in this disclosure can achieve the following technical effects: In this embodiment, the timing-linked detection module can calculate the rate of change of the load current, accurately capturing microsecond-level load surges. When the detected rate of change of the current exceeds a preset threshold, a load surge is considered to have occurred, and a high-level comparison signal is output. At this time, the drive adjustment module quickly intervenes to enhance the driving capability of the TXLDO amplifier, thereby rapidly adjusting the gate voltage of the TXLDO power MOSFET to achieve overshoot suppression. Furthermore, no additional components are set in the feedback loop of the TXLDO, so it will not affect the system response speed. In addition, the preset threshold is dynamically determined according to the operating timing of the TXLDO, and can be dynamically adjusted according to the operating state of the transmitting circuit to prevent false triggering of the overshoot suppression mechanism during circuit standby, and can also reduce amplifier drive to save circuit power consumption. The noise isolation module can also block the noise of the timing-linked detection module and the drive adjustment module, avoiding interference to the RF transmission link.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a circuit for TXLDO overshoot suppression provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another circuit for TXLDO overshoot suppression provided in an embodiment of this disclosure; Figure 3 This is a circuit diagram of a timing linkage detection module in a circuit for TXLDO overshoot suppression provided in an embodiment of this disclosure; Figure 4 This is a circuit diagram of a drive adjustment module in a circuit for TXLDO overshoot suppression provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of an amplifier in a circuit for TXLDO overshoot suppression provided in an embodiment of this disclosure; Figure 6 This is a circuit diagram of a noise isolation module in a circuit for TXLDO overshoot suppression provided in an embodiment of this disclosure.

[0021] Reference numerals: 100, Timing-linked detection module; 200, Drive adjustment module; 300, Noise isolation module; 400, TXLDO; EA, Amplifier; PM, Power MOSFET; R3, Third resistor; R4, Fourth resistor; 101, Current detection unit; 102, Current change rate calculation unit; 103, Timing-linked threshold comparison unit; PM1, First PMOS transistor; NM1, First NMOS transistor; NM2, Second NMOS transistor; R1, First resistor; C1, First capacitor; R2, second resistor; CMP, comparator; MUX, multiplexer; 201, drive adjustment unit; I1, current source; NM3, third NMOS transistor; C2, second capacitor; SMIT, first inverter; 401, reference unit; 402, enhancement unit; NM4, fourth NMOS transistor; NM5, fifth NMOS transistor; NM6, sixth NMOS transistor; NM7, seventh NMOS transistor; INV, second inverter; PM2, second PMOS transistor; PM3, third PMOS transistor. Detailed Implementation

[0022] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0023] The terms "first," "second," etc., used in the technical solutions described in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0024] Unless otherwise stated, the term "multiple" means two or more.

[0025] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0026] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0027] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0028] Combination Figure 1 As shown, this disclosure provides a circuit for TXLDO overshoot suppression, including: a timing linkage detection module 100, a drive adjustment module 200, and a noise isolation module 300.

[0029] The timing-linked detection module 100 is configured to detect the load current of the TXLDO400, determine the rate of change of the load current, compare the rate of change of the current with a preset threshold, and output a comparison signal; the preset threshold is dynamically determined according to the operating timing of the TXLDO400. The drive adjustment module 200 is configured to dynamically output the drive signal of the TXLDO400 amplifier based on the comparison signal to adjust the drive capability of the amplifier. The noise isolation module 300 is configured to block noise from the drive signal from coupling to the TXLDO400.

[0030] In this embodiment, the timing-linked detection module 100 can calculate the rate of change of the load current, accurately capturing microsecond-level load surges. When the detected rate of change of the current exceeds a preset threshold, it is considered that a load surge has occurred, and a high-level comparison signal is output. At this time, the drive adjustment module 200 quickly intervenes to enhance the driving capability of the TXLDO400 amplifier, thereby rapidly adjusting the gate voltage of the TXLDO400 power MOSFET to achieve overshoot suppression. Furthermore, no additional components are set in the feedback loop of the TXLDO400, so it will not affect the system response speed. In addition, the preset threshold is dynamically determined according to the working timing of the TXLDO400, and can be dynamically adjusted according to the working state of the transmitting circuit to prevent false triggering of the overshoot suppression mechanism when the circuit is in standby mode, and can also reduce the amplifier drive to save circuit power consumption. The noise isolation module 300 can also block the noise of the timing-linked detection module 100 and the drive adjustment module 200 to avoid interference with the RF transmitting link.

[0031] Optionally, combined Figure 2As shown, the TXLDO400 includes: amplifier EA, power MOSFET PM, third resistor R3, and fourth resistor R4. The negative input terminal of amplifier EA is connected to the reference voltage VREF, the positive input terminal is connected to the first terminal of the fourth resistor R4, and the output terminal is connected to the gate of the power MOSFET PM. The source of the power MOSFET PM is connected to the power supply VDD, and the drain is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is grounded. The drain of the power MOSFET PM is the output terminal Vout of the TXLDO400, generating the load current. The gate of the power MOSFET PM is connected to the timing linkage detection module 100. The noise isolation module 300 outputs a noise-isolated drive signal, which is applied to amplifier EA.

[0032] In this embodiment, the gate of the power MOSFET PM is connected to the timing linkage detection module 100. When the load changes suddenly, the timing linkage detection module 100 can detect the load current at the drain of the power MOSFET PM, thereby determining the rate of change of the load current. Finally, the noise isolation module 300 outputs a noise-isolated drive signal. The drive signal can enhance the drive capability of the amplifier EA, thereby accelerating the charging or discharging speed of the gate voltage of the power MOSFET PM and realizing fast overshoot suppression when the load changes suddenly.

[0033] Optionally, combined Figure 3 As shown, the timing-linked detection module 100 includes: a current detection unit 101, configured to detect the load current of the TXLDO400 and generate a detection current; a current change rate calculation unit 102, configured to calculate the current change rate of the detection current; and a timing-linked threshold comparison unit 103, configured to dynamically determine a preset threshold based on the working timing of the TXLDO400, compare the current change rate with the preset threshold, and output a comparison signal.

[0034] In this embodiment, the current detection unit 101 can perform non-destructive detection of the load current of the TXLDO400, monitor microsecond-level current changes, and accurately identify load change events by calculating the current change rate, thus avoiding false triggering due to small current fluctuations caused by fine-tuning of the transmit power. The timing linkage threshold comparison unit 103 can adapt to the high and low duty cycle operating modes of the circuit, ensuring a fast response at the moment of transmission and preventing false triggering due to small current fluctuations during standby.

[0035] Optionally, the detection bandwidth of the current detection unit 101 is greater than or equal to 100MHz.

[0036] Optionally, combined Figure 3As shown, the current detection unit 101 includes a first PMOS transistor PM1, a first NMOS transistor NM1, and a second NMOS transistor NM2; the current change rate calculation unit 102 includes a first resistor R1, a first capacitor C1, and a second resistor R2; the timing linkage threshold comparison unit 103 includes a comparator CMP and a multiplexer MUX. Wherein: the gate of the first PMOS transistor PM1 is connected to the gate of the TXLDO400 power MOS transistor PM, the source is connected to the power supply, and the drain is connected to the drain of the first NMOS transistor NM1, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor; the source of the first NMOS transistor NM1 is grounded; the drain of the second NMOS transistor is connected to the first terminal of the first resistor R1 and the first terminal of the first capacitor C1, and the source is grounded; the second terminal of the first resistor R1 is connected to the power supply; the second terminal of the first capacitor C1 is connected to the first terminal of the second resistor R2 and the first input terminal of the comparator CMP; the second terminal of the second resistor R2 is grounded; the second input terminal of the comparator CMP is connected to the output terminal of the multiplexer MUX, and the output terminal of the comparator CMP outputs the comparison signal V_Trig; the operating timing of the TXLDO400 is applied to the control terminal of the multiplexer MUX. The operating timing includes an enable signal TX_EN. When the enable signal is valid, the multiplexer MUX outputs a first preset threshold Vth_L. When the enable signal is invalid, the multiplexer MUX outputs a second preset threshold Vth_H. The first preset threshold is less than the second preset threshold.

[0037] In this embodiment, the gate of the first PMOS transistor PM1 is connected to the gate of the TXLDO400 power MOS transistor PM, enabling the first PMOS transistor PM1 and the power MOS transistor PM to operate under the same gate voltage condition. This achieves proportional replication of the load current, thereby realizing RF-compatible lossless current detection. The current change rate calculation unit 102 is an RC differentiating / filtering network. The voltage across the first capacitor C1 is proportional to the rate of change of the current flowing through it, thus converting small current surges into measurable voltage changes. The multiplexer MUX can select different preset thresholds to output based on different enable signals, thereby adaptively adjusting the detection threshold according to the time slot state of the transmitting circuit. When the enable signal is valid, a lower threshold allows the circuit to be more sensitive to sudden large currents, ensuring a fast response; when the enable signal is invalid, a higher threshold effectively shields small current fluctuations, preventing false triggering. When the current change rate exceeds the current threshold, the comparator CMP outputs a high-level comparison signal.

[0038] In the current change rate calculation unit 102, the leakage current Is of the second NOMS transistor NM2 is a proportional replica of the load current. Let the resistance of the first resistor R1 be r1 and the resistance of the second resistor R2 be r2. Then, the voltage across the first terminal of the first capacitor C1 is Vs = Is × r1. At this time, the current across the second terminal of the first capacitor C1 is Ir = C1 × (dVs / dt), and the voltage across the second terminal of the first capacitor C1 is Vr = Ir × r2 = r2 × r1 × C1 × (dIs / dt). This voltage acts on the first input terminal of the comparator CMP. Therefore, the first input terminal of the comparator CMP can reflect the current change rate of the load current.

[0039] Optionally, the first preset threshold includes a first preset value and a second preset value; when the enable signal is valid and the TXLDO400 is in the light load section, the multiplexer MUX outputs the first preset value; when the enable signal is valid and the TXLDO400 is in the heavy load section, the multiplexer MUX outputs the second preset value; the first preset value is less than the second preset value.

[0040] In this embodiment, when the enable signal is active, a single threshold may not perfectly cover all scenarios from light load to heavy load. In the light load segment, the absolute value of the current is small, but the rate of change may still be large. Therefore, setting a smaller first preset value ensures that the circuit maintains high sensitivity to sudden currents under light load conditions, preventing missed detections. In the heavy load segment, the current base is large and changes drastically. Therefore, setting a relatively high second preset value avoids misjudging abnormal disturbances due to excessively rapid current rise at the moment of heavy load startup, while ensuring that protection is still triggered under large current surges. By distinguishing different thresholds for light and heavy load segments, the circuit can more accurately determine when to enhance the driving capability of amplifier EA, thereby achieving more precise and robust overshoot suppression across the entire load range and further compressing the output voltage fluctuation range.

[0041] Optionally, the load current range corresponding to the light load segment is [0, 200mA]; the load current range corresponding to the heavy load segment is [200mA, 1A].

[0042] Optionally, the range of the first preset value is [40mA / μs, 60mA / μs]; the range of the second preset value is [150mA / μs, 250mA / μs].

[0043] Optionally, the value range of the second preset threshold is [500mA / μs, 600mA / μs].

[0044] Optionally, combined Figure 4As shown, the drive adjustment module 200 includes: a plurality of drive adjustment units 201, each drive adjustment unit 201 being connected in series. The first drive adjustment unit 201 receives a comparison signal, outputs the drive signal corresponding to the drive adjustment unit 201 after a preset delay, and applies the drive signal to the next drive adjustment unit 201 so that the next drive adjustment unit 201 has the corresponding drive signal after a preset delay.

[0045] In this embodiment, by connecting multiple drive adjustment units 201 in series and setting a preset delay, it can be determined that the enhancement or weakening of drive capability is a step-by-step and orderly process, avoiding output voltage fluctuations caused by sudden changes in drive capability and ensuring a smooth transition of the RF power supply voltage. The series structure of the drive adjustment module 200 allows the first-stage drive adjustment unit 201 to respond at the fastest speed, achieving rapid drive enhancement; while subsequent drive adjustment units 201 intervene with progressively delayed interventions, responsible for maintaining the long-term stability of the system and achieving smooth drive recovery.

[0046] Optionally, combined Figure 4 As shown, the drive adjustment unit 201 includes a current source I1, a third NMOS transistor NM3, a second capacitor C2, and a first inverter SMIT. Specifically: the input terminal of the current source I1 is connected to the power supply, and its output terminal is connected to the drain of the third NMOS transistor NM3, the first terminal of the second capacitor C2, and the input terminal of the first inverter SMIT; the gate of the third NMOS transistor NM3 receives a comparison signal or a drive signal from the previous drive adjustment unit 201, and its source is grounded; the second terminal of the second capacitor C2 is grounded; and the output terminal of the first inverter SMIT outputs the drive signal.

[0047] In this embodiment, when the gate of the third NMOS transistor NM3 receives a comparison signal or a drive signal from the previous drive adjustment unit 201, the third NMOS transistor NM3 is turned on, starting to charge or discharge the second capacitor C2. Due to the presence of the current source I1, the charging and discharging process of the second capacitor C2 is linear rather than abrupt, causing the voltage at the input terminal of the first inverter SMIT to slowly exceed the flip threshold, thereby causing the drive signal (Sw) output by the first inverter SMIT to... <0> Sw <1> Sw <2> The state transition of the drive adjustment unit 201 has a certain time delay. Through the delay design, it is ensured that the opening or closing of each stage of the drive adjustment unit 201 is a gradual process, avoiding output voltage drop or overshoot rebound caused by instantaneous switching of drive capability.

[0048] Optionally, combined Figure 5As shown, the amplifier EA of the TXLDO400 includes a reference unit 401 and multiple enhancement units 402 connected in parallel; each drive adjustment unit 201 outputs a drive signal corresponding to an enhancement unit 402; when the enhancement unit 402 receives a drive signal, the enhancement unit 402 is turned on or off according to the drive signal to adjust the total transconductance of the amplifier EA.

[0049] In this embodiment, in standby or stable state, only the reference unit 401 of amplifier EA is operational. At this time, the total transconductance of amplifier EA remains at a low level, ensuring extremely low quiescent current. When the load changes abruptly, the drive signal output by the drive adjustment unit 201 sequentially turns on the enhancement units 402. As the number of turned-on enhancement units 402 increases, the total transconductance of amplifier EA increases in a stepwise manner, thereby driving the gate capacitance of the power MOSFET PM with a larger current, increasing the charging and discharging speed of the power MOSFET PM's gate, and rapidly adjusting the gate voltage of the power MOSFET PM to achieve overshoot suppression.

[0050] Optionally, the reference unit 401 consists of a set of amplifier transistors to meet the driving requirements of standby and stable transmission states. Its quiescent current is less than or equal to 10μA.

[0051] Optionally, the enhancement unit 402 consists of a set of amplifying transistors with parameters identical to those of the reference unit 401, and is controlled to be connected or disconnected via a MOS switch. The MOS switch is controlled by a drive signal.

[0052] Optionally, the number of enhancement units 402 is three, and / or the number of drive adjustment units 201 is three.

[0053] In this embodiment, when the load current changes abruptly, the timing-linked detection module 100 outputs a high-level comparison signal, and after a preset delay, sequentially controls the three drive adjustment units 201 to output corresponding drive signals, thereby sequentially turning on the corresponding enhancement units 402. This triples the total transconductance of the amplifier EA, accelerating the charging and discharging speed of the power MOSFET PM gate (e.g., reducing the gate voltage adjustment time from 20μs to 5μs), achieving rapid output overshoot suppression. When the load current stabilizes, the timing-linked detection module 100 outputs a low-level comparison signal, and after a preset delay, sequentially controls the three drive adjustment units 201 to output corresponding drive signals, thereby sequentially turning off the corresponding enhancement units 402, preventing output voltage drops due to a sudden decrease in drive capability.

[0054] Optionally, the default delay is 100ns.

[0055] Optionally, combined Figure 6As shown, the noise isolation module 300 includes a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, a second inverter INV, a second PMOS transistor PM2, and a third PMOS transistor PM3. Specifically: the gate of the fourth NMOS transistor NM4 and the input of the second inverter INV receive the drive signal output from the drive adjustment module 200; the output of the second inverter INV is connected to the gate of the fifth NMOS transistor NM5; the sources of both the fourth and fifth NMOS transistors NM4 and NM5 are grounded; the drain of the fourth NMOS transistor NM4 is connected to the source of the sixth NMOS transistor NM6; the drain of the fifth NMOS transistor NM5 is connected to the source of the seventh NMOS transistor NM7; and the gate of the sixth NMOS transistor NM6 is connected to the source of the seventh NMOS transistor NM7. The gates of NMOS transistors NM7 are all connected to the bias voltage VB; the drain of the sixth NMOS transistor NM6 is connected to the drain and gate of the second PMOS transistor PM2 and the gate of the third PMOS transistor PM3, and serves as the first output terminal V_CTRLN of the noise isolation module 300; the drain of the seventh NMOS transistor NM7 is connected to the drain of the third PMOS transistor PM3, and serves as the second output terminal V_CTRLP of the noise isolation module 300; the sources of the second PMOS transistor PM2 and the third PMOS transistor PM3 are connected to the power supply. The first and second output terminals of the noise isolation module 300 are connected in parallel to output the drive signal after noise isolation, which is applied to the enhancement unit 402 of the amplifier EA of the TXLDO400.

[0056] In this embodiment, the drive signal output by the drive adjustment module 200 is divided into two paths: one path directly enters the gate of the fourth NMOS transistor NM4, and the other path passes through the second inverter INV and enters the gate of the fifth NMOS transistor NM5, forming a differential input structure. The gates of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are connected and subjected to a fixed bias voltage, serving as the load of the differential pair. Through the differential pair formed by the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, any common-mode noise from the power supply or ground will simultaneously act on the sources of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5. Since they have the same electrical environment, the output current change of the differential pair is almost zero, thereby effectively filtering out common-mode noise interference in the circuit (e.g., noise rejection ratio greater than or equal to 40dB). The sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the second PMOS transistor PM2, and the third PMOS transistor PM3 also form a current mirror of the common source and common gate structure, which has high output impedance and low transmission coefficient, and blocks the noise of the drive signal from coupling to the amplifier EA.

[0057] In one specific embodiment, combined with Figures 4 to 6As shown, after receiving the comparison signal, the drive adjustment module 200 sequentially generates three drive signals Sw through the three drive adjustment units 201. <0> Sw <1> Sw <2> The three drive signals are connected in parallel to form a three-bit signal Sw<2:0>, which is input to the noise isolation module 300. After passing through the noise isolation module 300, differential signals V_CTRLN<2:0> and V_CTRLLP<2:0> are generated. The differential signals are connected in parallel to form a noise-isolated drive signal V_CTRLLP. N<2:0> is input to amplifier EA to control the on or off of the three enhancement units 402. For example, when the drive signal Sw<2:0> is [0, 0, 0], all three enhancement units 402 are off; when the drive signal Sw<2:0> is [1, 1, 1], all three enhancement units 402 are on.

[0058] Optionally, the grounding terminal of the timing linkage detection module 100, the drive adjustment module 200 and the noise isolation module 300 is the first grounding terminal; the grounding terminal of the TXLDO400 is the second grounding terminal.

[0059] In this embodiment, grounding isolation is performed between the first grounding terminal and the second grounding terminal, which can cut off the channel for digital noise to propagate to the radio frequency analog domain through the ground wire, and avoid the influence of ground bounce noise through a single-point connection.

[0060] Optionally, the first grounding terminal is a digital ground and the second grounding terminal is an analog ground.

[0061] The circuit for overshoot suppression of TXLDO provided in this disclosure addresses the problems faced by the TXLDO400 in the RF transmission circuit, such as large output overshoot, long settling time, impact on transmission signal quality, and poor power consumption adaptability caused by wide-range load changes from 0 to 1A. It can achieve fast response and overshoot suppression when the load of the transmission circuit changes (especially at the moment of opening the transmission time slot), meet the strict timing requirements of the transmission time slot (settling time less than or equal to 10μs), operate with low power consumption in standby or stable transmission states, avoid the introduction of RF noise by the control circuit, and ensure the quality of the transmission signal.

[0062] In one specific embodiment, the present disclosure significantly optimizes the quality of the transmitted signal, reducing the output overshoot voltage from 50mV to 200mV to 10mV to 30mV, improving the ACLR of the transmitted signal by 2dB to 3dB, effectively reducing signal distortion, and meeting the RF performance requirements of protocols such as 5G NR and Wi-Fi 6. It also meets transmission timing requirements, with voltage stabilization time after load surges less than or equal to 5μs, ensuring voltage adjustment is completed within the transmission time slot and avoiding communication interruptions. Furthermore, it significantly reduces average power consumption, with the amplifier EA quiescent current in standby mode less than or equal to 10μA (a 60% to 80% reduction compared to a fixed high-drive scheme), adapting to the low duty cycle operating mode of the transmitting circuit and extending the overall battery life. It possesses high RF compatibility; through noise isolation design, the interference of the control circuit on the RF signal is less than or equal to -100dBm, without affecting the sensitivity and linearity of the transmission link. Furthermore, without changing the core topology of the TXLDO400, it can be achieved simply by adding a dynamic control module, making it compatible with XLDO designs for emitter circuits of different processes (such as 28nm and 40nm CMOS).

[0063] This disclosure also provides an RF transceiver that includes the circuitry described above for TXLDO overshoot suppression.

[0064] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the technical solutions described herein. As used in the technical solutions described herein, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein refers to any and all possible combinations of one or more of the associated listed elements. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

Claims

1. A circuit for overshoot suppression in TXLDOs, characterized in that, include: The timing-linked detection module is configured to detect the load current of the TXLDO, determine the rate of change of the load current, compare the rate of change of the current with a preset threshold, and output a comparison signal. The preset threshold is dynamically determined based on the working timing of the TXLDO; The drive adjustment module is configured to dynamically output the drive signal of the TXLDO amplifier based on the comparison signal, so as to adjust the drive capability of the amplifier. The noise isolation module is configured to block noise from the drive signal from coupling to the TXLDO.

2. The circuit according to claim 1, characterized in that, The timing-linked detection module includes: The current sensing unit is configured to detect the load current of the TXLDO and generate a detection current; The current change rate calculation unit is configured to calculate the current change rate of the detected current; The timing-linked threshold comparison unit is configured to dynamically determine a preset threshold based on the working timing of the TXLDO, compare the current change rate with the preset threshold, and output a comparison signal.

3. The circuit according to claim 2, characterized in that, The current detection unit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the current change rate calculation unit includes a first resistor, a first capacitor, and a second resistor; the timing-linked threshold comparison unit includes a comparator and a multiplexer; wherein: The gate of the first PMOS transistor is connected to the gate of the TXLDO power MOS transistor, its source is connected to the power supply, and its drain is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to the first terminal of the first resistor and the first terminal of the first capacitor, and its source is grounded. The second terminal of the first resistor is connected to the power supply. The second terminal of the first capacitor is connected to the first terminal of the second resistor and the first input terminal of the comparator. The second terminal of the second resistor is grounded. The second input terminal of the comparator is connected to the output terminal of the multiplexer, and the output terminal of the comparator outputs a comparison signal. The timing of the TXLDO operation applies to the control terminal of the multiplexer. The operating timing includes an enable signal. When the enable signal is valid, the multiplexer outputs a first preset threshold. When the enable signal is invalid, the multiplexer outputs a second preset threshold. The first preset threshold is less than the second preset threshold.

4. The circuit according to claim 3, characterized in that, The first preset threshold includes a first preset value and a second preset value; When the enable signal is valid and the TXLDO is in the light load section, the multiplexer outputs a first preset value; when the enable signal is valid and the TXLDO is in the heavy load section, the multiplexer outputs a second preset value; the first preset value is less than the second preset value.

5. The circuit according to claim 1, characterized in that, The drive adjustment module includes: Multiple drive adjustment units are connected in series. The first drive adjustment unit receives a comparison signal, outputs the corresponding drive signal after a preset delay, and applies the drive signal to the next drive adjustment unit so that the next drive adjustment unit has the corresponding drive signal after a preset delay.

6. The circuit according to claim 5, characterized in that, The drive adjustment unit includes a current source, a third NMOS transistor, a second capacitor, and a first inverter; wherein: The input terminal of the current source is connected to the power supply, and the output terminal is connected to the drain of the third NMOS transistor, the first terminal of the second capacitor, and the input terminal of the first inverter. The gate of the third NMOS transistor receives the comparison signal or the drive signal of the previous drive adjustment unit, and the source is grounded. The second terminal of the second capacitor is grounded. The output terminal of the first inverter outputs the drive signal.

7. The circuit according to claim 5, characterized in that, The TXLDO amplifier includes a reference unit and multiple enhancement units connected in parallel; the drive signal output by each drive adjustment unit corresponds to one enhancement unit. When the enhancement unit receives a drive signal, the enhancement unit is turned on or off according to the drive signal to adjust the total transconductance of the amplifier.

8. The circuit according to claim 7, characterized in that, The noise isolation module includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a second inverter, a second PMOS transistor, and a third PMOS transistor; wherein: The gate of the fourth NMOS transistor and the input of the second inverter receive the drive signal output by the drive adjustment module; the output of the second inverter is connected to the gate of the fifth NMOS transistor; the sources of the fourth and fifth NMOS transistors are both grounded; the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor; the gates of the sixth and seventh NMOS transistors are both connected to the bias voltage; the drain of the sixth NMOS transistor is connected to the drain and gate of the second PMOS transistor and the gate of the third PMOS transistor, and serves as the first output of the noise isolation module; the drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor, and serves as the second output of the noise isolation module; the sources of the second and third PMOS transistors are connected to the power supply. The first and second output terminals of the noise isolation module are connected in parallel to output a drive signal that has been noise isolated, which is then applied to the enhancement unit of the TXLDO amplifier.

9. The circuit according to any one of claims 1 to 8, characterized in that, The grounding terminal of the timing linkage detection module, the drive adjustment module, and the noise isolation module is the first grounding terminal; the grounding terminal of the TXLDO is the second grounding terminal.

10. A radio frequency transceiver, characterized in that, Includes the circuit for TXLDO overshoot suppression as described in any one of claims 1 to 9.

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