A class-ab output stage biasing circuit for high voltage operational amplifiers

Abstract

This invention relates to a CLASS-AB output stage bias circuit for a high-voltage operational amplifier. It includes an input stage module comprising a first bias module that processes an externally input bias voltage VAN to generate a stable first bias node voltage VBP; a second bias module that processes an externally input bias voltage VAP to generate a stable second bias node voltage VBN; a first negative feedback operational amplifier module, whose positive input is connected to the feedback terminal and serves as a clamping output node one connected to the output stage module, and whose negative input is connected to the first bias node voltage VBP; and a second negative feedback operational amplifier module, whose positive input is connected to the feedback terminal and serves as a clamping output node two connected to the output stage module, and whose negative input is connected to the second bias node voltage VBN. This invention enables near-perfect replication of the output stage MOSFET and the bias circuit's mirrored MOSFET during operational amplifier operation, overcoming the current mismatch caused by channel length modulation effects.

Description

Technical Field

[0001] This invention belongs to the field of CLASS-AB operational amplifier technology, and specifically relates to a CLASS-AB output stage bias circuit for high-voltage operational amplifiers. Background Technology

[0002] CLASS-AB output stage operational amplifiers (op-amps) offer advantages such as low quiescent power consumption, low distortion, high efficiency, and large output swing, making them widely used in various operational amplifiers. Their use of a transconducting linear loop for output stage biasing results in a simple circuit structure and easy control of the op-amp's quiescent current, contributing to their widespread adoption. However, with the continuous reduction in integrated circuit feature sizes and the increasing supply voltage of op-amps, the channel length modulation effect of MOSFETs becomes significant, especially in high-voltage op-amps. The transconducting linear loop is greatly affected by the channel modulation effect, leading to current mismatch and making precise control of the op-amp's output stage quiescent current difficult. When the supply voltage of a high-voltage op-amp varies significantly, the mismatch caused by the channel length modulation effect changes, resulting in greater uncertainty in the quiescent current of the two MOSFETs in the CLASS-AB output stage. This leads to a decrease in the PSRR (Power Supply Rejection Ratio) of the CLASS-AB output stage op-amp and an increase in op-amp distortion.

[0003] In high-voltage operational amplifiers (CLASS-AB output stage), a transconducting linear loop structure is often used to bias the two MOSFETs in the output stage, thereby setting the quiescent current of the op-amp output stage. A high-voltage op-amp (CLASS-AB output stage) operational amplifier circuit using a transconducting linear loop is shown below. Figure 1 As shown: Figure 1The high-voltage CLASS-AB output stage operational amplifier mainly includes a rail-to-rail input stage circuit, a CLASS-AB bias circuit, and an output stage circuit. The rail-to-rail input stage circuit is a folded cascode structure, which has a large output swing and high output impedance. PMOS transistors PM1 and PM2 and NMOS transistors NM3 and NM4 form a differential input pair, with PM1~PM2 and NM3~NM4 being high-voltage MOS transistors with high drain voltage tolerance. Current source I1 provides bias current to the PMOS differential input transistors and the NMOS differential input pair. NMOS transistor NM10 and PMOS transistor PM11 form a floating current source to control the quiescent current of the output stage. NM9~NM10 and PM11 are high-voltage MOS transistors with high drain voltage tolerance. The CLASS-AB bias circuit includes NMOS transistors NM16 and NM17 with stacked diode connections and PMOS transistors PM18 and PM19 with stacked diode connections, providing bias voltages for floating current source transistors NM10 and PM11, respectively. NM16~NM17 and PM18~PM19 are high-voltage MOS transistors with high drain withstand voltage. The output stage circuit includes NMOS transistor NM20 and PMOS transistor PM21. Resistor R and capacitor C form a Miller compensation structure to provide frequency compensation for the operational amplifier. NM20 and PM21 are high-voltage MOS transistors with high drain withstand voltage.

[0004] Figure 1 The NMOS transistors NM10, NM16, NM17, and NM20 in the circuit form a transconductance linear loop, and their gate-source voltages have the following relationship: Ideally, the ratio of the source-to-drain current of NM10 and NM17 should be equal to the ratio of their width-to-length ratio, i.e. The source-drain current formula of a MOSFET can be used to obtain... ,So In other words, the gate-source voltage difference of the output transistor NM20 is equal to that of NM16. If the width-to-length ratio of NM20 is K times that of NM16, then the current flowing through NM20 is also K times the current flowing through NM16. Since the bias current of NM16 is provided by the current source I2, the quiescent current of the output stage NMOS transistor NM20 is K*I2. Similarly, PMOS transistors PM11, PM18, PM19, and PM21 also form a transconductance linear loop, and their gate-source voltages have the following relationship: The bias current of the output stage PMOS transistor PM21 can also be adjusted by designing the size ratio of each transistor. , Therefore, the bias current of the output stage PMOS transistor PM21 is also K*I2.

[0005] The control accuracy of the quiescent current in the output stage circuit is related to the matching between transistors NM10 / NM17, NM16 / NM20, PM11 / PM18, and PM19 / PM21, due to the difference in drain-source voltage between NMOS transistors NM10 and NM17, and PM11 and PM18. They are different, and there is a channel length effect, which makes and , and They are not exactly equal, therefore , Therefore, the quiescent currents of the output stage NMOS transistor NM20 and PMOS transistor PM21 deviate from the theoretical values. The high-voltage operational amplifier has a higher power supply voltage, resulting in higher source-drain voltages for the output stage MOS transistors NM20 and PM21. The source-drain voltage of NM20 / PM21 increases with the power supply voltage, resulting in a significant difference between the source-drain voltage of NM20 / PM21 and the drain-source voltage of NM16 / PM19. Due to the channel modulation effect, a mismatch exists in the mirror ratio between NM20 / PM21 and NM16 / PM19. In summary, in high-voltage operational amplifiers, when the power supply voltage is high, the source-drain voltage of NM10 / PM11 and NM20 / PM21... The distortion is relatively large and is greatly affected by the channel modulation effect. The mirror current exhibits significant mismatch and variation, which brings greater uncertainty to the static current of the output stage MOSFET, reduces the PSRR (Power Supply Rejection Ratio) of the CLASS-AB output stage op-amp, and increases op-amp distortion.

[0006] Therefore, in the aforementioned high-voltage CLASS-AB output stage op-amp, a transconducting linear loop is used to control the quiescent current of the output stage. Due to the channel length modulation effect, there is a mismatch in the mirror current of the floating current source, resulting in a significant deviation in the output stage bias current. Furthermore, as the power supply voltage of the high-voltage op-amp increases, the source-drain voltage of the output stage MOSFET increases, and the quiescent current of the CLASS-AB output stage also changes significantly due to the channel modulation effect, reducing the PSRR of the CLASS-AB output stage op-amp and causing increased op-amp distortion.

[0007] A search revealed that while existing technologies often employ negative feedback structures to clamp the gate voltage of output transistors—for example, a CLASS-AB output stage bias circuit in patent publication CN117595803A—uses auxiliary operational amplifiers OPA1 and OPA2 to force the gate-source voltages of output transistor M20 to be equal to those of diode-connected M34, and output transistor M19 to be equal to those of diode-connected M33, thereby precisely setting the output stage quiescent current using a current mirror ratio. This solution overcomes, to some extent, the problem of channel length modulation effect in traditional transconductance linear loops. However, the following drawbacks still exist: 1) This negative feedback structure only clamps the gate-source voltage of the output transistor and the mirror transistor, but their drain-source voltages may still differ due to power supply voltage variations or current mirror mismatch. Under the influence of channel length modulation, even if the gate-source voltages are equal, if the drain-source voltages are unequal, the current flowing through the transistor cannot be accurately replicated. When the power supply voltage varies over a wide range, the output stage quiescent current will still exhibit non-negligible fluctuations, limiting the high-voltage applications of the op-amp and the improvement of PSRR.

[0008] 2) The non-ideal characteristics of the auxiliary operational amplifiers affect clamping accuracy. The input offset voltages and limited open-loop gain of the auxiliary operational amplifiers OPA1 and OPA2 can lead to residual errors between VGP and VBP, and between VGN and VBN. Especially in low-power (nanoampere) or high-precision applications, this error can be directly transmitted to the output stage quiescent current, causing the current setting to deviate from the theoretical value.

[0009] 3) The current mirror is still affected by power supply voltage changes: The M30 / M31 branch in this circuit still relies on the traditional common source and common gate current mirror (such as M12 and M21). When the power supply voltage changes, the drain-source voltage of these current mirrors will change, causing a slight shift in the current mirror replication ratio, which indirectly affects the stability of the output stage static current.

[0010] Therefore, there is an urgent need for this invention to propose a CLASS-AB output stage bias circuit for high-voltage operational amplifiers to solve the above-mentioned technical problems. Summary of the Invention

[0011] The purpose of this invention is to provide a CLASS-AB output stage bias circuit for high-voltage operational amplifiers. This invention enables near-complete replication of the output stage MOSFET and the bias circuit mirror MOSFET during operation of the operational amplifier, overcoming the current mismatch caused by the channel length modulation effect. At the same time, the bias circuit adjusts accordingly when the operational amplifier power supply voltage changes significantly, making the output stage current less affected by power supply voltage changes, thus broadening the application of CLASS-AB output stage operational amplifiers in high-voltage systems.

[0012] To solve the above-mentioned technical problems, the present invention provides a CLASS-AB output stage bias circuit for a high-voltage operational amplifier, comprising: The first bias module, by adopting a first current mirror structure and utilizing an unbalanced configuration of a set of current sources, processes the externally input bias voltage VAN to generate a stable first bias node voltage VBP. The second bias module, by employing a second current mirror structure and utilizing an unbalanced configuration of a set of current sources, processes the externally input bias voltage VAP to generate a stable second bias node voltage VBN. The first negative feedback operational amplifier module has its positive input terminal connected to the feedback terminal and used as the clamping output node one of the output stage module, and its negative input terminal connected to the first bias node voltage VBP. The second negative feedback operational amplifier module has its positive input terminal connected to the feedback terminal and used as the clamping output node two connected to the output stage module, and its negative input terminal connected to the second bias node voltage VBN. The first negative feedback operational amplifier module and the second negative feedback operational amplifier module clamp the gate voltage of the two MOS transistors in the output stage module, respectively, and ensure that the gate-source voltage and source-drain voltage of the two MOS transistors in the output stage module are the same as those of the two mirrored MOS transistors in the first current mirror structure and the second current mirror structure.

[0013] Preferably, the first current mirror structure includes: constant current sources IB4~IB5, a high-voltage NMOS transistor M33, and a high-voltage PMOS transistor M35; the gate of the high-voltage NMOS transistor M33 is connected to a bias voltage VAN, the source is connected to the constant current source IB5 grounded to VSS and the drain of the high-voltage PMOS transistor M35, the drain is connected to the gate of the high-voltage PMOS transistor M35 and the constant current source IB4 connected to the power supply VCC, and generates the first bias node voltage VBP; the source of the PMOS transistor M35 is connected to the power supply VCC; The second current mirror structure includes: constant current sources IB2~IB3, a high-voltage NMOS transistor M32, and a high-voltage PMOS transistor M34; the gate of the high-voltage PMOS transistor M34 is connected to a bias voltage VAP, the source is connected to the constant current source IB2 connected to the power supply VCC and the drain of the high-voltage NMOS transistor M32, the drain is connected to the gate of the high-voltage NMOS transistor M32 and the constant current source IB3 connected to ground VSS, and generates the second bias node voltage VBN; the source of the high-voltage NMOS transistor M32 is grounded to VSS.

[0014] Preferably, the constant current source IB2 is greater than the constant current source IB3, and the constant current source IB4 is less than the constant current source IB5.

[0015] Preferably, the current flowing through the high-voltage NMOS transistor M32 is equal to the difference between the constant current source IB2 and the constant current source IB3. Then, the current flowing through a MOS transistor in the output stage module is K1 times the difference between the constant current source IB2 and the constant current source IB3, where K1 is the ratio of the width to length of the MOS transistor in the output stage module to that of the high-voltage NMOS transistor M32. The current flowing through the high-voltage PMOS transistor M35 is equal to the difference between the constant current source IB5 and the constant current source IB4. Therefore, the current flowing through the other MOS transistor in the output stage module is K2 times the difference between the constant current source IB5 and the constant current source IB4, where K2 is the ratio of the width to length of the MOS transistor in the output stage module to that of the high-voltage PMOS transistor M35. Let IB2-IB3=IB5-IB4, and K1=K2.

[0016] Preferably, the first negative feedback operational amplifier module includes: an auxiliary operational amplifier OPA1 and a high-voltage NMOS transistor M31; the positive input terminal of the auxiliary operational amplifier OPA1 is connected to the drain of the high-voltage NMOS transistor M31 and serves as a clamping output node one connected to the output stage module; the negative input terminal is connected to the first bias node voltage VBP; the output terminal is connected to the gate of the high-voltage NMOS transistor M31, and the source of the high-voltage NMOS transistor M31 is connected to the connection node of the second negative feedback operational amplifier module; The second negative feedback operational amplifier module includes: an auxiliary operational amplifier OPA2 and a high-voltage NMOS transistor M30; the positive input terminal of the auxiliary operational amplifier OPA2 is connected to the drain of the high-voltage NMOS transistor M30 and serves as the clamping output node two connected to the output stage module; the negative input terminal is connected to the second bias node voltage VBN; the output terminal is connected to the gate of the high-voltage NMOS transistor M30, and the source of the high-voltage NMOS transistor M30 serves as the connection node connected to the first negative feedback operational amplifier module.

[0017] Preferably, the circuit further includes a bias voltage generating circuit, comprising: high-voltage PMOS transistors M36-M37 and resistors R1-R2; the gate and drain of the high-voltage PMOS transistor M36 are connected to the grounding resistor R2 connected to ground VSS and generate the bias voltage VAP; the source of the high-voltage PMOS transistor M36 is connected to the gate and drain of the high-voltage PMOS transistor M37 and generates the node voltage VA; the source of the high-voltage PMOS transistor M37 is connected to the resistor R1 connected to the power supply VCC and generates the bias voltage VAN.

[0018] Preferably, the resistance values ​​of resistor R1 and resistor R2 are equal.

[0019] The present invention also provides a high-voltage CLASS-AB output stage operational amplifier circuit, comprising: The folded common source cascode input module is used to receive the input signal for first-stage amplification and to generate the input signal for the output stage module; The output stage bias module adopts a CLASS-AB output stage bias circuit for high-voltage operational amplifiers as described above; it is used to generate the bias voltage of the MOS transistor in the output stage module and control its static current. The output stage module adopts a CLASS-AB output stage; it is used to drive external loads and compensates for the frequency characteristics of the operational amplifier through a Miller structure.

[0020] Preferably, the folded common-source common-gate input module includes: high-voltage PMOS transistors M1~M2, high-voltage NMOS transistors M3~M4, NMOS load transistors M5~M8, high-voltage NMOS transistor M9, PMOS load transistors M12~M15, PMOS load transistor M22, and a constant current source IB1; the source of the high-voltage PMOS transistors M1~M2 is connected to the constant current source IB1 connected to the power supply VCC, the drain of the high-voltage PMOS transistor M1 is connected to the drain of the NMOS load transistor M5 and the source of the NMOS load transistor M7, and the drain of the high-voltage PMOS transistor M2 is connected to the NMOS load transistor M6. The drain of the high-voltage PMOS transistor M1 and the source of the high-voltage NMOS transistor M4 are connected to the input port VIN, and the gates of the high-voltage PMOS transistor M2 and the high-voltage NMOS transistor M3 are connected to the input port VIP. The sources of the high-voltage NMOS transistors M3-M4 are connected to the constant current source IB1 grounded to VSS. The drain of the high-voltage NMOS transistor M3 is connected to the source of the PMOS load transistors M13 and M22, and the drain of the PMOS load transistor M15. The drain of the high-voltage NMOS transistor M4 is connected to the PMOS load transistor M12. The source and drain of PMOS load transistor M14 are connected to the power supply VCC, and the gates of PMOS load transistors M14-M15 are connected to the drains of PMOS load transistor M12 and high-voltage NMOS transistor M9; the gate of PMOS load transistor M12 is connected to the gates of PMOS load transistors M13 and M22, as well as the bias voltage VBP1; the drain of PMOS load transistor M13 is connected to the positive input terminal of the second negative feedback operational amplifier module, and the drain of PMOS load transistor M22 is connected to the first negative feedback... The positive input terminal of the operational amplifier module; the gate of the high-voltage NMOS transistor M9 is connected to the bias voltage VBN3, the source of the high-voltage NMOS transistor M9 is connected to the drain of the NMOS load transistor M7, and the gates of the NMOS load transistors M7~M8 are connected to the bias voltage VBN2; the drain of the NMOS load transistor M8 serves as a connection node connected to the source of the MOS transistor on the feedback terminal of the first negative feedback operational amplifier module and the second negative feedback operational amplifier module; the gates of the NMOS load transistors M5~M6 are connected to the bias voltage VBN1, and the sources of the NMOS load transistors M5~M6 are grounded to VSS.

[0021] Preferably, the output stage module includes: a high-voltage NMOS transistor M20, a high-voltage PMOS transistor M21, and two Miller structures connected in series by a resistor R and a capacitor C; the gate of the high-voltage NMOS transistor M20 is connected to the resistor terminal of one of the Miller structures, and generates a gate voltage VGN which is connected to the positive input terminal of the second negative feedback operational amplifier module; the source of the high-voltage NMOS transistor M20 is grounded to VSS; the gate of the high-voltage PMOS transistor M21 is connected to the resistor terminal of the other Miller structure, and generates a gate voltage VGP which is connected to the positive input terminal of the first negative feedback operational amplifier module; the source of the high-voltage PMOS transistor M21 is connected to the power supply VCC; the drains of the high-voltage NMOS transistor M20 and the high-voltage PMOS transistor M21 are connected to the capacitor terminals of the two Miller structures, and serve as the output port VOUT.

[0022] Compared with the prior art, the present invention has the following beneficial effects: This invention replaces the transconducting linear loop structure with a negative feedback structure of an auxiliary operational amplifier. Specifically, by using a negative feedback structure to control the gate voltage of the CLASS-AB output stage MOSFET, it ensures that the gate-source voltage of the output stage MOSFET and the mirrored MOSFET are the same, as well as that of the source-drain voltage. This prevents the output stage quiescent current from being affected by the channel length modulation effect. Even when the power supply voltage of the high-voltage CLASS-AB operational amplifier changes significantly, the quiescent current of the output stage MOSFET will not change significantly. This improves the PSRR of the high-voltage CLASS-AB operational amplifier and reduces its distortion. Therefore, it solves the problem of inaccurate mirror current between MOSFETs in the transconducting linear loop due to the channel length modulation effect, which leads to inaccurate control of the output stage transistor's quiescent current, thus improving the control accuracy of the output stage transistor's quiescent current.

[0023] This invention provides an additional feedback path for the negative feedback loop by employing an unbalanced current source configuration, thereby significantly suppressing the impact of the auxiliary operational amplifier's offset voltage and finite gain on clamping accuracy. Under the same operational amplifier performance, the quiescent current setting error of this invention is significantly smaller. Attached Figure Description

[0024] Figure 1 The circuit schematic of the high-voltage CLASS-AB output stage rail-to-rail operational amplifier circuit provided for existing technology.

[0025] Figure 2 The present invention provides a circuit schematic of a CLASS-AB output stage bias circuit for a high-voltage operational amplifier.

[0026] Figure 3 The circuit diagram of the bias voltage generation circuit provided by the present invention.

[0027] Figure 4 The circuit diagram of a high-voltage CLASS-AB output stage operational amplifier circuit provided by the present invention. Detailed Implementation

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0029] like Figure 2 As shown, this embodiment of the invention specifically provides a CLASS-AB output stage bias circuit for a high-voltage operational amplifier, comprising: The first bias module, by adopting a first current mirror structure and utilizing an unbalanced configuration of a set of current sources, processes the externally input bias voltage VAN to generate a stable first bias node voltage VBP. The second bias module, by employing a second current mirror structure and utilizing an unbalanced configuration of a set of current sources, processes the externally input bias voltage VAP to generate a stable second bias node voltage VBN. The first negative feedback operational amplifier module has its positive input terminal connected to the feedback terminal and used as the clamping output node one of the output stage module, and its negative input terminal connected to the first bias node voltage VBP. The second negative feedback operational amplifier module has its positive input terminal connected to the feedback terminal and used as the clamping output node two connected to the output stage module, and its negative input terminal connected to the second bias node voltage VBN. The first negative feedback operational amplifier module and the second negative feedback operational amplifier module clamp the gate voltage of the two MOS transistors in the output stage module, respectively, and ensure that the gate-source voltage and source-drain voltage of the two MOS transistors in the output stage module are the same as those of the two mirrored MOS transistors in the first current mirror structure and the second current mirror structure.

[0030] Continue reading Figure 2 As shown, in a preferred embodiment of the present invention, the first current mirror structure includes: constant current sources IB4~IB5, a high-voltage NMOS transistor M33, and a high-voltage PMOS transistor M35; the gate of the high-voltage NMOS transistor M33 is connected to a bias voltage VAN, the source is connected to the constant current source IB5 grounded to VSS and the drain of the high-voltage PMOS transistor M35, the drain is connected to the gate of the high-voltage PMOS transistor M35 and the constant current source IB4 connected to the power supply VCC, and generates the first bias node voltage VBP; the source of the PMOS transistor M35 is connected to the power supply VCC.

[0031] Continue reading Figure 2As shown, the second current mirror structure includes: constant current sources IB2~IB3, a high-voltage NMOS transistor M32, and a high-voltage PMOS transistor M34; the gate of the high-voltage PMOS transistor M34 is connected to a bias voltage VAP, the source is connected to the constant current source IB2 connected to the power supply VCC and the drain of the high-voltage NMOS transistor M32, the drain is connected to the gate of the high-voltage NMOS transistor M32 and the constant current source IB3 connected to ground VSS, and generates the second bias node voltage VBN; the source of the high-voltage NMOS transistor M32 is grounded to VSS.

[0032] Continue reading Figure 2 As shown, in a preferred embodiment of the present invention, the first negative feedback operational amplifier module includes: an auxiliary operational amplifier OPA1 and a high-voltage NMOS transistor M31; the positive input terminal of the auxiliary operational amplifier OPA1 is connected to the drain of the high-voltage NMOS transistor M31 and serves as a clamped output node one connected to the output stage module; the negative input terminal is connected to the first bias node voltage VBP; the output terminal is connected to the gate of the high-voltage NMOS transistor M31, and the source of the high-voltage NMOS transistor M31 is connected to the connection node of the second negative feedback operational amplifier module.

[0033] Continue reading Figure 2 As shown, the second negative feedback operational amplifier module includes: an auxiliary operational amplifier OPA2 and a high-voltage NMOS transistor M30; the positive input terminal of the auxiliary operational amplifier OPA2 is connected to the drain of the high-voltage NMOS transistor M30 and serves as the clamping output node two connected to the output stage module; the negative input terminal is connected to the second bias node voltage VBN; the output terminal is connected to the gate of the high-voltage NMOS transistor M30, and the source of the high-voltage NMOS transistor M30 serves as the connection node connected to the first negative feedback operational amplifier module.

[0034] like Figure 3 As shown, it also includes a bias voltage generation circuit, which includes: high-voltage PMOS transistors M36~M37 and resistors R1~R2; the gate and drain of the high-voltage PMOS transistor M36 are connected to the grounding resistor R2 connected to ground VSS and generate the bias voltage VAP; the source of the high-voltage PMOS transistor M36 is connected to the gate and drain of the high-voltage PMOS transistor M37 and generates the node voltage VA; the source of the high-voltage PMOS transistor M37 is connected to the resistor R1 connected to the power supply VCC and generates the bias voltage VAN; and R1=R2.

[0035] like Figure 4 As shown, this embodiment of the invention also provides a high-voltage CLASS-AB output stage operational amplifier circuit, comprising: The folded common source cascode input module is used to receive the input signal for first-stage amplification and to generate the input signal for the output stage module; The output stage bias module adopts a CLASS-AB output stage bias circuit for high-voltage operational amplifiers as described above; it is used to generate the bias voltage of the MOS transistor in the output stage module and control its static current. The output stage module adopts a CLASS-AB output stage; it is used to drive external loads and compensates for the frequency characteristics of the operational amplifier through a Miller structure.

[0036] Continue reading Figure 4 As shown, in a preferred embodiment of the present invention, the folded common-source common-gate input module includes: high-voltage PMOS transistors M1~M2, high-voltage NMOS transistors M3~M4, NMOS load transistors M5~M8, high-voltage NMOS transistor M9, PMOS load transistors M12~M15, PMOS load transistor M22, and a constant current source IB1; the source of the high-voltage PMOS transistors M1~M2 is connected to the constant current source IB1 connected to the power supply VCC, the drain of the high-voltage PMOS transistor M1 is connected to the drain of the NMOS load transistor M5 and the source of the NMOS load transistor M7, and the drain of the high-voltage PMOS transistor M2 is connected to... The drain of NMOS load transistor M6 and the source of NMOS load transistor M8 are connected; the gates of the high-voltage PMOS transistor M1 and the high-voltage NMOS transistor M4 are connected to the input port VIN, and the gates of the high-voltage PMOS transistor M2 and the high-voltage NMOS transistor M3 are connected to the input port VIP; the sources of the high-voltage NMOS transistors M3-M4 are connected to the constant current source IB1 grounded to VSS; the drain of the high-voltage NMOS transistor M3 is connected to the source of PMOS load transistors M13 and M22, and the drain of PMOS load transistor M15; the drain of the high-voltage NMOS transistor M4 is connected to the PMOS... The source of load transistor M12 and the drain of PMOS load transistor M14 are connected; the sources of PMOS load transistors M14-M15 are connected to power supply VCC, and the gates of PMOS load transistors M14-M15 are connected to the drains of PMOS load transistor M12 and high-voltage NMOS transistor M9; the gate of PMOS load transistor M12 is connected to the gates of PMOS load transistors M13 and M22, as well as the bias voltage VBP1; the drain of PMOS load transistor M13 is connected to the positive input terminal of the second negative feedback operational amplifier module, and the drain of PMOS load transistor M22 is connected to the first... The positive input terminal of the negative feedback operational amplifier module; the gate of the high-voltage NMOS transistor M9 is connected to the bias voltage VBN3, the source of the high-voltage NMOS transistor M9 is connected to the drain of the NMOS load transistor M7, and the gates of the NMOS load transistors M7~M8 are connected to the bias voltage VBN2; the drain of the NMOS load transistor M8 serves as a connection node connected to the source of the MOS transistor on the feedback terminal of the first negative feedback operational amplifier module and the second negative feedback operational amplifier module; the gates of the NMOS load transistors M5~M6 are connected to the bias voltage VBN1, and the sources of the NMOS load transistors M5~M6 are grounded to VSS.

[0037] Continue reading Figure 4 As shown, in a preferred embodiment of the present invention, the output stage module includes: a high-voltage NMOS transistor M20, a high-voltage PMOS transistor M21, and two Miller structures connected in series by a resistor R and a capacitor C; the gate of the high-voltage NMOS transistor M20 is connected to the resistor terminal of one of the Miller structures, and generates a gate voltage VGN which is connected to the positive input terminal of the second negative feedback operational amplifier module; the source of the high-voltage NMOS transistor M20 is grounded to VSS; the gate of the high-voltage PMOS transistor M21 is connected to the resistor terminal of the other Miller structure, and generates a gate voltage VGP which is connected to the positive input terminal of the first negative feedback operational amplifier module; the source of the high-voltage PMOS transistor M21 is connected to the power supply VCC; the drains of the high-voltage NMOS transistor M20 and the high-voltage PMOS transistor M21 are connected to the capacitor terminals of the two Miller structures, and serve as the output port VOUT.

[0038] As a further description of the embodiments of the present invention, the CLASS-AB output stage bias module of the high-voltage operational amplifier of the present invention includes: high-voltage NMOS transistors M30~M33, high-voltage PMOS transistors M34 and M35, auxiliary operational amplifiers OPA1 and OPA2, and fixed current sources IB2~IB5, wherein IB2>IB3 and IB4<IB5. The drain of NMOS transistor M30 is connected to the drain of the common-source common-gate current mirror PMOS load transistor M13 in the folded common-source common-gate input module, the gate is connected to the output terminal of the auxiliary operational amplifier OPA2, and the source is connected to the drain of NMOS load transistor M8 in the folded common-source common-gate input module; the source of NMOS transistor M31 is connected to the source of NMOS transistor M30, the gate is connected to the output terminal of the auxiliary operational amplifier OPA1, and the drain is connected to the drain of M22 in the folded common-source common-gate input module. The positive input terminal of the auxiliary operational amplifier OPA1 is connected to the drain of NMOS transistor M31 and the gate of PMOS output transistor M21 in the output stage module to VGP. The negative input terminal is connected to the gate of PMOS transistor M35 to VBP, and the output terminal is connected to the gate of NMOS transistor M31. The source of PMOS transistor M35 is connected to the power supply VCC, the drain is connected to the source of NMOS transistor M33, and the gate is connected to the drain of M33 to VBP. One end of current source IB4 is connected to the power supply VCC, and the other end is connected to the gate of M35 to VBP. The drain of NMOS transistor M33 is connected to the gate of M35 to VBP. The gate is connected to the source of PMOS transistor M37 in the bias module to VAN, and the source is connected to current source IB5. The other end of current source IB5 is grounded to the potential VSS.

[0039] The positive input terminal of the auxiliary operational amplifier OPA2 is connected to the drain of NMOS transistor M30 and the gate of NMOS output transistor M20 in the output stage module to VGN. The negative input terminal is connected to the gate of NMOS transistor M32 to VBN, and the output terminal is connected to the gate of NMOS transistor M30. The drain of PMOS transistor M34 is connected to the gate of NMOS transistor M32 to VBN. The gate is connected to the drain of PMOS transistor M36 in the bias module to VAP. The source is connected to current source IB2, and the other end of current source IB2 is connected to power supply VCC. The drain of NMOS transistor M32 is connected to the source of M34, and the gate is connected to the drain of M34 to VBN. The source is grounded at potential VSS. One end of current source IB3 is connected to the gate of NMOS transistor M32 to VBN, and the other end is grounded at potential VSS.

[0040] As a further description of the embodiments of the present invention, the following working principle is also included: The gate voltage VGN of NMOS output transistor M20 serves as the positive input signal to the auxiliary operational amplifier OPA2, and the gate voltage VBN of NMOS transistor M32 serves as the negative input signal to the auxiliary operational amplifier OPA2. The output of OPA2 controls the gate of NMOS transistor M30, and the drain of M30 is connected to the positive input VGN of the operational amplifier, forming a negative feedback structure. When the VGN voltage increases, the output voltage of the auxiliary operational amplifier OPA2 increases, that is, the gate voltage of NMOS transistor M30 increases, and the drain voltage (VGN) of M30 decreases. Ultimately, the voltages at the positive and negative terminals of the auxiliary operational amplifier become equal, i.e., VGN = VBN. Through the above negative feedback structure, the gate-source voltage difference of NMOS output transistor M20 is made equal to the gate-source voltage difference of NMOS transistor M32, i.e. Drain-source voltage of NMOS transistor M32 =VAP+ Since VAP=VA- VA = VCC / 2, then =VA- + ,Right now It is approximately equal to VCC / 2; typically, the op-amp output common-mode voltage is VCC / 2, therefore VOUT = VCC / 2, that is... =VCC / 2. Because , =VCC / 2, and the current flowing through M32 is provided by current sources IB2-IB3. Therefore, the current flowing through NMOS transistor M20 is K1 times that of current sources IB2-IB3, where K1 is the width-to-length ratio of M20 and M32. Similarly, by using the negative feedback structure of auxiliary operational amplifier OPA1, the gate-source voltage difference of PMOS output transistor M21 is made equal to the gate-source voltage of PMOS transistor M35 in the bias module, i.e. Drain-source voltage of PMOS transistor M35 =VAN- Since VAN = VA + VA = VCC / 2, then = VA+ - ,Right now It is approximately equal to VCC / 2. Because , =VCC / 2, and the current flowing through M35 is provided by current source IB5-IB4. Therefore, the current flowing through PMOS transistor M21 is K2 times that of current source IB5-IB4, where K2 is the ratio of the width to the length of M21 to M35. Usually, we let IB2-IB3 = IB5-IB4, and K1 = K2.

[0041] In summary, this invention uses the aforementioned negative feedback structure instead of the transconducting linear loop structure to bias the output stage MOSFET. By directly clamping the gate voltage of the output stage MOSFET using the negative feedback structure, it ensures that the gate-source voltage of the output stage MOSFET and the mirrored MOSFET are the same, as well as that of the source-drain voltage. Compared to the traditional transconducting linear loop structure, this eliminates the influence of channel length modulation effect on the floating current source and the output stage MOSFET, enabling more precise control of the output stage bias current. It solves the problem of inaccurate current mirroring in the transconducting linear loop caused by channel length modulation effect, which leads to inaccurate bias current control of the output stage transistor. Furthermore, when the operational amplifier power supply voltage changes significantly, the static current change of the output stage MOSFET is smaller, improving the power supply rejection ratio of the CLASS-AB output stage operational amplifier.

[0042] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A CLASS-AB output stage bias circuit for a high-voltage operational amplifier, characterized in that, include: The first bias module, by adopting a first current mirror structure and utilizing an unbalanced configuration of a set of current sources, processes the externally input bias voltage VAN to generate a stable first bias node voltage VBP. The second bias module, by employing a second current mirror structure and utilizing an unbalanced configuration of a set of current sources, processes the externally input bias voltage VAP to generate a stable second bias node voltage VBN. The first negative feedback operational amplifier module has its positive input terminal connected to the feedback terminal and used as the clamping output node one of the output stage module, and its negative input terminal connected to the first bias node voltage VBP. The second negative feedback operational amplifier module has its positive input terminal connected to the feedback terminal and used as the clamping output node two connected to the output stage module, and its negative input terminal connected to the second bias node voltage VBN. The first negative feedback operational amplifier module and the second negative feedback operational amplifier module clamp the gate voltage of the two MOS transistors in the output stage module, respectively, and ensure that the gate-source voltage and source-drain voltage of the two MOS transistors in the output stage module are the same as those of the two mirrored MOS transistors in the first current mirror structure and the second current mirror structure.

2. The CLASS-AB output stage bias circuit for a high-voltage operational amplifier as described in claim 1, characterized in that, The first current mirror structure includes: constant current sources IB4~IB5, a high-voltage NMOS transistor M33, and a high-voltage PMOS transistor M35; the gate of the high-voltage NMOS transistor M33 is connected to a bias voltage VAN, the source is connected to the constant current source IB5 grounded to VSS and the drain of the high-voltage PMOS transistor M35, the drain is connected to the gate of the high-voltage PMOS transistor M35 and the constant current source IB4 connected to the power supply VCC, and generates the first bias node voltage VBP; the source of the PMOS transistor M35 is connected to the power supply VCC; The second current mirror structure includes: constant current sources IB2~IB3, a high-voltage NMOS transistor M32, and a high-voltage PMOS transistor M34; the gate of the high-voltage PMOS transistor M34 is connected to a bias voltage VAP, the source is connected to the constant current source IB2 connected to the power supply VCC and the drain of the high-voltage NMOS transistor M32, the drain is connected to the gate of the high-voltage NMOS transistor M32 and the constant current source IB3 connected to ground VSS, and generates the second bias node voltage VBN; the source of the high-voltage NMOS transistor M32 is grounded to VSS.

3. The CLASS-AB output stage bias circuit for a high-voltage operational amplifier as described in claim 2, characterized in that, The constant current source IB2 is greater than the constant current source IB3, and the constant current source IB4 is less than the constant current source IB5.

4. The CLASS-AB output stage bias circuit for a high-voltage operational amplifier as described in claim 3, characterized in that, The current flowing through the high-voltage NMOS transistor M32 is equal to the difference between the constant current source IB2 and the constant current source IB3. Therefore, the current flowing through a MOS transistor in the output stage module is K1 times the difference between the constant current source IB2 and the constant current source IB3, where K1 is the ratio of the width to the length of the MOS transistor in the output stage module to the width of the high-voltage NMOS transistor M32. The current flowing through the high-voltage PMOS transistor M35 is equal to the difference between the constant current source IB5 and the constant current source IB4. Therefore, the current flowing through the other MOS transistor in the output stage module is K2 times the difference between the constant current source IB5 and the constant current source IB4, where K2 is the ratio of the width to length of the MOS transistor in the output stage module to that of the high-voltage PMOS transistor M35. Let IB2-IB3=IB5-IB4, and K1=K2.

5. The CLASS-AB output stage bias circuit for a high-voltage operational amplifier as described in claim 1, characterized in that, The first negative feedback operational amplifier module includes: an auxiliary operational amplifier OPA1 and a high-voltage NMOS transistor M31; the positive input terminal of the auxiliary operational amplifier OPA1 is connected to the drain of the high-voltage NMOS transistor M31 and serves as the clamping output node one connected to the output stage module; the negative input terminal is connected to the first bias node voltage VBP; the output terminal is connected to the gate of the high-voltage NMOS transistor M31, and the source of the high-voltage NMOS transistor M31 is connected to the connection node of the second negative feedback operational amplifier module; The second negative feedback operational amplifier module includes: an auxiliary operational amplifier OPA2 and a high-voltage NMOS transistor M30; the positive input terminal of the auxiliary operational amplifier OPA2 is connected to the drain of the high-voltage NMOS transistor M30 and serves as the clamping output node two connected to the output stage module; the negative input terminal is connected to the second bias node voltage VBN; the output terminal is connected to the gate of the high-voltage NMOS transistor M30, and the source of the high-voltage NMOS transistor M30 serves as the connection node connected to the first negative feedback operational amplifier module.

6. The CLASS-AB output stage bias circuit for a high-voltage operational amplifier as described in claim 1, characterized in that, It also includes a bias voltage generation circuit, which comprises: high-voltage PMOS transistors M36~M37 and resistors R1~R2; the gate and drain of the high-voltage PMOS transistor M36 are connected to the grounding resistor R2 connected to ground VSS and generate the bias voltage VAP; the source of the high-voltage PMOS transistor M36 is connected to the gate and drain of the high-voltage PMOS transistor M37 and generates the node voltage VA; the source of the high-voltage PMOS transistor M37 is connected to the resistor R1 connected to the power supply VCC and generates the bias voltage VAN.

7. The CLASS-AB output stage bias circuit for a high-voltage operational amplifier as described in claim 6, characterized in that, The resistance values ​​of resistor R1 and resistor R2 are equal.

8. A high-voltage CLASS-AB output stage operational amplifier circuit, characterized in that, include: The folded common source cascode input module is used to receive the input signal for first-stage amplification and to generate the input signal for the output stage module; The output stage bias module adopts a CLASS-AB output stage bias circuit for high-voltage operational amplifiers as described in any one of claims 1 to 7. Used to generate the bias voltage of the MOSFET in the output stage module and control its quiescent current; The output stage module adopts a CLASS-AB output stage; it is used to drive external loads and compensates for the frequency characteristics of the operational amplifier through a Miller structure.

9. The high-voltage CLASS-AB output stage operational amplifier circuit as described in claim 8, characterized in that, The folded common-source common-gate input module includes: high-voltage PMOS transistors M1~M2, high-voltage NMOS transistors M3~M4, NMOS load transistors M5~M8, high-voltage NMOS transistor M9, PMOS load transistors M12~M15, PMOS load transistor M22, and a constant current source IB1; the source of the high-voltage PMOS transistors M1~M2 is connected to the constant current source IB1 connected to the power supply VCC, the drain of the high-voltage PMOS transistor M1 is connected to the drain of NMOS load transistor M5 and the source of NMOS load transistor M7, and the drain of the high-voltage PMOS transistor M2 is connected to the drain of NMOS load transistor M6. The source of the NMOS load transistor M8 is connected to the high-voltage PMOS transistor M1 and the high-voltage NMOS transistor M4; the gates of the high-voltage PMOS transistor M2 and the high-voltage NMOS transistor M3 are connected to the input port VIP; the sources of the high-voltage NMOS transistors M3-M4 are connected to the constant current source IB1 grounded to VSS; the drain of the high-voltage NMOS transistor M3 is connected to the source of the PMOS load transistors M13 and M22, and the drain of the PMOS load transistor M15; the drain of the high-voltage NMOS transistor M4 is connected to the source of the PMOS load transistor M12. The source of each PMOS load transistor M14-M15 is connected to the power supply VCC, and the gate of each PMOS load transistor M14-M15 is connected to the drain of each PMOS load transistor M12 and the high-voltage NMOS transistor M9. The gate of each PMOS load transistor M12 is connected to the gate of each PMOS load transistor M13 and PMOS load transistor M22, as well as the bias voltage VBP1. The drain of each PMOS load transistor M13 is connected to the positive input terminal of the second negative feedback operational amplifier module, and the drain of each PMOS load transistor M22 is connected to the first negative feedback operational amplifier module. The positive input terminal of the amplifier module; the gate of the high-voltage NMOS transistor M9 is connected to the bias voltage VBN3, the source of the high-voltage NMOS transistor M9 is connected to the drain of the NMOS load transistor M7, and the gates of the NMOS load transistors M7~M8 are connected to the bias voltage VBN2; the drain of the NMOS load transistor M8 is connected as a connection node to the source of the MOS transistor on the feedback terminal of the first negative feedback operational amplifier module and the second negative feedback operational amplifier module; the gates of the NMOS load transistors M5~M6 are connected to the bias voltage VBN1, and the sources of the NMOS load transistors M5~M6 are grounded to VSS.

10. The high-voltage CLASS-AB output stage operational amplifier circuit as described in claim 8, characterized in that, The output stage module includes: a high-voltage NMOS transistor M20, a high-voltage PMOS transistor M21, and two Miller structures connected in series by a resistor R and a capacitor C; the gate of the high-voltage NMOS transistor M20 is connected to the resistor terminal of one of the Miller structures, generating a gate voltage VGN which is connected to the positive input terminal of the second negative feedback operational amplifier module; the source of the high-voltage NMOS transistor M20 is grounded to VSS; the gate of the high-voltage PMOS transistor M21 is connected to the resistor terminal of the other Miller structure, generating a gate voltage VGP which is connected to the positive input terminal of the first negative feedback operational amplifier module; the source of the high-voltage PMOS transistor M21 is connected to the power supply VCC; the drains of the high-voltage NMOS transistor M20 and the high-voltage PMOS transistor M21 are connected to the capacitor terminals of the two Miller structures, serving as the output port VOUT.

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