Electronic circuit module

Abstract

An electronic circuit module is provided. It suppresses wiring length and suppresses interference between baluns. The electronic circuit module includes: a main substrate; a first semiconductor substrate disposed on the main substrate, having a first side and a second side different from the first side; a second semiconductor substrate disposed on the main substrate, having a third side and a fourth side different from the third side; a first balun disposed on a first region of the main substrate adjacent to the first side of the first semiconductor substrate and adjacent to the third side of the second semiconductor substrate; and a second balun disposed on a second region of the main substrate adjacent to the second side of the first semiconductor substrate and adjacent to the fourth side of the second semiconductor substrate.

Description

Technical Field

[0001] This disclosure relates to an electronic circuit module. Background Technology

[0002] Patent Document 1 describes a high-frequency module. In the high-frequency module described in Patent Document 1, two baluns are separately configured. As a result, the high-frequency module described in Patent Document 1 can suppress mutual interference between the two baluns.

[0003] However, Patent Document 1 does not provide details on the specific configuration of the switching IC and the balun.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-175053 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In high-frequency modules, if the switching IC and the balun are configured separately, the wiring between them becomes longer. Therefore, the switching IC and the balun are preferably configured close to each other.

[0009] On the other hand, if two baluns are configured close to each other, they will interfere with each other.

[0010] This disclosure was made in view of the above circumstances, and its purpose is to suppress the length of the wiring and to suppress interference between baluns.

[0011] Solution for solving the problem

[0012] An electronic circuit module of one aspect of this disclosure includes: a main substrate; a first semiconductor substrate disposed on the main substrate, having a first side and a second side different from the first side; a second semiconductor substrate disposed on the main substrate, having a third side and a fourth side different from the third side; a first balun disposed on a first region of the main substrate adjacent to the first side of the first semiconductor substrate and adjacent to the third side of the second semiconductor substrate; and a second balun disposed on a second region of the main substrate adjacent to the second side of the first semiconductor substrate and adjacent to the fourth side of the second semiconductor substrate.

[0013] An electronic circuit module of one aspect of this disclosure includes: a main substrate; a first semiconductor substrate disposed on the main substrate; a second semiconductor substrate disposed on the main substrate; a first balun disposed on the main substrate; and a second balun disposed on the main substrate. The first balun is connected to the first semiconductor substrate in a first connection direction. The second balun is connected to the first semiconductor substrate in a second connection direction different from the first connection direction. The first balun is connected to the second semiconductor substrate in a third connection direction. The second balun is connected to the second semiconductor substrate in a fourth connection direction different from the third connection direction.

[0014] The effects of the invention

[0015] According to this disclosure, it is possible to suppress the length of the wiring and suppress interference between baluns and unbalanced converters. Attached Figure Description

[0016] Figure 1 This is a diagram showing the circuit structure of the high-frequency module according to the first embodiment.

[0017] Figure 2 This is a top view showing the structure of the electronic circuit module according to the first embodiment.

[0018] Figure 3 This is a diagram showing the first wiring layer of the substrate of the electronic circuit module according to the first embodiment.

[0019] Figure 4 This is a diagram showing the second wiring layer of the substrate of the electronic circuit module of the first embodiment.

[0020] Figure 5 This is a cross-sectional view showing the electronic circuit module of the first embodiment.

[0021] Figure 6 This is a diagram showing the structure of the electronic circuit module according to the second embodiment. Detailed Implementation

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, the invention is not intended to be limited by these embodiments. The embodiments are illustrative, and it is self-evident that partial substitutions or combinations of the structures shown in different embodiments are possible. In embodiments following the second embodiment, descriptions of matters common to the first embodiment are omitted, and only the differences are described. In particular, the same effects achieved by the same structure are not mentioned sequentially for each embodiment.

[0023] <First Implementation Method>

[0024] (Circuit Structure)

[0025] Figure 1 This is a diagram showing the circuit structure of the high-frequency module according to the first embodiment.

[0026] The electronic circuit module 1 can be implemented, for example, as a printed circuit board (PCB) by mounting multiple semiconductor substrates (multiple semiconductor devices) on a substrate (e.g., a printed wiring board (PWB)).

[0027] Electronic circuit module 1 includes amplifier 11, divider 12, amplifier 13, amplifier 14, amplifier 15, amplifier 16, capacitor 17, capacitor 18, balun 19, balun 20, switch 21, and switch 22.

[0028] Electronic circuit module 1 has a first mode (hereinafter, sometimes referred to as "high power mode"), in which all amplifiers 13 to 16 perform amplification, i.e., outputting relatively high power. Additionally, electronic circuit module 1 has a second mode (hereinafter, sometimes referred to as "low power mode"), in which only amplifiers 15 and 16 perform amplification, while amplifiers 13 and 14 do not perform amplification, i.e., outputting relatively low power. An example is given where the output power of the second mode is half that of the first mode, but this disclosure is not limited thereto.

[0029] Amplifier 13 includes transistor 31. Amplifier 14 includes transistor 32. Amplifier 15 includes transistor 33. Amplifier 16 includes transistor 34.

[0030] In this disclosure, each transistor is assumed to be a bipolar transistor, but this disclosure is not limited thereto. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but this disclosure is not limited thereto. A transistor can also be, for example, a field-effect transistor (FET). A transistor can also be a polyfinite transistor formed by electrically connecting multiple unit transistors in parallel. A unit transistor refers to the minimum structural design required to constitute a transistor.

[0031] When each transistor is a FET, its source corresponds to the emitter of the bipolar transistor, its gate corresponds to the base of the bipolar transistor, and its drain corresponds to the collector of the bipolar transistor.

[0032] In this embodiment, transistors 31 to 34 are assumed to have the same size (index), but this disclosure is not limited thereto. The sizes of transistors 31 to 34 may also be different.

[0033] The balun 19 includes a first winding 41 and a second winding 42. The balun 20 includes a first winding 43 and a second winding 44.

[0034] The balun 20 corresponds to an example of the "first balun" of this disclosure. The balun 19 corresponds to an example of the "second balun" of this disclosure.

[0035] In this embodiment, the inductance values ​​of the first winding 41 to the second winding 44 are assumed to be the same, but this disclosure is not limited to this. The inductance values ​​of the first winding 41 to the second winding 44 may also be different.

[0036] Switch 21 is an example of the "first switch" of this disclosure. Switch 22 is an example of the "second switch" of this disclosure.

[0037] A single-ended (unbalanced) high-frequency signal RF is input to terminal 71 of electronic circuit module 1.

[0038] The input terminal of amplifier 11 is electrically connected to terminal 71. Amplifier 11 amplifies the single-ended high-frequency signal RF input to the input terminal and outputs the amplified single-ended high-frequency signal RFIN from the output terminal.

[0039] The input terminal 51 of the distributor 12 is electrically connected to the output terminal of the amplifier 11. The distributor 12 converts the single-ended high-frequency signal RFIN input to the input terminal 51 into a first-phase high-frequency signal RFIN+ and a second-phase high-frequency signal RFIN- constituting a differential signal (balanced signal). The distributor 12 outputs the first-phase high-frequency signal RFIN+ from the first output terminal 52 and the third output terminal 54. The distributor 12 outputs the second-phase high-frequency signal RFIN- from the second output terminal 53 and the fourth output terminal 55.

[0040] In this embodiment, the first phase is assumed to be positive (positive polarity) and the second phase is assumed to be negative (negative polarity), but this disclosure is not limited to this. Alternatively, the first phase may be assumed to be negative and the second phase to be positive.

[0041] Bias circuit 201 outputs a base bias current to the base of transistor 31 according to the control signal S1 output from control circuit 205. Bias circuit 202 outputs a base bias current to the base of transistor 32 according to the control signal S2 output from control circuit 205. Bias circuit 203 outputs a base bias current to the base of transistor 33 according to the control signal S3 output from control circuit 205. Bias circuit 204 outputs a base bias current to the base of transistor 34 according to the control signal S4 output from control circuit 205.

[0042] The emitter of transistor 31 is electrically connected to a reference potential. Ground potential is exemplified as a reference potential, but this disclosure is not limited thereto. The base of transistor 31 is electrically connected to the first output terminal 52 of distributor 12 and the bias circuit 201. A first-phase high-frequency signal RFIN+ is input from the first output terminal 52 of distributor 12 to the base of transistor 31, and a base bias current is input from the bias circuit 201 to the base of transistor 31.

[0043] The collector of transistor 31 is electrically connected to one end of the first winding 41 of the balun 19. The midpoint of the first winding 41 is electrically connected to terminal 72 of the electronic circuit module 1. A power supply voltage Vcc is input to the midpoint of the first winding 41 via terminal 72. The power supply voltage Vcc is also input to the collector of transistor 31 via terminal 72, the midpoint of the first winding 41, and one end of the first winding 41. Transistor 31 amplifies the first-phase high-frequency signal RFIN+ input to its base and outputs the amplified first-phase high-frequency signal RF1 from its collector.

[0044] The emitter of transistor 32 is electrically connected to a reference potential. The base of transistor 32 is electrically connected to the second output terminal 53 of distributor 12 and the bias circuit 202. A second-phase high-frequency signal RFIN- is input from the second output terminal 53 of distributor 12 to the base of transistor 32, and a base bias current is input from the bias circuit 202 to the base of transistor 32.

[0045] The collector of transistor 32 is electrically connected to the other end of the first winding 41 of balun 19. A power supply voltage Vcc is input to the collector of transistor 32 via terminal 72, the midpoint of the first winding 41, and the other end of the first winding 41. Transistor 32 amplifies the second-phase high-frequency signal RFIN- input to its base and outputs the amplified second-phase high-frequency signal RF2 from its collector.

[0046] One end of capacitor 17 is electrically connected to the collector of transistor 31. The other end of capacitor 17 is electrically connected to the collector of transistor 32.

[0047] Capacitor 17 serves to match the impedance between the collector of transistor 31 and the collector of transistor 32.

[0048] In the first winding 41 of the balun 19, the first phase high-frequency signal RF1 output from the collector of transistor 31 and the second phase high-frequency signal RF2 output from the collector of transistor 32 are superimposed (synthesized).

[0049] The emitter of transistor 33 is electrically connected to a reference potential. The base of transistor 33 is electrically connected to the third output terminal 54 of distributor 12 and the bias circuit 203. A first-phase high-frequency signal RFIN+ is input from the third output terminal 54 of distributor 12 to the base of transistor 33, and a base bias current is input from the bias circuit 203 to the base of transistor 33.

[0050] The collector of transistor 33 is electrically connected to one end of the first winding 43 of the balun 20. The midpoint of the first winding 43 is electrically connected to terminal 73 of the electronic circuit module 1. A power supply voltage Vcc is input to the midpoint of the first winding 43 via terminal 73. The power supply voltage Vcc is also input to the collector of transistor 33 via terminal 73, the midpoint of the first winding 43, and one end of the first winding 43. Transistor 33 amplifies the first-phase high-frequency signal RFIN+ input to its base and outputs the amplified first-phase high-frequency signal RF3 from its collector.

[0051] The power supply voltage input to terminal 72 can be the same as or different from the power supply voltage input to terminal 73.

[0052] The emitter of transistor 34 is electrically connected to a reference potential. The base of transistor 34 is electrically connected to the fourth output terminal 55 of distributor 12 and the bias circuit 204. A second-phase high-frequency signal RFIN- is input from the fourth output terminal 55 of distributor 12 to the base of transistor 34, and a base bias current is input from the bias circuit 204 to the base of transistor 34.

[0053] The collector of transistor 34 is electrically connected to the other end of the first winding 43 of the balun 20. A power supply voltage Vcc is input to the collector of transistor 34 via terminal 73, the midpoint of the first winding 43, and the other end of the first winding 43. Transistor 34 amplifies the second-phase high-frequency signal RFIN- input to its base and outputs the amplified second-phase high-frequency signal RF4 from its collector.

[0054] One end of capacitor 18 is electrically connected to the collector of transistor 33. The other end of capacitor 18 is electrically connected to the collector of transistor 34.

[0055] Capacitor 18 serves to match the impedance between the collector of transistor 33 and the collector of transistor 34.

[0056] In the first winding 43 of the balun 20, the first phase high-frequency signal RF3 output from the collector of transistor 33 and the second phase high-frequency signal RF4 output from the collector of transistor 34 are superimposed (synthesized).

[0057] One end of the second winding 42 of the balun 19 is electrically connected to terminal 74. The other end of the second winding 42 is grounded in a DC or AC manner. For example, an example is shown where the other end of the second winding 42 is electrically connected to a reference potential, but this disclosure is not limited thereto.

[0058] The first winding 41 and the second winding 42 are magnetically coupled as shown by dashed line 151. Therefore, the high-frequency signal generated in the first winding 41 propagates to the second winding 42 by means of magnetic coupling and is output from terminal 74.

[0059] One end of switch 21 is electrically connected to one end of the second winding 42 of balun 19 and terminal 74. The other end of switch 21 is electrically connected to one end of the second winding 44 of balun 20 and terminal 61 of switch 22. The other end of the second winding 44 of balun 20 is grounded in a DC or AC manner. For example, an example is shown where the other end of the second winding 44 is electrically connected to a reference potential, but this disclosure is not limited thereto.

[0060] Switch 21 is controlled to be in an on or off state according to the control signal S5 output from control circuit 205.

[0061] The first winding 43 and the second winding 44 of the balun 20 are magnetically coupled as shown by dashed line 152. Therefore, the high-frequency signal generated in the first winding 43 propagates to the second winding 44 via magnetic coupling.

[0062] Terminals 62a, 62b, ..., 62n (n is a natural number) of switch 22 are electrically connected to terminals 75a, 75b, ..., 75n of electronic circuit module 1, respectively.

[0063] According to the control signal S6 output from the control circuit 205, the switch 22 does not electrically connect terminal 61 to any of the multiple terminals 62a, 62b, ..., 62n (switch open state).

[0064] In addition, switch 22 electrically connects terminal 61 to any one of the multiple terminals 62a, 62b, ..., 62n according to control signal S6 (switch on state).

[0065] (Movement in Mode 1)

[0066] When electronic circuit module 1 operates in the first mode, control circuit 205 controls the output of base bias current for all bias circuits from bias circuit 201 to bias circuit 204. As a result, all amplifiers from amplifier 13 to amplifier 16 perform amplification operations.

[0067] In addition, when the electronic circuit module 1 operates in the first mode, the control circuit 205 controls the switch 21 to be in the on state.

[0068] In addition, when the electronic circuit module 1 operates in the first mode, the control circuit 205 controls the switch 22 to be in the off state.

[0069] When switch 21 is in the ON state, one end of the second winding 44 of the balun 20 is electrically connected to one end of the second winding 42 of the balun 19 and terminal 74. That is, the second winding 42 and the second winding 44 are connected in parallel.

[0070] Therefore, the high-frequency output signal RFOUT1 output from terminal 74 becomes a signal obtained by adding the current of the high-frequency signal output from one end of the second winding 42 and the high-frequency signal output from one end of the second winding 44.

[0071] (Action in the second mode)

[0072] When electronic circuit module 1 operates in the second mode, control circuit 205 controls the output base bias current of bias circuits 203 and 204. As a result, amplifiers 15 and 16 perform amplification operations.

[0073] Furthermore, when electronic circuit module 1 operates in the second mode, control circuit 205 controls the output of base bias current to be absent from bias circuits 201 and 202. Consequently, amplifiers 13 and 14 do not perform amplification.

[0074] In addition, when the electronic circuit module 1 operates in the second mode, the control circuit 205 controls the switch 21 to be in the off state.

[0075] Furthermore, when electronic circuit module 1 operates in the second mode, control circuit 205 controls switch 22 to the ON state. Thus, terminal 61 is electrically connected to any one of the plurality of terminals 62a, 62b, ..., 62n.

[0076] When switch 21 is in the open state, one end of the second winding 42 of the balancing-unbalancing converter 19, one end of the second winding 44 of the balancing-unbalancing converter 20, and terminal 61 of switch 22 are electrically disconnected.

[0077] Therefore, the high-frequency output signal RFOUT2, which is input to terminal 61 of switch 22 and output from any of the terminals 62a, 62b, ..., 62n of switch 22, is a high-frequency signal output from one end of the second winding 44.

[0078] (Effect) (1)

[0080] Consider the following scenario: there is no switch 21, and one end of the second winding 44 of the balancing-unbalancing converter 20 is always electrically connected to one end of the second winding 42 and terminal 74 of the balancing-unbalancing converter 19.

[0081] When electronic circuit module 1 operates in the second mode, amplifiers 13 and 14 do not perform amplification.

[0082] In this case, when the electronic circuit module 1 is viewed from the side of terminals 75a, 75b, ..., 75n (load side), the parallel resonant circuit consisting of capacitor 17 and the first winding 41 of the balun 19 appears to be electromagnetically connected to terminals 75a, 75b, ..., 75n by means of magnetic field coupling between the first winding 41 and the second winding 42 (refer to dashed line 151).

[0083] The resonant frequency of the parallel resonant circuit (capacitor 17 and first winding 41) is approximately the same as the frequency of the high-frequency signals (first phase high-frequency signal RFIN+, second phase high-frequency signal RFIN-, high-frequency output signal RFOUT1, and high-frequency output signal RFOUT2).

[0084] Therefore, the electronic circuit module 1 experiences power loss and reduced efficiency due to the aforementioned parallel resonant circuit (capacitor 17 and first winding 41).

[0085] On the other hand, in the implementation, when the electronic circuit module 1 operates in the second mode, the control circuit 205 controls the switch 21 to be in the off state.

[0086] As a result, one end of the second winding 44 is electrically disconnected from one end of the second winding 42.

[0087] In this case, when the electronic circuit module 1 is viewed from the terminals 75a, 75b, ..., 75n (load side), the aforementioned parallel resonant circuit (capacitor 17 and first winding 41) appears to have no electromagnetic connection with the terminals 75a, 75b, ..., 75n.

[0088] Therefore, electronic circuit module 1 can suppress power loss caused by the above-mentioned parallel resonant circuit (capacitor 17 and first winding 41) and suppress the reduction in efficiency.

[0089] In this way, electronic circuit module 1 can suppress power loss, suppress the reduction of efficiency, and achieve a first mode with relatively large output power and a second mode with relatively small output power. (2)

[0091] When the electronic circuit module 1 operates in the first mode, it outputs a high-frequency output signal RFOUT1 from terminal 74.

[0092] In addition, when the electronic circuit module 1 operates in the second mode, it outputs a high-frequency output signal RFOUT2 from any of the terminals 75a, 75b, ..., 75n.

[0093] Therefore, when the electronic circuit module 1 operates in the first mode and when it operates in the second mode, the signal paths of the high-frequency output signal RFOUT1 and the high-frequency output signal RFOUT2 are different. (3)

[0095] A power supply voltage Vcc is provided to the midpoint of the first winding 41 of the balun 19 via terminal 72. A power supply voltage Vcc is provided to the midpoint of the first winding 43 of the balun 20 via terminal 73. That is, terminal 72, which provides the power supply voltage Vcc to amplifiers 13 and 14, is separate from terminal 73, which provides the power supply voltage Vcc to amplifiers 15 and 16.

[0096] Therefore, compared to the case where only one terminal is set for supplying the power supply voltage Vcc from amplifier 13 to amplifier 16, the current value of each power supply terminal can be suppressed.

[0097] (Structure of electronic circuit module)

[0098] Figure 2 This is a top view showing the structure of the electronic circuit module according to the first embodiment.

[0099] The electronic circuit module 1 includes a substrate 81, a semiconductor substrate 82, and a semiconductor substrate 83.

[0100] Substrate 81 corresponds to an example of the "main substrate" of this disclosure. Semiconductor substrate 82 corresponds to an example of the "first semiconductor substrate" of this disclosure. Semiconductor substrate 83 corresponds to an example of the "second semiconductor substrate" of this disclosure.

[0101] Regarding substrate 81, a printed wiring substrate (PWB) is illustrated, but this disclosure is not limited thereto. Semiconductor substrate 82 and semiconductor substrate 83 may each be a bare die or be encapsulated in a package.

[0102] The semiconductor substrate 82 includes amplifier 11, distributor 12, amplifier 13, amplifier 14, amplifier 15 and amplifier 16.

[0103] The semiconductor substrate 83 includes switches 21 and 22.

[0104] The substrate 81 has a first main surface 81a (the main surface on the front end side of the Z axis) extending along the XY plane. Semiconductor substrate 82 and semiconductor substrate 83 are each mounted on the first main surface 81a of the substrate 81.

[0105] In this embodiment, semiconductor substrate 82 and semiconductor substrate 83 each have a quadrilateral shape (rectangular in this embodiment) when viewed from above, but the present invention is not limited thereto. Semiconductor substrate 82 and semiconductor substrate 83 may also each be polygonal (triangular, pentagonal, etc.) when viewed from above.

[0106] In this disclosure, a top view refers to viewing the first principal surface 81a from a direction perpendicular to it. In other words, a top view refers to viewing the first principal surface 81a from the front end side of the Z-axis toward the base end side.

[0107] The substrate 81 has a region 121 adjacent to the edge 82a (the edge on the base side of the Y-axis) of the semiconductor substrate 82 and the edge 83a (the edge on the base side of the X-axis) of the semiconductor substrate 83. A balun 19 is disposed in the region 121 of the substrate 81.

[0108] Edge 82a corresponds to an example of the "first edge" of this disclosure. Edge 83a corresponds to an example of the "third edge" of this disclosure. Region 121 corresponds to an example of the "first region" of this disclosure. Balance-to-unbalance converter 19 corresponds to an example of the "first balance-to-unbalance converter" of this disclosure.

[0109] In one embodiment, the balun 19 is formed on a first wiring layer (the wiring layer closest to the Z-axis front end) and a second wiring layer (the wiring layer adjacent to the Z-axis base end of the first wiring layer) on the substrate 81, but this disclosure is not limited thereto. The electronic components of the balun 19 may also be mounted on the first main surface 81a.

[0110] The substrate 81 has a region 122 adjacent to the edge 82b (the front edge side of the X-axis) of the semiconductor substrate 82 and the edge 83b (the front edge side of the Y-axis) of the semiconductor substrate 83. A balun 20 is disposed in the region 122 of the substrate 81.

[0111] Edge 82b corresponds to an example of the "second edge" of this disclosure. Edge 83b corresponds to an example of the "fourth edge" of this disclosure. Region 122 corresponds to an example of the "second region" of this disclosure. Balance-to-unbalance converter 20 corresponds to an example of the "second balance-to-unbalance converter" of this disclosure.

[0112] In one embodiment, the balun 20 is formed on the first and second wiring layers of the substrate 81, but this disclosure is not limited thereto. The electronic components of the balun 20 may also be mounted on the first main surface 81a.

[0113] Edges 82a and 82b are adjacent edges. In an embodiment, edges 82a and 82b are continuous at a 90° angle, but this disclosure is not limited to this. Edges 82a and 82b may be continuous at an angle less than 90° or at an angle greater than 90°.

[0114] Edges 83a and 83b are adjacent edges. In an embodiment, edges 83a and 83b are continuous at an angle of 90°, but this disclosure is not limited to this. Edges 83a and 83b may be continuous at an angle of less than 90° or at an angle of greater than 90°.

[0115] The semiconductor substrate 82 has terminals 91, 92, 93, and 94 on the surface facing the substrate 81 (the surface on the base end side of the Z-axis). Each of terminals 91, 92, 93, and 94 may also be a pad.

[0116] The output terminal of amplifier 13 is electrically connected to terminal 91. The output terminal of amplifier 14 is electrically connected to terminal 92. The output terminal of amplifier 15 is electrically connected to terminal 93. The output terminal of amplifier 16 is electrically connected to terminal 94.

[0117] The semiconductor substrate 83 has terminals 101 and 102 on the surface facing the substrate 81 (the surface on the base end side of the Z-axis). Terminals 101 and 102 may each be pads.

[0118] One end of switch 21 is electrically connected to terminal 101. The other end of switch 21 is electrically connected to terminal 102. One end of switch 22 is electrically connected to terminal 102.

[0119] The balun 19 includes a first winding 41 formed on a first wiring layer of substrate 81 and a second winding 42 formed on a second wiring layer of substrate 81.

[0120] The balun 20 includes a first winding 43 formed on a first wiring layer of substrate 81 and a second winding 44 formed on a second wiring layer of substrate 81.

[0121] Figure 3 This is a diagram showing the first wiring layer of the substrate of the electronic circuit module according to the first embodiment. Figure 4 This is a diagram showing the second wiring layer of the substrate of the electronic circuit module of the first embodiment. Figure 5 This is a cross-sectional view showing the electronic circuit module of the first embodiment.

[0122] Figure 5 yes Figure 2 A cross-sectional view of electronic circuit module 1 at line AB.

[0123] The first winding 41 of the balun 19 (refer to) Figure 2 , Figure 3 as well as Figure 5 The first wiring layer formed on substrate 81 (refer to) Figure 5 The first winding 41, viewed from top, starts from one end 41b (see reference). Figure 2 , Figure 3 as well as Figure 5 )Wrap counterclockwise to the other end 41c (refer to) Figure 2 and Figure 3 The central portion 41a of the first winding 41 (refer to...) Figure 2 and Figure 3 It is electrically connected to the power supply voltage Vcc. An example is shown in which the central portion 41a is electrically connected to the power supply wiring formed on other wiring layers via a through-hole, but this disclosure is not limited thereto.

[0124] One end 41b of the first winding 41 (refer to...) Figure 2 , Figure 3 as well as Figure 5 ) Via wiring 111 extending along the Y-axis (refer to Figure 2 , Figure 3 as well as Figure 5 And with terminal 91 (refer to) Figure 2 and Figure 5 Electrical connection. The other end 41c of the first winding 41 (refer to...) Figure 2 and Figure 3 ) Via wiring 112 extending along the Y-axis (refer to Figure 2 and Figure 3 And with terminal 92 (refer to) Figure 2 Electrical connection.

[0125] The balun 19 is connected to the semiconductor substrate 82 in a direction from the base side of the Y-axis toward the front side.

[0126] The direction from the base side of the Y-axis toward the front side is an example of the "first connection direction" of this disclosure.

[0127] The second winding 42 of the balun 19 (refer to) Figure 4and Figure 5 The second wiring layer formed on substrate 81 (refer to) Figure 5 The second winding 42, viewed from top, starts from one end 42a (see reference). Figure 4 )Clockwise to the other end 42b (refer to) Figure 4 ).

[0128] One end 42a of the second winding 42 (refer to...) Figure 4 and Figure 5 ) Via wiring 115 extending along the X-axis (refer to) Figure 4 and Figure 5 ) and through hole 131 (refer to) Figure 5 And with terminal 101 (refer to) Figure 2 and Figure 5 Electrical connection. The other end 42b of the second winding 42 (refer to...) Figure 4 The other end 42b is electrically connected to a reference potential. An example is shown where the other end 42b is electrically connected to a reference potential wiring formed on another wiring layer via a via, but this disclosure is not limited thereto.

[0129] The balun 19 is connected to the semiconductor substrate 83 in a direction from the base side of the X-axis toward the front side.

[0130] The direction from the base side of the X-axis toward the front end side is an example of the "third connection direction" of this disclosure.

[0131] The first winding 43 of the balun 20 (refer to) Figure 2 and Figure 3 The first wiring layer of the substrate 81 is formed. The first winding 43, viewed from top, is wound counterclockwise from one end 43b to the other end 43c. The central portion 43a of the first winding 43 (see reference) Figure 2 and Figure 3 It is electrically connected to the power supply voltage Vcc. An example is shown where the central portion 43a is electrically connected to the power supply wiring formed on other wiring layers via a through-hole, but this disclosure is not limited thereto.

[0132] One end 43b of the first winding 43 (refer to...) Figure 2 and Figure 3 ) Via wiring 113 extending along the X-axis (refer to Figure 2 and Figure 3 And with terminal 93 (refer to) Figure 2 Electrical connection. The other end 43c of the first winding 43 (refer to...) Figure 2 and Figure 3 ) Via wiring 114 extending along the X-axis (refer to Figure 3 And with terminal 94 (refer to) Figure 2 Electrical connection.

[0133] The balun 20 is connected to the semiconductor substrate 82 in a direction from the front end side of the X-axis toward the base end side.

[0134] The direction from the front end side of the X-axis toward the base end side is an example of the "second connection direction" of this disclosure.

[0135] The second winding 44 of the balun 20 (refer to) Figure 4 The second wiring layer is formed on the substrate 81. The second winding 44, viewed from top, is wound clockwise from one end 44a to the other end 44b. One end 44a of the second winding 44 (refer to...) Figure 4 ) Via wiring 116 extending along the Y-axis (refer to Figure 4 And with terminal 102 (refer to) Figure 2 Electrical connection. The other end 44b of the second winding 44 (refer to...) Figure 4 It is electrically connected to a reference potential. An example is shown where the other end 44b is electrically connected to a reference potential wiring formed on another wiring layer via a via, but this disclosure is not limited thereto.

[0136] The balun 20 is connected to the semiconductor substrate 83 in a direction from the front end side of the Y-axis toward the base end side.

[0137] The direction from the front end side of the Y-axis toward the base end side is an example of the "fourth connection direction" of this disclosure.

[0138] In one embodiment, the first connection direction (the direction from the base side of the Y-axis toward the front end side) forms a 90° angle with the second connection direction (the direction from the front end side of the X-axis toward the base side), but this disclosure is not limited to this. The first connection direction and the second connection direction may form an angle less than 90° or an angle greater than 90°.

[0139] In one embodiment, the third connection direction (the direction from the base side of the X-axis toward the front end side) forms a 90° angle with the fourth connection direction (the direction from the front end side of the Y-axis toward the base side), but this disclosure is not limited to this. The third connection direction and the fourth connection direction may form an angle less than 90° or an angle greater than 90°.

[0140] In one embodiment, the first connection direction (the direction from the base end of the Y-axis toward the front end) forms a 90° angle with the third connection direction (the direction from the base end of the X-axis toward the front end), but this disclosure is not limited to this. The first connection direction and the third connection direction may form an angle less than 90° or an angle greater than 90°.

[0141] In one embodiment, the second connection direction (the direction from the front end side of the X-axis toward the base end side) forms a 90° angle with the fourth connection direction (the direction from the front end side of the Y-axis toward the base end side), but this disclosure is not limited to this. The second connection direction and the fourth connection direction may form an angle less than 90° or an angle greater than 90°.

[0142] (Effect)

[0143] Region 121 and Region 122 are not adjacent. Therefore, the balun 19 configured in Region 121 is separate from the balun 19 configured in Region 121.

[0144] Therefore, electronic circuit module 1 can suppress mutual interference between the signals of balun 19 and balun 20. Consequently, electronic circuit module 1 can improve high-frequency characteristics.

[0145] Semiconductor substrate 82 is adjacent to region 121. Therefore, electronic circuit module 1 can shorten the length of wiring 111 and wiring 112 between semiconductor substrate 82 and the first winding 41 of balun 19.

[0146] Therefore, electronic circuit module 1 can suppress path loss of high-frequency signals flowing between semiconductor substrate 82 and first winding 41. Consequently, electronic circuit module 1 can improve high-frequency characteristics.

[0147] Semiconductor substrate 82 is adjacent to region 122. Therefore, electronic circuit module 1 can shorten the length of wiring 113 and wiring 114 between semiconductor substrate 82 and the first winding 43 of balun 20.

[0148] Therefore, electronic circuit module 1 can suppress path loss of high-frequency signals flowing between semiconductor substrate 82 and first winding 43. Consequently, electronic circuit module 1 can improve high-frequency characteristics.

[0149] Semiconductor substrate 83 is adjacent to region 121. Therefore, electronic circuit module 1 can shorten the length of wiring 115 between semiconductor substrate 83 and the second winding 42 of balun 19.

[0150] Therefore, electronic circuit module 1 can suppress path loss of high-frequency signals flowing between semiconductor substrate 83 and second winding 42. Consequently, electronic circuit module 1 can improve high-frequency characteristics.

[0151] Semiconductor substrate 83 is adjacent to region 122. Therefore, electronic circuit module 1 can shorten the length of wiring 116 between semiconductor substrate 83 and the second winding 44 of balun 20.

[0152] Therefore, electronic circuit module 1 can suppress path loss of high-frequency signals flowing between semiconductor substrate 83 and second winding 44. Consequently, electronic circuit module 1 can improve high-frequency characteristics.

[0153] Semiconductor substrate 82, semiconductor substrate 83, region 121 and region 122 are arranged in a grid pattern with no extra space, and the whole is arranged in a roughly rectangular shape.

[0154] Therefore, the electronic circuit module 1 can reduce the arrangement area of ​​the semiconductor substrate 82, semiconductor substrate 83, balun 19, and balun 20. Consequently, the electronic circuit module 1 can reduce size and cost. Furthermore, the electronic circuit module 1 enables miniaturization of electronic devices equipped with it, thus reducing the cost of the electronic devices.

[0155] <Second Implementation Method>

[0156] (Circuit Structure)

[0157] The circuit structure of the electronic circuit module 1A in the second embodiment is the same as that of the electronic circuit module 1 in the first embodiment (see reference). Figure 1 Since the diagrams and explanations are the same, they are omitted.

[0158] (Structure of electronic circuit module)

[0159] The same reference numerals are used for the components of the electronic circuit module 1A in the second embodiment that are the same as those in the electronic circuit module 1 in the first embodiment, and the descriptions are omitted.

[0160] Figure 6 This is a diagram showing the structure of the electronic circuit module according to the second embodiment.

[0161] The substrate 81 has a region 121 adjacent to the edge 82a (the edge on the base side of the Y-axis) of the semiconductor substrate 82 and the edge 83c (the edge on the base side of the Y-axis) of the semiconductor substrate 83. A balun 19 is disposed in the region 121 of the substrate 81.

[0162] Edge 82a corresponds to an example of the "first edge" of this disclosure. Edge 83c corresponds to an example of the "third edge" of this disclosure. Region 121 corresponds to an example of the "first region" of this disclosure. Balanced-to-unbalanced converter 19 corresponds to an example of the "first balanced-to-unbalanced converter" of this disclosure.

[0163] The substrate 81 has a region 122 adjacent to the edge 82c (the edge on the front end side of the Y-axis) of the semiconductor substrate 82 and the edge 83b (the edge on the front end side of the Y-axis) of the semiconductor substrate 83. A balun 20 is disposed in the region 122 of the substrate 81.

[0164] Edge 82c corresponds to an example of the "second edge" of this disclosure. Edge 83b corresponds to an example of the "fourth edge" of this disclosure. Region 122 corresponds to an example of the "second region" of this disclosure. Balanced-to-unbalanced converter 20 corresponds to an example of the "second balanced-to-unbalanced converter" of this disclosure.

[0165] Edges 82a and 82c are facing edges. In one embodiment, there is one edge between one end of edge 82a and one end of edge 82c, but this disclosure is not limited to this. There may also be two or more edges between one end of edge 82a and one end of edge 82c. Furthermore, there is one edge between the other end of edge 82a and the other end of edge 82c, but this disclosure is not limited to this. There may also be two or more edges between the other end of edge 82a and the other end of edge 82c.

[0166] Edges 83b and 83c are facing edges. In one embodiment, there is one edge between one end of edge 83b and one end of edge 83c, but this disclosure is not limited to this. There may also be two or more edges between one end of edge 83b and one end of edge 83c. Furthermore, there is one edge between the other end of edge 83b and the other end of edge 83c, but this disclosure is not limited to this. There may also be two or more edges between the other end of edge 83b and the other end of edge 83c.

[0167] One end 41b of the first winding 41 of the balun 19 is electrically connected to terminal 91 via wiring 111 extending along the Y-axis. The other end 41c of the first winding 41 is electrically connected to terminal 92 via wiring 112 extending along the Y-axis.

[0168] The balun 19 is connected to the semiconductor substrate 82 in a direction from the base side of the Y-axis toward the front side.

[0169] The direction from the base side of the Y-axis toward the front side is an example of the "first connection direction" of this disclosure.

[0170] One end (not shown) of the second winding 42 of the balun 19 is electrically connected to terminal 101 via wiring 115 extending along the Y-axis.

[0171] The balun 19 is connected to the semiconductor substrate 83 in a direction from the base side of the Y-axis toward the front side.

[0172] The direction from the base side of the Y-axis toward the front side is an example of the "third connection direction" of this disclosure.

[0173] One end 43b of the first winding of the balun 20 is electrically connected to terminal 93 via wiring 113 extending along the Y-axis. The other end 43c of the first winding 43 is electrically connected to terminal 94 via wiring 114 extending along the Y-axis.

[0174] The balun 20 is connected to the semiconductor substrate 82 in a direction from the front end side of the Y-axis toward the base end side.

[0175] The direction from the front end side of the Y-axis toward the base end side is an example of the "second connection direction" of this disclosure.

[0176] One end (not shown) of the second winding 44 of the balun 20 is electrically connected to terminal 102 via wiring 116 extending along the Y-axis.

[0177] The balun 20 is connected to the semiconductor substrate 83 in a direction from the front end side of the Y-axis toward the base end side.

[0178] The direction from the front end side of the Y-axis toward the base end side is an example of the "fourth connection direction" of this disclosure.

[0179] In one embodiment, the first connection direction (the direction from the base end side of the Y-axis toward the front end side) forms a 180° angle with the second connection direction (the direction from the front end side of the Y-axis toward the base end side), but this disclosure is not limited thereto. The first connection direction and the second connection direction may form an angle less than 180° or an angle greater than 180°.

[0180] In this embodiment, the third connection direction (the direction from the base end side of the Y-axis toward the front end side) forms a 180° angle with the fourth connection direction (the direction from the front end side of the Y-axis toward the base end side), but this disclosure is not limited to this. The third connection direction and the fourth connection direction may form an angle of less than 180° or an angle of greater than 180°.

[0181] In this embodiment, the first connection direction (the direction from the base end side of the Y-axis toward the front end side) forms a 0° angle with the third connection direction (the direction from the base end side of the Y-axis toward the front end side), but this disclosure is not limited to this. The first connection direction and the third connection direction may form an angle less than 0° or an angle greater than 0°.

[0182] In this embodiment, the second connection direction (the direction from the front end side of the Y-axis toward the base end side) forms a 0° angle with the fourth connection direction (the direction from the front end side of the Y-axis toward the base end side), but this disclosure is not limited to this. The second connection direction and the fourth connection direction may form an angle less than 0° or an angle greater than 0°.

[0183] (Effect)

[0184] Region 121 and Region 122 are not adjacent. Therefore, the balun 19 configured in Region 121 is separate from the balun 19 configured in Region 121.

[0185] Therefore, electronic circuit module 1A can suppress mutual interference between the signals of balun 19 and balun 20. Consequently, electronic circuit module 1A can improve high-frequency characteristics.

[0186] Semiconductor substrate 82 is adjacent to region 121. Therefore, electronic circuit module 1A can shorten the length of wiring 111 and wiring 112 between semiconductor substrate 82 and the first winding 41 of balun 19.

[0187] Therefore, electronic circuit module 1A can suppress path loss of high-frequency signals flowing between semiconductor substrate 82 and first winding 41. Consequently, electronic circuit module 1A can improve high-frequency characteristics.

[0188] Semiconductor substrate 82 is adjacent to region 122. Therefore, electronic circuit module 1A can shorten the length of wiring 113 and wiring 114 between semiconductor substrate 82 and the first winding 43 of balun 20.

[0189] Therefore, electronic circuit module 1A can suppress path loss of high-frequency signals flowing between semiconductor substrate 82 and first winding 43. Consequently, electronic circuit module 1A can improve high-frequency characteristics.

[0190] Semiconductor substrate 83 is adjacent to region 121. Therefore, electronic circuit module 1A can shorten the length of wiring 115 between semiconductor substrate 83 and the second winding 42 of balun 19.

[0191] Therefore, electronic circuit module 1A can suppress path loss of high-frequency signals flowing between semiconductor substrate 83 and second winding 42. Consequently, electronic circuit module 1A can improve high-frequency characteristics.

[0192] Semiconductor substrate 83 is adjacent to region 122. Therefore, electronic circuit module 1A can shorten the length of wiring 116 between semiconductor substrate 83 and the second winding 44 of balun 20.

[0193] Therefore, electronic circuit module 1A can suppress path loss of high-frequency signals flowing between semiconductor substrate 83 and second winding 44. Consequently, electronic circuit module 1A can improve high-frequency characteristics.

[0194] Semiconductor substrate 82, semiconductor substrate 83, region 121 and region 122 are configured as a whole in a generally rectangular shape with no extra space.

[0195] Therefore, the electronic circuit module 1A can reduce the arrangement area of ​​the semiconductor substrate 82, semiconductor substrate 83, balun 19, and balun 20. Consequently, the electronic circuit module 1A can reduce size and cost. Furthermore, the electronic circuit module 1A enables miniaturization of electronic devices equipped with it, thus reducing the cost of the electronic device.

[0196] <Postscript>

[0197] In this embodiment, the first winding 41 of the balun 19 is formed on a first wiring layer and the second winding 42 is formed on a second wiring layer, but this disclosure is not limited thereto. The first winding 41 and the second winding 42 can be formed on different wiring layers. For example, the first winding 41 can be formed on the first wiring layer and the second winding 42 on a third wiring layer. Alternatively, the second winding 42 can be formed on the first wiring layer and the first winding 41 on the second wiring layer. The balun 20 is similar.

[0198] In this embodiment, the first winding 41 and the second winding 42 are each formed on a wiring layer, but this disclosure is not limited thereto. Multiple windings of the first winding 41 and the second winding 42, each formed on multiple wiring layers, can also be electrically connected via vias. The same applies to the first winding 43 and the second winding 44.

[0199] The bias circuits 201 to 204 and the control circuit 205 may also be included in the electronic circuit module 1. For example, the bias circuits 201 to 204 and the control circuit 205 may be included in the semiconductor substrate 82 or the semiconductor substrate 83. Alternatively, the bias circuits 201 to 204 and the control circuit 205 may be formed on a third semiconductor substrate, which is mounted on the substrate 81.

[0200] Furthermore, the above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the interpretation of the embodiments of the present invention. The present invention can be modified / improved without departing from its spirit, and the present invention also includes its equivalents.

[0201] Explanation of reference numerals in the attached figures

[0202] 1. 1A Electronic Circuit Module

[0203] Amplifiers 11, 13, 14, 15, and 16

[0204] 12 Distributors

[0205] Capacitors 17 and 18

[0206] 19, 20 Balanced-to-Unbalanced Converters

[0207] Switches 21 and 22

[0208] 31, 32, 33, 34 Transistors

[0209] 81 substrate

[0210] 82, 83 Semiconductor substrates

Claims

1. An electronic circuit module, comprising: main substrate; A first semiconductor substrate is disposed on the main substrate and has a first side and a second side different from the first side; A second semiconductor substrate is disposed on the main substrate and has a third side and a fourth side different from the third side; A first balun is disposed in a first region of the main substrate that is adjacent to the first side of the first semiconductor substrate and the third side of the second semiconductor substrate. as well as A second balun is disposed in a second region of the main substrate that is adjacent to the second side of the first semiconductor substrate and the fourth side of the second semiconductor substrate.

2. The electronic circuit module according to claim 1, wherein, The first edge of the first semiconductor substrate is adjacent to the second edge. The third side of the second semiconductor substrate is adjacent to the fourth side.

3. The electronic circuit module according to claim 1 or 2, wherein, The first edge and the second edge of the first semiconductor substrate are angularly continuous. The third side and the fourth side of the second semiconductor substrate are angularly continuous.

4. The electronic circuit module according to claim 1, wherein, The first edge of the first semiconductor substrate faces the second edge. The third side of the second semiconductor substrate faces the fourth side.

5. An electronic circuit module, comprising: main substrate; A first semiconductor substrate is disposed on the main substrate; A second semiconductor substrate is disposed on the main substrate; A first balun is disposed on the main substrate; as well as A second balun is disposed on the main substrate. The first balun is connected to the first semiconductor substrate in the first connection direction. The second balance-to-unbalance converter is connected to the first semiconductor substrate in a second connection direction different from the first connection direction. The first balun is connected to the second semiconductor substrate in the third connection direction. The second balun is connected to the second semiconductor substrate in a fourth connection direction, which is different from the third connection direction.

6. The electronic circuit module according to claim 5, wherein, The first connection direction forms a 90° angle with the second connection direction. The third connection direction forms a 90° angle with the fourth connection direction.

7. The electronic circuit module according to claim 5 or 6, wherein, The first connection direction forms a 90° angle with the third connection direction. The second connection direction forms a 90° angle with the fourth connection direction.

8. The electronic circuit module according to claim 5, wherein, The first connection direction forms a 180° angle with the second connection direction. The third connection direction forms an angle of 180° with the fourth connection direction.

9. The electronic circuit module according to claim 5 or 8, wherein, The first connection direction forms a 0° angle with the third connection direction. The second connection direction forms a 0° angle with the fourth connection direction.

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