Design method and system of iir digital filter with frequency response self-adjusting function

Abstract

This invention relates to the field of digital signal processing technology for radio frequency (RF) receiver chips, and discloses a design method and system for an IIR digital filter with self-adjusting frequency response. The method includes: acquiring digital baseband sampling sequence data; constructing a basic dataset for adjacent channel blocking analysis; extracting a blocking detection feature set; performing adjacent channel blocking decision; constructing a second-order IIR notch filter prototype; generating a target filter coefficient set; and performing smooth switching filtering and adjacent channel blocking suppression processing. Compared to existing fixed-parameter IIR digital filters, especially in broadband RF receiver chips facing multi-standard bandwidth switching conditions, this invention addresses the technical problem of not being able to synchronously adjust the filter stopband position and suppression depth according to the actual adjacent channel blocking state. This improvement addresses the interference suppression capability under dynamic adjacent channel blocking scenarios through a design mechanism involving blocking decision, parameter constraint generation, and stability constraint fixed-point mapping.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology for radio frequency receiver chips, and in particular to a design method and system for an IIR digital filter with self-adjusting frequency response. Background Technology

[0002] Currently, in the digital baseband processing link of broadband RF receiver chips, in order to suppress adjacent channel blocking interference, out-of-band leakage components, and residual spectral components introduced by strong interference, digital filters are typically configured after analog-to-digital conversion, digital down-conversion, and decimation signal extraction to perform passband preservation and interference suppression processing on the target signal. Among these, IIR digital filters are widely used in narrowband notch filtering, band-stop filtering, and channel shaping processing scenarios due to their compact structure, low implementation order, low computational complexity, and ease of fixed-point deployment within the chip.

[0003] However, most existing IIR digital filters employ pre-designed fixed-parameter structures. Their stopband position, stopband width, and suppression depth are typically set during the offline design phase, making it difficult to synchronously adjust them based on adjacent channel interference center frequency drift, interference bandwidth changes, receiver gain margin variations, and frequency band switching during actual operation. Consequently, when the broadband RF receiver chip is in a dynamic adjacent channel blocking environment, fixed-parameter IIR digital filters are prone to problems such as stopband position mismatch with the actual interference frequency band, insufficient stopband width coverage, or unreasonable suppression depth allocation.

[0004] For example, in the actual operation of broadband RF receiver chips, the target signal and adjacent channel strong interference signals often enter the receiving front end simultaneously. After analog-to-digital conversion and digital down-conversion, the adjacent channel blocking interference in the digital baseband may manifest as a shift in center frequency over time, a broadening of the spectral energy distribution, or an enhancement of local peaks. If a fixed-parameter IIR digital filter is still used, on the one hand, it may not be able to effectively align and suppress the actual adjacent channel blocking interference components, causing residual adjacent channel energy to continue to leak into the subsequent demodulation link. On the other hand, it may also erode the edge of the target passband due to an excessively wide stopband setting or position offset, resulting in distortion of the useful signal amplitude. At the same time, under the condition of fixed-point chip implementation, directly modifying the IIR filter parameters can easily lead to problems such as poles exceeding the unit circle, instability after quantization, or abrupt changes in coefficients causing output oscillation. Existing technology cannot fully meet the requirements of broadband RF receiver chips in dynamic adjacent channel blocking scenarios, which require both interference suppression capability, filtering stability, and output continuity.

[0005] Therefore, there is an urgent need for a design method that can still achieve self-adjustment of IIR digital filter frequency response, stable generation of target filter coefficients, and smooth suppression of adjacent channel blocking interference even under conditions of adjacent channel blocking interference center frequency drift, interference bandwidth variation, standard switching, and fixed-point quantization, so as to improve the anti-interference capability, filtering reliability, and output signal quality of broadband RF receiver chip digital baseband link. Summary of the Invention

[0006] To address the aforementioned technical shortcomings, the purpose of this invention is to propose a design method for an IIR digital filter with self-adjusting frequency response. This method aims to solve the technical problem in existing fixed-parameter IIR digital filters, especially when broadband RF receiver chips face multi-standard bandwidth switching conditions, where the filter stopband position and suppression depth cannot be synchronously adjusted according to the actual adjacent channel blocking state.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention provides a design method for an IIR digital filter with self-adjusting frequency response.

[0008] The design method for the IIR digital filter with self-adjusting frequency response includes:

[0009] Step S10: Obtain the digital baseband sequence data after analog-to-digital conversion, digital down-conversion and decimation signal extraction of the broadband radio frequency receiving chip. Based on the digital baseband sequence data, use the frequency band mapping and parameter initialization construction mechanism to perform the task of constructing the basic dataset for adjacent channel blocking analysis, and output the frequency band mapping result and the initial set of IIR parameters.

[0010] Step S20: Based on the frequency band mapping results and the initial set of IIR parameters, the Welch spectrum analysis method is used to perform the blocking detection feature extraction task and output the blocking detection feature set;

[0011] Step S30: Based on the blocking detection feature set, a preprocessing task is performed using an adjacent channel blocking decision mechanism to output a self-adjusting target constraint set;

[0012] Step S40: Based on the self-adjusting target constraint set, the target filter coefficient generation task is performed using a stability constraint-based fixed point mapping design mechanism, and the target filter coefficient set is output.

[0013] Step S50: Perform smooth switching filtering and adjacent channel blocking suppression processing on the adjacent channel blocking interference component in the digital baseband sequence data according to the target filter coefficient set, and output the complex digital baseband signal after adjacent channel blocking suppression.

[0014] Preferably, step S10, which involves acquiring the digital baseband sequence data after analog-to-digital conversion, digital down-conversion, and decimation signal extraction from the broadband RF receiver chip, and then using a frequency band mapping and parameter initialization mechanism to construct the basic dataset for adjacent channel blocking analysis based on the digital baseband sequence data, and outputting the frequency band mapping results and the initial set of IIR parameters, specifically includes:

[0015] Step S101: Acquire the digital baseband sequence data after analog-to-digital conversion, digital down-conversion, and decimation signal extraction by the broadband RF receiver chip. The digital baseband sequence data includes complex digital baseband sampling sequences. Current sampling rate Target channel bandwidth Automatic gain control gain margin Digital downconversion frequency shift Decimation signal extraction factor and calibration status flags Where n is the discrete-time sampling point number in the digital baseband sampling sequence, used to characterize the nth sampling point in the complex digital baseband sampling sequence after analog-to-digital conversion, digital down-conversion, and decimation signal extraction; complex digital baseband sampling sequence The real part in the equation represents the sampling components of the in-phase branch, and the imaginary part represents the sampling components of the quadrature branch.

[0016] Step S102: Establish the target passband set based on digital baseband sequence data. Adjacent Track Observation Zone Set Noise reference band set and frequency resolution ;

[0017] Based on target passband set Adjacent Track Observation Zone Set Noise reference band set and frequency resolution Construct and output the frequency band junction results;

[0018] Step S103: Based on the frequency band junction results and calibration status flags Initialize the IIR parameter control variables to obtain the initial value of the notch filter center angular frequency. Initial value of pole radius Initial value of the depth mixing coefficient When the calibration status flag The parameters are frozen and updated in time, and the output frequency band mapping results and the initial set of IIR parameters are output.

[0019] Preferably, in step S102, the target passband set is: The adjacent observation zone set is The noise reference band set is ; frequency resolution is ;in, The frequency variable in the complex digital baseband spectrum after digital down-conversion and decimation signal extraction; Configure the bandwidth for the current target channel to limit the target passband range where the useful target signal is located; This is the maximum cutoff frequency boundary of the adjacent channel observation band, used to limit the upper limit of the detection frequency for adjacent channel blocking interference; The complex digital baseband equivalent sampling rate after decimation signal extraction is used to determine the Nyquist frequency range and frequency resolution. This represents the number of Fast Fourier Transform points used in spectrum analysis to determine the discrete sampling accuracy of the spectrum.

[0020] Preferably, step S20, which involves performing a blocking detection feature extraction task based on the frequency band mapping results and the initial set of IIR parameters using the Welch spectrum analysis method, and outputting a blocking detection feature set, specifically includes:

[0021] Step S201: Based on the frequency band mapping results, perform frame segmentation, mean removal, and windowing processing on the digital baseband sequence data to obtain multi-segment analysis frame data for spectrum analysis;

[0022] Step S202: Combine the initial values ​​of the notch center angular frequency, pole radius, and depth mixing coefficient in the initial set of IIR parameters to perform initial state marking on multiple analysis frame data segments, and output the analysis frame data;

[0023] Step S203: Based on the analysis frame data, the Welch spectrum analysis method is used to perform frequency domain transformation and power spectrum averaging on each segment of the analysis frame data to obtain the power spectral density distribution results corresponding to the frequency band mapping results; and based on the power spectral density distribution results, frequency band partitioning statistics are performed to extract the power distribution information in the target passband, the power distribution information in the adjacent channel observation band, and the background noise distribution information in the noise reference band.

[0024] Step S204: Perform structured association and encapsulation of the power distribution information in the target passband, the power distribution information in the adjacent channel observation band, and the background noise distribution information in the noise reference band, and output the blockage detection feature set.

[0025] Preferably, step S30, which involves performing a preprocessing task based on the blocking detection feature set using an adjacent channel blocking decision mechanism and outputting a self-adjusting target constraint set, specifically includes:

[0026] Step S301: Extract the target's typical power from the blockage detection feature set. Adjacent channel power Noise floor estimation And obtain the automatic gain control gain margin from the digital baseband sequence data. Construct a comprehensive detection threshold ;Will With comprehensive detection threshold Compare and output the adjacent channel blocking decision result;

[0027] Step S302: When the adjacent channel blocking decision result indicates the existence of adjacent channel blocking interference, based on the adjacent channel observation band set... The peak frequency is first extracted using a method combining peak search and power centroid analysis. Then, focusing on the peak frequency... Construct a local frequency window W, and calculate the estimated center frequency of the blocking interference using the power centroid method. Finally, based on the estimated center frequency of the jamming interference... Bandwidth occupied by blocking interference was calculated using analysis methods based on 5% and 95% energy points. ;

[0028] Step S303: Based on the bandwidth occupied by blocking interference Peak frequency Estimated center frequency of jamming interference and estimated center frequency of jamming interference Construct and output a set of self-adjusting objective constraints.

[0029] Preferably, in step S301, the comprehensive detection threshold is... ; ; ;in, The maximum value function is used to select the larger of the noise threshold and the relative threshold as the benchmark term for the comprehensive detection threshold; The noise threshold is used to characterize the upper limit of background noise power allowed in the adjacent channel observation band under the current noise floor estimation level. It is a relative threshold, used to characterize the upper limit of the adjacent channel power that is allowed relative to the target passband power; The adjacent channel power integration window bandwidth is used to characterize the adjacent channel observation bandwidth corresponding to the power integration and noise threshold conversion performed within the adjacent channel observation band. This is the noise threshold compensation amount, used to adjust the detection sensitivity corresponding to the noise floor estimate to suppress misjudgments caused by background noise fluctuations. This is a relative threshold compensation amount, used to offset the adjacent channel detection threshold corresponding to the target passband power; This is the gain margin linkage compensation amount, used to dynamically correct the comprehensive detection threshold based on the automatic gain control gain margin. Specifically, when the automatic gain control gain margin decreases, the gain margin linkage compensation amount increases.

[0030] Preferably, step S40, which involves performing the target filter coefficient generation task based on a stability constraint-based fixed-point mapping design mechanism using a self-adjusting target constraint set, and outputting the target filter coefficient set, specifically includes:

[0031] Step S401: Based on the self-adjusting target constraint set, the notch center angular frequency, pole radius, and depth mixing coefficient of the IIR digital filter are parameterized and updated to obtain the updated notch center angular frequency, updated pole radius, and updated depth mixing coefficient; wherein, the parameterization update process includes: introducing a parameter update step size, and performing asymptotic updates on the notch center angular frequency, pole radius, and depth mixing coefficient in combination with the parameter update step size;

[0032] Step S402: Based on the updated notch center angular frequency, updated pole radius and updated depth mixing coefficient, construct a second-order IIR notch prototype filter and perform gain normalization on the second-order IIR notch prototype filter to obtain floating-point filter coefficients.

[0033] Step S403: First, perform pole position verification on the denominator polynomial corresponding to the floating-point filter coefficients to determine whether all poles are located within the unit circle. If not all poles are located within the unit circle, perform shrinkage correction on the updated pole radius and regenerate the floating-point filter coefficients. If all poles are located within the unit circle, perform fixed-point mapping on the floating-point filter coefficients to obtain fixed-point filter coefficients. Then, perform pole position verification again on the denominator coefficients after fixed-point mapping to determine whether all poles after fixed-point mapping are still located within the unit circle. If not all poles after fixed-point mapping are located within the unit circle, perform shrinkage correction on the updated pole radius again and regenerate the floating-point filter coefficients and perform fixed-point mapping.

[0034] Step S404: Encapsulate the fixed-point filter coefficients, the updated notch center angular frequency, the updated pole radius, the updated depth mixing coefficients, and the pole position verification results together to output the target filter coefficient set.

[0035] This invention also provides an IIR digital filter design system with self-adjusting frequency response, comprising:

[0036] The basic data construction module is used to acquire digital baseband sequence data after analog-to-digital conversion, digital down-conversion and decimation signal extraction of the broadband RF receiver chip. Based on the digital baseband sequence data, the module uses a frequency band mapping and parameter initialization construction mechanism to perform the task of constructing the basic dataset for adjacent channel blocking analysis, and outputs the frequency band mapping results and the initial set of IIR parameters.

[0037] The feature extraction module is used to perform the blocking detection feature extraction task based on the frequency band mapping results and the initial set of IIR parameters, and outputs the blocking detection feature set.

[0038] The preprocessing module is used to perform preprocessing tasks based on the blocking detection feature set using the adjacent channel blocking decision mechanism, and outputs a self-adjusting target constraint set;

[0039] The coefficient generation module is used to perform the target filter coefficient generation task based on the self-adjusting target constraint set and the stability constraint-based fixed point mapping design mechanism, and outputs the target filter coefficient set.

[0040] The suppression output module is used to perform smooth switching filtering and adjacent channel blocking suppression processing on the adjacent channel blocking interference component in the digital baseband sequence data according to the target filter coefficient set, and output the complex digital baseband signal after adjacent channel blocking suppression.

[0041] The present invention also provides an IIR digital filter design device with frequency response self-adjustment function, comprising: a memory, a processor, and an IIR digital filter design program with frequency response self-adjustment function stored in the memory and executable on the processor. When the IIR digital filter design program with frequency response self-adjustment function is executed by the processor, an IIR digital filter design method with frequency response self-adjustment function is implemented.

[0042] The present invention also provides a computer program product, including an IIR digital filter design program with self-adjusting frequency response function, wherein the IIR digital filter design program with self-adjusting frequency response function implements the IIR digital filter design method with self-adjusting frequency response function when executed by a processor.

[0043] The beneficial effects of this invention are as follows: By introducing a Welch spectrum analysis-based adjacent channel blocking detection mechanism, a blocking interference center frequency and occupied bandwidth extraction mechanism, and a parameterized progressive update mechanism for the notch center angular frequency, pole radius, and depth mixing coefficients, this invention enables the IIR digital filter's stopband position, stopband width, and suppression depth to synchronously self-adjust with the spectral changes of adjacent channel blocking interference. Compared to the existing technology that uses fixed-parameter IIR filters that can only perform static suppression near a preset interference frequency, this invention can still effectively track and target the actual adjacent channel blocking interference components when the broadband RF receiver chip encounters adjacent channel blocking interference center frequency drift, interference bandwidth changes, and multi-mode channel bandwidth switching. This avoids the adjacent channel residual leakage problem caused by the mismatch between the fixed stopband and the actual interference frequency band, and improves the adjacent channel blocking suppression capability and target passband signal fidelity of the broadband RF receiver link in dynamic interference environments.

[0044] This invention introduces pole position verification, pole radius shrinkage correction, pole verification after fixed-point mapping, and a smooth switching filtering mechanism to ensure that the target filter coefficients simultaneously meet stability constraints and engineering implementation constraints during generation and switching. Compared to existing adaptive IIR filters, which are prone to poles exceeding the unit circle, fixed-point quantization instability, and output oscillations caused by coefficient mutations after parameter updates, this invention can achieve stable generation and seamless switching of target filter coefficients in the digital baseband link of a broadband RF receiver chip. This avoids filter instability after quantization and output transient degradation, improving the operational reliability, parameter update security, and output signal continuity of the IIR digital filter under chip fixed-point implementation conditions. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating the first embodiment of the design method for an IIR digital filter with self-adjusting frequency response according to the present invention.

[0047] Figure 2 This is a schematic diagram of an IIR digital filter design method with self-adjusting frequency response function according to the present invention. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Example 1: As Figure 1 The diagram shown is a flowchart of the first embodiment of the IIR digital filter design method with self-adjusting frequency response function of the present invention, and the first embodiment of the IIR digital filter design method with self-adjusting frequency response function of the present invention is presented.

[0050] In the first embodiment, the IIR digital filter design method with frequency response self-adjustment function includes:

[0051] Step S10: Obtain the digital baseband sequence data after analog-to-digital conversion, digital down-conversion and decimation signal extraction of the broadband radio frequency receiving chip. Based on the digital baseband sequence data, use the frequency band mapping and parameter initialization construction mechanism to perform the task of constructing the basic dataset for adjacent channel blocking analysis, and output the frequency band mapping result and the initial set of IIR parameters.

[0052] It should be noted that the "digital baseband sequence data" in this step refers to the complex discrete sequence data formed after the analog radio frequency signal received by the broadband radio frequency receiver chip front end is discretized by the analog-to-digital conversion module, then the target frequency band is shifted to the baseband range by the digital down-conversion module, and the sampling rate is compressed by the decimation signal extraction module. The digital baseband sequence data includes in-phase branch data and quadrature branch data, both of which jointly characterize the complex spectral characteristics of the target received signal, adjacent channel blocking interference components, and background noise components in the baseband domain. "Frequency band mapping" refers to the process of dividing the frequency intervals in the digital baseband sequence data according to the current sampling rate, target channel bandwidth, the baseband center position after digital down-conversion, and the spectral distribution relationship after signal extraction. This includes the establishment of the target passband interval, adjacent channel observation interval, and noise reference interval. Among them, the target passband interval is used to characterize the main distribution range of the target useful signal, the adjacent channel observation interval is used to characterize the potential distribution range of adjacent channel blocking interference, and the noise reference interval is used to characterize the background noise distribution range that does not contain the target main energy and the main adjacent channel blocking energy. The "parameter initialization mechanism" refers to the process of initializing the initial values ​​of the notch center angular frequency, pole radius, and deep mixing coefficients required for the subsequent self-adjustment of the IIR digital filter after the frequency band mapping is completed, based on the current chip operating mode, sampling rate, target bandwidth, and filter structure constraints. This initialization process does not simply provide a fixed default value, but rather provides a unified starting reference framework for subsequent steps such as adjacent channel blocking decision, interference center frequency extraction, stopband width adjustment, and fixed-point coefficient quantization, ensuring that the subsequent self-adjustment process is based on data consistent with the current RF receiving environment.

[0053] Understandably, firstly, by acquiring digital baseband sequence data after analog-to-digital conversion, digital down-conversion, and decimation signal extraction, this invention confines the subsequent design and adjustment process of the IIR digital filter within the digital baseband domain, which has already undergone frequency shifting and sampling rate compression. This significantly reduces the computational scale of subsequent spectrum analysis and filter parameter adjustment, enabling subsequent blocking detection and frequency response self-adjustment to be completed under lower data throughput conditions. Secondly, by pre-constructing the target passband, adjacent channel observation interval, and noise reference interval in this step, the boundaries of the analysis objects for the target signal, adjacent channel blocking interference, and background noise in subsequent steps become clearer, avoiding the problems of target signal and adjacent channel interference overlapping and statistical range ambiguity in subsequent spectrum estimation. Thirdly, by introducing an initial set of IIR parameters, a unified starting point constraint can be provided for the notch center position, stopband width control, and suppression depth control before the algorithm enters the self-adjustment stage. This ensures that subsequent parameter updates are not unconstrained drifts but gradually converge near a controllable initial state. For example, in an application scenario of a broadband cellular communication RF receiver chip, suppose the front end of the receiving link receives a 20MHz target signal, while an adjacent channel blocking interference signal with significantly higher power than the target signal exists in an adjacent frequency band. This analog RF signal undergoes analog-to-digital conversion to obtain a high-sampling-rate discrete sequence, which is then digitally down-converted to shift the target frequency band to near zero intermediate frequency. Finally, decimation is used to reduce the sampling rate to a range suitable for digital baseband processing. If the traditional method is still used, directly feeding the entire decimated digital sequence into a fixed-parameter filter, suppression often relies solely on a pre-assumed stopband position. Once the actual center frequency of the adjacent channel blocking interference shifts relative to the preset position, or the target bandwidth changes from 20MHz to 10MHz under different system configurations, the original fixed analysis boundaries and fixed initial filter parameters become ineffective. In step S10 of this invention, the target passband and adjacent channel observation band are first clearly defined based on the current sampling rate and the target channel bandwidth under the current standard. Then, a corresponding noise reference band is established according to the current chip operating state, and the initial values ​​of the notch center angular frequency, pole radius, and depth mixing coefficient are given simultaneously. In this way, when the subsequent steps begin to perform Welch spectrum analysis, its analysis window already clearly knows which frequency components belong to the target signal region, which belong to the adjacent channel blocking candidate region, and which belong to the background noise reference region, thereby enabling more accurate extraction of target passband power, adjacent channel power, and noise floor information. Furthermore, since the initial set of IIR parameters is already matched with the current operating mode, subsequent parameter updates only need to be corrected around a reasonable starting point, without having to perform a large-scale search from an unconstrained state. Therefore, it can not only shorten the self-adjusting convergence path but also reduce the risk of filter instability caused by parameter mutations.Therefore, this step is not a simple data reading step, but rather, in a real RF receiver chip scenario, it lays a stable and executable foundation in advance for subsequent adjacent channel blocking detection and IIR frequency response self-adjustment by uniformly constructing digital baseband sequence data, frequency band boundary relationships and filter initial parameters.

[0054] Step S20: Based on the frequency band mapping results and the initial set of IIR parameters, the Welch spectrum analysis method is used to perform the blocking detection feature extraction task and output the blocking detection feature set;

[0055] It should be noted that the "Welch spectrum analysis method" in this step refers to a method that segments digital baseband sequence data according to a preset frame length, and performs mean removal, window function weighting, frequency domain transformation, and power spectrum averaging on each segment to obtain a smoother and more stable power spectral density distribution result compared to a single spectrum estimation. The blocking detection feature extraction task is not merely about acquiring a set of spectrum curves, but rather, based on the target passband, adjacent channel observation band, and noise reference band established in step S10, it performs targeted frequency band partitioning statistics on the power spectral density distribution result obtained from the Welch spectrum analysis to form feature results that can be directly used for subsequent adjacent channel blocking decisions and parameter updates. The "blocking detection feature set" refers to a collection containing target passband power distribution information, adjacent channel observation band power distribution information, noise reference band background noise distribution information, power spectral density distribution results, and analysis label information associated with the current initial state of IIR parameters. The target passband power distribution information is used to characterize the distribution of the main energy of the useful signal, the adjacent channel observation band power distribution information is used to characterize the energy distribution of adjacent channel blocking interference, and the background noise distribution information of the noise reference band is used to characterize the noise floor level and noise fluctuation characteristics in the current digital baseband environment. The analysis label information associated with the initial state of the IIR parameters is used to ensure that subsequent steps can perform a unified analysis based on the initial operating state of the current filter when determining adjacent channel blocking interference. It should also be noted that this step uses Welch spectrum analysis instead of directly using single-frame fast Fourier transform for spectrum analysis because in the digital baseband environment of a broadband RF receiver chip, adjacent channel blocking interference often has characteristics such as high energy, high dynamics, and short-term fluctuations. If only single-frame spectrum results are used, they are easily affected by transient fluctuations and local spectral peak jitter, leading to unstable subsequent blocking decision results. The piecewise averaging Welch spectrum analysis method can effectively reduce the spectral estimation variance, allowing the blocking detection feature set to more stably reflect the actual power relationship between adjacent channel blocking interference and the target signal.

[0056] It should be understood that, compared to the traditional approach of directly using fixed-length FFT results as the basis for interference judgment on the digital baseband side, this step introduces the Welch spectrum analysis method, so that blockage detection no longer relies on the instantaneous results of a single spectrum estimation, but is based on stable spectral features after averaging multiple segments. Traditional methods are prone to misidentifying local spectral peaks as blockage interference when faced with rapidly fluctuating adjacent channel blocking interference power, low target signal power, or unstable background noise references, or when real blocking interference is not identified in time due to single-frame spectrum estimation errors. In contrast, this invention, by performing averaged spectrum estimation and partitioned statistical processing on each analysis frame in this step, not only improves the stability of blockage detection features, but also improves the consistency of feature extraction results under different bandwidth configurations, sampling rate conditions, and signal-to-noise ratio scenarios, thus providing a more reliable feature basis for subsequent adjacent channel blocking decisions and IIR filter parameter updates. For example, in a scenario where a broadband RF receiver chip receives a 20MHz target useful signal, assuming that after digital down-conversion and decimation signal extraction, a strong adjacent channel blocking interference component located outside the target passband exists simultaneously in the digital baseband sequence data. If a traditional single-frame FFT analysis method is used, the adjacent channel blocking interference may experience local transient enhancement at one analysis moment, while at another analysis moment, the peak value may decrease due to noise fluctuations or brief fading of interference, making subsequent blocking decisions prone to unstable switching. However, in this step, by performing Welch spectrum analysis on multiple consecutive analysis frames, the power spectral density results within multiple time segments can be averaged, ensuring that the true blocking spectral peak in the adjacent channel observation band is stably preserved, while suppressing the error effects caused by random noise, local sudden disturbances, and short-term unstable components. Thus, the output blocking detection feature set can not only clearly reflect the main energy distribution of the useful signal within the target passband, but also accurately provide the energy distribution location of the blocking interference and the background noise baseline level within the adjacent channel observation band, thereby providing strong support for the subsequent step S30 to accurately extract the blocking center frequency and blocking occupied bandwidth.

[0057] Step S30: Based on the blocking detection feature set, a preprocessing task is performed using an adjacent channel blocking decision mechanism to output a self-adjusting target constraint set;

[0058] It should be noted that the "adjacent channel blocking decision mechanism" in this step refers to a processing mechanism that comprehensively judges whether there is adjacent channel blocking interference in the current digital baseband link that requires triggering IIR filter frequency response self-adjustment, based on the target passband power distribution information, adjacent channel observation band power distribution information, noise reference band background noise distribution information, and power spectral density distribution results output in step S20. The comprehensive judgment is not based solely on whether a local spectral peak in the adjacent channel observation band exceeds a certain fixed threshold, but simultaneously considers the total power level of the adjacent channel observation band, the target passband power level, and the background noise benchmark of the noise reference band, thereby avoiding misjudgment due to relying solely on a single local feature. The "preprocessing task" refers to the process of further refining the spectral information in the blocking detection feature set after determining the existence of adjacent channel blocking interference, forming the constraint parameter set required for subsequent IIR filter coefficient generation. The "self-adjustment target constraint set" includes, but is not limited to, the estimated center frequency of the blocking interference, the bandwidth occupied by the blocking interference, the target notch center position constraint, the target stopband width constraint, the required additional suppression amount, and the parameter update step size.

[0059] It should be understood that, compared to traditional techniques that simply trigger a preset notch filter or select a fixed stopband template after detecting adjacent channel interference, this step constructs a self-adjusting target constraint set, giving the subsequent filter self-adjustment process a clear target direction and quantitative basis. Traditional techniques often only answer "whether adjacent channel interference exists," but cannot further answer key questions such as "where is the adjacent channel interference located, how wide is the spectrum, how much needs to be suppressed, and how quickly should the filter be updated." Therefore, subsequent processing can only be carried out using fixed parameters or coarse switching methods. However, this invention introduces blocking center frequency estimation, blocking occupied bandwidth estimation, and additional suppression quantity construction in this step, so that the subsequent filter design is no longer an empirical selection, but a directional parameter generation process based on the actual spectrum of the current adjacent channel blocking interference. Especially when the broadband RF receiver chip operates under multi-standard bandwidth switching, adjacent channel blocking center frequency drift, or automatic gain control margin changes, this step can significantly improve the pertinence and consistency of subsequent filter parameter generation, which is difficult to achieve with traditional fixed parameter filtering methods.

[0060] For example, in the digital baseband processing of a broadband RF receiver chip, the blocking detection feature set output in step S20 indicates that the useful signal energy in the target passband is mainly concentrated within a preset bandwidth, while there is a set of energy peaks in the adjacent channel observation band that are significantly higher than the background noise. If a traditional approach is used, as soon as an abnormal increase in the power of the adjacent channel observation band is detected, the system directly switches to a notch filter with a fixed center frequency and fixed bandwidth. However, when the actual blocking interference shifts relative to the preset position or the interference bandwidth significantly widens, this fixed notch filter may not be able to effectively cover the actual blocking area. In this step, the local spectral peak is first determined using the adjacent channel observation band power information and power spectral density distribution results from the blocking detection feature set. Then, a local frequency window is constructed around this peak. The estimated center frequency of the blocking interference is calculated using the power centroid within the local frequency window. The bandwidth occupied by the blocking interference is then determined using the cumulative power distribution. Finally, the required additional suppression is calculated by combining the difference between the target passband power and the adjacent channel power. In this way, the signal received in the subsequent step S40 is no longer a vague "interference from adjacent channels exists" signal, but a set of self-adjustment target constraints that clearly indicate "where the stopband should be established, how wide the stopband should be, how deep the suppression should be, and how fast the update should be", thereby significantly improving the accuracy and effectiveness of the overall frequency response self-adjustment process.

[0061] Step S40: Based on the self-adjusting target constraint set, the target filter coefficient generation task is performed using a stability constraint-based fixed point mapping design mechanism, and the target filter coefficient set is output.

[0062] It should be noted that the "fixed-point mapping design mechanism based on stability constraints" in this step refers to the process of generating the target coefficients of the IIR digital filter. Instead of simply quantizing the floating-point design results into fixed-point numbers, the notch center angular frequency, pole radius, and depth mixing coefficients are first parameterized and updated based on the self-adjusting target constraint set output in step S30. Then, a second-order IIR notch prototype filter is constructed based on the updated parameters. Afterward, pole position verification is performed on the constructed floating-point filter coefficients, followed by fixed-point mapping under the premise of satisfying stability conditions. A pole position verification is performed again after fixed-point mapping to ensure that the target filter after fixed-point implementation still meets the stability requirements. The "target filter coefficient set" includes not only the fixed-point filter coefficients themselves but also the updated notch center angular frequency, updated pole radius, updated depth mixing coefficients, and the corresponding stability verification results. Furthermore, the parameterization update in this step refers to mapping the estimated center frequency of the blocking interference output in step S30 to the target notch center position, mapping the bandwidth occupied by the blocking interference to the target stopband width control parameter, and mapping the required additional suppression amount to the target suppression depth control parameter. The parameter update step size controls these parameters to gradually change from their initial values ​​to their target values, thereby avoiding a large, one-time jump in the coefficients. It should also be noted that the pole position verification in this step refers to determining whether all poles are located within the unit circle based on the pole positions corresponding to the denominator polynomial of the IIR filter. The so-called pole radius shrinkage correction refers to reducing the pole radius and regenerating floating-point coefficients when the pole position crosses the unit circle boundary or is too close to the unit circle, so that the filter returns to the stable region.

[0063] Understandably, the self-adjusting target constraint set output in step S30 is directly transformed into a target filter coefficient set that can be deployed in the chip's digital baseband link, thus realizing the abstract design requirement of "how the frequency response should be adjusted" as the concrete result of "how the filter coefficients should be valued". By introducing the continuous generation chain of "parameterization update - floating-point construction - pole verification - fixed-point mapping - quantization verification" in this step, the target filter coefficients can satisfy both the current adjacent channel blocking suppression requirements and the stability requirements of the IIR filter under the chip fixed-point implementation conditions.

[0064] It should be understood that, compared to traditional techniques that directly call pre-stored filter templates or truncate floating-point coefficients to fixed-point coefficients after detecting interference, this step significantly improves the reliability of the IIR digital filter during dynamic updates through a fixed-point mapping design under stability constraints. In traditional techniques, if floating-point coefficients are directly generated according to the target center frequency and target bandwidth, and then quantized to a fixed-point format without stability checks, a situation often arises where the theoretical model is stable, but the quantized model is unstable, especially when the poles are close to the unit circle. In contrast, this invention performs pole position verification first, then fixed-point mapping, and then verifies the pole positions again after mapping. Simultaneously, a pole radius shrinkage correction mechanism is introduced, ensuring that the generated target filter coefficient set not only reflects the specificity for actual blocking interference but also remains stable under chip fixed-point implementation conditions. This dual control method of "pre-design constraint—post-design verification" is more suitable than traditional techniques for the online update requirements of IIR digital filters in dynamic interference environments in broadband RF receiver chips.

[0065] Step S50: Perform smooth switching filtering and adjacent channel blocking suppression processing on the adjacent channel blocking interference component in the digital baseband sequence data according to the target filter coefficient set, and output the complex digital baseband signal after adjacent channel blocking suppression.

[0066] It should be noted that the "smooth switching filtering" in this step refers to the process of gradually transitioning or cross-mixing the filter output over time between the old filter coefficient set and the newly generated target filter coefficient set in step S40, rather than using abrupt coefficient replacement. This reduces the transient impact on the output signal during coefficient updates. "Adjacent channel blocking suppression processing" refers to using the target filter coefficient set output in step S40 to attenuate high-energy blocking interference components located in the adjacent channel observation area of ​​the digital baseband sequence data, while minimizing significant disruption to the main energy distribution of the useful signal within the target passband. Furthermore, the "complex digital baseband signal after adjacent channel blocking suppression" in this step refers to the combined output signal of the in-phase and quadrature branches obtained after loading the target filter coefficient set, smooth switching filtering, and blocking interference suppression. This signal can be directly used as input for subsequent demodulation, synchronization, or baseband analysis modules.

[0067] Understandably, applying the target filter coefficient set generated in step S40 to the digital baseband sequence data suppresses adjacent channel blocking interference in the actual signal link and ensures that the filter parameter switching process does not cause significant transient disturbances to the target signal. Since the feasibility of the target filter coefficient set has been ensured in the previous step through stability constraints and fixed-point mapping design, this step can stably perform filtering operations in the chip's digital baseband link. Simultaneously, the smooth switching mechanism avoids the output oscillation, waveform tearing, or short-term energy surge problems that easily occur in traditional IIR filters when coefficients are abruptly loaded. Therefore, this step not only undertakes the final function of suppressing adjacent channel blocking interference but also ensures the continuity of filtering execution and the engineering usability of the output signal.

[0068] It should be understood that, compared to traditional techniques that directly switch to another set of fixed filter coefficients or abruptly update IIR coefficients after detecting adjacent channel interference, this step, through smooth switching filtering and blocking suppression processing, makes the loading process of the target filter coefficient set more in line with the requirements of continuous data stream processing in broadband RF receiver chips. Traditional methods often introduce additional transient components at the moment of coefficient switching, which can even cause short-term distortion of the useful signal in the target passband, thereby affecting synchronization, channel estimation, or demodulation performance. This invention, by introducing a smooth switching mechanism in this step, allows for a gradual transition from the old filtering state to the new filtering state, thus significantly reducing output disturbance at the moment of switching. Furthermore, traditional techniques typically only emphasize whether the adjacent channel power is reduced after filtering, neglecting whether the output result after filtering can still maintain the continuity of the complex digital baseband signal and the adaptability to subsequent processing; this invention, however, simultaneously considers blocking suppression effect and output availability, making it more suitable for deployment in the real-time digital baseband link of broadband RF receiver chips. For example, in the real-time operation scenario of a broadband RF receiver chip, significant adjacent channel blocking interference was not detected at one moment, and filtering parameters close to full pass were used. At the next moment, due to strong adjacent channel interference entering the receiving environment, step S40 generates a new set of target filter coefficients. The notch center position and stopband width of this coefficient set have been matched to the current blocking interference. If a traditional abrupt coefficient replacement method is used at this time, the sudden switch between the old and new filter states may cause transient oscillations at the output, causing waveform disturbances in the useful signal in the target passband within a short period. In this step, by smoothly transitioning the old filter output to the new filter output, the target passband signal remains continuous, and the adjacent channel blocking interference component is gradually suppressed. Furthermore, after blocking suppression is completed, the suppressed target passband power and the remaining adjacent channel power can be re-statistically analyzed, and these statistical results can be fed back to the previous detection and decision process so that the stopband position, stopband width, and suppression depth can be further corrected in the next round of processing based on the new power distribution. Therefore, this step not only achieves actual suppression of adjacent channel blocking interference, but also ensures that the entire frequency response self-adjusting IIR digital filter design method can work continuously and stably in dynamic interference environments through smooth switching and effect feedback.

[0069] Example 2: Furthermore, the present invention provides an IIR digital filter design system with self-adjusting frequency response, employing an IIR digital filter design method with self-adjusting frequency response as described in the above embodiments, which can solve the technical problem of designing an IIR digital filter with self-adjusting frequency response. The beneficial effects of the IIR digital filter design system with self-adjusting frequency response provided by the present invention are the same as those of the IIR digital filter design method with self-adjusting frequency response provided in the above embodiments, and other technical features of the IIR digital filter design system with self-adjusting frequency response are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0070] Example 3: This invention provides a design device for an IIR digital filter with self-adjusting frequency response. Please refer to... Figure 2An IIR digital filter design device with self-adjusting frequency response includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to perform the IIR digital filter design method with self-adjusting frequency response described in Embodiment 1 above. The IIR digital filter design device with self-adjusting frequency response in this embodiment of the invention may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. An IIR digital filter design device with self-adjusting frequency response is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the invention. A self-adjusting IIR digital filter design device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the self-adjusting IIR digital filter design device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An I / O interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows an IIR digital filter design device with self-adjusting frequency response to communicate wirelessly or wiredly with other devices to exchange data. While the figure shows an IIR digital filter design device with self-adjusting frequency response and various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0071] Example 4: This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method for designing an IIR digital filter with self-adjusting frequency response. The computer program product provided by this invention can solve the technical problem of designing an IIR digital filter with self-adjusting frequency response. Compared with the prior art, the beneficial effects of the computer program product provided by this invention are the same as those of the IIR digital filter design method with self-adjusting frequency response provided in the above embodiments, and will not be repeated here.

[0072] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0073] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0074] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A design method for an IIR digital filter with self-adjusting frequency response, characterized in that, The methods include: Step S10: Obtain the digital baseband sequence data after analog-to-digital conversion, digital down-conversion and decimation signal extraction of the broadband radio frequency receiving chip. Based on the digital baseband sequence data, use the frequency band mapping and parameter initialization construction mechanism to perform the task of constructing the basic dataset for adjacent channel blocking analysis, and output the frequency band mapping result and the initial set of IIR parameters. Step S20: Based on the frequency band mapping results and the initial set of IIR parameters, the Welch spectrum analysis method is used to perform the blocking detection feature extraction task and output the blocking detection feature set; Step S30: Based on the blocking detection feature set, a preprocessing task is performed using an adjacent channel blocking decision mechanism to output a self-adjusting target constraint set; Step S40: Based on the self-adjusting target constraint set, the target filter coefficient generation task is performed using a stability constraint-based fixed point mapping design mechanism, and the target filter coefficient set is output. Step S50: Perform smooth switching filtering and adjacent channel blocking suppression processing on the adjacent channel blocking interference component in the digital baseband sequence data according to the target filter coefficient set, and output the complex digital baseband signal after adjacent channel blocking suppression.

2. The design method for an IIR digital filter with self-adjusting frequency response as described in claim 1, characterized in that, Step S10 involves acquiring the digital baseband sequence data after analog-to-digital conversion, digital down-conversion, and decimation signal extraction from the broadband RF receiver chip. Based on this digital baseband sequence data, a frequency band mapping and parameter initialization mechanism is used to construct the basic dataset for adjacent channel blocking analysis, outputting the frequency band mapping results and the initial set of IIR parameters. Specifically, this includes: Step S101: Acquire the digital baseband sequence data after analog-to-digital conversion, digital down-conversion, and decimation signal extraction by the broadband RF receiver chip. The digital baseband sequence data includes complex digital baseband sampling sequences. Current sampling rate Target channel bandwidth Automatic gain control gain margin Digital downconversion frequency shift Decimation signal extraction factor and calibration status flags Where n is the discrete-time sampling point number in the digital baseband sampling sequence, used to characterize the nth sampling point in the complex digital baseband sampling sequence after analog-to-digital conversion, digital down-conversion, and decimation signal extraction; complex digital baseband sampling sequence The real part in the equation represents the sampling components of the in-phase branch, and the imaginary part represents the sampling components of the quadrature branch. Step S102: Establish the target passband set based on digital baseband sequence data. Adjacent Track Observation Zone Set Noise reference band set and frequency resolution ; Based on target passband set Adjacent Track Observation Zone Set Noise reference band set and frequency resolution Construct and output the frequency band junction results; Step S103: Based on the frequency band junction results and calibration status flags Initialize the IIR parameter control variables to obtain the initial value of the notch filter center angular frequency. Initial value of pole radius Initial value of the depth mixing coefficient When the calibration status flag The parameters are frozen and updated in time, and the output frequency band mapping results and the initial set of IIR parameters are output.

3. The design method for an IIR digital filter with self-adjusting frequency response as described in claim 2, characterized in that, In step S102, the target passband set is: The adjacent observation zone set is ; The noise reference band set is ; frequency resolution is ;in, The frequency variable in the complex digital baseband spectrum after digital down-conversion and decimation signal extraction; Configure the bandwidth for the current target channel to limit the target passband range where the useful target signal is located; This is the maximum cutoff frequency boundary of the adjacent channel observation band, used to limit the upper limit of the detection frequency for adjacent channel blocking interference; The complex digital baseband equivalent sampling rate after decimation signal extraction is used to determine the Nyquist frequency range and frequency resolution. This represents the number of Fast Fourier Transform points used in spectrum analysis to determine the discrete sampling accuracy of the spectrum.

4. The design method of an IIR digital filter with self-adjusting frequency response as described in claim 1, characterized in that, Step S20, which involves performing the blocking detection feature extraction task using the Welch spectrum analysis method based on the frequency band mapping results and the initial set of IIR parameters, and outputting the blocking detection feature set, specifically includes: Step S201: Based on the frequency band mapping results, perform frame segmentation, mean removal, and windowing processing on the digital baseband sequence data to obtain multi-segment analysis frame data for spectrum analysis; Step S202: Combine the initial values ​​of the notch center angular frequency, pole radius, and depth mixing coefficient in the initial set of IIR parameters to perform initial state marking on multiple analysis frame data segments, and output the analysis frame data; Step S203: Based on the analysis frame data, the Welch spectrum analysis method is used to perform frequency domain transformation and power spectrum averaging on each segment of the analysis frame data to obtain the power spectral density distribution results corresponding to the frequency band mapping results; and based on the power spectral density distribution results, frequency band partitioning statistics are performed to extract the power distribution information in the target passband, the power distribution information in the adjacent channel observation band, and the background noise distribution information in the noise reference band. Step S204: Perform structured association and encapsulation of the power distribution information in the target passband, the power distribution information in the adjacent channel observation band, and the background noise distribution information in the noise reference band, and output the blockage detection feature set.

5. The design method of an IIR digital filter with self-adjusting frequency response as described in claim 2, characterized in that, Step S30, which involves performing a preprocessing task based on the blocking detection feature set using an adjacent channel blocking decision mechanism and outputting a self-adjusting target constraint set, specifically includes: Step S301: Extract the target's typical power from the blockage detection feature set. Adjacent channel power Noise floor estimation And obtain the automatic gain control gain margin from the digital baseband sequence data. Construct a comprehensive detection threshold ;Will With comprehensive detection threshold Compare and output the adjacent channel blocking decision result; Step S302: When the adjacent channel blocking decision result indicates the existence of adjacent channel blocking interference, based on the adjacent channel observation band set... The peak frequency is first extracted using a method combining peak search and power centroid analysis. Then, focusing on the peak frequency... Construct a local frequency window W, and calculate the estimated center frequency of the blocking interference using the power centroid method. Finally, based on the estimated center frequency of the jamming interference... Bandwidth occupied by blocking interference was calculated using analysis methods based on 5% and 95% energy points. ; Step S303: Based on the bandwidth occupied by blocking interference Peak frequency Estimated center frequency of jamming interference and estimated center frequency of jamming interference Construct and output a set of self-adjusting objective constraints.

6. The design method of an IIR digital filter with self-adjusting frequency response as described in claim 5, characterized in that, In step S301, the comprehensive detection threshold is... ; ; ;in, The maximum value function is used to select the larger of the noise threshold and the relative threshold as the benchmark term for the comprehensive detection threshold; The noise threshold is used to characterize the upper limit of background noise power allowed in the adjacent channel observation band under the current noise floor estimation level. It is a relative threshold, used to characterize the upper limit of the adjacent channel power that is allowed relative to the target passband power; The adjacent channel power integration window bandwidth is used to characterize the adjacent channel observation bandwidth when performing power integration and noise threshold conversion within the adjacent channel observation band. This is the noise threshold compensation amount, used to adjust the detection sensitivity corresponding to the noise floor estimate to suppress misjudgments caused by background noise fluctuations. This is a relative threshold compensation amount, used to offset the adjacent channel detection threshold corresponding to the target passband power; This is the gain margin linkage compensation amount, used to dynamically correct the comprehensive detection threshold based on the automatic gain control gain margin. Specifically, when the automatic gain control gain margin decreases, the gain margin linkage compensation amount increases.

7. The design method of an IIR digital filter with self-adjusting frequency response as described in claim 1, characterized in that, Step S40, which involves generating target filter coefficients using a stability-constrained fixed-point mapping design mechanism based on a self-adjusting target constraint set and outputting the target filter coefficient set, specifically includes: Step S401: Based on the self-adjusting target constraint set, the notch center angular frequency, pole radius, and depth mixing coefficient of the IIR digital filter are parameterized and updated to obtain the updated notch center angular frequency, updated pole radius, and updated depth mixing coefficient; wherein, the parameterization update process includes: introducing a parameter update step size, and performing asymptotic updates on the notch center angular frequency, pole radius, and depth mixing coefficient in combination with the parameter update step size; Step S402: Based on the updated notch center angular frequency, updated pole radius and updated depth mixing coefficient, construct a second-order IIR notch prototype filter and perform gain normalization on the second-order IIR notch prototype filter to obtain floating-point filter coefficients. Step S403: First, perform pole position verification on the denominator polynomial corresponding to the floating-point filter coefficients to determine whether all poles are located within the unit circle. If not all poles are located within the unit circle, perform shrinkage correction on the updated pole radius and regenerate the floating-point filter coefficients. If all poles are located within the unit circle, perform fixed-point mapping on the floating-point filter coefficients to obtain fixed-point filter coefficients. Then, perform pole position verification again on the denominator coefficients after fixed-point mapping to determine whether all poles after fixed-point mapping are still located within the unit circle. If not all poles after fixed-point mapping are located within the unit circle, perform shrinkage correction on the updated pole radius again and regenerate the floating-point filter coefficients and perform fixed-point mapping. Step S404: Encapsulate the fixed-point filter coefficients, the updated notch center angular frequency, the updated pole radius, the updated depth mixing coefficients, and the pole position verification results together to output the target filter coefficient set.

8. A design system for an IIR digital filter with self-adjusting frequency response, applied to the design method for an IIR digital filter with self-adjusting frequency response as described in any one of claims 1 to 7, characterized in that, The IIR digital filter design system with self-adjusting frequency response includes: The basic data construction module is used to acquire digital baseband sequence data after analog-to-digital conversion, digital down-conversion and decimation signal extraction of the broadband RF receiver chip. Based on the digital baseband sequence data, the module uses a frequency band mapping and parameter initialization construction mechanism to perform the task of constructing the basic dataset for adjacent channel blocking analysis, and outputs the frequency band mapping results and the initial set of IIR parameters. The feature extraction module is used to perform the blocking detection feature extraction task based on the frequency band mapping results and the initial set of IIR parameters, and outputs the blocking detection feature set. The preprocessing module is used to perform preprocessing tasks based on the blocking detection feature set using the adjacent channel blocking decision mechanism, and outputs a self-adjusting target constraint set; The coefficient generation module is used to perform the target filter coefficient generation task based on the self-adjusting target constraint set and the stability constraint-based fixed point mapping design mechanism, and outputs the target filter coefficient set. The suppression output module is used to perform smooth switching filtering and adjacent channel blocking suppression processing on the adjacent channel blocking interference component in the digital baseband sequence data according to the target filter coefficient set, and output the complex digital baseband signal after adjacent channel blocking suppression.

9. A design device for an IIR digital filter with self-adjusting frequency response, characterized in that, The IIR digital filter design device with self-adjusting frequency response includes: a memory, a processor, and an IIR digital filter design program with self-adjusting frequency response stored in the memory and executable on the processor. When the IIR digital filter design program with self-adjusting frequency response is executed by the processor, it implements an IIR digital filter design method with self-adjusting frequency response as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes an IIR digital filter design program with self-adjusting frequency response, which, when executed by a processor, implements an IIR digital filter design method with self-adjusting frequency response as described in any one of claims 1 to 7.

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