Methods and apparatus for notch filtering using parallel filter circuitry

Abstract

This application relates to methods and apparatus for notch filtering using a parallel filter circuit system. An example apparatus includes: a decimation filter circuit system (205) having an output; a multiplexer circuit system (230) having an input, a first output, and a second output, the input of the multiplexer circuit system being coupled to the output of the decimation filter circuit system; a first delay circuit system (240) having an input and an output, the input of the first delay circuit system being coupled to the first output of the multiplexer circuit system; a first filter circuit system (255) having an input coupled to the output of the first delay circuit system; a second delay circuit system (245) having an input and an output, the input of the second delay circuit system being coupled to the second output of the multiplexer circuit system; and a second filter circuit system (260) having an input coupled to the output of the second delay circuit system.

Description

Technical Field

[0001] This specification relates generally to filtering, and more specifically, to methods and apparatus for notch filtering using parallel filter circuit systems. Background Technology

[0002] In signal processing systems, filter circuits reduce processing complexity by minimizing signal interference outside their frequency range. Several different types of filters include high-pass filters, low-pass filters, band-pass filters, and notch filters. High-pass filter circuits attenuate signals with frequencies below their cutoff frequency. Low-pass filter circuits attenuate signals with frequencies above their cutoff frequency. Band-pass filter circuits attenuate signals with frequencies below a first cutoff frequency or above a second cutoff frequency. Notch filter circuits attenuate signals of a specific frequency. Notch filter circuits allow the system to suppress signals with frequencies within the system's operating bandwidth. Summary of the Invention

[0003] For a method and apparatus for notch filtering using a parallel filter circuit system, an example apparatus includes: a decimation filter circuit system having an output; a multiplexer circuit system having an input, a first output, and a second output, the input of the multiplexer circuit system being coupled to the output of the decimation filter circuit system; a first delay circuit system having an input and an output, the input of the first delay circuit system being coupled to the first output of the multiplexer circuit system; a first filter circuit system having an input coupled to the output of the first delay circuit system; a second delay circuit system having an input and an output, the input of the second delay circuit system being coupled to the second output of the multiplexer circuit system; and a second filter circuit system having an input coupled to the output of the second delay circuit system. Other examples are described.

[0004] For methods and apparatuses using parallel filter circuit systems for notch filtering, example apparatuses include: an analog-to-digital converter (ADC) having an output; a decimation filter circuit system having an input and an output, the input of the decimation filter circuit system being coupled to the output of the ADC; a multiplexer circuit system having an input, a first output, and a second output, the input of the multiplexer circuit system being coupled to the output of the decimation filter circuit system; a first filter circuit system having an input coupled to the first output of the multiplexer circuit system; and a second filter circuit system having an input coupled to the second output of the multiplexer circuit system. Other examples are described.

[0005] For methods and apparatuses using parallel filter circuit systems for notch filtering, example apparatuses include: a multiplexer circuit system having a first output and a second output; a first delay circuit system having an input and an output, the input of the first delay circuit system being coupled to the first output of the multiplexer circuit system, the first delay circuit system being configured to delay a signal for a duration based on the number of filter circuit systems, a notch frequency, and an oversampling rate; a second delay circuit system having an input and an output, the input of the second delay circuit system being coupled to the second output of the multiplexer circuit system, the second delay circuit system being configured to delay the signal for the duration; a first filter circuit system having an input coupled to the output of the first delay circuit system; and a second filter circuit system having an input coupled to the output of the second delay circuit system. Other examples are described. Attached Figure Description

[0006] Figure 1 This is a block diagram of an example Δ-Σ analog-to-digital converter (ADC) circuit system that includes a notch filter circuit system.

[0007] Figure 2 It includes an example controller circuit system with parallel coupling and multiple example filter circuit systems. Figure 1 A block diagram of an example notch filter circuit system.

[0008] Figure 3 yes Figure 2 A block diagram of an example filter circuit system.

[0009] Figure 4 It means that it can be used. Figure 2 and 3 Example implementations of filter circuit systems or more generally Figure 1 and 2 A flowchart of example machine-readable instructions or example operations performed by the notch filter circuit system, including execution, instantiation, and / or operation.

[0010] Figure 5 yes Figure 2 A block diagram of an example implementation of the controller circuit system.

[0011] Figure 6 It means that it can be used. Figure 2 and 5 Example implementations of controller circuit systems or more generally Figure 1 and 2 A flowchart of example machine-readable instructions or example operations performed by the notch filter circuit system, including execution, instantiation, and / or operation.

[0012] Figure 7 yes Figure 1 and 2 The timing diagram shows an example operation of the notch filter circuit system filtering the notch signal at the notch frequency.

[0013] Figure 8 At notch frequency Figure 7 Filtering the notch signal Figure 2 and 3 Timing diagrams of example operations of the plurality of example filter circuit systems.

[0014] Figure 9 This is a block diagram of an example processing platform containing a programmable circuit system configured to execute, instantiate, or perform example machine-readable instructions or perform... Figure 4 and 6 Example operations to implement Figure 2 and 5 The controller circuit system or more generally Figure 1 and 2 Notch filter circuit system.

[0015] Figure 10 yes Figure 9 A block diagram of an example implementation of a programmable circuit system.

[0016] Figure 11 yes Figure 9 A block diagram of another example implementation of a programmable circuit system.

[0017] The accompanying drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to the same or similar features and / or parts (functionally and / or structurally). Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be invisible, mixed, or irregular. Detailed Implementation

[0018] In signal processing systems, filter circuits reduce processing complexity by minimizing signal interference outside their frequency range. Several different types of filters include high-pass filters, low-pass filters, band-pass filters, and notch filters. High-pass filter circuits attenuate signals with frequencies below their cutoff frequency. Low-pass filter circuits attenuate signals with frequencies above their cutoff frequency. Band-pass filter circuits attenuate signals with frequencies below a first cutoff frequency or above a second cutoff frequency. Notch filter circuits attenuate signals of a specific frequency. Notch filter circuits allow the system to suppress signals with frequencies within the system's operating bandwidth.

[0019] For example, some devices in analog-to-digital converters (ADCs) use notch filters to attenuate noisy signals at specific frequencies. These frequencies are called notch frequencies. In some designs, the sampling rate of the ADC's architecture is adjusted to filter the signal at the notch frequency. In such designs, the sampling rate is set to a multiple of the notch frequency to filter the signal at the notch frequency at the ADC output. However, for low-frequency notch filtering, this type of notch filtering limits the ADC's sampling rate to a fraction of the notch frequency, such as an integer fraction. With the continuous advancement of electronic technology, increasingly faster signal processing relies on increasingly faster ADCs.

[0020] The examples described herein include methods and apparatus for notch filtering using parallel filter circuitry systems. Some of the described examples include a notch filter circuitry system, which further includes a decimation filter circuitry system, a multiplexer circuitry system, and multiple filter channels. The decimation filter circuitry system receives digital input values ​​from an ADC circuitry system. The decimation filter circuitry system decimates the digital input values ​​at an oversampling rate (OSR). During decimation, the decimation filter circuitry system averages several digital input values. The number of digital values ​​averaged by the decimation filter circuitry system is set by the OSR. The decimation filter circuitry system provides oversampled samples to the multiplexer circuitry system. An oversampled sample is a single value representing the decimation of multiple digital values. The multiplexer circuitry system provides oversampled samples to one of the filter channels based on a conversion cycle. The conversion cycle causes the multiplexer circuitry system to sequentially and cyclically provide oversampled samples to each filter channel. The conversion cycle is equal to the line cycle period of the notch frequency divided by the product of the number of filter channels and the number of samples filtered within each notch frequency cycle. Such calculations combine... Figure 6 and 7 Further illustration and description.

[0021] In such an example, the filter channel comprises a delay circuit system and a filter circuit system. The delay circuit system delays oversampled samples from the multiplexer circuit system by a filter delay. The filter circuit system is a non-decimated moving average filter. The filter circuit system averages the oversampled samples from the delay circuit system. In example operation, during a first conversion cycle, the multiplexer circuit system provides oversampled samples to the first delay circuit system of the first filter channel. The first delay circuit system provides oversampled samples to the first filter circuit system to delay the filter delay. The first filter circuit system averages the oversampled samples from subsequent conversion cycles to attenuate the signal at a notch frequency. After the first conversion cycle, during a second conversion cycle, the multiplexer circuit system provides oversampled samples to the second delay circuit system of the second filter channel. Similar to the first filter channel, during the second conversion cycle, the delay circuit system provides oversampled samples to the second filter circuit system to delay the filter delay. The second filter circuit system averages the oversampled samples from subsequent conversion cycles to attenuate the signal at a notch frequency. In such example operation, the multiplexer circuit system cycles through each filter channel using conversion cycles.

[0022] Advantageously, the filter channel averages the amplitude of the signal at the notch frequency. Advantageously, the signal at the notch frequency is periodically attenuated by averaging. Advantageously, the notch filter circuit system filters the notch frequency without changing the ADC sampling rate.

[0023] Figure 1 This is a block diagram of an example Δ-Σ analog-to-digital converter (ADC) circuit system 100. Figure 1 In the example, the Δ-Σ ADC circuit system 100 includes an analog front-end (AFE) 110, a multiplexer circuit system 120, an ADC 130, a notch filter circuit system 140, and a control buffer circuit system 150. Figure 1 Example AFE 110 includes example scaling circuitry system 160 and example sample-and-hold circuitry system 170.

[0024] The Δ-Σ ADC circuit system 100 has a first input, a second input, a third input, and an output. The first input of the Δ-Σ ADC circuit system 100 is configured to couple to provide a first analog signal (ANALOG). IN_0 The first analog signal source is provided by the Δ-Σ ADC circuit system 100. The second input is configured to couple to provide the second analog signal (ANALOG). IN_1 The second analog signal source is provided. The third input of the Δ-Σ ADC circuit system 100 is configured to couple to provide a third analog signal (ANALOG). IN_NThe third analog signal source is the Δ-Σ ADC circuit system 100. In some examples, the Δ-Σ ADC circuit system 100 may have any number of inputs coupled to any number of analog signal sources, each providing any number of analog signals. However, as the number of inputs to the Δ-Σ ADC circuit system 100 increases, the conversion speed or data rate of the analog signals decreases. The output of the Δ-Σ ADC circuit system 100 (DIGITAL) OUT It is configured to be coupled to an external circuit system.

[0025] The AFE 110 has a first input, a second input, a third input, a first output, a second output, and a third output. The first, second, and third inputs of the AFE 110 are coupled to the first, second, and third inputs (ANALOG) of the Δ-Σ ADC circuit system 100. IN_0 ANALOG IN_1 ANALOG IN_N The corresponding components in the AFE 110. The first, second, and third outputs of the AFE 110 are coupled to the multiplexer circuit system 120.

[0026] The multiplexer circuit system 120 has a first input, a second input, a third input, a control input, and an output. The first, second, and third inputs of the multiplexer circuit system 120 are coupled to an AFE 110. The control input of the multiplexer circuit system 120 is coupled to a control buffer circuit system 150. The output of the multiplexer circuit system 120 is coupled to an ADC 130.

[0027] The ADC 130 has inputs and outputs. The input of the ADC 130 is coupled to a multiplexer circuit system 120. The output of the ADC 130 is coupled to a notch filter circuit system 140.

[0028] The notch filter circuit system 140 has inputs and outputs. The input of the notch filter circuit system 140 is coupled to the ADC 130. The output of the notch filter circuit system 140 is coupled to the control buffer circuit system 150 (DIGITAL). OUT The example of notch filter circuit system 140 is further combined. Figure 2 Show and describe.

[0029] The control buffer circuit system 150 has an input, a first output, and a second output. The input of the control buffer circuit system 150 is coupled to the notch filter circuit system 140. The first output of the control buffer circuit system 150 is coupled to the multiplexer circuit system 120. The second output of the control buffer circuit system 150 is coupled to the output of the Δ-Σ ADC circuit system 100.

[0030] The scaling circuit system 160 has a first input, a second input, a third input, a first output, a second output, and a third output. The first, second, and third inputs of the scaling circuit system 160 are coupled to the first, second, and third inputs of the Δ-Σ ADC circuit system 100 (ANALOG). IN_0 ANALOG IN_1 ANALOG IN_N The corresponding components in the scaling circuit system 160 are coupled to the sample-and-hold circuit system 170.

[0031] The sample-and-hold circuit system 170 has a first input, a second input, a third input, a first output, a second output, and a third output. The first, second, and third inputs of the sample-and-hold circuit system 170 are coupled to the scaling circuit system 160. The first, second, and third outputs of the sample-and-hold circuit system 170 are coupled to the multiplexer circuit system 120.

[0032] In the example operation, the AFE 110 receives the first, second, and third analog signals (ANALOG) from an external analog signal source. IN_0 ANALOG IN_1 ANALOG IN_N In some examples, AFE 110 can receive any number of analog signals. Scaling circuitry 160 scales the first, second, and third analog signals with a gain. In some examples, scaling circuitry 160 scales the analog signals with respective gain values. Sample-and-hold circuitry 170 periodically samples the first, second, and third analog signals. Sample-and-hold circuitry 170 provides the sampled analog values ​​to multiplexer circuitry 120. Control buffer circuitry 150 sequentially supplies the sampled analog values ​​to ADC 130.

[0033] In this example operation, ADC 130 converts the sampled analog values ​​into sequential digital values. ADC 130 provides the digital values ​​to notch filter circuitry 140. Notch filter circuitry 140 decimates the digital values ​​and averages them to filter the signal at the notch frequency from the digital values. Notch filter circuitry 140 provides the filtered digital values ​​to control buffer circuitry 150. Control buffer circuitry 150 buffers the filtered digital values. In some examples, control buffer circuitry 150 reconstructs the signal paths of the first, second, and third analog signals by positioning different digital outputs in different buffers. For example, control buffer circuitry 150 can generate first, second, and third digital signals corresponding to one of the first, second, or third analog signals, respectively. Advantageously, notch filter circuitry 140 filters the signal at the notch frequency without reducing the sampling rate of the Δ-Σ ADC circuitry 100. The example operation of notch filter circuitry 140 is combined with... Figure 2 , 3 4, 5 and 6 are further shown and described.

[0034] Figure 2 yes Figure 1 A block diagram of an example notch filter circuit system 140. Figure 2 The example notch filter circuit system 140 includes an example decimation filter circuit system 205, an example oversampling rate (OSR) circuit system 210, an example offset calibration circuit system 215, an example gain calibration circuit system 220, an example clipping circuit system 225, an example multiplexer circuit system 230, an example channel control circuit system 235, a first example delay circuit system 240, a second example delay circuit system 245, a third example delay circuit system 250, a first example filter circuit system 255, a second example filter circuit system 260, and a third example filter circuit system 265.

[0035] The notch filter circuit system 140 has an input, a first output, a second output, and a third output. The input of the notch filter circuit system 140 (DIGITAL) DATA ) is configured to be coupled to a digital signal source, for example Figure 1 The ADC 130. The first, second, and third outputs of the notch filter circuit system 140 (DIGITAL) DATA_0 DIGITAL DATA_1 DIGITAL DATA_N ) is constructed to be coupled to Figure 1 The control buffer circuit system 150.

[0036] The decimation filter circuit system 205 has a first input, a second input, and an output. The first input of the decimation filter circuit system 205 is coupled to the input (DIGITAL) of the notch filter circuit system 140. DATA The second input of the decimation filter circuit system 205 is coupled to the OSR circuit system 210. The output of the decimation filter circuit system 205 is coupled to the offset calibration circuit system 215.

[0037] OSR circuitry 210 has an output coupled to decimation filter circuitry 205. In some examples, OSR circuitry 210 is configured as part of a memory circuitry, such as a register or a relatively large memory structure, to store the oversampling rate. In such examples, OSR circuitry 210 may be programmed by controller circuitry 270. Alternatively, OSR circuitry 210 may be shown or described as part of decimation filter circuitry 205 or controller circuitry 270.

[0038] Offset calibration circuit system 215 has inputs and outputs. The input of offset calibration circuit system 215 is coupled to decimation filter circuit system 205. The output of offset calibration circuit system 215 is coupled to gain calibration circuit system 220.

[0039] The gain calibration circuit system 220 has inputs and outputs. The input of the gain calibration circuit system 220 is coupled to the offset calibration circuit system 215. The output of the gain calibration circuit system 220 is coupled to the clipping circuit system 225.

[0040] The clipping circuit system 225 has inputs and outputs. The input of the clipping circuit system 225 is coupled to the gain calibration circuit system 220. The output of the clipping circuit system 225 is coupled to the multiplexer circuit system 230.

[0041] Multiplexer circuit system 230 has a data input, a control input, a first output, a second output, and a third output. The data input of multiplexer circuit system 230 is coupled to clipping circuit system 225. In some examples, as shown by the dashed outline, the first input of multiplexer circuit system 230 is directly coupled to decimation filter circuit system 205. The control input of multiplexer circuit system 230 is coupled to channel control circuit system 235. The first output of multiplexer circuit system 230 is coupled to delay circuit system 240. The second output of multiplexer circuit system 230 is coupled to delay circuit system 245. The third output of multiplexer circuit system 230 is coupled to delay circuit system 250. Multiplexer circuit system 230 can also be referred to as a demultiplexer.

[0042] Channel control circuitry system 235 has inputs and outputs. The inputs of channel control circuitry system 235 are coupled to controller circuitry system 270. The outputs of channel control circuitry system 235 are coupled to multiplexer circuitry system 230. In some examples, channel control circuitry system 235 is part of a memory circuitry system, such as a register or a relatively large memory structure, configured to store control values. In such examples, channel control circuitry system 235 may be programmed by controller circuitry system 270. Alternatively, channel control circuitry system 235 may be shown or described as part of multiplexer circuitry system 230 or controller circuitry system 270.

[0043] The delay circuit system 240 has data input, control input, and output. The data input of the delay circuit system 240 is coupled to the multiplexer circuit system 230. The control input of the delay circuit system 240 is coupled to the delay circuit systems 245 and 250 and the controller circuit system 270. The output of the delay circuit system 240 is coupled to the filter circuit system 255.

[0044] The delay circuit system 245 has data input, control input, and output. The data input of the delay circuit system 245 is coupled to the multiplexer circuit system 230. The control input of the delay circuit system 245 is coupled to the delay circuit systems 240 and 250 and the controller circuit system 270. The output of the delay circuit system 245 is coupled to the filter circuit system 260.

[0045] The delay circuit system 250 has data input, control input, and output. The data input of the delay circuit system 250 is coupled to the multiplexer circuit system 230. The control input of the delay circuit system 250 is coupled to the delay circuit systems 240 and 245 and the controller circuit system 270. The output of the delay circuit system 250 is coupled to the filter circuit system 265.

[0046] Filter circuit system 255 has data input, control input, and output. The data input of filter circuit system 255 is coupled to delay circuit system 240. The control input of filter circuit system 255 is coupled to filter circuit systems 260 and 265 and controller circuit system 270. The output of filter circuit system 255 is coupled to the first output (DIGITAL) of notch filter circuit system 140. DATA_0 ).

[0047] Filter circuit system 260 has data input, control input, and output. The data input of filter circuit system 260 is coupled to delay circuit system 245. The control input of filter circuit system 260 is coupled to filter circuit systems 255 and 265 and controller circuit system 270. The output of filter circuit system 260 is coupled to the second output (DIGITAL) of notch filter circuit system 140.DATA_1 ).

[0048] Filter circuit system 265 has data input, control input, and output. The data input of filter circuit system 265 is coupled to delay circuit system 250. The control input of filter circuit system 265 is coupled to filter circuit systems 255 and 260 and controller circuit system 270. The output of filter circuit system 265 is coupled to the third output (DIGITAL) of notch filter circuit system 140. DATA_N ).

[0049] Figure 3 This is a block diagram of an example of a filter circuit system 300, which is Figure 2 Example implementations of filter circuit systems 255, 260, and 265. Figure 3 The example filter circuit system 300 includes an example stabilization circuit system 310, a first example averaging circuit system 320, an example sample numbering circuit system 330, an example multiplexer circuit system 340, an example mode circuit system 350, a second example averaging circuit system 360, and a third example averaging circuit system 370.

[0050] The filter circuit system 300 has a data input, a first control input, a second control input, and an output. The data input (OSR_SAMPLE) of the filter circuit system 300 is configured to be coupled to a delay circuit system, for example... Figure 2 The delay circuit systems 240, 245, and 250. The first and second control inputs (MODE, NUM_SAMPLES) of the filter circuit system 300 are configured to be coupled to the controller circuit system, for example... Figure 2 The controller circuit system 270. The output of the filter circuit system 300 (DIGITAL). DATA_N ) is configured to be coupled to a buffer circuit system, for example Figure 1 The control buffer circuit system 150.

[0051] The stabilizing circuit system 310 has inputs and outputs. The input of the stabilizing circuit system 310 is coupled to the data input (OSR_SAMPLE) of the filter circuit system 300. The output of the stabilizing circuit system 310 is coupled to the averaging circuit system 320.

[0052] The averaging circuit system 320 has data input, control input, and output. The data input of the averaging circuit system 320 is coupled to the stabilizing circuit system 310. The control input of the averaging circuit system 320 is coupled to the sample counting circuit system 330 and the averaging circuit systems 360 and 370. The output of the averaging circuit system 320 is coupled to the multiplexer circuit system 340.

[0053] The sample counting circuit system 330 has inputs and outputs. The input of the sample counting circuit system 330 is coupled to the first control input of the filter circuit system 300. The output of the sample counting circuit system 330 is coupled to the averaging circuit systems 320, 360, and 370.

[0054] The multiplexer circuit system 340 has a data input, a control input, a first output, and a second output. The data input of the multiplexer circuit system 340 is coupled to an averaging circuit system 320. The control input of the multiplexer circuit system 340 is coupled to a mode circuit system 350. The first output of the multiplexer circuit system 340 is coupled to the output of the averaging circuit system 370 and the filter circuit system 300 (DIGITAL). DATA_N The second output of the multiplexer circuit system 340 is coupled to the averaging circuit system 360.

[0055] The mode circuit system 350 has inputs and outputs. The input of the mode circuit system 350 is coupled to the second control input of the filter circuit system 300. The output of the mode circuit system 350 is coupled to the multiplexer circuit system 340.

[0056] The averaging circuit system 360 has data input, control input, and output. The data input of the averaging circuit system 360 is coupled to the multiplexer circuit system 340. The control input of the averaging circuit system 360 is coupled to the averaging circuit systems 320 and 370 and the sample counting circuit system 330. The output of the averaging circuit system 360 is coupled to the averaging circuit system 370.

[0057] The averaging circuit system 370 has data input, control input, and output. The data input of the averaging circuit system 370 is coupled to the averaging circuit system 360. The control input of the averaging circuit system 370 is coupled to the averaging circuit systems 320 and 360 and the sample counting circuit system 330. The output of the averaging circuit system 370 is coupled to the output of the multiplexer circuit system 340 and the filter circuit system 300 (DIGITAL). DATA_N ).

[0058] Figure 4 It means that it can be used. Figure 2 and 3 Filter circuit systems 255, 260, 265 or more generally Figure 1 and 2 A flowchart of example machine-readable instructions or example operations 400 executed, instantiated, and / or performed by the notch filter circuit system 140. Figure 4 Example operation 400 begins Figure 6 Example operation 600, i.e. Figure 2 The controller circuit system 270 sets the filter delay. In example operation, such as in combination Figure 6 Further shown and described, the controller circuit system 270 is configured Figure 2 OSR circuit system 210 Figure 2 Channel control circuit system 235 Figure 2 Delay circuit systems 240, 245, 250, Figure 3 The number of samples in the circuit system 330 and Figure 3 The controller circuit system 270 is a modular circuit system 350. In some examples, one or more portions of the controller circuit system 270 are integrated on a chip. In other examples, one or more portions of the controller circuit system 270 may be implemented off-chip. In such examples, another device implements said one or more portions of the controller circuit system 270 to perform prior to runtime. Figure 6 Operation 600, for example, during calibration or upon power-up. Control continues to block 405.

[0059] The notch filter circuit system 140 receives the input (box 405). In example operation, Figure 1 The ADC 130 provides a digital value in response to converting the analog value of the analog signal. In this example operation, the notch filter circuitry 140 is configured to attenuate the signal at the notch frequency from the digital value.

[0060] Figure 2 The decimation filter circuitry 205 decimates the input at an oversampling rate (Box 410). In example operation, the OSR circuitry 210 provides the oversampling rate to the decimation filter circuitry 205. The oversampling rate represents the number of subsequent digital values ​​filtered by the decimation filter circuitry 205. In such example operation, the decimation filter circuitry 205 averages several subsequent digital values ​​to produce an oversampled sample (OSR_SAMPLE). For example, in response to an OSR of 128, the decimation filter circuitry 205 divides the sum of 128 sequential digital values ​​by 128 to produce a first oversampled sample. In such an example, the decimation filter circuitry 205 divides the sum of the subsequent 128 sequential digital values ​​by 128 to produce a second oversampled sample. Advantageously, the decimation filter circuitry 205 filters relatively high frequencies in response to averaging multiple digital values.

[0061] In some examples, as shown by the dashed outline, Figure 2 The offset calibration circuitry 215 is configured to correct the offset data (box 415). In example operation, the offset calibration circuitry 215 removes the DC offset from the oversampled samples. Advantageously, the offset calibration circuitry 215 reduces the averaging error caused by the DC offset.

[0062] In some examples, as shown by the dashed outline, Figure 2The gain calibration circuitry 220 is configured for gain correction data (box 420). In example operation, the gain calibration circuitry 220 amplifies the sampled values. In such example operation, the gain calibration circuitry 220 takes into account the gain of the notch filter circuitry 140. Furthermore, in some examples, the gain calibration circuitry 220 scales the sampled values ​​to account for gain errors in the AFE 110 or external components.

[0063] In some examples, as shown by the dashed outline, Figure 2 The clipping circuit system 225 is configured for clipping correction data (box 425). In example operation, the clipping circuit system 225 determines whether the amplitude of the sampled value is between a maximum and a minimum value. In such example operation, the clipping circuit system 225 sets the amplitude of the sampled value to either the maximum or minimum value in response to determining that the sampled value is not between the maximum and minimum values. Advantageously, the gain calibration circuit system 220 and the clipping circuit system 225 increase the likelihood that the oversampled sample is within the value range.

[0064] Figure 2 The multiplexer circuit system 230 determines the filter channels for the data samples (box 430). In example operation, the multiplexer circuit system 230 responds to... Figure 2 The channel control circuit system 235 provides oversampled samples to one of the delay circuit systems 240, 245, and 250. In this example operation, the multiplexer circuit system 230 cycles through each of the delay circuit systems 240, 245, and 250 based on a conversion cycle. The conversion cycle represents the periodic division of the notch frequency sampled by the filter circuit systems 255, 260, and 265. For example, as... Figure 8 As further shown, the channel control circuit system 235 changes the supply of oversampled samples after each conversion cycle. The multiplexer circuit system 230 cyclically supplies oversampled samples to each of the delay circuit systems 240, 245, and 250.

[0065] At least one of the delay circuit systems 240, 245, and 250 uses a filter delay to delay the data samples (Box 435). In example operation, delay circuit systems 240, 245, and 250 provide an oversampled sample delay—a filter delay—to filter circuit systems 255, 260, and 265. The filter delay takes into account the time difference between the conversion period and the oversampling timing of filter circuit systems 255, 260, and 265. An example sequence combining filter delay, oversampling, and conversion period is shown. Figure 6 , 7 8 further illustrates and describes.

[0066] In some examples, as shown by the dashed outline, Figure 3The stabilizing circuit system 310 allows data samples to be stabilized (Box 440). In example operation, the stabilizing circuit system 310 discards (e.g., removes, ignores, etc.) one or more oversampled samples before providing stable oversampled samples. In some examples, the switching components of the multiplexer circuit system 230 introduce noise into the oversampled samples. In such examples, the stabilizing circuit system 310 filters the noise introduced by the switching of the multiplexer circuit system 230 in response to ignoring the initial oversampled samples during the transition cycle. Advantageously, the stabilizing circuit system 310 allows the oversampled samples to be stabilized before further filtering.

[0067] Figure 3 The averaging circuit system averages 320 logarithmic data samples. (Box 445). In the example operation, Figure 3 The sample numbering circuit system 330 configures the averaging circuit system 320 to average a logarithmic number of samples. In this example operation, the averaging circuit system 320 averages a logarithmic number of samples over multiple sampling periods. The sampling period of the notch filter circuit system 140 is the duration for which oversampled samples are cyclically supplied to each of the delay circuit systems 240, 245, and 250. For example, if the notch filter circuit system 140 cycles between eight instances of the filter circuit system 300, then the sampling period is eight switching periods. Unlike the decimation filter circuit system 205, the averaging circuit system 320 provides a moving average of oversampled samples from previous sampling periods. For example, the averaging circuit system 320 averages the first, second, third, and fourth oversampled samples to produce a first filtered output. In this example, the averaging circuit system 320 produces a second filtered output in response to averaging the second, third, fourth, and fifth oversampled samples. Advantageously, the averaging circuit system 320 filters the notch frequency in response to averaging oversampled values ​​from different sampling periods.

[0068] Figure 3 The multiplexer circuit system 340 determines whether the filter is a multi-order filter. (Box 450). In the example operation, Figure 3The mode circuit system 350 controls the multiplexer circuit system 340 to set the modes of the filter circuit systems 255, 260, and 265. In the first mode, the multiplexer circuit system 340 provides averaged oversampled samples at the output of the filter circuit system 300. In the second mode, the multiplexer circuit system 340 provides averaged oversampled samples to the averaging circuit system 360 for further filtering. In the second mode, the additional averaging of the oversampled samples increases the accuracy of the notch frequency filtering. In both examples, the averaging circuit systems 320, 360, and 370 average several (N) samples from the sample numbering circuit system 330. The number of times (M) the sampled values ​​are averaged is determined by the mode setting. In the first mode, the filter circuit system 300 averages the oversampled samples once. In the second mode, the filter circuit system averages the oversampled samples three times. This type of averaging forms a cascaded moving average filter, represented by equation (1).

[0069] Equation (1)

[0070] If the multiplexer circuit system 340 determines that the filter is a multi-order filter (e.g., box 450 returns a result of "yes"), then Figure 3 The averaging circuitry 360 averages several samples of the average data (box 455). In an example operation, the sample counting circuitry 330 configures the averaging circuitry 360 to average several samples. In such an example operation, the averaging circuitry 360 averages several samples across multiple sampling periods. Advantageously, the averaging circuitry 360 filters the notch frequency in response to averaging oversampled samples at different sampling periods.

[0071] Figure 3 The averaging circuitry 370 averages another number of samples of the averaged data (box 460). In an example operation, the sample numbering circuitry 330 configures the averaging circuitry 370 to average a logarithmic number of samples. In such an example operation, the averaging circuitry 370 averages a logarithmic number of samples across multiple sampling periods. Advantageously, the averaging circuitry 370 filters the notch frequency in response to averaging oversampled samples at different sampling periods.

[0072] If the multiplexer circuit system 340 determines that the filter is not a multi-order filter (e.g., block 450 returns a result of "No") or control continues from block 460, then Figure 1The control buffer circuit system 150 buffers the filtered data (box 465). In example operation, filter circuit systems 255, 260, 265, 300 attenuate the signal at the notch frequency to provide a digital output value. In this example operation, the control buffer circuit system 150 buffers the digital output values ​​of filter circuit systems 255, 260, 265 to reconstruct a digital representation of the analog signal. Advantageously, the control buffer circuit system 150 sorts the outputs of the notch filter circuit system 140 to represent the analog input of the ADC 130. Control continues to box 405.

[0073] Example methods are referenced Figure 4 The flowchart shown is illustrated. However, many other implementations may also be used in this specification. Figure 2 and 3 Filter circuit systems 255, 260, 265 or more generally Figure 1 and 2 The method of the notch filter circuit system 140. For example, the execution order of the blocks can be varied, or some of the blocks described can be changed, removed, or combined. Similarly, additional operations can be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0074] Figure 5 yes Figure 2 A block diagram of an example implementation of the controller circuit system 270. Figure 5 The controller circuit system 270 can be instantiated (e.g., create an instance, exist for any duration, materialize, implement, etc.) by executing first instructions through a programmable circuit system, such as a central processing unit (CPU). Alternatively or concurrently, Figure 5 The controller circuit system 270 can be instantiated (e.g., instantiated, exist for any length of time, materialized, implemented, etc.) by: (i) an application-specific integrated circuit (ASIC); or (ii) a field-programmable gate array (FPGA) constructed or configured in response to the execution of a second instruction to perform an operation corresponding to the first instruction. Therefore, Figure 5 Some or all of the circuit systems in the system can be instantiated at the same or different times. Figure 5 Some or all of the circuitry can be instantiated, for example, in one or more threads that execute simultaneously or sequentially on the hardware. Furthermore, in some examples, Figure 5 Some or all of the circuitry can be implemented by executing instructions through a microprocessor circuitry or performing operations through an FPGA circuitry to implement one or more virtual machines or containers.

[0075] exist Figure 5In the example, the controller circuit system 270 includes a bus 500, a notch frequency circuit system 510, a filter channel number circuit system 520, a number of samples per cycle circuit system 530, a filter order circuit system 540, a conversion cycle calculator circuit system 550, an oversampling determination circuit system 560, a delay determination circuit system 570, and a channel clock circuit system 580.

[0076] The controller circuit system 270 has inputs, a first output, a second output, a third output, a fourth output, and a fifth output. The inputs of the controller circuit system 270 are configured to be coupled to an external device. In some examples, the external device provides user input to the controller circuit system 270 via an interface. In other examples, the controller circuit system 270 receives the value of the user input from a memory circuit system. The first output (OSR) of the controller circuit system 270 is configured to be coupled to... Figure 2 The OSR circuit system 210. The second output (CHANNEL_CTRL) of the controller circuit system 270 is configured to couple to Figure 2 The channel control circuit system 235. The third output (DELAY) of the controller circuit system 270 is configured to couple to Figure 2 The delay circuit systems 240, 245, and 250. The fourth output (NUM_SAMPLES) of the controller circuit system 270 is configured to couple to Figure 3 The sample number circuit system 330. The fifth output (MODE) of the controller circuit system 270 is configured to be coupled to Figure 3 The mode circuit system 350.

[0077] Bus 500 is coupled to the inputs of notch frequency circuit system 510, filter channel number circuit system 520, sample number per cycle circuit system 530, filter order circuit system 540, conversion cycle calculator circuit system 550, oversampling determination circuit system 560, delay determination circuit system 570, channel clock circuit system 580, and controller circuit system 270.

[0078] Notch frequency circuitry system 510 is coupled to bus 500. In some examples, notch frequency circuitry system 510 executes notch frequency commands via a programmable circuitry system to perform, for example, by... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0079] The filter channel numbering circuitry 520 is coupled to bus 500. In some examples, the filter channel numbering circuitry 520 executes filter channel numbering instructions via a programmable circuitry to perform, for example, actions by... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0080] The per-cycle sample count circuitry 530 is coupled to the fourth output (NUM_SAMPLES) of the bus 500 and the controller circuitry 270. In some examples, the per-cycle sample count circuitry 530 executes per-cycle sample count instructions via a programmable circuitry to perform, for example, actions by... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0081] The filter order circuitry system 540 is coupled to the fifth output (MODE) of the bus 500 and the controller circuitry system 270. In some examples, the filter order circuitry system 540 executes filter order circuitry system instructions via a programmable circuitry system to perform, for example, actions... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0082] The conversion cycle calculator circuit system 550 is coupled to bus 500. In some examples, the conversion cycle calculator circuit system 550 executes conversion cycle calculator instructions via a programmable circuit system to perform, for example, actions by... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0083] The oversampling determination circuitry 560 is coupled to the bus 500 and the first output (OSR) of the controller circuitry 270. In some examples, the oversampling determination circuitry 560 executes oversampling determination instructions via a programmable circuitry to perform, for example, by... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0084] The delay determination circuitry 570 is coupled to the bus 500 and the third output (DELAY) of the controller circuitry 270. In some examples, the delay determination circuitry 570 executes delay determination instructions via a programmable circuitry to perform, for example, actions by... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0085] The channel clock circuitry 580 is coupled to the second output (CHANNEL_CNTRL) of the bus 500 and the controller circuitry 270. In some examples, the channel clock circuitry 580 executes channel clock instructions via a programmable circuitry to perform, for example, actions... Figure 6 The flowchart represents the operations used to instantiate those operations.

[0086] Figure 6 It means that it can be used. Figure 2 and 5 Example implementation of controller circuit system 270 or more generally Figure 1 and 2A flowchart of example machine-readable instructions or example operations 600 executed, instantiated, and / or performed by the notch filter circuit system 140.

[0087] Figure 6 Example operation 600 begins at box 605, i.e. Figure 5 The notch frequency circuit system 510 receives the notch frequency. The notch frequency is used as... Figure 1 The target frequency within the bandwidth of the Δ-Σ ADC circuit system 100. The notch filter circuit system 140 from... Figure 1 The signal at the notch frequency is filtered in the output of the ADC 130. In some examples, the notch frequency corresponds to a frequency that a noisy signal might have. For example, if the mains connection provides power at 60 Hz, then the notch filter circuitry 140 filters noise from the mains connection in response to setting the notch frequency to 60 Hz. In example operation, the notch frequency circuitry 510 stores the notch frequency. In some examples, the notch frequency of the notch frequency circuitry 510 is set by user input. In other examples, the notch frequency of the notch frequency circuitry 510 is set in response to loading the notch frequency from memory. Advantageously, the notch filter circuitry 140 allows the circuitry to filter signals having a notch frequency that is within the system's bandwidth.

[0088] Figure 5 The number of filter channels in the circuit system 520 is the number of receive filter channels (box 610). The filter channels of the notch filter circuit system 140 include... Figure 2 One of the delay circuit systems 240, 245, and 250 and Figure 2 and 3 One of the filter circuit systems 255, 260, 265, and 300. In Figure 2 In the example, delay circuit system 240 and filter circuit system 255 form a first filter channel, delay circuit system 245 and filter circuit system 260 form a second filter channel, and delay circuit system 250 and filter circuit system 265 form a third filter channel. Alternatively, notch filter circuit system 140 can be modified to include any number of filter channels. In the example operation, filter channel number circuit system 520 stores the number of filter channels of notch filter circuit system 140. In some examples, the number of filter channels of filter channel number circuit system 520 is set by user input. In other examples, the number of filter channels of filter channel number circuit system 520 is set in memory.

[0089] Figure 5The filter order of the filter circuit system 540 is the receiving filter order (box 615). The filter order corresponds to the number of oversampled samples averaged by filter circuit systems 255, 260, 265, and 300 to filter the notch frequency. In some examples, such as in... Figure 3 In the filter circuit system 300, two filter orders are supported, each set by a filter mode. In the first mode, Figure 3 The mode circuit system 350 will Figure 3 The multiplexer circuit system 340 is configured to provide the output of the averaging circuit system 320 at the output of the filter circuit system 300. In the second mode, the mode circuit system 350 configures the multiplexer circuit system 340 to provide the output of the filter circuit system 300. Figure 3 The average output of the circuit system 370 is taken. In the second mode, in response to... Figure 3 The averaging circuit systems 320, 360, and 370 filter, with filter circuit system 300 considered to have a high filter order. In example operation, filter order circuit system 540 stores the filter orders of filter circuit systems 255, 260, 265, and 300. In some examples, the filter order of filter order circuit system 540 is set by user input. In other examples, the filter order of filter order circuit system 540 is set in memory. Furthermore, in some examples, the filter order is set with reference to the pattern of filter circuit systems 255, 260, 265, and 300.

[0090] Figure 5 The number of samples per cycle circuitry 530 receives the number of samples per cycle (box 620). The number of samples per cycle represents the number of samples of the signal averaged at the notch frequency for any given period across the notch frequency by the averaging circuitry 320, 360, and 370 circuitries. In some examples, Figure 3 The sample number circuit system 330 is configured to average the same number of samples per cycle with the averaging circuit systems 320, 360, and 370. Alternatively, the averaging circuit systems 320, 360, and 370 can average different numbers of samples per cycle for the notch frequency. In example operation, the per-cycle sample number circuit system 530 stores the per-cycle sample number of the filter circuit systems 255, 260, 265, and 300. In some examples, the per-cycle sample number of the per-cycle sample number circuit system 530 is set by user input. In other examples, the per-cycle sample number of the per-cycle sample number circuit system 530 is set in memory. Furthermore, in some examples, the per-cycle sample number is set with reference to the averaging circuit systems 320, 360, and 370.

[0091] Figure 5 The conversion cycle calculator circuit system 550 is based on the notch frequency ( ) Calculate the line cycle period ( (Box 625). The line cycle period is the period of a single cycle of the signal at the notch frequency. In example operation, the conversion cycle calculator circuit system 550 determines the line cycle period in response to dividing one by the notch frequency. In some examples, the conversion cycle calculator circuit system 550 may determine the line cycle period by referring to the number of cycles of a reference clock signal. The line cycle period can be determined using equation (2).

[0092] Equation (2)

[0093] The conversion cycle calculator circuit system 550 is based on the line cycle period ( ), number of channels ( ) and sample size ( To calculate the conversion period () (Box 630). The conversion period is the period of the notch frequency divided by the total number of samples required to cycle through the filter channels of the notch filter circuit system 140. For example, if the averaging circuit system 320 averages four samples, then the number of samples is four; if the notch filter circuit system 140 has eight instances of the filter circuit system 300, then the number of channels is eight. In example operation, the conversion period is evenly divided into linear cycle periods between each instance of the filter circuit system 300. In such example operation, as... Figure 7 and 8 Further illustrated, during the first conversion cycle, multiplexer circuit system 230 supplies a value to delay circuit system 240; during the second conversion cycle, multiplexer circuit system 230 supplies a value to delay circuit system 245; and during the final conversion cycle, multiplexer circuit system 230 supplies a value to delay circuit system 250. Advantageously, conversion cycle calculator circuit system 550 uniformly divides the linear cycle period among the filter channels of filter circuit systems 255, 260, and 265.

[0094] Equation (3)

[0095] Figure 5 The oversampling determination circuit system 560 determines the oversampling rate (box 635). (As in conjunction with...) Figure 4 To describe further, Figure 2The decimation filter circuitry 205 decimates the digital input value from the ADC 130 at an oversampling rate (OSR). In this type of example, the decimation filter circuitry 205 provides the oversampled values ​​to filter circuitry 255, 260, and 265. In example operation, filter circuitry 255, 260, and 265 can receive multiple oversampled values ​​during a corresponding conversion cycle. For example, the conversion cycle can be long enough that the decimation filter circuitry 205 can provide four oversampled values ​​at a first OSR or two oversampled values ​​at a second OSR. In this type of example, the second OSR is twice the first OSR. Some example OSRs contain thirty-two samples, sixty-four samples, one hundred and twenty-eight samples, etc. In some example operations, the oversampling determination circuitry 560 uses the input sampling rate and the conversion cycle to determine the OSR. Furthermore, when using... Figure 3 In the example of the stabilizing circuit system 310, the oversampling determination circuit system 560 may further consider the minimum number of sampled values ​​in the conversion cycle. For example, if the stabilizing circuit system 310 discards the first three samples of the conversion cycle, then the oversampling determination circuit system 560 selects an OSR that provides at least four oversampled samples per conversion cycle.

[0096] Figure 5 The delay determination circuit system 570 uses a filter order ( ), conversion cycle ( ) and oversampling rate ( Determine the filter delay ( (Box 640). The filter order represents the number of oversampled samples per conversion cycle required by the filter circuitry 300. In some examples, the oversampling determination circuitry 560 determines that the conversion cycle cannot be divided by the determined OSR. In such examples, the delay circuitry 240, 245, 250 implements a filter delay to align the conversion cycle with the OSR. Furthermore, in examples using the stabilization circuitry 310, the oversampling determination circuitry 560 may require the minimum number of oversampled values ​​in the conversion cycle. For example, if the stabilization circuitry 310 discards the first three samples of the conversion cycle, then the filter order is four. In such example operations, the filter delay corresponds to the portion of the conversion cycle that aligns the number of samples equal to the filter order with the end of the conversion cycle. Such a filter delay can be found using equation (4). Furthermore, the example conversion cycle is combined with... Figure 7 and 8 Further illustration and description.

[0097] Equation (4)

[0098] The delay determination circuitry 570 determines whether the filter delay is greater than zero (box 645). In some examples, the delay determination circuitry 570 may determine that the decimation filter circuitry 205 cannot provide a number of samples equal to the filter order in a given conversion cycle. In such examples, the OSR determined in box 635 cannot be implemented.

[0099] If the delay determination circuitry 570 determines that the filter delay does not exceed zero (e.g., box 645 returns a result of "No"), then the oversampling determination circuitry 560 determines an alternative oversampling rate (box 650). In example operation, the oversampling determination circuitry 560 selects a different OSR in response to determining that the conversion period is not long enough to support the previous OSR.

[0100] If delay determination circuitry 570 determines that the filter delay is greater than zero (e.g., box 645 returns a result of "yes"), then delay determination circuitry 570 sets the delay of the filter channel (box 655). In example operation, delay determination circuitry 570 sets the delays of delay circuitry 240, 245, 250 to the filter delay of box 640. In such example operation, delay circuitry 240, 245, 250 aligns the oversampled samples of the transition cycles of filter circuitry 255, 260, 265. In some examples, such delays of delay circuitry 240, 245, 250 correspond to the filter delay of equation (4). In other examples, different processes can be used to delay or change the timing of the oversampled samples. Advantageously, the filter delays of delay circuitry 240, 245, 250 enable oversampled sample alignment, allowing filtering through filter circuitry 255, 260, 265.

[0101] Oversampling determination circuitry 560 sets the oversampling rate (box 660). In example operation, oversampling determination circuitry 560 provides the oversampling rate to OSR circuitry 210. In this type of example, OSR circuitry 210 uses the selected OSR to configure decimation filter circuitry 205 to perform decimation.

[0102] Filter order circuitry 540 sets the mode of the filter channels (Box 665). In example operation, filter order circuitry 540 provides values ​​representing the modes of filter circuitry 255, 260, 265 to mode circuitry 350. In this type of example, mode circuitry 350 controls multiplexer circuitry 340.

[0103] The per-cycle sample count circuitry 530 sets the sample count (box 670). In example operation, the per-cycle sample count circuitry 530 provides the sample count to the sample count circuitry 330. In this type of example, the sample count circuitry 330 configures the averaging circuitry 320, 360, 370 to average the number of samples. Control returns.

[0104] Example methods are referenced Figure 6 The flowchart shown is illustrated. However, many other implementations may also be used in this specification. Figure 2 and 5 The controller circuit system 270 or more generally Figure 1 and 2 The method of the notch filter circuit system 140. For example, the execution order of the blocks can be varied, or some of the blocks described can be changed, removed, or combined. Similarly, additional operations can be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0105] Figure 7 This involves filtering the example notch signal 710 at the notch frequency. Figure 1 and 2 Timing diagram 700 shows an example operation of the notch filter circuit system 140. Notch signal 710 represents the response of the notch filter circuit system 140 to... Figure 4 and 6 The signal is filtered using operations 400 and 600. In some examples, the period of the notch signal 710 is called the line cycle period.

[0106] The first conversion cycle begins before 7:25 AM. During the first conversion cycle, Figure 2 The multiplexer circuit system 230 will transfer oversampled samples from Figure 2 The decimation filter circuit system 205 is provided to the first filter channel. Figure 2 In the example, the first filter channel contains Figure 2 Delay circuit system 240 and Figure 2 The filter circuit system 255. At the first time 725, the filter circuit system 255 accumulates the first channel oversampled sample (0-1) of the notch signal 710.

[0107] The period between the first time 725 and the second time 730 is the second conversion cycle. During the second conversion cycle, the multiplexer circuit system 230 provides oversampled samples from the decimation filter circuit system 205 to the second filter channel. Figure 2 In the example, the second filter channel contains Figure 2 Delay circuit system 245 and Figure 2The filter circuit system 260. At the second time 730, the filter circuit system accumulates the second channel oversampled sample (1-1) of the notch signal 710.

[0108] After the second time period 730, a third conversion cycle (not shown for simplicity) occurs. During the third conversion cycle, the multiplexer circuit system 230 provides oversampled samples from the decimation filter circuit system 205 to the third filter channel. Figure 2 In the example, the third filter channel contains Figure 2 Delay circuit system 250 and Figure 2 The filter circuit system 265. Although in Figure 2 and 7 In the example, the notch filter circuit system 140 is shown and described in combination with three filter channels, but in some examples, the notch filter circuit system 140 may contain any number of filter channels.

[0109] At time 735, the fourth conversion cycle ends, during which filter circuit system 255 accumulates another oversampled sample (0-2) of the first channel of the notch signal 710. At time 740, the fifth conversion cycle ends, during which filter circuit system 260 accumulates another oversampled sample (1-2) of the second channel of the notch signal 710. Similar to the time intervals between 730 and 735, between time 745 and the fifth time interval 745, the sixth conversion cycle occurs, during which filter circuit system 265 accumulates another oversampled sample of the third channel.

[0110] At time 745, the seventh conversion cycle ends, during which filter circuit system 255 accumulates another oversampled sample (0-3) of the first channel of the notch signal 710. At time 750, the eighth conversion cycle ends, during which filter circuit system 260 accumulates another oversampled sample (1-3) of the second channel of the notch signal 710. Similar to the time intervals 740 and 745, between time 750 and time 755, the ninth conversion cycle occurs, during which filter circuit system 265 accumulates another oversampled sample of the third channel.

[0111] At time 755, the tenth conversion cycle ends, during which filter circuit system 255 accumulates the final first channel oversampled samples (0-4) of the notch signal 710. At time 760, the eleventh conversion cycle ends, during which filter circuit system 260 accumulates the final second channel oversampled samples (1-4) of the notch signal 710. Similar to the time intervals between 750 and 755, between time 760 (eighth time) and time 765 (ninth time), the twelfth conversion cycle occurs, during which filter circuit system 265 accumulates the final third channel oversampled samples.

[0112] At time 755, filter circuit system 255 averages the oversampled samples of the first channel accumulated at times 725, 735, 745, and 755. Advantageously, the average amplitude of the notch signal 710 at times 725 and 745 is approximately zero, and the average amplitude of the notch signal 710 at times 735 and 755 is approximately zero. Advantageously, filter circuit system 255 attenuates the notch signal 710 in response to averaging the oversampled samples at times 725, 735, 745, and 755.

[0113] At time 760, the filter circuit system 260 averages the oversampled samples of the second channel accumulated at times 730, 740, 750, and 760. Advantageously, the average amplitude of the notch signal 710 at times 730 and 750 is approximately zero, and the average amplitude of the notch signal 710 at times 740 and 760 is approximately zero. Advantageously, the filter circuit system 260 attenuates the notch signal 710 in response to averaging the oversampled samples at times 730, 740, 750, and 760.

[0114] At the ninth time 765, the filter circuit system 255 accumulates another oversampled sample from the first channel. However, at the ninth time 765, the filter circuit system averages the oversampled samples from the first channel accumulated at times 735, 745, 755, and 765. This type of averaging is called a moving average or windowing. At the ninth time 765, the filter circuit system 255 provides another filtered output. Advantageously, after a time delay between times 725 and 760, the notch filter circuit system 140 provides another filtered output for each conversion cycle.

[0115] exist Figure 7 In the example, a line cycle occurs between times 725 and 765. The line cycle is the period of the notch signal 710. During subsequent sampling operations, sampling occurs periodically at times 725, 730, 735, 740, 745, 750, 755, and 760. Although in Figure 7 In one example, the averaging circuitry 320 averages four oversampled samples, but in other examples, it can average any number of oversampled samples. In such alternative examples, the conversion period can be modified to reflect any number of oversampled samples. Furthermore, in some examples, the filter delay is modified to prevent filter circuitry 255, 260, 265 from averaging oversampled samples corresponding to zero-crossing of the notch signal 710. Advantageously, ensuring that oversampled sample averaging occurs at non-zero-crossing points can improve the filtering performance of the notch filter circuitry 140.

[0116] Figure 8 At notch frequency Figure 7Example notch signal 710 is filtered. Figure 2 and 3 Timing diagram 800 for example operation of the plurality of example filter circuit systems 255, 260, 265, 300. Figure 8 In the example, timing diagram 800 shows a first conversion cycle 805, a second conversion cycle 810, a third conversion cycle 815, a line cycle 820, and a fourth conversion cycle 825. Conversion cycles 805, 810, 815, and 825 represent the transitions from... Figure 6 The conversion cycle starting at box 630 corresponds to equation (3). The line cycle period 820 represents the period of the notch signal 710. The line cycle period 820 can be found using equation (2).

[0117] The example conversion periods 805, 810, 815, and 825 include an example filter delay 830, a first example oversampled sample 835, a second example oversampled sample 840, a third example oversampled sample 845, and a fourth example oversampled sample 850. In the example operation, the filter delay 830 represents the transition from... Figure 6 The filter delay starting at box 640 corresponds to equation (4). The filter delay 830 aligns with the oversampled samples 835, 840, 845, and 850 of the conversion periods 805, 810, 815, and 825. Figure 8 In the example, Figure 2 The filter circuit systems 255, 260, and 265 include Figure 3 Example stabilization circuit system 310. In this example, stabilization circuit system 310 allows oversampled samples to be stabilized by removing oversampled samples 835, 840, 845. In this example operation, Figure 3 The averaging circuitry 320 averages the oversampled sample 850, which is the fourth oversampled sample of the conversion period 805. Alternatively, in some examples without stabilization circuitry 310, the filter delay 830 or OSR of the decimation filter circuitry 205 can be modified to provide the oversampled sample 850. Advantageously, stabilization circuitry 310 allows the sampled values ​​to be stabilized before the notch signal 710 is filtered.

[0118] Figure 9 Is it constructed to be executed or instantiated? Figure 4 and 6 One or more of the example machine-readable instructions or example operations are used to implement Figure 2 and 5 The controller circuit system 270 or more generally Figure 1 and 2This is a block diagram of an example programmable circuit system platform 900, comprising one or a combination of notch filter circuitry 140. For example, the programmable circuit system platform 900 may be a server, personal computer, workstation, self-learning machine (e.g., neural network), or mobile device (e.g., mobile phone, smartphone, such as iPad). TM Tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices or any other type of computing or electronic device.

[0119] The programmable circuit system platform 900 shown in the example includes a programmable circuit system 912. The programmable circuit system 912 shown in the example is hardware. For example, the programmable circuit system 912 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuit system 912 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 912 is implemented... Figure 2 and 5 The controller circuit system 270.

[0120] The programmable circuit system 912 of the illustrated example includes local memory 913 (e.g., cache, registers, etc.). The programmable circuit system 912 of the illustrated example communicates with main memories 914 and 916 via bus 918, the main memories comprising volatile memory 914 and non-volatile memory 916. Volatile memory 914 may be implemented by one or more synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), or any other type of RAM device. Non-volatile memory 916 may be implemented by flash memory or one or a combination of any other desired type of memory device. Access to the main memories 914 and 916 of the illustrated example is controlled by a memory controller 917. In some examples, the memory controller 917 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry for managing data flow to and from the main memories 914 and 916.

[0121] The programmable circuit system platform 900 shown in the example also includes an interface circuit system 920. The interface circuit system 920 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect High Speed ​​(PCIe) interface.

[0122] In the illustrated example, one or more input devices 922 are connected to the interface circuitry system 920. The input devices 922 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry system 912. The input devices 922 may be implemented as one or a combination of, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, a contour point device, or a voice recognition system.

[0123] One or more output devices 924 are also connected to the interface circuit system 920 of the illustrated example. The output devices 924 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuit system 920 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuit system such as a GPU.

[0124] The interface circuit system 920 of the example shown also includes communication devices, such as one or a combination of a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 926. Communication can be carried out via, for example, Ethernet connection, digital subscriber line (DSL) connection, telephone line connection, coaxial cable system, satellite system, line-of-sight wireless system, line-of-sight wireless system, cellular telephone system, optical connection, etc.

[0125] The programmable circuit system platform 900 shown in the example also includes one or more mass storage disks or devices 928 for storing firmware, software, or data. Examples of such mass storage disks or devices 928 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices such as flash memory devices and SSDs.

[0126] can be Figure 4 and 6The machine-readable instructions 932 implemented by the machine-readable instructions can be stored in one or a combination of a mass storage device 928, a volatile memory 914, a non-volatile memory 916, or at least a removable, non-transitory computer-readable storage medium such as a CD or DVD.

[0127] Figure 10 yes Figure 9 A block diagram of an example implementation of the programmable circuit system 912. In this example, Figure 9 The programmable circuit system 912 is implemented via a microprocessor 1000. For example, the microprocessor 1000 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit system). The microprocessor 1000 executes... Figure 4 and 6 Some or all of the machine-readable instructions in the flowchart are used to... Figure 5 The circuit system is effectively instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such examples, Figure 2 and 5 The circuit system is instantiated through the hardware circuitry of the microprocessor 1000 combined with machine-readable instructions. For example, the microprocessor 1000 can be implemented using a multi-core hardware circuitry system, such as a CPU, DSP, GPU, XPU, etc. This example microprocessor 1000 is a multi-core semiconductor device containing N cores, but it can contain any number of example cores 1002 (e.g., one core). The cores 1002 of the microprocessor 1000 can operate independently or in combination to execute machine-readable instructions. For example, machine code corresponding to firmware, built-in software programs, or software programs can be executed by one of the cores 1002, or by multiple cores 1002 at the same or different times. In some examples, the machine code corresponding to firmware, built-in software programs, or software programs is divided into threads and executed in parallel by two or more cores 1002. The software program can correspond to... Figure 4 and 6 A flowchart represents part or all of machine-readable instructions or operations.

[0128] Core 1002 can communicate via a first example bus 1004. In some examples, the first bus 1004 can be implemented as a communication bus to enable communication with one or more associated devices in core 1002. For example, the first bus 1004 can be implemented as at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Alternatively, the first bus 1004 can be implemented as any other type of computing or electrical bus. Core 1002 can receive data, instructions, and signals from one or more external devices via example interface circuitry 1006. Core 1002 can output data, instructions, and signals to said one or more external devices via interface circuitry 1006. Although the core 1002 of this example includes example local memory 1020 (e.g., a Level 1 (L1) cache that can be partitioned into an L1 data cache and an L1 instruction cache), the microprocessor 1000 also includes example shared memory 1010 that can be shared by the cores (e.g., a Level 2 (L2) cache) to enable high-speed access to data and instructions. Data and instructions can be transferred (e.g., shared) by performing one or a combination of writing to or reading from shared memory 1010. The local memory 1020 and shared memory 1010 of each core 1002 can be cache memory and main memory containing multiple levels (e.g., Figure 9 The cache is part of the memory device hierarchy (914, 916) of the main memory. Generally, higher-level memories in the hierarchy have lower access times and smaller storage capacities compared to lower-level memories. Variations in the various levels of the cache hierarchy are managed by cache coherence policies (e.g., coordination).

[0129] Each core 1002 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuit system. Each core 1002 includes a control unit circuit system 1014, an arithmetic and logic (AL) circuit system (sometimes called an ALU) 1016, multiple registers 1018, local memory 1020, and a second example bus 1022. Other structures may exist. For example, each core 1002 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating-point unit (FPU) circuit system, etc. The control unit circuit system 1014 includes semiconductor-based circuitry configured to control (e.g., coordinate) the movement of data within the corresponding core 1002. The AL circuit system 1016 includes semiconductor-based circuitry configured to perform one or more mathematical or logical operations on the data within the corresponding core 1002. Some examples of the AL circuit system 1016 perform integer-based operations. In other examples, the AL circuit system 1016 also performs floating-point operations. In other examples, the AL circuit system 1016 may include a first AL circuit system that performs integer-based operations and a second AL circuit system that performs floating-point operations. In some examples, the AL circuit system 1016 may be referred to as an arithmetic logic unit (ALU).

[0130] Register 1018 is a semiconductor-based structure used to store data and instructions, such as the results of one or more operations performed by the AL circuit system 1016 corresponding to core 1002. For example, register 1018 may contain vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 1018 can be as follows: Figure 10 The diagram shows a memory bank arrangement. Alternatively, register 1018 can be organized in any other arrangement, format, or structure, for example, by distributing it throughout core 1002 to reduce access time. The second bus 1022 can be implemented using at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0131] Each core 1002 or more generally, the microprocessor 1000 may include additional or alternative structures to the structures shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stops (CMS), one or more shifters (e.g., barrel shifters) or other circuitry may be present. The microprocessor 1000 is manufactured as a semiconductor device containing a plurality of transistors interconnected to implement the structures described above in one or more integrated circuit systems (ICs) contained in one or more packages.

[0132] Microprocessor 1000 may include or work in conjunction with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented via logic circuitry to perform specific tasks faster and more efficiently than a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, or other programmable devices may also be accelerators. Accelerators may be on microprocessor 1000, in the same chip package as microprocessor 1000, or in one or more separate packages from microprocessor 1000.

[0133] Figure 11 yes Figure 9 A block diagram of another example implementation of the programmable circuit system 912. In this example, the programmable circuit system 912 is implemented via an FPGA circuit system 1100. For example, the FPGA circuit system 1100 can be implemented via an FPGA. The FPGA circuit system 1100 can be used, for example, to execute instructions that would otherwise be executed by a machine that executes corresponding machine-readable instructions. Figure 10 The example microprocessor 1000 performs the operations. However, once configured, the FPGA circuit system 1100 instantiates operations and functions corresponding to machine-readable instructions in hardware, thus typically performing operations / functions much faster than if they could be executed by a general-purpose microprocessor executing the corresponding software.

[0134] More specifically, compared to what was described above Figure 10 The microprocessor 1000 (which is a general-purpose device that can be programmed to execute commands) is a microprocessor that is a general-purpose device that can be programmed to execute commands. Figure 4 and 6 The flowchart represents some or all of the machine-readable instructions, but once manufactured, its interconnections and logic circuitry are fixed. Figure 11 The example FPGA circuit system 1100 includes interconnect and logic circuit systems, which can be configured, constructed, programmed, and interconnected in different ways after manufacturing, one or a combination thereof, to instantiate, for example, with... Figure 4 and 6The flowchart represents some or all of the machine-readable instructions corresponding to the operations / functions. Specifically, the FPGA circuit system 1100 can be viewed as an array of logic gates, interconnects, and switches. Switches can be programmed to change the way logic gates are interconnected via interconnects, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit system 1100 is reprogrammed). The configured logic circuits enable logic gates to cooperate in different ways to perform different operations on data received from the input circuit system. Those operations can correspond to... Figure 4 and 6 The flowchart represents some or all of the instructions (e.g., software and / or firmware). Therefore, the FPGA circuit system 1100 can be configured or constructed in at least one way to interact with... Figure 4 and 6 The flowchart's machine-readable instructions correspond to some or all of the operations / functions, which are effectively instantiated into dedicated logic circuits, thereby executing the operations / functions corresponding to those software instructions in a dedicated manner similar to ASICs. Therefore, compared to a general-purpose microprocessor, the FPGA circuit system 1100 can execute operations / functions corresponding to those software instructions much faster. Figure 4 and 6 Some or all of the corresponding operations / functions in the machine-readable instructions.

[0135] exist Figure 11 In some examples, the FPGA circuit system 1100 is configured or constructed in response to being programmed (and / or reprogrammed once or multiple times) based on a binary file. In some examples, the binary file may be one or both compiled or generated based on instructions in a hardware description language (HDL), such as Lucid, VHSIC Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or programs corresponding to one or more operations / functions in HDL; the code / program may be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be converted (e.g., by a compiler, software application, etc.) into a binary file. In some examples, Figure 11 The FPGA circuit system 1100 can perform at least one of binary file access or loading, enabling Figure 11 The FPGA circuit system 1100 is configured or constructed to perform at least one of the said one or more operations / functions. For example, the binary file can be transmitted via a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or data that can be transmitted via a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), or data that can be transmitted via a bit stream (e.g., computer-readable data, machine-readable data, etc.). Figure 11 The FPGA circuit system 1100 accesses one or a combination of machine-readable instructions to implement [the following]. Figure 11At least one of the FPGA circuit system 1100 or a portion thereof is configured or constructed.

[0136] In some examples, the binary file can be compiled, generated, transformed, or otherwise output from at least one of the uniform software platform outputs for FPGA programming. For example, the uniform software platform can translate first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to said one or more operations / functions in HDL. In some such examples, the binary file is compiled, generated, or otherwise output from at least one of the uniform software platform outputs based on the second instructions. In some examples, Figure 11 The FPGA circuit system 1100 can perform at least one of binary file access or loading, enabling Figure 11 The FPGA circuit system 1100 is capable of being configured or constructed to perform at least one of the said operations / functions. For example, binary files can be transmitted via bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or data that can be transmitted via bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), or data that can be transmitted via bit streams (e.g., computer-readable data, machine-readable data, etc.). Figure 11 The FPGA circuit system 1100 accesses one or a combination of machine-readable instructions to implement, in order to Figure 11 At least one of the FPGA circuit system 1100 or a portion thereof is configured or constructed.

[0137] Figure 11 The FPGA circuit system 1100 includes an example input / output (I / O) circuit system 1102 for receiving data or outputting data to at least one of the example configuration circuit system 1104 or external hardware 1106. For example, the configuration circuit system 1104 may be implemented via an interface circuit system capable of receiving binary files, which may be implemented via one or more bitstreams, data, or machine-readable instructions to configure the FPGA circuit system 1100 or portions thereof. In some such examples, the configuration circuit system 1104 may receive binary files from one or more of a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement artificial intelligence / machine learning (AI / ML) models to generate binary files, or any combination thereof). In some examples, the external hardware 1106 may be implemented via an external hardware circuit system. For example, the external hardware 1106 may be implemented via... Figure 10 The microprocessor 1000 is implemented.

[0138] The FPGA circuit system 1100 also includes an array of example logic gate circuit systems 1108, multiple example configurable interconnects 1110, and example memory circuit systems 1112. The logic gate circuit system 1108 and the configurable interconnects 1110 are configurable to instantiate corresponding to... Figure 4 and 6 One or more operations / functions and / or other desired operations are provided by at least some machine-readable instructions. Figure 11 The logic gate system 1108 shown is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures configurable into logic circuits. In some examples, the electrical structures contain logic gates (e.g., AND gates, OR gates, Nor gates, etc.) that provide basic building blocks for the logic circuits. Electrically controlled switches (e.g., transistors) are present in each of the logic gate system 1108 to enable the configuration of one or a combination of electrical structures or logic gates, thereby forming a circuit to perform the desired operation / function. The logic gate system 1108 may contain other electrical structures, such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0139] The configurable interconnect 1110 of the example shown is a conductive path, trace, via, etc., that may contain electrically controlled switches (e.g., transistors), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit system 1108 to program the desired logic circuit.

[0140] The storage circuitry system 1112 shown in the example is configured to store the results of one or more operations performed by corresponding logic gates. The storage circuitry system 1112 may be implemented using registers, etc. In the example shown, the storage circuitry system 1112 is distributed within the logic gate circuitry system 1108 to facilitate access and improve execution speed.

[0141] Figure 11 The example FPGA circuit system 1100 also includes an example dedicated operating circuit system 1114. In this example, the dedicated operating circuit system 1114 includes a dedicated circuit system 1116, which can be invoked to implement common functions, eliminating the need for field programming of these functions. Examples of such dedicated circuit systems 1116 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory and multiplier-accumulator circuit systems. Other types of dedicated circuit systems may be present. In some examples, the FPGA circuit system 1100 may also include an example general-purpose programmable circuit system 1118, such as an example CPU 1120 or an example DSP 1122. Other general-purpose programmable circuit systems 1118, such as GPUs, XPUs, etc., may also be present, either additionally or alternatively.

[0142] although Figure 10 and 11 It shows Figure 9 Two example implementations of the programmable circuit system 912 are provided, but many other approaches are considered. For example, the FPGA circuit system may include an onboard CPU, such as... Figure 10 One or more of the example CPUs 1120. Therefore, Figure 9 The programmable circuit system 912 can also be combined with at least Figure 10 Example microprocessor 1000 and Figure 11 Example FPGA circuit system 1100 implementation. In some such hybrid examples, Figure 10 One or more cores of 1002 can execute by Figure 4 and 6 The flowchart represents the first part of machine-readable instructions to perform a first operation / function. Figure 11 The FPGA circuit system 1100 can be configured or constructed to perform actions corresponding to those performed by the FPGA circuit system 1100. Figure 4 and 6 The flowchart represents the second operation / function of the second part of the machine-readable instructions, and / or the ASIC can be configured or constructed to perform at least one of the operations corresponding to those performed by the ASIC. Figure 4 and 6 The flowchart represents the third operation / function of the third part of the machine-readable instruction.

[0143] therefore, Figure 5 Some or all of the circuit systems can be instantiated at the same or different times. For example, Figure 10 The same and / or different parts of the microprocessor 1000 can be programmed to execute machine-readable instructions at the same and / or different times. In some examples, Figure 11 At least one of the same and / or different parts of the FPGA circuit system 1100 can be configured or constructed to perform the operation / function corresponding to the part of the machine-readable instructions at the same and / or different times.

[0144] In some examples, Figure 5 Some or all of the circuit system can be instantiated, for example, in one or more threads that execute simultaneously and / or sequentially. For example, Figure 10 The microprocessor 1000 can execute machine-readable instructions in one or more threads that execute simultaneously and / or sequentially. In some examples, Figure 11 The FPGA circuit system 1100 can be configured or constructed to perform at least one operation / function simultaneously and / or sequentially. Furthermore, in some examples, Figure 5 Some or all of the circuit systems can be in Figure 10 An implementation within one or more virtual machines or containers that runs on a microprocessor 1000.

[0145] In some examples, Figure 9 The programmable circuit system 912 can be housed in one or more packages. For example, Figure 10 microprocessor 1000 or Figure 11 At least one of the FPGA circuitry systems 1100 can be housed in one or more packages. In some examples, the XPU can be housed in one or more packages. Figure 9 The programmable circuit system 912 is implemented. For example, the XPU can be contained within a packaged CPU (e.g., Figure 10 microprocessor 1000, Figure 11 CPU 1120, etc.), and DSP in another package (e.g., Figure 11 DSP 1122), GPU in another package, and FPGA in yet another package (e.g., Figure 11 FPGA circuit system 1100).

[0146] Despite Figure 5 The implementation is shown in the figure. Figure 2 The example method of the controller circuit system 270, but Figure 5 One or more of the elements, processes, or apparatuses shown may be combined, divided, rearranged, omitted, removed, or implemented in any other way. Furthermore, Figure 2 and 5 Example controller circuit system 270 or more generally Figure 1 and 2 The notch filter circuit system 140 can be implemented solely in hardware or through a combination of hardware, software, and firmware. Therefore, for example, Figure 2 and 5 The controller circuit system 270 or more generally Figure 1 and 2 Any component in the notch filter circuit system 140 can be implemented using a programmable circuit system in conjunction with one or more machine-readable instructions (e.g., firmware or software), a processor circuit system, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), or a field-programmable logic device (FPLD) such as an FPGA. Furthermore, Figure 2 and 5 Example controller circuit system 270 or more generally Figure 1 and 2 The notch filter circuit system 140 may include one or more components, processes or devices as... Figure 2and 5 The elements, processes, and apparatus shown may be supplements or alternatives to those shown, or may include more than one of any or all of the shown elements, processes, and apparatus.

[0147] This indicates that it can be executed by a programmable circuit system to control... Figure 2 and 5 The controller circuit system 270 or more generally Figure 1 and 2 At least one example machine-readable instruction or representation of the notch filter circuit system 140 implemented or instantiated may be executed by a programmable circuit system to perform on the notch filter circuit system 140. Figure 2 and 5 The controller circuit system 270 or more generally Figure 1 and 2 A flowchart illustrating example operations of at least one of the implementations or instantiations of the notch filter circuit system 140 is shown in Figure 4 and 6 As shown below. Machine-readable instructions can be one or more executable programs or portions thereof, for example, in conjunction with the following. Figure 9 The programmable circuit system 912 shown in the example processor platform 900 described herein is executed by the programmable circuit system and may be implemented by the programmable circuit system described below. Figure 10 Or, as described in example 11, a programmable circuit system (e.g., an FPGA) performs one or more functions or portions of functions. In some examples, machine-readable instructions enable operations, tasks, etc., to be performed or executed automatically in the real world. As used herein, “automatic” means without human intervention.

[0148] The program may be embodied as instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage device or disk (e.g., floppy disk, hard disk drive (HDD) etc.), optical storage device or disk (e.g., Blu-ray disc, optical disc (CD), digital versatile optical disc (DVD) etc.), redundant array of independent disks (RAID), registers, ROM, solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory etc.), volatile memory (e.g., random access memory (RAM) of any type etc.), or any other storage device or disk. The instructions on the non-transitory computer-readable and / or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated or embodied in one or more hardware devices other than a programmable circuit system. Machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices can be implemented by end-user client hardware devices (e.g., hardware devices associated with human and / or machine users) or by an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that facilitates communication between server and end-user client hardware devices. Similarly, non-transitory computer-readable storage media can contain one or more media. Furthermore, although the example programs are for reference only... Figure 4 and 6 The flowchart shown illustrates the implementation, but many other implementations are alternatively available. Figure 2 and 5 Example controller circuit system 270 or more generally Figure 1 and 2The method of the notch filter circuit system 140. For example, the execution order of the flowchart blocks can be changed, or some of the described blocks can be changed, removed, or combined. Alternatively or additionally, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete, integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware. The programmable circuit system can be distributed across different network locations or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuit system can be one or a combination of the following: a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., or any combination thereof.

[0149] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and packaged format. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., as parts of instructions, code, code representations, etc.), which can be used to create, manufacture, or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located in the same or different locations (e.g., cloud, edge devices, etc.) within a network or network set. Machine-readable instructions may require one or more of the following processes: installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., so that they can be directly read, interpreted, or executed by computing devices or other machines. For example, machine-readable instructions may be stored in multiple parts, which may be individually compressed, encrypted, or stored on separate computing devices, wherein, upon decryption, decompression, or combination, these parts form a set of computer-executable or machine-executable instructions that perform one or more functions or operations, which may together form a program, as described herein.

[0150] In another example, machine-readable instructions may be stored in a state that can be read by a programmable circuit system, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the machine-readable instructions on a particular computing device or another device. In yet another example, machine-readable instructions may need to be configured (e.g., storing settings, input data, recording network addresses, etc.) before the machine-readable instructions or their corresponding programs can be executed, in whole or in part. Therefore, as used herein, machine-readable, computer-readable, or machine-readable media may contain one or a combination of instructions or programs, regardless of the particular format or state of the machine-readable instructions or programs.

[0151] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C-Sharp, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0152] As mentioned above, Figure 4 and 6Example operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device or disk, excluding propagation signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk in which information is stored for any duration (e.g., extended time period, permanent, transient, for temporary buffering, for caching information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware designed to retain information for a period of time, excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include one or a combination of any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of mechanical, electromechanical, or electrical equipment, hardware, or circuitry, which may or may not be configured to execute computer-readable instructions, machine-readable instructions, etc., or may or may not be manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0153] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., including, comprising, including, having, etc.) in the preamble or in any kind of claim statement, additional elements, items, etc., may be present without falling outside the scope of the corresponding claim or statement. As used herein, for example, when the phrase "at least" is used as a transitional term in the preamble of a claim, it is open-ended, just as the terms "comprising" and "including" are open-ended. When used in the form of, for example, A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0154] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude plurals. As used herein, the term "a / an" refers to one or more of the stated objects. The terms "a / an", "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that the combination of features is unfeasible and / or disadvantageous.

[0155] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the Earth. The first part is above the second part if the second part has at least one section between the Earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the Earth than the second part. As mentioned above, the first part can be above or below the second part, where one or more of the following exist: there are other parts between them, there are no other parts between them, the first and second parts are in contact, or the first and second parts are in direct contact with each other.

[0156] As used in such a patent, stating that any part (e.g., layer, film, region, area, or plate) is located on another part in any way (e.g., positioned on it, located on it, placed on it, or formed on it, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0157] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate member between at least one of the referenced elements in a relative movement between the connection reference or elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected or fixed to each other. As used herein, the statement that any part is in “contact” with another part is defined to mean that there is no intermediate portion between the two parts.

[0158] Unless otherwise specifically stated, descriptors such as “first,” “second,” and “third” are used herein without any meaning that indicates priority, physical order, arrangement in a list, or sorting, but merely as labels or at least one of any names to distinguish elements in order to facilitate understanding of the described examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in the claims by different descriptors (such as “second” or “third”). In such cases, such descriptors are used only to clearly identify these elements in the context of the discussion (as in the claims), for example, where these elements may otherwise share the same name.

[0159] As used herein, “approximately” and “about” modify their objects / values ​​to identify variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified, “approximately” and “about” may indicate that these dimensions are within a tolerance of + / - 10%.

[0160] As used herein, the phrase “communication” includes variations thereof, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and not requiring direct physical (e.g., wired) communication or constant communication, but also including selective communication carried out at at least one of periodic intervals, predetermined intervals, non-periodic intervals or one-off events.

[0161] As used herein, a “programmable circuit system” is defined to include at least one of the following: (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) configured to perform a particular operation and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that are programmable to perform one or more particular functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as a central processing unit (CPU) capable of executing first instructions to perform one or more operations or functions; an FPGA programmable with second instructions that enable a field-programmable gate array (FPGA) to be configured and / or constructed to instantiate one or more operations or functions corresponding to the first instructions; a graphics processing unit (GPU) capable of executing first instructions to perform one or more operations or functions; a digital signal processor (DSP) capable of executing first instructions to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers capable of executing first instructions to perform one or more operations or functions; or integrated circuits, such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented in a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., or any combination thereof) and orchestration techniques (e.g., application programming interfaces (APIs)) that can assign computational tasks to programmable circuit systems of suitable type that can perform computational tasks.

[0162] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupled with multiple circuit elements, system-on-a-chip (SoC), etc.

[0163] In this specification, the term "coupled" may cover a connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by the control signal generated by device A.

[0164] A device “configured” to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform the function and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Such configuration may be achieved through at least one of the device’s firmware or software programming, through at least one of the device’s hardware components and interconnects’ construction or layout, or through a combination thereof.

[0165] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless explicitly stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0166] In the specification and claims, the described "circuit system" may comprise one or more circuits. A circuit or device described herein as containing certain components can actually be used to couple to those components to form the described circuit system or device. For example, a structure described as comprising one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage and / or current sources) can actually comprise only a semiconductor element within a single physical device (e.g., at least one in a semiconductor die or integrated circuit (IC) package) and can be used, during or after manufacturing, for example by at least one of an end user or a third party, to couple to at least some of the passive elements or sources to form the described structure.

[0167] The circuits described herein can be reconfigured to include the replaced components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some components in the described examples are included in the integrated circuit, and other components are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as outside the integrated circuit may be included in the integrated circuit, and some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are at least one of the following: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0168] The use of the phrase “ground” in the above description includes at least one of the following: chassis ground, earth, floating ground, virtual ground, digital ground, public ground, or any other form of ground connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates a difference of + / -10% from said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0169] Within the scope of the claims, the described embodiments may be modified, and other embodiments are possible.

Claims

1. An apparatus comprising: A decimation filter circuit system that has an output; A multiplexer circuit system having an input, a first output, and a second output, wherein the input of the multiplexer circuit system is coupled to the output of the decimation filter circuit system; A first delay circuit system has an input and an output, wherein the input of the first delay circuit system is coupled to the first output of the multiplexer circuit system; A first filter circuit system having an input coupled to the output of the first delay circuit system; A second delay circuit system having an input and an output, wherein the input of the second delay circuit system is coupled to the second output of the multiplexer circuit system; as well as A second filter circuit system having an input coupled to the output of the second delay circuit system.

2. The device of claim 1, wherein the first filter circuit system includes an averaging circuit system having an input coupled to the output of the first delay circuit system.

3. The device according to claim 2, wherein the multiplexer circuit system is a first multiplexer circuit system, the averaging circuit system is a first averaging circuit system, the first averaging circuit system further has an output, and the first filter circuit system further comprises: A second multiplexer circuit system has an input, a first output, and a second output, wherein the input of the second multiplexer circuit system is coupled to the output of the first averaging circuit system; and The second averaging circuit system has an input coupled to the first output of the second multiplexer circuit system.

4. The device of claim 3, wherein the second averaging circuit system further has an output, and the first filter circuit system further includes a third averaging circuit system having an input and an output, the input of the third averaging circuit system being coupled to the output of the second averaging circuit system, and the output of the third averaging circuit system being coupled to the second output of the second multiplexer circuit system.

5. The device of claim 3, wherein the second multiplexer circuit system further has a control input, the first averaging circuit system further has a control input, and the first filter circuit system further comprises: A sample counting circuit system having an output coupled to the control input of the first averaging circuit system; and A mode circuit system having an output coupled to the control input of the second multiplexer circuit system.

6. The device according to claim 1, further comprising: An offset calibration circuit system having an input and an output, wherein the input of the offset calibration circuit system is coupled to the output of the decimation filter circuit system; A gain calibration circuit system having an input and an output, wherein the input of the gain calibration circuit system is coupled to the output of the offset calibration circuit system; as well as A clipping circuit system having an input and an output, the input of the clipping circuit system being coupled to the output of the gain calibration circuit system, and the output of the clipping circuit system being coupled to the input of the multiplexer circuit system.

7. The device of claim 1, wherein the decimation filter circuit system further has an input, the multiplexer circuit system further has a control input, and the device further comprises: An oversampling rate OSR circuit system having an output coupled to the input of the decimation filter circuit system; as well as A channel control circuit system having an output coupled to the control input of the multiplexer circuit system.

8. The device of claim 1, wherein the decimation filter circuit system further has an input, and the device further includes an analog-to-digital converter (ADC) having an output coupled to the input of the decimation filter circuit system.

9. The device of claim 8, wherein the multiplexer circuit system is a first multiplexer circuit system, the first filter circuit system further has an output, the second filter circuit system has an output, the ADC further has an input, and the device further comprises: A second multiplexer circuit system having a control input and an output, wherein the output of the second multiplexer circuit system is coupled to the input of the ADC; as well as A buffer circuit system having a first input, a second input, and an output, wherein the first input of the buffer circuit system is coupled to the output of a first filter circuit system, the second input of the buffer circuit system is coupled to the output of a second filter circuit system, and the output of the buffer circuit system is coupled to the control input of a second multiplexer circuit system.

10. An apparatus comprising: An analog-to-digital converter (ADC) with an output; A decimation filter circuit system having an input and an output, wherein the input of the decimation filter circuit system is coupled to the output of the ADC; A multiplexer circuit system having an input, a first output, and a second output, wherein the input of the multiplexer circuit system is coupled to the output of the decimation filter circuit system; A first filter circuit system having an input coupled to the first output of the multiplexer circuit system; as well as The second filter circuit system has an input coupled to the second output of the multiplexer circuit system.

11. The device according to claim 10, further comprising: A first delay circuit system has an input and an output, the input of the first delay circuit system being coupled to the first output of the multiplexer circuit system, and the output of the first delay circuit system being coupled to the input of the first filter circuit system; as well as A second delay circuit system has an input and an output, the input of the second delay circuit system being coupled to the second output of the multiplexer circuit system, and the output of the second delay circuit system being coupled to the input of the second filter circuit system.

12. The device of claim 10, wherein the first filter circuit system comprises: A stabilizing circuit system having an input and an output, the input of the stabilizing circuit system being coupled to the first output of the multiplexer circuit system; and An averaging circuit system having an input coupled to the output of the stable circuit system.

13. The device of claim 12, wherein the multiplexer circuit system is a first multiplexer circuit system, the averaging circuit system is a first averaging circuit system, the first averaging circuit system further has an output, and the first filter circuit system further comprises: A second multiplexer circuit system has an input, a first output, and a second output, wherein the input of the second multiplexer circuit system is coupled to the output of the first averaging circuit system. A second averaging circuit system has an input and an output, wherein the input of the second averaging circuit system is coupled to the first output of the second multiplexer circuit system. as well as A third averaging circuit system has an input and an output, wherein the input of the third averaging circuit system is coupled to the output of the second averaging circuit system, and the output of the third averaging circuit system is coupled to the second output of the second multiplexer circuit system.

14. The apparatus of claim 10, further comprising: An offset calibration circuit system having an input and an output, wherein the input of the offset calibration circuit system is coupled to the output of the decimation filter circuit system; A gain calibration circuit system having an input and an output, wherein the input of the gain calibration circuit system is coupled to the output of the offset calibration circuit system; as well as A clipping circuit system having an input and an output, the input of the clipping circuit system being coupled to the output of the gain calibration circuit system, and the output of the clipping circuit system being coupled to the input of the multiplexer circuit system.

15. The device of claim 10, wherein the decimation filter circuit system further has a control input, the multiplexer circuit system further has a control input, and the device further comprises: An oversampling rate OSR circuit system having an output coupled to the control input of the decimation filter circuit system; as well as A channel control circuit system having an output coupled to the control input of the multiplexer circuit system.

16. The device of claim 10, wherein the ADC further has an input, the multiplexer circuit system is a first multiplexer circuit system, the first filter circuit system further has an output, the second filter circuit system further has an output, and the device further comprises: A second multiplexer circuit system having a control input and an output, wherein the output of the second multiplexer circuit system is coupled to the input of the ADC; as well as A buffer circuit system having a first input, a second input, and an output, wherein the first input of the buffer circuit system is coupled to the output of a first filter circuit system, the second input of the buffer circuit system is coupled to the output of a second filter circuit system, and the output of the buffer circuit system is coupled to the control input of a second multiplexer circuit system.

17. An apparatus comprising: A multiplexer circuit system having a first output and a second output; A first delay circuit system having an input and an output, the input of the first delay circuit system being coupled to the first output of the multiplexer circuit system, the first delay circuit system being configured to delay a signal by a filter delay, the filter delay being based on the number of filter circuit systems, the notch frequency and the oversampling rate; A second delay circuit system having an input and an output, the input of the second delay circuit system being coupled to the second output of the multiplexer circuit system, the second delay circuit system being configured to delay the signal by the filter delay; A first filter circuit system having an input coupled to the output of the first delay circuit system; as well as A second filter circuit system having an input coupled to the output of the second delay circuit system.

18. The device of claim 17, wherein the multiplexer circuit system is configured to cycle between the first filter circuit system and the second filter circuit system based on a switching period, the switching period being a line cycle period divided by the number of filter circuit systems, the line cycle period being the period of the notch frequency.

19. The device of claim 17, wherein the first filter circuit system is configured to average a plurality of samples from the first delay circuit system over a cross-line cycle period, the plurality of samples being separated by a line cycle period, the line cycle period being the period of the notch frequency.

20. The device of claim 17, wherein the first filter circuit system is configured to attenuate the signal at the notch frequency.

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