A method of pulse shaping based on a superconducting nanowire single-photon imager

Abstract

A pulse shaping method based on a superconducting nanowire single-photon imager (SNSPI) is proposed. The SNSPI outputs a pair of positive and negative 100µV weak pulses. The positive pulse is input to a low-noise amplifier (LNA) at a 40K cryogenic environment to improve the signal-to-noise ratio. The LNA output signal is split into three paths by a power divider. One path is input to a latch comparator at a 40K cryogenic environment to capture the precise timing of the original signal for calibration. The other two paths are input to dual-channel RC integrator comparators at a 300K ambient temperature environment to cancel clutter and broaden the pulse. The two paths are combined to generate a stepped wave, which is then input to a comparator, normalized into a square wave, and input to the latch enable port of the latch comparator via an attenuator. The output is an LVDS level signal, which is input to the subsequent FPGA and TDC circuits. The negative pulse processing principle is similar; an inverter is added after the LNA to ensure the polarity of the two pulses is consistent, making it suitable for subsequent integration and combining.

Description

Technical Field

[0001] This invention belongs to the field of single-photon imaging technology of superconducting nanowires, specifically relating to a pulse shaping technique. Background Technology

[0002] Traditional imaging techniques rely on light intensity integration, which leads to imaging failure due to noise interference when the photon count decreases to the single-photon level. Single-photon imaging, on the other hand, detects only one photon per pixel, capturing the spatiotemporal information carried by that single photon. Algorithms are then used to reconstruct the target's three-dimensional information, enabling image reconstruction in extremely low-light scenarios. This technology overcomes the sensitivity limits of traditional imaging techniques, solving imaging problems in low-light, scattering medium-blocked, and long-distance transmission scenarios, and holds value in cutting-edge fields such as quantum information processing, biological fluorescence imaging, and deep space exploration.

[0003] Superconducting nanowire single-photon detectors (SNSPDs) exhibit broad-spectrum response characteristics, with detection efficiency >90%, dark count rate <1Hz, and timing jitter <10ps, demonstrating optimal overall performance. Traditional SNSPD arrays require complex on-chip readout circuitry, which increases dramatically with array size. Furthermore, the integration of the readout module is limited in extremely low-temperature operating environments.

[0004] In 2017, Professor Karl Berggren and Zhao Qingyuan's team at MIT jointly proposed the superconducting nanowire single-photon imager (SNSPI), pioneering a single-photon imaging method that eliminates the need for on-chip readout circuitry. They designed the superconducting nanowire as a microwave transmission line structure, utilizing a high-dynamic-range inductor to construct a low-speed microwave delay link. When a photon is absorbed at a certain location on the nanowire, the local superconducting state transforms into a resistive state, exciting a pair of reverse-propagating electrical pulses. By analyzing the time difference between the arrival times of the pulses at both ends, they achieve dual readout of the photon's spatial position and arrival time. This intrinsic readout method avoids the introduction of low-temperature digital circuitry, fully preserving the low-jitter advantage of SNSPD, making it suitable for scenarios relying on photon flight time for measurement. Its core materials utilize superconducting thin films such as niobium nitride (NbN) and tungsten silicon (WSi), fabricated at the nanoscale to achieve a balance between high detection efficiency and fast response. Some devices with optimized optical cavity designs achieve detection efficiencies exceeding 50%.

[0005] SNSPI has advantages in 3D imaging in environments with strong background noise and in imaging scenarios involving scattering media penetration, but there is still room for technological improvement. The transmission line structure and nanowire fabrication of SNSPI are limited by photolithography precision, material uniformity, and the difficulty of impedance control, preventing perfect impedance matching. This results in a low effective detection area duty cycle, uncontrollable uniformity in large-area imaging, inability to effectively distinguish simultaneous arrival of multiple photons, and a multi-peak tailing phenomenon in the output response pulse. Multiple low-amplitude secondary pulses are superimposed after the main peak, with the tailing duration reaching hundreds of nanoseconds. This multi-peak tail is misinterpreted by the subsequent pulse processing circuit as the response signal of multiple independent photons, resulting in repeated counting, inaccurate photon counting, and poor timing. Summary of the Invention

[0006] To address the technical challenges of weak SNSPI signals, large-area material inhomogeneity, impedance mismatch, pulse multi-peak and tailing, and inaccurate optical counting, this invention adds a low-temperature, low-noise amplifier and a room-temperature latch comparator to the 40K low-temperature region to adapt to 0.1-1mV weak signals. It employs dual-channel RC integrators, inverters, and combiners to suppress multi-peak distortion. A closed-loop, dynamically matched waveform is formed using a microcontroller, DAC, latch comparator, and DC blocker. This eliminates the need for additional weak signal amplification modules, active level conversion chips, multi-stage shaping and filtering circuits, and manual adjustment components. It achieves integrated low-temperature processing of the original SNSPI signal, low-noise amplification, and low-jitter shaping, completely eliminating cross-temperature transmission interference between the low-temperature amplified signal and the room-temperature comparator, such as thermal noise coupling due to temperature difference, transmission line impedance abrupt changes, and signal attenuation. This reduces noise floor and time jitter, simplifying the design of cross-temperature signal links.

[0007] A superconducting nanowire single-photon imager (SNSPI) outputs a pair of positive and negative 100µV weak pulses. The positive pulse is input to a low-noise amplifier (LNA) in a 40K cryogenic environment to improve the signal-to-noise ratio. The LNA output signal is split into three paths by a power divider. One path is input to a latch comparator in a 40K cryogenic environment to capture the precise timing of the original signal for calibration. The other two paths are input to dual-channel RC integrator comparators in a 300K ambient temperature environment to cancel clutter and broaden the pulse. The two paths are combined to generate a stepped wave, which is input to the comparator, normalized into a square wave, and then input to the latch enable port of the latch comparator via an attenuator. The output is an LVDS level signal, which is converted into a TTL signal by a passive DC blocker and input to the subsequent FPGA and TDC circuits. The negative pulse processing principle is similar. An inverter is added after the low-noise amplifier (LNA) to make the polarity of the two pulses consistent, which is suitable for subsequent integration and combining.

[0008] Furthermore, one of the dual RC channels uses a small capacitance value to retain the rising edge characteristic of the pulse, while the other channel uses a large capacitance value to achieve pulse widening. The integration time constant of the small capacitance value is less than one-tenth of the original pulse width of SNSPI, and the integration time constant of the large capacitance value is greater than the original pulse width, so that the pulse widening reaches three times the integration time constant. The output voltage of the combiner is the sum of the two outputs.

[0009] Furthermore, an STM32 microcontroller is used to calibrate multiple optimal bias points for the SNSPI, controlling the dynamic discrimination level output of the DAC. The amplitude is 50% of the first step of the stepped wave, which is then input to a low-noise amplifier (LNA), a comparator, and a latch comparator to achieve closed-loop feedback and adjust the bias current of the SNSPI in real time.

[0010] Furthermore, a 50Ω impedance matching design is adopted for the entire link, and the amplification, shaping, and level conversion circuits are integrated in the SNSPI low-temperature environment to achieve integrated signal processing.

[0011] This invention employs a 40K low-temperature LNA to improve the signal-to-noise ratio, uses a dual-channel RC integral combining circuit to eliminate clutter peaks, and uses dynamic matching of bias and discrimination levels to effectively suppress multi-peak distortion and tailing caused by material inhomogeneity in SNSPI, reduce repetitive pulse counting, and achieve high counting accuracy.

[0012] Electronic pulse stretchers for industrial testing, electronic measurement, signal processing, and other applications are based on analog circuits and utilize component characteristics or simple logic control.

[0013] The first type is a passive RC integrating stretcher, which uses a resistor R and a capacitor C to form a passive integrating network. The capacitor charges and accumulates energy, converting narrow pulses into trapezoidal or triangular waves. The stretching factor is determined by the time constant τ=RC. The input pulse width must be much smaller than τ to achieve effective stretching. The output amplitude decays with the stretching factor, the RC parameters are greatly affected by temperature, and multi-peak signals are distorted due to the superposition of the integration effect, making it unsuitable for weak signals. Its simple structure makes it suitable for low-cost scenarios where waveform accuracy requirements are not high.

[0014] The second type is an active integrating stretcher, which uses an operational amplifier to construct an active integrating circuit. A feedback resistor compensates for amplitude attenuation, improving linearity and stability. The stretching factor can be precisely controlled by adjusting the input resistor or feedback capacitor.

[0015] Conventional electronic stretchers have shortcomings in extending the time domain of narrow pulses, weak signal processing, low temperature adaptation, multi-peak suppression, and programmability.

[0016] The first type of passive RC integrating stretcher requires additional amplification of weak signals, introducing noise. Its monostable multivibrator input threshold is ≥1V, making it unsuitable for direct application. This invention integrates a 40K low-temperature, low-noise amplifier (LNA) with a noise figure of only 0.1-0.5dB. It stably amplifies weak pulse signals of 0.1-1mV, improving the signal-to-noise ratio (SNR) by 5-10dB and reducing the noise floor to 13% of conventional room-temperature solutions. This provides a high-quality signal for subsequent stretching and discrimination without requiring an additional amplification link.

[0017] The first type of passive RC integrating stretcher suffers from the integral effect, leading to the superposition of clutter peaks and amplifying multi-peak distortion. This causes the monostable multi-peak trigger to erroneously fire. This invention employs a dual-channel RC integrating circuit combined with bias-discrimination level linkage control. Addressing the multi-peak tailing caused by material inhomogeneity in SNSPI devices, it reduces the repetition count rate to below 0.08% and improves the optical counting accuracy to over 99.9%.

[0018] The first passive RC integrating type pulse stretcher uses a fixed RC integration and transmission line scheme with a fixed pulse width, and the monostable multivibrator only outputs a fixed pulse width. This invention, based on the principle of RC integration time constant, achieves programmable pulse width control from 100ns to 1μs without circuit modification. It is suitable for downstream devices with different sampling rates, such as TDC and FPGA. It employs a microcontroller + DAC closed-loop control, calibrates 3-5 optimal bias points, and is applicable to NbN / MoSi materials for SNSPI, different linewidths, and a temperature range of 4K-40K.

[0019] This invention employs a 9.3GHz bandwidth latch comparator with a measured rise time of 24ps, uses full-link 50Ω impedance matching, and features a trigger window compression design, resulting in extremely low time jitter and supporting picosecond-level time measurements.

[0020] This invention uses the RC integral time constant principle to quantize the pulse width, achieving programmable pulse width control within the range of 100ns-1μs. It can be adapted to devices with different sampling rates such as TDC and FPGA without modifying the circuit, avoiding the problem of missed detection caused by the original pulse (100-200ns) being too narrow, and has strong hardware compatibility.

[0021] This invention uses a fully analog circuit, without complex algorithms, with mature component selection, standardized impedance design, and a simple, reliable, highly integrated, and low-power circuit architecture that is easy to engineer.

[0022] This invention features programmable stretching capabilities and is suitable for scenarios such as quantum key distribution, lidar, biofluorescence imaging, and multi-channel SNSPI array detection, meeting diverse needs for low bit error rate, centimeter-level ranging, single-photon time distribution acquisition, and multi-channel synchronous acquisition. Attached Figure Description

[0023] Figure 1 This is a diagram illustrating the principles of plastic surgery.

[0024] Figure 2 It shows the original waveform and its noise discrimination diagram.

[0025] Figure 3 It is a waveform regularization diagram.

[0026] Figure 4 This is the output waveform diagram. Detailed Implementation

[0027] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] The shaping principle of this invention is as follows: Figure 1 As shown, the superconducting nanowire single-photon imager (SNSPI) outputs a weak pulse signal of hundreds of microvolts. One path is input to a low-noise amplifier (LNA) in a 40K cryogenic environment to improve the signal-to-noise ratio. Its output signal is split into three paths by a power divider. One path is input to a latch comparator in a 40K cryogenic environment to capture the precise time of the original signal for calibration.

[0029] Two dual-channel RC integrators and comparators, each with a 300K ambient temperature environment input, cancel out noise and broaden the pulse. The pulses are then combined to generate a stepped wave, which is input to the comparator, normalized into a square wave, and then input to the latch enable port of the latch comparator via an attenuator. The output is an LVDS level signal, which is then input to the subsequent FPGA and TDC circuits.

[0030] This invention does not employ the existing single-channel general integrator / comparator selection technique, but instead uses a dual-channel RC integrator comparator adapted to a 300K ambient temperature environment. At the same time, it adds a combiner and an attenuator as dedicated supporting devices for pulse shaping and signal adaptation, and specifically utilizes the latch enable port of the latch comparator to achieve signal linkage.

[0031] This invention establishes dedicated parameters for 300K ambient temperature adaptation and precise dual-channel synchronous matching across the entire signal processing chain. It sets the stepped wave as a dedicated intermediate signal parameter for pulse shaping and sets attenuation adaptation parameters for the signal input to the latch comparator. This differs from existing technologies that lack environment-specific adaptation, direct processing, dual-channel synchronous parameters, intermediate state parameters for stepped wave stages, and general parameter settings without attenuation adaptation requirements.

[0032] The STM32 microcontroller is calibrated to select 3-5 optimal bias points for SNSPI, which control the dynamic discrimination level output of the DAC. The amplitude is 50% of the first step of the stepped wave. These points are then input to the low-noise amplifier (LNA), comparator, and latch comparator to achieve closed-loop feedback and adjust the bias current of SNSPI in real time.

[0033] This invention uses an STM32 microcontroller paired with a DAC, LNA, and latch comparator to construct a closed-loop link, unlike the open-loop structure of existing technologies consisting of general-purpose MCU / analog circuits and static level sources. It explicitly calibrates 3-5 optimal bias points and sets the discrimination level to 50% of the first step of the stepped wave, unlike the single bias point and fixed level amplitude of existing technologies. In particular, the newly added "multiple optimal bias point calibration" pre-process forms a complete step chain of "dynamic level output → multi-device signal processing → closed-loop real-time adjustment", which is different from the static preset and open-loop calibration process of existing technologies.

[0034] SNSPI outputs a pair of positive and negative pulses. The other path is processed in a similar way. An inverter is added after the low-noise amplifier (LNA) to make the polarity of the two pulses consistent, which is suitable for subsequent integration and combining.

[0035] The entire link adopts a 50Ω impedance matching design, and the amplification, shaping and level conversion circuits are integrated in the SNSPI low-temperature environment to achieve integrated signal processing.

[0036] Original waveform and its noise identification, such as Figure 2 As shown, the closer to the rising edge, the higher the peak-to-bottom value of the multi-peaks. If the discrimination level is lowered, the comparator will not distinguish the multi-peaks near the rising edge. If the noise floor amplitude is high, the comparator will distinguish the noise floor and output a square wave pulse, resulting in a trailing effect. The thermal noise of the amplifier is proportional to the absolute temperature and follows the Nyquist noise formula. Where k represents the Boltzmann constant, T represents the absolute temperature, and B represents the bandwidth, the thermal noise power in the 40K temperature range is only 13% of that at room temperature. By pre-amplifying the low-noise amplifier (LNA) in the 40K temperature range, the noise figure is reduced to 0.1-0.5 dB, and the signal-to-noise ratio (SNR) can be improved by 5-10 dB for weak SNSPI pulses. Selecting an appropriate discrimination level, reading the noise floor at low temperatures, improving multi-peak pre-amplification, laying the foundation for multi-peak suppression, and enhancing the SNR are all crucial steps.

[0037] The waveform is regular. Figure 3 As shown, different values ​​of integrating capacitors are selected to adjust the pulse width and achieve differentiated pulse shaping. If the capacitance is small, the integration time constant τ is much smaller than the original pulse width of SNSPI. ,Right now The charging speed is fast, and the output waveform retains the rising edge position and steep characteristics of the original pulse. However, with a large capacitance, the time constant τ is much larger than the original pulse width. Discharging before the battery is fully charged significantly increases pulse broadening. ,achieve Combiner output voltage ,in , These represent the output voltages of the two RC integrator comparators. The stepped wave, after passing through the comparator, is dynamically discriminated and normalized into a square wave with a relatively high amplitude. The amplitude is then reduced by an attenuator and used at the enable port of the matching latch comparator for SNSPI's optical and dark counting.

[0038] The rise time of the comparator output pulse is much slower than that of the latch comparator. The resolution of the time interval measurement is limited by time jitter, and the rise time of the pulse determines the magnitude of the trigger jitter. Time measurement follows... ,in This represents the root mean square value that triggers the jitter. Rise time represents the rise time within the 20%-80% pulse amplitude range; SNR represents the signal-to-noise ratio. The longer the time window, the wider the time window from the low level to the trigger threshold, resulting in greater random deviations in trigger timing caused by noise and worsening time jitter. Using a slow-rising-edge signal for SNSPI time interval measurement increases time jitter and degrades measurement resolution. Regularizing the signal into a square wave with a steep rising edge significantly reduces time jitter. After attenuation, the signal is input to a latch comparator for high-precision time interval measurement.

[0039] When light illuminates the SNSPI, it outputs light counting pulses. The amplitude of these pulses is positively correlated with the bias voltage; that is, the higher the SNSPI bias voltage, the larger the light pulse amplitude. The discrimination level of the latch comparator must be precisely matched with the SNSPI bias voltage to achieve effective light pulse discrimination. The microcontroller sets the DAC discrimination level corresponding to each bias point, such as... Figure 2 As shown, the discrimination level falls within the range of 1 / 2 to 2 / 3 of the optical counting pulse amplitude, avoiding noise-induced false triggering and preventing missed detection of optical pulses.

[0040] The quantization relationship between bandwidth and rising edge of high-speed devices follows Where BW represents bandwidth and Tr represents rising edge. The equivalent input bandwidth of the high-speed latch comparator is 9.3GHz, with a theoretical rising edge of approximately 37.6ps, greater than the measured 24ps. Hardware redundancy is employed to achieve an extremely low rising edge. The output waveform is as follows: Figure 4 As shown. By combining end-to-end 50Ω impedance matching, a steep 90ps rise time is achieved at the system level, compressing the trigger time window and suppressing system timing jitter to 45ps rms. By combining the synergy between the RC integrator comparator network and the device latching characteristics, a programmable pulse broadening of 100ns-1μs is achieved, ensuring sufficient effective capture time for the initial 100-200ns narrow pulse of SNSPI. The latch comparator uses the LVDS level standard, boosted to TTL level by a DC blocker before inputting to subsequent FPGA and TAC circuits.

[0041] This invention deploys a low-noise amplifier in the 40 K low-temperature region and combines it with the distribution pattern of high amplitude at the bottom of the multi-peak near the rising edge of the SNSPI pulse. It also synchronously adjusts and lowers the discrimination level of the comparator to suppress multi-peak interference from the source, achieving precise suppression of low-amplitude clutter near the rising edge. This solves the technical problems of high amplification noise at room temperature and incomplete suppression of multi-peaks.

[0042] This invention employs dual independent RC integrator circuits to differentiate the positive and negative SNSPI pulses. One circuit uses a small capacitance value to preserve the rising edge characteristics of the pulse, while the other circuit uses a large capacitance value to broaden the pulse. The two integrated signals are combined by a combiner to generate a stepped wave, which is then dynamically discriminated by a DAC and normalized into a square wave. This invention overcomes the technical limitations of existing single-channel integrators, which cannot simultaneously preserve the rising edge and broaden the pulse width. It achieves the dual goals of multi-peak elimination and waveform normalization, with a simple structure and no need for complex algorithms.

[0043] This invention overcomes the technical defects of traditional comparators, such as high jitter and narrow adaptation range. By using ultra-high-speed devices and system-level optimization, it achieves the dual technical effects of low jitter time measurement and programmable pulse width adaptation, meeting the picosecond-level timestamp extraction requirements of SNSPI.

[0044] The above are embodiments of the present invention and do not limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention are included within the protection scope of the present invention.

Claims

1. A pulse shaping method based on a superconducting nanowire single-photon imager, characterized in that, include: A superconducting nanowire single-photon imager (SNSPI) outputs a pair of positive and negative 100µV weak pulses. The positive pulse is input to a low-noise amplifier (LNA) in a 40K cryogenic environment to improve the signal-to-noise ratio. The LNA output signal is split into three paths by a power divider. One path is input to a latch comparator in a 40K cryogenic environment to capture the precise timing of the original signal for calibration. The other two paths are input to dual-channel RC integrator comparators in a 300K ambient temperature environment to cancel clutter and broaden the pulse. The two paths are combined to generate a stepped wave, which is then input to a comparator, normalized into a square wave, and input to the latch enable port of the latch comparator via an attenuator. The output is an LVDS level signal, which is input to the subsequent FPGA and TDC circuits. The negative pulse processing principle is similar. An inverter is added after the LNA to make the polarity of the two pulses consistent, which is suitable for subsequent integration and combining.

2. The pulse shaping method based on a superconducting nanowire single-photon imager according to claim 1, characterized in that, One of the dual-channel RC circuits uses a small capacitance value to preserve the rising edge characteristic of the pulse, while the other uses a large capacitance value to achieve pulse widening. The integration time constant of the small capacitance value is less than one-tenth of the original pulse width of SNSPI, and the integration time constant of the large capacitance value is greater than the original pulse width, so that the pulse widening reaches three times the integration time constant. The output voltage of the combiner is the sum of the two outputs.

3. The pulse shaping method based on a superconducting nanowire single-photon imager according to claim 1, characterized in that, Also includes: Multiple optimal bias points for SNSPI are calibrated using an STM32 microcontroller to control the dynamic discrimination level output of the DAC. The amplitude is 50% of the first step of the stepped wave. These are then input to a low-noise amplifier (LNA), a comparator, and a latch comparator to achieve closed-loop feedback and adjust the bias current of SNSPI in real time.

4. The pulse shaping method based on a superconducting nanowire single-photon imager according to claim 1, characterized in that, Also includes: The entire link is designed with 50Ω impedance matching, and the amplification, shaping and level conversion circuits are integrated in the SNSPI low-temperature environment to achieve integrated signal processing.

Images