Clock duty cycle calibration circuit

Abstract

The clock duty cycle calibration circuit disclosed in this application comprises multiple cascaded duty cycle calibration modules. The duty cycle controlled adjustment unit in a subsequent duty cycle calibration module is connected to the clock signal restoration unit in the preceding duty cycle calibration module. The two clock signals input to the duty cycle controlled adjustment unit in the subsequent duty cycle calibration module are the two clock signals restored by the clock signal restoration unit in the preceding duty cycle calibration module. The two clock signals to be calibrated input to the duty cycle controlled adjustment unit in the first duty cycle calibration module are the initial two clock signals to be calibrated. The two clock signals output by the clock signal restoration unit in the final duty cycle calibration module are the calibrated clock signals. This multi-stage duty cycle calibration module employs a strategy combining coarse and fine adjustments, enabling it to progressively approach the target value and achieve the target accuracy even with a large deviation in the duty cycle of the input clock signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a clock duty cycle calibration circuit. Background Technology

[0002] In the field of high-speed integrated circuits, the duty cycle of the clock signal is a key parameter affecting system performance. Especially for synchronous digital systems, data acquisition systems, and clock data recovery circuits (CDR), various core circuit structures, including dual-edge flip-flops, dynamic logic circuits, and analog-to-digital converters (ADCs), are highly sensitive to the duty cycle of the clock signal. Only when the duty cycle of the input clock signal is precisely 50% can its performance indicators such as operating speed, power consumption, and signal-to-noise ratio reach their optimal state.

[0003] Currently, in traditional clock signal duty cycle circuits, a single-stage calibration circuit is used to calibrate the duty cycle of the input clock signal. When the duty cycle deviation of the input clock signal is large, the single-stage calibration circuit cannot calibrate the duty cycle of the clock signal to the target accuracy. Summary of the Invention

[0004] The main technical problem solved by this invention is that when the duty cycle deviation of the input clock signal is large, the single-stage calibration circuit cannot calibrate the duty cycle of the clock signal to the target accuracy.

[0005] One embodiment provides a clock duty cycle calibration circuit, including: a plurality of duty cycle calibration modules; For any duty cycle calibration module, there are three components: a duty cycle controlled adjustment unit, an error detection unit, and a clock signal restoration unit. The duty cycle controlled adjustment unit receives two clock signals to be calibrated and converts them into corresponding current signals. When the duty cycle of the two clock signals to be calibrated does not reach a preset threshold, it adjusts the duty cycle of the two clock signals to be calibrated in response to an input error control signal to adjust the generated current signal. The clock signal restoration unit is connected to the duty cycle controlled adjustment unit. It receives the current signal output by the duty cycle controlled adjustment unit and restores the corresponding two clock signals based on the received current signal. The error detection unit is connected to both the duty cycle controlled adjustment unit and the clock signal restoration unit. It receives the restored two clock signals and generates the error control signal, which is output to the duty cycle controlled adjustment unit to adjust the generated current signal. The multiple duty cycle calibration modules are cascaded. The duty cycle controlled adjustment unit in the subsequent duty cycle calibration module is connected to the clock signal restoration unit in the preceding duty cycle calibration module. The two clock signals input to the duty cycle controlled adjustment unit in the subsequent duty cycle calibration module are the two clock signals restored by the clock signal restoration unit in the preceding duty cycle calibration module. The two clock signals to be calibrated input to the duty cycle controlled adjustment unit in the first duty cycle calibration module are the initial two clock signals to be calibrated. The two clock signals output by the clock signal restoration unit in the last duty cycle calibration module are the calibrated clock signals.

[0006] In one embodiment, the duty cycle controlled adjustment unit includes: The clock signal access circuit includes a first signal access terminal, a second signal access terminal, a first signal output terminal, and a second signal output terminal. The clock signal access circuit is used to access the two clock signals to be calibrated through the first signal access terminal and the second signal access terminal respectively, and to selectively output the corresponding sink current through the first signal output terminal or the second signal output terminal based on the two clock signals to be calibrated. A current mirror circuit is connected to the first signal output terminal and the second signal output terminal. The current mirror circuit is used to receive the corresponding sink current through its input branch and mirror the corresponding sink current, and output the corresponding current signal through its output branch. A current regulation circuit is connected to the error detection unit and the current mirror circuit. The current regulation circuit is used to adjust the input current of the current mirror circuit in response to the input error control signal, so as to adjust the current signal output by the current mirror circuit.

[0007] In one embodiment, the duty cycle controlled adjustment unit further includes: An acceleration circuit is connected to the first signal output terminal and the second signal output terminal. The acceleration circuit is used to accelerate the reversal process of the output terminal of the corresponding inhalation current when the output of the corresponding inhalation current switches between the first signal output terminal and the second signal output terminal.

[0008] In one embodiment, the clock signal access circuit includes: The input differential pair includes a first transistor and a second transistor. The control terminals of the first transistor and the second transistor are respectively the first signal input terminal and the second signal input terminal. The first terminal of the first transistor and the first terminal of the second transistor are respectively the first signal output terminal and the second signal output terminal. The input differential pair is used to selectively guide the tail current to the first transistor or the second transistor based on the two clock signals to be calibrated, so as to provide sink current through the guided transistor. The two clock signals to be calibrated include a first clock signal and its inverse clock signal.

[0009] In one embodiment, the current mirror circuit includes: The first current mirror has a power supply terminal for connecting to the power supply terminal, an input branch for connecting to the first signal output terminal, and an output branch for connecting to the clock signal restoration unit. The first current mirror is used to mirror the sink current output by the first signal output terminal to its output branch when the first signal output terminal outputs a sink current, so as to output a corresponding current signal to the clock signal restoration unit. The second current mirror has a power supply terminal for connecting to the power supply terminal, and its input branch is connected to the second signal output terminal. The second current mirror is used to mirror the sink current output by the second signal output terminal to its output branch when the second signal output terminal outputs a sink current. The third current mirror has its input branch connected to the output branch of the second current mirror, and its output branch connected to the clock signal restoration unit. The power supply terminal of the third current mirror is grounded. The third current mirror is used to absorb the current signal output from the output branch of the second current mirror and mirror it to its output branch so as to output the corresponding current signal to the clock signal restoration unit.

[0010] In one embodiment, the current regulation circuit includes: The calibration differential pair includes a third transistor and a fourth transistor. The control terminals of the third transistor and the fourth transistor are respectively connected to the error detection unit. The first terminal of the third transistor is connected to the first signal output terminal, and the first terminal of the fourth transistor is connected to the second signal output terminal. The calibration differential pair is used to adjust the sink current of the output of the first signal output terminal or the second signal output terminal based on the error control signal, so that the current mirror circuit adjusts the generated current signal. The error control signal includes a first error signal and a second error signal that is complementary to it.

[0011] In one embodiment, the acceleration circuit includes: A cross-coupled transistor pair includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is connected to the second signal output terminal, the second terminal of the fifth transistor is used to connect to the power supply terminal, and the control terminal of the fifth transistor is connected to the first signal output terminal. The first terminal of the sixth transistor is connected to the first signal output terminal, the second terminal of the sixth transistor is used to connect to the power supply terminal, and the control terminal of the sixth transistor is connected to the second signal output terminal. The cross-coupled transistor pair is used to increase the sink current of the second signal output terminal in response to a decrease in the sink current output of the first signal output terminal, and to increase the sink current of the first signal output terminal in response to a decrease in the sink current output of the second signal output terminal.

[0012] In one embodiment, the clock signal restoration unit includes: A level conversion circuit is used to receive the current signal generated by the duty cycle controlled adjustment unit and convert it into a level signal; A level buffer circuit is used to receive the level signal output by the level conversion circuit, and after waveform shaping and drive enhancement, generate a corresponding clock signal to serve as one of the two restored clock signals. An inverter circuit is used to receive the level signal output by the level conversion circuit, and in response to the enable signal being valid, it outputs a corresponding clock signal at its output terminal based on the level signal, so as to serve as the other clock signal in the two restored clock signals.

[0013] In one embodiment, the error detection unit includes: A voltage integrating circuit is connected to the level buffer circuit and the inverter circuit. The voltage integrating circuit is used to generate a corresponding integrated voltage in response to the clock signal output by the level buffer circuit and to generate a corresponding integrated voltage in response to the clock signal output by the inverter circuit. An error amplifier circuit is connected to the voltage integral circuit and the duty cycle controlled adjustment unit. The error amplifier circuit is used to receive the two integrated voltages generated by the voltage integral circuit and amplify the difference between the two integrated voltages to form the error control signal.

[0014] In one embodiment, the voltage integration circuit includes: a first current source, a second current source, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first integrating capacitor, and a second integrating capacitor; The first terminal of the seventh transistor is connected to the power supply terminal through the first current source. The control terminal of the seventh transistor is connected to the output terminal of the level buffer circuit. The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The second terminal of the eighth transistor is grounded. The control terminal of the eighth transistor is connected to the first terminal of the seventh transistor. One terminal of the first integrating capacitor is connected to the first terminal of the seventh transistor. The other terminal of the first integrating capacitor is grounded. The first terminal of the ninth transistor is connected to the power supply terminal through the second current source. The control terminal of the ninth transistor is connected to the output terminal of the inverter circuit. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the second terminal of the seventh transistor. The second terminal of the tenth transistor is grounded. One terminal of the second integrating capacitor is connected to the first terminal of the ninth transistor. The second terminal of the second integrating capacitor is grounded. The error amplifier circuit includes a third current source, a fourth current source, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first filter capacitor, and a second filter capacitor. The first terminal of the eleventh transistor is connected to the power supply terminal through the third current source. The control terminal of the eleventh transistor is connected to one terminal of the first integrating capacitor. The second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor. The control terminal of the twelfth transistor is connected to the first terminal of the eleventh transistor. The second terminal of the twelfth transistor is grounded. The first filter capacitor is connected to the first terminal of the eleventh transistor. The first terminal of the eleventh transistor is also connected to the duty cycle controlled adjustment unit. The first terminal of the thirteenth transistor is grounded through the fourth current source. The control terminal of the thirteenth transistor is connected to one terminal of the second integrating capacitor. The second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor and the second terminal of the eleventh transistor. The control terminal of the fourteenth transistor is connected to the first terminal of the thirteenth transistor. The second terminal of the fourteenth transistor is grounded. The second filter capacitor is connected to the first terminal of the thirteenth transistor. The first terminal of the thirteenth transistor is also connected to the duty cycle controlled adjustment unit.

[0015] In one embodiment, the clock duty cycle calibration circuit further includes: The selection circuit includes a selection switch channel, the number of which is greater than or equal to the number of the plurality of duty cycle calibration modules. The clock signal restoration unit in each duty cycle calibration module is connected to a corresponding selection switch channel. When the corresponding selection switch channel is in the on state, its two clock signals are output through the corresponding selection switch channel.

[0016] The clock duty cycle calibration circuit according to the above embodiment includes a multi-stage duty cycle calibration module. The subsequent stage of the duty cycle calibration module can calibrate the duty cycle of the clock signal output by the previous stage of the duty cycle calibration module. The multi-stage duty cycle calibration module adopts a strategy that combines coarse adjustment and fine adjustment. The first stage (or multiple preceding stages) is responsible for reducing the large range of duty cycle deviation and pulling the signal into a smaller error range. The subsequent stage (or fine adjustment stage) performs high-precision fine adjustment on this basis. Compared with single-stage calibration, even if the duty cycle deviation of the input clock signal is large (such as far as 50%), it can approach the target value step by step and finally achieve the target accuracy, avoiding the inability to converge due to insufficient gain or limited adjustment range of a single stage. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating the principle of a clock duty cycle calibration circuit according to one embodiment. Figure 2 This is a circuit diagram of a clock duty cycle calibration circuit according to one embodiment; Figure 3 This is a circuit diagram of a duty cycle controlled adjustment unit according to one embodiment; Figure 4 This is a circuit diagram of a clock signal restoration unit according to one embodiment; Figure 5 A circuit diagram of a voltage integration circuit according to one embodiment; Figure 6 This is a circuit diagram of an error amplifier circuit according to one embodiment. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0019] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the order of the steps or actions in the method description can be changed or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0020] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0021] In some embodiments, such as Figure 1 , Figure 2 As shown, the clock duty cycle calibration circuit may include multiple duty cycle calibration modules 10. For any one duty cycle calibration module 10: the duty cycle calibration module 10 may include a duty cycle controlled adjustment unit 11, an error detection unit 13, and a clock signal restoration unit 12.

[0022] The duty cycle controlled adjustment unit 11 is used to receive two clock signals (clk and clkb) to be calibrated, convert the two clock signals to be calibrated into corresponding current signals, and adjust the duty cycle of the two clock signals to be calibrated in response to the received error control signals (err and errb) to adjust the generated current signal.

[0023] The clock signal restoration unit 12 is connected to the duty cycle controlled adjustment unit 11. The clock signal restoration unit 12 is used to receive the current signal output by the duty cycle controlled adjustment unit 11 and restore the corresponding two clock signals (clk_on and clk_op) based on the received current signal.

[0024] The error detection unit 13 is connected to the duty cycle controlled adjustment unit 11 and the clock signal restoration unit 12. The error detection unit 13 is used to receive the two restored clock signals and generate an error control signal to be output to the duty cycle controlled adjustment unit 11 to adjust the generated current signal.

[0025] In this configuration, multiple duty cycle calibration modules 10 are cascaded. The duty cycle controlled adjustment unit 11 in the subsequent duty cycle calibration module 10 is connected to the clock signal restoration unit 12 in the preceding duty cycle calibration module 10. The two clock signals input to the duty cycle controlled adjustment unit 11 in the subsequent duty cycle calibration module 10 are the two clock signals restored by the clock signal restoration unit 12 in the preceding duty cycle calibration module 10. The two clock signals to be calibrated input to the duty cycle controlled adjustment unit 11 in the first duty cycle calibration module 10 are the initial two clock signals to be calibrated. The two clock signals output by the clock signal restoration unit 12 in the last duty cycle calibration module 10 are the calibrated clock signals.

[0026] Specifically, the duty cycle controlled adjustment unit 11 includes two clock signal input terminals, one current output terminal, and two error signal input terminals. The two clock signal input terminals of the duty cycle controlled adjustment unit 11 are used to connect two clock signals to be calibrated respectively. When the duty cycle controlled adjustment unit 11 belongs to the first-level duty cycle calibration module 10, the two clock signals to be calibrated are the initial two clock signals to be calibrated. When the duty cycle controlled adjustment unit 11 belongs to a non-first-level duty cycle calibration module 10 (e.g., the second-level or third-level duty cycle calibration module 10, etc.), the duty cycle controlled adjustment unit 11 will be used for other purposes. When the two clock signals to be calibrated are the clock signals output by the clock signal restoration unit 12 of the duty cycle calibration module 10 connected to the previous stage, the current output terminal is used to output the current signal corresponding to the two clock signals to be calibrated and output it to the connected clock signal restoration unit 12; the two error signal input terminals are used to input the error control signal, which includes the first error signal err and the second error signal errb, which is complementary to it. The first error signal err and the second error signal errb are respectively input through the two error signal input terminals.

[0027] like Figure 2 As shown, the clock signal restoration unit 12 includes a current input terminal and two clock signal output terminals. The current input terminal is connected to the current output terminal of the duty cycle controlled adjustment unit 11 in the same duty cycle calibration module 10. The two clock signal output terminals are respectively connected to the error detection unit 13, and two restored clock signals are output through the two clock signal output terminals. When the duty cycle calibration module 10 to which the clock signal restoration unit 12 belongs is not the last stage of the duty cycle calibration module 10, the two restored clock signals are output to the error detection unit 13 and the duty cycle controlled adjustment unit 11 in the next stage of the duty cycle calibration module 10.

[0028] The error detection unit 13 includes two clock signal input terminals and two error signal output terminals. The two clock signal input terminals of the error detection unit 13 are respectively connected to the two clock signal output terminals of the clock signal restoration unit 12 in the duty cycle calibration module 10, so as to receive the restored two clock signals output by the two clock signal output terminals. The two error signal output terminals are respectively connected to the two error signal input terminals, and the first error signal err and the second error signal errb are output to the two error signal input terminals through the two error signal output terminals.

[0029] The duty cycle controlled adjustment unit 11, clock signal restoration unit 12, and error detection unit 13 in the same duty cycle calibration module 10 form a feedback adjustment system. In this feedback system, the error detection unit 13 extracts the duty cycle deviation information of the two incoming clock signals in real time and outputs an error control signal. The duty cycle controlled adjustment unit 11 outputs a corresponding current signal according to the error control signal. The clock signal restoration unit 12 restores the corresponding two clock signals to the error detection unit 13 according to the current signal to support closed-loop stable operation.

[0030] During specific calibration, for the first-stage duty cycle calibration module 10: the initial two clock signals to be calibrated are connected through the duty cycle controlled adjustment unit 11, and the corresponding current signals are output to the clock signal restoration unit 12 in the corresponding duty cycle calibration module 10. The clock signal restoration unit 12 outputs the corresponding two clock signals to the error detection unit 13 in the corresponding duty cycle calibration module 10 according to the connected current signals. The error detection unit 13 outputs the corresponding first error signal err and second error signal errb to the two error signal input terminals of the duty cycle controlled adjustment unit 11 according to the connected two restored clock signals. The duty cycle controlled adjustment unit 11 outputs the corresponding current signal according to the connected first error signal err and second error signal errb to form a closed-loop feedback adjustment.

[0031] For duty cycle calibration modules 10 that are not in the first stage: the duty cycle controlled adjustment unit 11 receives two clock signals output from the clock signal restoration unit 12 of the previous stage and outputs corresponding current signals to the clock signal restoration unit 12 in the corresponding duty cycle calibration module 10. The clock signal restoration unit 12 outputs two corresponding clock signals to the error detection unit 13 in the corresponding duty cycle calibration module 10 based on the input current signals. The error detection unit 13 outputs the corresponding first error signal err and second error signal errb to the two error signal input terminals of the duty cycle controlled adjustment unit 11 based on the input first error signal err and second error signal errb, so as to form a closed-loop feedback adjustment. Among them, the two clock signals output by the last stage duty cycle calibration module 10 are clock signals output to the outside, which can be understood as two clock signals after calibration.

[0032] Therefore, the multi-stage duty cycle calibration module 10 of the clock duty cycle calibration circuit in this application starts calibration from the first-stage duty cycle calibration module 10, and adopts a strategy combining coarse and fine adjustment. The first stage (or multiple pre-stages) is responsible for reducing the large range of duty cycle deviation and pulling the signal into a smaller error range. The subsequent stage (or fine adjustment stage) performs high-precision fine adjustment on this basis. Compared with single-stage calibration, even if the duty cycle deviation of the input clock signal is large (such as far as 50%), it can approach the target value step by step and finally achieve the target accuracy, avoiding the inability to converge due to insufficient gain of a single stage or limited adjustment range.

[0033] In some embodiments, the initial two clock signals to be calibrated include a first clock signal and a second clock signal that is inverted thereon. The second clock signal can be a clock signal that forms a differential clock signal with the first clock signal, or it can be a clock signal that is inverted from the first clock signal by an inverter. When the second clock signal forms a differential clock signal with the first clock signal, it can be understood as a dual-input mode; when the second clock signal is a clock signal that is inverted from the first clock signal by an inverter, it can be understood as a single-input mode. The single-input mode corresponds to the single-output mode, and the dual-input mode corresponds to the dual-output mode. Therefore, this clock duty cycle calibration circuit can be compatible with and convert between single-ended and differential clock signals, and has a wide range of applications.

[0034] In some embodiments, such as Figure 2As shown, the duty cycle controlled adjustment unit 11 may include a clock signal input circuit 111, a current mirror circuit 113, and a current adjustment circuit 112. The clock signal input circuit 111 includes a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. The clock signal input circuit 111 is used to input two clock signals to be calibrated through the first and second signal input terminals respectively, and selectively outputs a corresponding sink current through either the first or second signal output terminal based on the two clock signals to be calibrated. The current mirror circuit 113 is connected to the first and second signal output terminals. The current mirror circuit 113 is used to input the corresponding sink current through its input branch, mirror the corresponding sink current, and output a corresponding current signal through its output branch. The current adjustment circuit 112 is connected to the error detection unit 13 and the clock signal restoration unit 12. The current adjustment circuit 112 is used to adjust the sink current of the input branch of the current mirror circuit 113 in response to the input error control signal, thereby adjusting the current signal output by the current mirror circuit 113.

[0035] In this embodiment, the first signal input terminal and the second signal input terminal of the clock signal input circuit 111 are the two clock signal input terminals of the duty cycle controlled adjustment unit 11. The first signal output terminal and the second signal output terminal are respectively connected to the input branch of the current mirror circuit 113. The clock signal input circuit 111 selectively outputs the corresponding sink current to the input branch of the current mirror circuit 113 through the first signal output terminal or the second signal output terminal according to the two clock signals to be calibrated. The current mirror circuit 113 mirrors the sink current input to the input branch and outputs a current signal (the current signal is the current signal output by the duty cycle controlled adjustment unit 11) to the clock signal restoration unit through its output branch.

[0036] In some embodiments, Figure 3 As shown, the clock signal input circuit 111 includes an input differential pair transistor, which includes a first transistor 1111 and a second transistor 1112. The control terminals of the first transistor 1111 and the second transistor 1112 are respectively the first signal input terminal and the second signal input terminal. The first terminal of the first transistor 1111 and the first terminal of the second transistor 1112 are respectively the first signal output terminal and the second signal output terminal. The input differential pair transistor is used to selectively guide the tail current to the first transistor 1111 or the second transistor 1112 based on the two clock signals to be calibrated, so as to provide sink current through the guided transistor. The two clock signals to be calibrated include the first clock signal and its inverse clock signal.

[0037] Specifically, the clock signal input circuit 111 includes an input differential pair transistor and a first current sink 1113. The first terminal of the first transistor 1111 and the first terminal of the second transistor 1112 are respectively connected to the power supply terminal Vdd. The second terminals of the first transistor 1111 and the second terminal of the second transistor 1112 are respectively grounded to VSS through the first current sink 1113. For any pair of input differential transistors: when the clock signal connected to the first transistor 1111 is high, the first transistor 1111 is turned on and the second transistor 1112 is turned off. The first terminal of the first transistor 1111 provides sink current, which flows to point X. Conversely, when the clock signal connected to the first transistor 1111 is low, the first transistor 1111 is turned off and the second transistor 1112 is turned on. The first terminal of the second transistor 1112 provides sink current, which flows to point Y. The duty cycle information of the two clock signals to be calibrated is converted into the average current difference between points X and Y through the input differential transistors.

[0038] In some embodiments, such as Figure 3 As shown, the current mirror circuit 113 may include a first current mirror 1131, a second current mirror 1132, and a third current mirror 1133. The power supply terminal of the first current mirror 1131 is connected to the power supply terminal Vdd. The input branch of the first current mirror 1131 is connected to the first signal output terminal, and the output branch of the first current mirror 1131 is connected to the clock signal restoration unit 12. When the first signal output terminal outputs a sinking current, the first current mirror 1131 mirrors the sinking current output by the first signal output terminal to its output branch, thereby outputting a corresponding current signal to the clock signal restoration unit 12. The power supply terminal of the second current mirror 1132 is connected to the power supply terminal Vdd. The input branch of the second current mirror 1132 is connected to the second signal output terminal. When the second signal output terminal outputs a sinking current, the second current mirror 1132 mirrors the sinking current output by the second signal output terminal to its output branch. The input branch of the third current mirror 1133 is connected to the output branch of the second current mirror 1132. The output branch of the third current mirror 1133 is connected to the clock signal restoration unit. The power supply terminal of the third current mirror 1133 is grounded to VSS. The third current mirror 1133 is used to absorb the current signal output from the output branch of the second current mirror 1132 and mirror it to its output branch to output the corresponding current signal to the clock signal restoration unit.

[0039] Specifically, the first current mirror 1131 includes a fifteenth transistor 1131a and a sixteenth transistor 1131b. The second terminals of the fifteenth transistor 1131a and the sixteenth transistor 1131b are respectively connected to the power supply terminal Vdd. The first terminal of the fifteenth transistor 1131a (point X mentioned above) is connected to the first terminal of the first transistor 1111. The first terminal of the fifteenth transistor 1131a is also connected to its control terminal. The control terminal of the fifteenth transistor 1131a is connected to the control terminal of the sixteenth transistor 1131b. The first terminal of the sixteenth transistor 1131b is connected to the clock signal restoration unit 12. When the first terminal of the first transistor 1111 provides a sink current, the first current mirror 1131 replicates the sink current and generates a current signal at the first terminal of the sixteenth transistor 1131b.

[0040] The second current mirror 1132 includes a seventeenth transistor 1132a and an eighteenth transistor 1132b. The second terminals of the seventeenth transistor 1132a and the eighteenth transistor 1132b are respectively connected to the power supply terminal Vdd. The first terminal of the seventeenth transistor 1132a is connected to the first terminal of the second transistor 1112. The first terminal of the seventeenth transistor 1132a is also connected to its control terminal. The control terminal of the seventeenth transistor 1132a is connected to the control terminal of the eighteenth transistor 1132b. When the first terminal of the second transistor 1112 provides a sink current, the second current mirror 1132 replicates the sink current and generates a replicated current at the first terminal of the eighteenth transistor 1132b, which is then provided to the third current mirror 1133.

[0041] The third current mirror 1133 includes a nineteenth transistor 1133a and a twentieth transistor 1133b. The first terminal of the nineteenth transistor 1133a is connected to the first terminal of the eighteenth transistor 1132b. The first terminal of the nineteenth transistor 1133a is also connected to its control terminal. The second terminals of the nineteenth transistor 1133a and the second terminals of the twentieth transistor 1133b are respectively grounded (vss). The first terminal of the twentieth transistor 1133b is connected to the first terminal of the sixteenth transistor 1131b (or it can be considered as connected to the clock signal restoration unit 12). The third current mirror 1133 replicates the current provided by the first terminal of the eighteenth transistor 1132b and generates a current signal at the first terminal of the twentieth transistor 1133b to the clock signal restoration unit 12.

[0042] Therefore, the first current mirror 1131, the second current mirror 1132, and the third current mirror 1133 are used to output the current signal, which can characterize the duty cycle information of the two clock signals to be calibrated, to the clock signal restoration unit 12. In this embodiment, the first current mirror 1131 is used for differential-mode current sampling of the main path, copying the current difference at point X from the main path to the output branch; the second current mirror 1132 is used for differential-mode current sampling of the auxiliary path, copying the current difference at point Y from the main path to the output branch; the third current mirror 1133 is used for common-mode level conversion and stabilization, pulling down the current at point comon to provide a stable DC operating point for point comp, while stabilizing the common-mode level of the entire output stage.

[0043] In some embodiments, such as Figure 3 As shown, the current regulation circuit 112 may include a calibration differential pair transistor, which includes a third transistor 1121 and a fourth transistor 1122. The control terminals of the third transistor 1121 and the fourth transistor 1122 are respectively connected to the error detection unit 13. The first terminal of the third transistor 1121 is connected to the first signal output terminal, and the first terminal of the fourth transistor 1122 is connected to the second signal output terminal. The calibration differential pair transistor is used to adjust the sink current of the output of the first signal output terminal or the second signal output terminal based on the error regulation signal, so that the current mirror circuit 113 adjusts the generated current signal.

[0044] Specifically, the current regulation circuit 112 includes a calibration differential pair transistor and a second current sink 1123. The control terminals of the third transistor 1121 and the fourth transistor 1122 are respectively connected to the first error signal err and the second error signal errb. The second terminals of the third transistor 1121 and the fourth transistor 1122 are respectively grounded to VSS through the second current sink 1123. The first terminal of the third transistor 1121 is connected to the first terminal of the first transistor 1111, and the first terminal of the fourth transistor 1122 is connected to the first terminal of the second transistor 1112. When the third transistor 1121 is turned on, it adjusts the sink current provided by the first terminal of the first transistor 1111, that is, the sink current input to the input branch of the first current mirror 1131. When the fourth transistor 1122 is turned on, it adjusts the sink current provided by the first terminal of the second transistor 1112, that is, the sink current input to the input branch of the second current mirror 1132.

[0045] In some embodiments, such as Figure 3 As shown, the clock signal input circuit 111 also includes an acceleration circuit 114, which is connected to the first signal output terminal and the second signal output terminal. The acceleration circuit 114 is used to accelerate the reversal process of the output terminal of the corresponding suction current when the output corresponding suction current switches between the first signal output terminal and the second signal output terminal.

[0046] In some embodiments, the acceleration circuit 114 may include a cross-coupled pair of transistors, which includes a fifth transistor 1141 and a sixth transistor 1142. The first terminal of the fifth transistor 1141 is connected to the second signal output terminal, the second terminal of the fifth transistor 1141 is connected to the power supply terminal Vdd, and the control terminal of the fifth transistor 1141 is connected to the first signal output terminal. The first terminal of the sixth transistor 1142 is connected to the first signal output terminal, the second terminal of the sixth transistor 1142 is connected to the power supply terminal Vdd, and the control terminal of the sixth transistor 1142 is connected to the second signal output terminal. The cross-coupled pair of transistors is used to increase the sink current of the second signal output terminal in response to a decrease in the sink current output of the first signal output terminal, and to increase the sink current of the first signal output terminal in response to a decrease in the sink current output of the second signal output terminal.

[0047] Specifically, the first terminal of the fifth transistor 1141 is connected to the first terminal of the second transistor 1112, the second terminal of the fifth transistor 1141 is connected to the power supply terminal Vdd, the control terminal of the fifth transistor 1141 is connected to the first terminal of the sixth transistor 1142, the first terminal of the sixth transistor 1142 is connected to the first terminal of the first transistor 1111, the second terminal of the sixth transistor 1142 is connected to the power supply terminal Vdd, and the control terminal of the sixth transistor 1142 is connected to the first terminal of the fifth transistor 1141.

[0048] In some embodiments, such as Figure 4 As shown, the clock signal restoration unit 12 may include a level conversion circuit 121, a level buffer circuit 122, and an inverter circuit 123. The level conversion circuit 121 is used to receive the current signal generated by the duty cycle controlled adjustment unit 11 and convert it into a level signal. The level buffer circuit 122 is used to receive the level signal output by the level conversion circuit 121, and after waveform shaping and drive enhancement, it generates a corresponding clock signal as one of the two clock signals to be restored. The inverter circuit 123 is used to receive the level signal output by the level conversion circuit 121, and in response to the enable signal being valid, it outputs a corresponding clock signal based on the level signal as the other clock signal to be restored.

[0049] In some embodiments, such as Figure 4As shown, the level conversion circuit 121 includes a resistor 1211 and a first inverter 1212. One end of the resistor 1211 is connected to the input terminal of the first inverter 1212, and the other end of the resistor 1211 is connected to the output terminal of the first inverter 1212. The connection between the resistor 1211 and the input terminal of the first inverter 1212 is connected to the first terminal of the eighteenth transistor 1132b, which can also be understood as the connection to the first terminal of the twentieth transistor 1133b. The level buffer circuit 122 includes a second inverter 1221 and a third inverter 1222. The input of the second inverter 1221 is connected to the output of the first inverter 1212, and the output of the second inverter 1221 is connected to the input of the third inverter 1222. The output of the third inverter 1222 outputs a restored clock signal. After waveform shaping and drive enhancement of the level signal output by the level conversion circuit 121 through the second and third inverters 1221 and 1222, the corresponding clock signal is generated. The inverter circuit 123 includes a fourth inverter 1232 and a transmission gate 1231. The input of the transmission gate 1231 is connected to the output of the first inverter 1212, and the output of the transmission gate 1231 is connected to the input of the fourth inverter 1232. The output of the fourth inverter 1232 outputs another restored clock signal.

[0050] In some embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown, the error detection unit 13 may include a voltage integrating circuit 131 and an error amplifying circuit 132. The voltage integrating circuit 131 is connected to the level buffer circuit 122 and the inverter circuit 123. The voltage integrating circuit 131 is used to generate a corresponding integrated voltage in response to the clock signal output by the level buffer circuit 122 and to generate a corresponding integrated voltage in response to the clock signal output by the inverter circuit 123. The error amplifying circuit 132 is connected to the voltage integrating circuit 131 and the duty cycle controlled adjustment unit 11. The error amplifying circuit 132 is used to input the two integrated voltages generated by the voltage integrating circuit and amplify the difference between the two integrated voltages to form an error control signal.

[0051] Specifically, such as Figure 5As shown, the voltage integrating circuit 131 includes a first current source 1313, a second current source 1316, a seventh transistor 1311, an eighth transistor 1312, a ninth transistor 1314, a tenth transistor 1315, a first integrating capacitor 1317, and a second integrating capacitor 1318. The first terminal of the seventh transistor 1311 is connected to the power supply terminal Vdd through the first current source 1313. The control terminal of the seventh transistor 1311 is connected to the output terminal of the level buffer circuit 122. The second terminal of the seventh transistor 1311 is connected to the first terminal of the eighth transistor 1312. The second terminal of the eighth transistor 1312 is grounded to VSS. The control terminal of the eighth transistor 1312 is connected to the seventh transistor 1311. The first terminal of the first integrating capacitor 1317 is connected to the first terminal of the seventh transistor 1311, and the other terminal of the first integrating capacitor 1317 is grounded (vss). The first terminal of the ninth transistor 1314 is connected to the power supply terminal (vdd) through the second current source 1316. The control terminal of the ninth transistor 1314 is connected to the output terminal of the inverter circuit 123. The second terminal of the ninth transistor 1314 is connected to the first terminal of the tenth transistor 1315 and the second terminal of the seventh transistor 1311. The second terminal of the tenth transistor 1315 is grounded (vss). One terminal of the second integrating capacitor 1318 is connected to the first terminal of the ninth transistor 1314, and the second terminal of the second integrating capacitor 1318 is grounded (vss).

[0052] like Figure 6As shown, the error amplifier circuit 132 includes a third current source 1323, a fourth current source 1326, an eleventh transistor 1321, a twelfth transistor 1322, a thirteenth transistor 1324, a fourteenth transistor 1325, a first filter capacitor 1327, and a second filter capacitor 1328. The first terminal of the eleventh transistor 1321 is connected to the power supply terminal Vdd through the third current source 1323. The control terminal of the eleventh transistor 1321 is connected to one end of the first integrating capacitor 1317. The second terminal of the eleventh transistor 1321 is connected to the first terminal of the twelfth transistor 1322. The control terminal of the twelfth transistor 1322 is connected to the first terminal of the eleventh transistor 1321. The second terminal of the twelfth transistor 1322 is grounded to VSS. The first filter capacitor 1327 is connected to the eleventh transistor 1328. The first terminal of transistor 1321 is also connected to the duty cycle controlled adjustment unit 11; the first terminal of transistor 1324 is connected to the power supply terminal Vdd through the fourth current source 1326; the control terminal of transistor 1324 is connected to one terminal of the second integrating capacitor 1318; the second terminal of transistor 1324 is connected to the first terminal of transistor 1425 and the second terminal of transistor 1121; the control terminal of transistor 1425 is connected to the first terminal of transistor 1324; the second terminal of transistor 1425 is grounded to VSS; the second filter capacitor 1328 is connected to the first terminal of transistor 1324; and the first terminal of transistor 1324 is also connected to the duty cycle controlled adjustment unit 11. In this embodiment, the control terminal of the seventh transistor 1311 is connected to the output terminal of the third inverter 1222, the control terminal of the ninth transistor 1314 is connected to the output terminal of the fourth inverter 1232, the first terminal of the eleventh transistor 1321 is connected to the control terminal of the fourth transistor 1122, and the first terminal of the thirteenth transistor 1324 is connected to the control terminal of the third transistor 1121.

[0053] To understand the calibration process of this clock duty cycle calibration circuit, the calibration process of the first-level duty cycle calibration module 10 will be used as an example for explanation, as follows: The control terminals of the first transistor 1111 and the second transistor 1112 are respectively connected to two clock signals to be calibrated. When the clock signal connected to the control terminal of the first transistor 1111 is high, the first terminal of the first transistor 1111 provides a sink current; conversely, the first terminal of the second transistor 1112 provides a sink current. After the sink current is generated, the current mirror circuit 113 mirrors the sink current and outputs it to the input terminal of the first inverter 1212 through the output branch (the sink current provided by the first terminal of the first transistor 1111 is replicated by the first current mirror 1131, and the sink current provided by the first terminal of the second transistor 1112 is replicated by the second current mirror 1132). A level conversion circuit 121, consisting of an inverter 1212 and a resistor 1211, works together to convert the current signal into a CMOS level. The CMOS level is then converted into a restored clock signal by a second inverter 1221 and a third inverter 1222. When the enable signal at the transmission gate 1231 is active, the signal is converted into another restored clock signal by the transmission gate 1231 and a fourth inverter 1232. When the clock signal output by the third inverter 1222 is high, the seventh transistor 1311 is turned on, and the first current source 1313 charges the first integrating capacitor 1317. The control terminal of the eighth transistor 1312 is controlled by the voltage at the first terminal of the seventh transistor 1311. (The eighth transistor 1312 may also be turned on, but the on-resistance of the seventh transistor 1311 is very small, and the charging current provided by the first current source 1313 to the first integrating capacitor 1317 is dominant.) When the clock signal output from the third inverter 1222 is low, the seventh transistor 1311 is turned off. At this time, there is no charging current at the first terminal of the seventh transistor 1311, and the first integrating capacitor 1317 discharges, causing the eighth transistor 1312 to turn on and causing the first integrating capacitor 1317 to discharge to ground. If the duty cycle of the clock signal output by the seventh transistor 1311 is greater than 50% (the high-level duty cycle is longer), then the charging time of the first integrating capacitor 1317 is greater than the discharging time. The average DC voltage at the first terminal of the seventh transistor 1311 increases over time. Conversely, if the duty cycle is less than 50%, the average DC voltage at the first terminal of the seventh transistor 1311 decreases. As a result, the average DC voltage at the first terminal of the seventh transistor 1311 is proportional to the duty cycle of the clock signal output from the output terminal of the third inverter 1222. The change in the average DC voltage at the first terminal of the ninth transistor 1314 can be referred to the above process of the change in the average DC voltage at the first terminal of the seventh transistor 1311, and will not be elaborated on here. The average DC voltage at the first terminal of the ninth transistor 1314 is proportional to the duty cycle of the clock signal output from the output terminal of the fourth inverter 1232.

[0054] Assuming the voltage at the first terminal of the seventh transistor 1311 is greater than the voltage at the first terminal of the ninth transistor 1314, and the conduction capability of the eleventh transistor 1321 is stronger than that of the thirteenth transistor 1324, a stronger pull-down current flows through the eleventh transistor 1321, thereby causing the voltage at the control terminal of the sixth transistor 1142 to decrease. At the same time, since the conduction of the thirteenth transistor 1324 is weaker, the voltage at the control terminal of the fifth transistor 1141 increases (because the third current source 1323 and the fourth current source 1326 are pulling upwards). Therefore, it can be concluded that when the voltage at the first terminal of the seventh transistor 1311 is greater than the voltage at the first terminal of the ninth transistor 1314, the voltage at the control terminal of the fifth transistor 1141 increases, and the voltage at the control terminal of the sixth transistor 1142 decreases. The voltage difference between the control terminals of the fifth transistor 1141 and the sixth transistor 1142 is amplified.

[0055] The DC voltage at the first terminal of the eleventh transistor 1321 is proportional to the difference between the DC voltage at the first terminal of the seventh transistor 1311 and the DC voltage at the first terminal of the ninth transistor 1314, which is also proportional to the difference between the duty cycle of the clock signal output by the third inverter 1222 and 50%. The DC voltage at the first terminal of the thirteenth transistor 1324 and the DC voltage at the first terminal of the eleventh transistor 1321 are complementary signals, proportional to the difference between the DC voltage at the first terminal of the ninth transistor 1314 and the DC voltage at the first terminal of the seventh transistor 1311. The DC voltage at the first terminal of the eleventh transistor 1321 and the DC voltage at the first terminal of the thirteenth transistor 1324 are error control signals.

[0056] For the third transistor 1121 and the fourth transistor 1122, the increased DC voltage at the first terminal of the thirteenth transistor 1324 means that the third transistor 1121 has a stronger conduction capability and draws more current from point X; the increased DC voltage at the first terminal of the eleventh transistor 1321 means that the fourth transistor 1122 has a stronger conduction capability and draws more current from point Y. Therefore, the voltage at point X is pulled down, and the voltage at point Y relatively increases. This change is transmitted through the current mirror circuit 113, ultimately causing the high voltage of the clock signal output by the third inverter 1222 to rise. As the duty cycle shortens (approaching 50%), the high-level time of the clock signal output by the fourth inverter 1232 becomes longer. When the duty cycle of the clock signal output by the third inverter 1222 is adjusted to 50%, the DC voltage at the first terminal of the seventh transistor 1311 is equal to the DC voltage at the first terminal of the ninth transistor 1314, and the voltage at the first terminal of the eleventh transistor 1321 is equal to the voltage at the first terminal of the thirteenth transistor 1324. The third transistor 1121 and the fourth transistor 1122 stop adjusting, and the clock duty cycle calibration circuit reaches a locked state.

[0057] Among them, the first filter capacitor 1327 and the second filter capacitor 1328 play a filtering role.

[0058] For the third transistor 1121 and the fourth transistor 1122, the error control signals connected to the control terminals of the third transistor 1121 and the fourth transistor 1122 are differential DC voltages. The difference reflects the deviation of the duty cycle of the two restored clock signals output by the third inverter 1222 and the fourth inverter 1232 from a 50% duty cycle. When the voltage at the control terminal of the third transistor 1121 is greater than the voltage at the control terminal of the fourth transistor 1122, the conduction capability of the third transistor 1121 is stronger than that of the fourth transistor. The body transistor 1122 draws more current from point X, causing the voltage at point X to drop, thereby adjusting the duty cycle of the output clock signal. The tail current of the third transistor 1121 is provided by the second current sink 1123, and the tail current of the first transistor 1111 is provided by the first current sink 1113. The tail current of the first transistor 1111 is n times the tail current of the third transistor 1121, where n > 1, can be 1.5-3, and preferably n = 1.67. The first current sink 1113 and the second current sink 1123 constitute a current mirror.

[0059] The gates of the fifth transistor 1141 and the sixth transistor 1142 are cross-connected to each other's drains, forming a positive feedback loop. When the voltage at point X drops, the gate voltage of the sixth transistor 1142 drops, and the conduction of the sixth transistor 1142 is enhanced, which pulls up the voltage at point Y. The increased voltage at point Y further acts on the gate of the fifth transistor 1141, further pulling down the voltage at point X. This positive feedback mechanism accelerates the voltage switching of the x / y node and improves the gain and speed of the circuit.

[0060] As can be seen, the clock duty cycle calibration circuit is implemented entirely by analog circuits, without the need for complex digital control algorithms, which simplifies the circuit structure and reduces circuit area and power consumption. Verification shows that the clock duty cycle calibration circuit can operate normally at a power supply voltage of 0.9V or even lower under 28nm process, with a single-stage operating current of less than 150μA.

[0061] In some embodiments, the first transistor 1111, the second transistor 1112, the third transistor 1121, the fourth transistor 1122, the nineteenth transistor 1133a, the twentieth transistor 1133b, the seventh transistor 1311, the eighth transistor 1312, the ninth transistor 1314, the tenth transistor 1315, the eleventh transistor 1321, the twelfth transistor 1322, the thirteenth transistor 1324, and the fourteenth transistor 1325 may all be N-MOS transistors (N-type Metal-Oxide-Semiconductor Field-Effect Transistors); the fifth transistor 1141, the sixth transistor 1142, the fifteenth transistor 1131a, the sixteenth transistor 1131b, the seventeenth transistor 1132a, and the eighteenth transistor 1132b may all be P-MOS transistors (P-type Metal-Oxide-Semiconductor Field-Effect Transistors). (e.g., a metal-oxide-semiconductor field-effect transistor). In any of the above transistors, the control terminal refers to the gate, the first terminal refers to the drain, and the second terminal refers to the source.

[0062] In some embodiments, the clock duty cycle calibration circuit further includes a selection circuit 20, which includes a selection switch channel. The number of selection switch channels is greater than or equal to the number of multiple duty cycle calibration modules 10. The clock signal restoration unit in each duty cycle calibration module 10 is connected to a selection switch channel. When the corresponding selection switch channel is in the on state, its two clock signals are output through the corresponding selection switch channel.

[0063] Specifically, the selection circuit 20 can be a multiplexer (MUX). The output terminals of the third inverter 1222 and the fourth inverter 1232 in each stage of the duty cycle calibration module 10 are connected to one channel of the multiplexer. The multiplexer can select the corresponding duty cycle calibration module 10 to work, thereby saving power consumption.

[0064] For example, the test can be performed by shutting down the channel corresponding to the last stage duty cycle calibration module 10. If the clock signal output by the channel connected to the previous stage duty cycle calibration module 10 can meet the accuracy requirements, then the channel connected to the last stage duty cycle calibration module 10 can be shut down. Similarly, the verification can be performed by shutting down the channel connected to the duty cycle calibration module 10 that does not need to participate in the duty cycle calibration.

[0065] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0066] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A clock duty cycle calibration circuit, characterized in that, include: Multiple duty cycle calibration modules; For any duty cycle calibration module, there are a duty cycle controlled adjustment unit, an error detection unit, and a clock signal restoration unit; The duty cycle controlled adjustment unit is used to receive two clock signals to be calibrated, convert the two clock signals to be calibrated into corresponding current signals, and adjust the duty cycle of the two clock signals to be calibrated in response to the received error control signal when the duty cycle of the two clock signals to be calibrated does not reach a preset threshold, so as to adjust the generated current signal. The clock signal restoration unit is connected to the duty cycle controlled adjustment unit. The clock signal restoration unit is used to receive the current signal output by the duty cycle controlled adjustment unit and restore the corresponding two clock signals based on the received current signal. The error detection unit is connected to the duty cycle controlled adjustment unit and the clock signal restoration unit. The error detection unit is used to receive the restored two clock signals and generate the error control signal, which is output to the duty cycle controlled adjustment unit to adjust the generated current signal. The multiple duty cycle calibration modules are cascaded, and the duty cycle controlled adjustment unit in the subsequent duty cycle calibration module is connected to the clock signal restoration unit in the preceding duty cycle calibration module. The two clock signals accessed by the duty cycle controlled adjustment unit in the subsequent duty cycle calibration module are the two clock signals restored by the clock signal restoration unit in the preceding duty cycle calibration module. The two clock signals to be calibrated in the duty cycle controlled adjustment unit of the first-stage duty cycle calibration module are the initial two clock signals to be calibrated. The two clock signals output by the clock signal restoration unit in the last-stage duty cycle calibration module are the clock signals after calibration is completed.

2. The clock duty cycle calibration circuit as described in claim 1, characterized in that, The duty cycle controlled adjustment unit includes: The clock signal access circuit includes a first signal access terminal, a second signal access terminal, a first signal output terminal, and a second signal output terminal. The clock signal access circuit is used to access the two clock signals to be calibrated through the first signal access terminal and the second signal access terminal respectively, and to selectively output the corresponding sink current through the first signal output terminal or the second signal output terminal based on the two clock signals to be calibrated. A current mirror circuit is connected to the first signal output terminal and the second signal output terminal. The current mirror circuit is used to receive the corresponding sink current through its input branch and mirror the corresponding sink current, and output the corresponding current signal through its output branch. A current regulation circuit is connected to the error detection unit and the current mirror circuit. The current regulation circuit is used to adjust the input current of the current mirror circuit in response to the input error control signal, so as to adjust the current signal output by the current mirror circuit.

3. The clock duty cycle calibration circuit as described in claim 2, characterized in that, The duty cycle controlled adjustment unit further includes: An acceleration circuit is connected to the first signal output terminal and the second signal output terminal. The acceleration circuit is used to accelerate the reversal process of the output terminal of the corresponding inhalation current when the output of the corresponding inhalation current switches between the first signal output terminal and the second signal output terminal.

4. The clock duty cycle calibration circuit as described in claim 2 or 3, characterized in that, The clock signal access circuit includes: The input differential pair includes a first transistor and a second transistor. The control terminals of the first transistor and the second transistor are respectively the first signal input terminal and the second signal input terminal. The first terminal of the first transistor and the first terminal of the second transistor are respectively the first signal output terminal and the second signal output terminal. The input differential pair is used to selectively guide the tail current to the first transistor or the second transistor based on the two clock signals to be calibrated, so as to provide sink current through the guided transistor. The two clock signals to be calibrated include a first clock signal and its inverse clock signal.

5. The clock duty cycle calibration circuit as described in claim 2 or 3, characterized in that, The current mirror circuit includes: The first current mirror has a power supply terminal for connecting to the power supply terminal, an input branch for connecting to the first signal output terminal, and an output branch for connecting to the clock signal restoration unit. The first current mirror is used to mirror the sink current output by the first signal output terminal to its output branch when the first signal output terminal outputs a sink current, so as to output a corresponding current signal to the clock signal restoration unit. The second current mirror has a power supply terminal for connecting to the power supply terminal, and its input branch is connected to the second signal output terminal. The second current mirror is used to mirror the sink current output by the second signal output terminal to its output branch when the second signal output terminal outputs a sink current. The third current mirror has its input branch connected to the output branch of the second current mirror, and its output branch connected to the clock signal restoration unit. The power supply terminal of the third current mirror is grounded. The third current mirror is used to absorb the current signal output from the output branch of the second current mirror and mirror it to its output branch so as to output the corresponding current signal to the clock signal restoration unit.

6. The clock duty cycle calibration circuit as described in claim 2 or 3, characterized in that, The current regulation circuit includes: The calibration differential pair includes a third transistor and a fourth transistor. The control terminals of the third transistor and the fourth transistor are respectively connected to the error detection unit. The first terminal of the third transistor is connected to the first signal output terminal, and the first terminal of the fourth transistor is connected to the second signal output terminal. The calibration differential pair is used to adjust the sink current of the output of the first signal output terminal or the second signal output terminal based on the error control signal, so that the current mirror circuit adjusts the generated current signal. The error control signal includes a first error signal and a second error signal that is complementary to it.

7. The clock duty cycle calibration circuit as described in claim 3, characterized in that, The acceleration circuit includes: A cross-coupled transistor pair includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is connected to the second signal output terminal, the second terminal of the fifth transistor is used to connect to the power supply terminal, and the control terminal of the fifth transistor is connected to the first signal output terminal. The first terminal of the sixth transistor is connected to the first signal output terminal, the second terminal of the sixth transistor is used to connect to the power supply terminal, and the control terminal of the sixth transistor is connected to the second signal output terminal. The cross-coupled transistor pair is used to increase the sink current of the second signal output terminal in response to a decrease in the sink current output of the first signal output terminal, and to increase the sink current of the first signal output terminal in response to a decrease in the sink current output of the second signal output terminal.

8. The clock duty cycle calibration circuit as described in any one of claims 1-3, characterized in that, The clock signal restoration unit includes: A level conversion circuit is used to receive the current signal generated by the duty cycle controlled adjustment unit and convert it into a level signal; A level buffer circuit is used to receive the level signal output by the level conversion circuit, and after waveform shaping and drive enhancement, generate a corresponding clock signal to serve as one of the two restored clock signals. An inverter circuit is used to receive the level signal output by the level conversion circuit, and in response to the enable signal being valid, it outputs a corresponding clock signal at its output terminal based on the level signal, so as to serve as the other clock signal in the two restored clock signals.

9. The clock duty cycle calibration circuit as described in claim 8, characterized in that, The error detection unit includes: A voltage integrating circuit is connected to the level buffer circuit and the inverter circuit. The voltage integrating circuit is used to generate a corresponding integrated voltage in response to the clock signal output by the level buffer circuit and to generate a corresponding integrated voltage in response to the clock signal output by the inverter circuit. An error amplifier circuit is connected to the voltage integral circuit and the duty cycle controlled adjustment unit. The error amplifier circuit is used to receive the two integrated voltages generated by the voltage integral circuit and amplify the difference between the two integrated voltages to form the error control signal.

10. The clock duty cycle calibration circuit as described in claim 9, characterized in that, The voltage integration circuit includes: a first current source, a second current source, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first integrating capacitor, and a second integrating capacitor; The first terminal of the seventh transistor is connected to the power supply terminal through the first current source. The control terminal of the seventh transistor is connected to the output terminal of the level buffer circuit. The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The second terminal of the eighth transistor is grounded. The control terminal of the eighth transistor is connected to the first terminal of the seventh transistor. One terminal of the first integrating capacitor is connected to the first terminal of the seventh transistor. The other terminal of the first integrating capacitor is grounded. The first terminal of the ninth transistor is connected to the power supply terminal through the second current source. The control terminal of the ninth transistor is connected to the output terminal of the inverter circuit. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the second terminal of the seventh transistor. The second terminal of the tenth transistor is grounded. One terminal of the second integrating capacitor is connected to the first terminal of the ninth transistor. The second terminal of the second integrating capacitor is grounded. The error amplifier circuit includes a third current source, a fourth current source, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first filter capacitor, and a second filter capacitor. The first terminal of the eleventh transistor is connected to the power supply terminal through the third current source. The control terminal of the eleventh transistor is connected to one terminal of the first integrating capacitor. The second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor. The control terminal of the twelfth transistor is connected to the first terminal of the eleventh transistor. The second terminal of the twelfth transistor is grounded. The first filter capacitor is connected to the first terminal of the eleventh transistor. The first terminal of the eleventh transistor is also connected to the duty cycle controlled adjustment unit. The first terminal of the thirteenth transistor is grounded through the fourth current source. The control terminal of the thirteenth transistor is connected to one terminal of the second integrating capacitor. The second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor and the second terminal of the eleventh transistor. The control terminal of the fourteenth transistor is connected to the first terminal of the thirteenth transistor. The second terminal of the fourteenth transistor is grounded. The second filter capacitor is connected to the first terminal of the thirteenth transistor. The first terminal of the thirteenth transistor is also connected to the duty cycle controlled adjustment unit.

11. The clock duty cycle calibration circuit as described in any one of claims 1-3, characterized in that, The clock duty cycle calibration circuit also includes: The selection circuit includes a selection switch channel, the number of which is greater than or equal to the number of the plurality of duty cycle calibration modules. The clock signal restoration unit in each duty cycle calibration module is connected to a corresponding selection switch channel. When the corresponding selection switch channel is in the on state, its two clock signals are output through the corresponding selection switch channel.

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