High resolution signal generation apparatus and method

Abstract

This application relates to a high-resolution signal generation apparatus and method. The apparatus includes: a signal processing module for receiving multiple signal groups, each signal group including a PWM control signal and a corresponding phase selection signal; processing the multiple signal groups sequentially according to priority within the current clock cycle; for the current signal group to be processed, determining the current phase data group based on the PWM control signal and the corresponding phase selection signal, until all signal groups are processed to obtain the phase data group within the current clock cycle; a delay module connected to the signal processing module for delaying the data corresponding to each phase through a delay chain corresponding to each phase to obtain multiple phase-delayed signals; and an XOR module connected to the delay module for performing bitwise XOR processing on the multiple phase-delayed signals to generate a single high-resolution PWM signal. The apparatus using this application can simultaneously avoid glitches and pulse width limitations.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a high-resolution signal generation apparatus and method. Background Technology

[0002] Pulse Width Modulation (PWM) technology is widely used in motor control and power management. Existing high-resolution PWM generation schemes are mainly divided into multi-phase sampling methods based on phase-locked loops (PLLs) and phase gating methods based on delay chains. While the PLL scheme achieves high precision, it suffers from complex circuit structure, large area overhead, long lock-in time, and high power consumption during normal PLL operation. The delay chain gating scheme, although relatively simple in structure, typically requires strict timing constraints to avoid glitches during phase switching, limiting the phase change range between adjacent cycles and the shortest output pulse width. Summary of the Invention

[0003] Therefore, it is necessary to provide a high-resolution signal generation device and method that can simultaneously avoid glitches and pulse width limitations in order to address the aforementioned technical problems.

[0004] A high-resolution signal generation apparatus, the apparatus comprising:

[0005] A signal processing module is used to receive multiple signal groups, each of which includes a PWM control signal and a corresponding phase selection signal; within the current clock cycle, the multiple signal groups are processed sequentially according to priority; for the current signal group to be processed, the current phase data group is determined according to the PWM control signal and the corresponding phase selection signal, until all multiple signal groups are processed, and the phase data group within the current clock cycle is obtained; the phase data group includes data corresponding to each phase.

[0006] The delay module, connected to the signal processing module, includes multiple delay chains, each corresponding to a different phase and having a different delay time; it is used to perform delay processing on the data corresponding to each phase through the delay chain corresponding to each phase to obtain multi-channel phase-delayed signals.

[0007] An XOR module, connected to the delay module, is used to perform bitwise XOR processing on the multiple phase delay signals to generate a high-resolution PWM signal.

[0008] A high-resolution signal generation method, the method comprising:

[0009] Receives multiple signal groups, each of which includes a PWM control signal and a corresponding phase selection signal;

[0010] Within the current clock cycle, the multiple signal groups are processed sequentially according to priority. For the current signal group to be processed, the current phase data group is determined based on the PWM control signal and the corresponding phase selection signal until all multiple signal groups are processed, thereby obtaining the phase data group within the current clock cycle. The phase data group includes data corresponding to each phase.

[0011] By using delay chains corresponding to each phase, the data corresponding to each phase is delayed to obtain multi-phase delayed signals; there are multiple delay chains, each corresponding to a different phase and having a different delay time;

[0012] The multi-channel phase delay signals are XORed to generate a single high-resolution PWM signal.

[0013] The aforementioned high-resolution signal generation device and method include a signal processing module that receives multiple signal groups, each including a PWM control signal and a phase selection signal. The module processes these signal groups within the current clock cycle to generate data corresponding to each phase within the current cycle. By using delay chains with different delay times to delay the data corresponding to each phase, multiple phase-delayed signals are obtained. This avoids the glitches caused by phase switching via a selector and eliminates the need to restrict the phases of adjacent cycles to remain unchanged or to the minimum pulse width. The XOR module performs bitwise XOR processing on the multiple phase-delayed signals to generate a single high-resolution PWM signal. This method is simple to implement and less prone to errors. Compared to a phase-locked loop (PLL) solution, it reduces resident power consumption, locking time, and area overhead. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a structural block diagram of a high-resolution signal generation device in one embodiment;

[0016] Figure 2 This is a schematic diagram of the signal processing module in one embodiment;

[0017] Figure 3 This is a flowchart illustrating a high-resolution signal generation method in one embodiment;

[0018] Figure 4 This is a timing diagram of the signal processing module in one embodiment;

[0019] Figure 5 This is a timing diagram of the delay module and the XOR module in one embodiment. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly. The connection can be a direct connection or an indirect connection.

[0023] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0024] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0025] It is understood that the "data acquisition" operation in the embodiments of this application includes, but is not limited to, the following implementation methods: directly reading data pre-stored in the device; data received from external devices; or indirect acquisition methods after data collection, conversion and processing.

[0026] Traditional delay chain gating schemes typically use multiplexers (MUX) to directly select one delay chain as the output. Since the voltage levels of different delay chains are often inconsistent at the same time, when the selection signal switches, the MUX is prone to short-term race conditions due to asynchronous input signal level transitions, leading to fatal glitches at the output. To mitigate this risk, traditional schemes are forced to introduce strict timing constraints in the control logic, mandating switching only within a "safe window" when the voltage levels of adjacent delay chains are consistent (e.g., both are low). This not only limits the range of phase selection changes between adjacent cycles (preventing large jumps) but also makes it difficult to find a switching point that satisfies voltage consistency within a very short time. Consequently, the system cannot generate narrow pulses with a width smaller than this "safe window," severely restricting the dynamic response and resolution of the PWM signal. To address these issues, a high-resolution signal generation device is proposed in this embodiment.

[0027] In one embodiment, such as Figure 1 The diagram shown is a structural block diagram of a high-resolution signal generation device in one embodiment. Figure 1 The system includes a signal processing module 110, a delay module 120, and an XOR module 130 connected to each other. The signal processing module 110 receives multiple (K) signal groups, each including a PWM control signal pwm_ctrl[2:1] and a corresponding phase selection signal pwm_sel[M:1]. For the current signal group to be processed, the current phase data group de_i[N:1] is determined based on the PWM control signal pwm_ctrl[2:1] and the PWM control signal pwm_sel[M:1], until all signal groups are processed, obtaining the phase data group de_i[N:1] for the current clock cycle; the phase data group includes data corresponding to each phase.

[0028] The delay module 120, connected to the signal processing module 110, includes multiple delay chains, each corresponding to a different phase and having a different delay time; it is used to perform delay processing on the data corresponding to each phase through the delay chains corresponding to each phase to obtain multiple (N) phase-delayed signals de_o.

[0029] The XOR module 130 is connected to the delay module 120; it is used to perform bitwise XOR processing on multiple phase delay signals de_o to generate a high-resolution PWM signal hrpwm_out.

[0030] Here, a signal group refers to a set of control signals input to the signal processing module 110, including a PWM control signal (pwm_ctrl) and a phase selection signal (pwm_sel). This embodiment supports receiving K such signal groups simultaneously (K≥1). The K PWM signals are independent of each other and synchronized with the clock CLK.

[0031] The PWM control signal (pwm_ctrl[2:1]) is a signal used to indicate the output status. In this embodiment, it uses 2-bit encoding to represent four states: Hold, Set High, Set Low, and Toggle.

[0032] The phase selection signal (pwm_sel[M:1]) is an M-bit variable-width selection signal used to indicate the phase and specify which fine time phase (corresponding to which delay chain) to process. For example, if the phase selection signal indicates phase 1, then delay chain 1 with only a fixed delay time x is selected for delay. Preferably, the phase selection signal can cover N delay chains, and its value must not be greater than N or less than 1.

[0033] The phase data group can specifically include the phase indicated by the number of delay chains N and the corresponding data, that is, the phase data group includes N phases and their corresponding data (high level or low level). The phase data group is essentially a status register that records the historical accumulated information of what data is needed at each phase point in order to obtain a high-resolution PWM signal.

[0034] A delay chain includes at least one delay unit for delaying an input signal by a specific time. This device includes N different delay chains, each with a different delay time.

[0035] High-resolution PWM signals refer to signals with a time resolution higher than the system master clock cycle. The pulse width modulation signal. The resolution of a high-resolution PWM signal depends on the clock cycle. With a delay chain number N, the minimum pulse width or edge position accuracy can reach / N. Wherein The smaller the value of N, the larger the value of N, and the higher the resolution. .

[0036] Specifically, the signal processing module 110 receives K signal groups, each including a PWM control signal (pwm_ctrl) and a corresponding phase selection signal (pwm_sel). The signal processing module 110 processes multiple signal groups sequentially according to priority. For the current signal group to be processed, it updates the current phase data group de_i [N:1] based on the PWM control signal and the corresponding phase selection signal, until all signal groups are processed, thus obtaining the complete phase data group de_i [N:1] for the current period. The phase data group for the current period then includes the data corresponding to each phase. Specifically, the signal processing module 110 can send the phase data group de_i [N:1] for the current period to the delay module 120 at the edge of the clock cycle.

[0037] Once the delay module 120 receives the de_i [N:1] within a complete cycle, it can input the data corresponding to each phase into the corresponding delay chain in parallel, and perform delay processing on the data corresponding to each phase in parallel, thereby simultaneously obtaining multiple phase-delayed signals. Assuming phase 1 corresponds to data 1, phase 2 corresponds to data 0, and phase 3 corresponds to data 1, then by delaying data 1 through delay chain 1 corresponding to phase 1, the phase-delayed signal corresponding to phase 1 is obtained; by delaying data 0 through delay chain 2 corresponding to phase 2, the phase-delayed signal corresponding to phase 2 is obtained; and by delaying data 1 through delay chain 3 corresponding to phase 3, the phase-delayed signal corresponding to phase 3 is obtained, thus obtaining multiple phase-delayed signals.

[0038] The XOR module 130, connected to the delay module 120, is used to continuously perform bitwise XOR processing on multiple phase delay signals to generate a high-resolution PWM signal corresponding to each PWM control signal. For example, if phase 1 indicates a high level, phase 2 remains unchanged, phase 3 indicates a toggle, and phase 4 indicates a low level, then the corresponding high-resolution PWM signal is 1100.

[0039] In this embodiment, the signal processing module 110 is used to receive multiple signal groups, each signal group including a PWM control signal and a phase selection signal. It processes multiple signal groups within the current clock cycle to generate data corresponding to each phase within the current cycle. By using delay chains with different delay times, the data corresponding to each phase is delayed to obtain multiple phase-delayed signals. This avoids the glitches caused by phase switching through a selector and eliminates the need to restrict the phase of adjacent cycles to remain unchanged and the minimum pulse width. The XOR module 130 is used to perform bitwise XOR processing on the multiple phase-delayed signals to generate a high-resolution PWM signal. The implementation method is simple and error-free. Compared with the phase-locked loop scheme, it reduces resident power consumption, locking time, and area overhead.

[0040] In one embodiment, the signal processing module 110 is configured to: process the phase selection signals in each signal group in ascending order during the current clock cycle; if the phase selection signals are the same, process them in ascending order according to the group number of the signal group.

[0041] Specifically, the clock period is the period indicated by the clock signal. The signal processing module 110 prioritizes processing the phase selection signals in each signal group in ascending order. For example, it processes them in the order of phase 1, phase 2, (phase 3 missing), phase 4, and phase 5. When there are identical phase selection signals, they are processed in ascending order according to the group number k; for example, phase 1, phase 2 (k=1), phase 2 (k=2), phase 4, and phase 5.

[0042] In this embodiment, within the same phase period, the phase selection signals in each signal group are processed in ascending order. If the phase selection signals are the same, they are processed in ascending order according to the group number of the signal group, thus providing a deterministic arbitration mechanism for multi-channel conflicts.

[0043] In one embodiment, the signal processing module 110 is configured to: for the current group of signals to be processed, if the current phase selection signal is the same as the existing phase selection signal, ignore the current group of signals to be processed and continue processing the next group of signals to be processed.

[0044] The existing phase selection signal refers to the phase selection signal that has already been processed in the current clock cycle's processing flow. In hardware implementation, it is usually stored in a temporary phase register.

[0045] Specifically, the high-resolution PWM signal can only flip once per phase within each clock cycle. If the current pwm_sel[k] is the same as the processed pwm_sel[k], it indicates that the current phase cannot be flipped again. The output change indicated by the current pwm_sel[k] will be ignored, and no flipping operation or state update operation will be performed. The data of the corresponding phase in the current phase data group will be maintained as the data of the corresponding phase in the previous phase data group.

[0046] In this embodiment, there may be conflicting phases within a clock cycle. Therefore, when the current phase selection signal is the same as the existing phase selection signal, the output change indicated by the current pending signal group is ignored, and the next pending signal group is processed. This allows a phase to respond to a valid instruction at most once. When it is detected that the currently requested phase has been occupied, subsequent conflicting signals are automatically ignored, thereby eliminating output glitches and level oscillations caused by multiple signals competing for the same phase from the logical root.

[0047] In one embodiment, the signal processing module 110 is configured to: for the current group of signals to be processed, when the PWM control signal indicates that the output remains unchanged, maintain the data of the corresponding phase in the current phase data group as the data of the corresponding phase in the previous phase data group.

[0048] Specifically, for the current group of signals to be processed, when the PWM control signal indicates that the output remains unchanged, the data of the corresponding phase in the current phase data group is the same as the data of the corresponding phase in the previous phase data group. That is, the current group of signals to be processed is ignored, and the next group of signals to be processed is processed.

[0049] In this embodiment, when the PWM control signal indicates that the output remains unchanged, the current signal group to be processed can be left unprocessed. The data of the corresponding phase in the current phase data group is maintained as the data of the corresponding phase in the previous phase data group. By recognizing the "output remains unchanged" instruction and directly using the data from the previous cycle, invalid phase decoding, logic operations, and register write operations are avoided, effectively reducing system power consumption.

[0050] In one embodiment, the signal processing module 110 is configured to: for the current group of signals to be processed, when the PWM control signal indicates that the output is flipped, invert the data corresponding to the current phase selection signal in the previous phase data group, and update the data corresponding to the current phase selection signal in the phase data group.

[0051] Output switching refers to switching from a high level to a low level or from a low level to a high level.

[0052] Specifically, for the current group of signals to be processed, when the PWM control signal pwm_ctrl[k] indicates an output flip, the bit corresponding to the current phase selection signal pwm_sel[k] in the previous phase data group de_i[N:1] is inverted, and the data corresponding to the current phase selection signal is updated in the phase data group de_i[N:1]. For example, if the previous phase 2 was 0, then the current phase 2 is 1, and the data corresponding to phase 2 in de_i[N:1] is updated to 1.

[0053] In this embodiment, when the PWM control signal indicates that the output is flipped, the data corresponding to the current phase selection signal in the previous phase data group is inverted, and the data corresponding to the current phase selection signal in the phase data group is updated. This can obtain a bitwise XOR result that is the opposite of the previous data. Only the corresponding bit in the phase data group needs to be inverted to directly change the level state of the final output. This relative quantity control method not only greatly simplifies the complexity of logic operations and reduces hardware resource consumption, but also ensures the immediacy and determinism of the edge flipping response.

[0054] In one embodiment, the signal processing module 110 is configured to: for the current group of signals to be processed, when the PWM control signal indicates the output target level, compare the bitwise XOR result of the previous phase data group with the target level; if they are the same, maintain the data of the corresponding phase in the current phase data group as the data of the corresponding phase in the previous phase data group.

[0055] The target level is either high or low. The bitwise XOR result of the previous phase data group is the result of performing a bitwise XOR operation on de_i [N:1]. It can be understood that the bitwise XOR result of the previous phase data group is equivalent to the output result of the final high-resolution PWM signal at that phase.

[0056] Specifically, for the current group of signals to be processed, if the PWM control signal pwm_ctrl[k] indicates a high or low output level, the bitwise XOR result of the previous phase data group de_i[N:1] is compared with the target level. If they are the same, it means that the output does not need to be changed, and the data of the corresponding phase in the current phase data group is maintained as the data of the corresponding phase in the previous phase data group. For example, if the bitwise XOR result of the previous phase data group is 0 and the target level is also 0, then the phase data group remains unchanged.

[0057] In this embodiment, when the PWM control signal indicates the target output level, the bitwise XOR result of the previous phase data group is compared with the target level. If they are the same, the data of the corresponding phase in the current phase data group is maintained as the data of the corresponding phase in the previous phase data group. By pre-judging the consistency between the current XOR result and the target level, intelligent control of "on-demand flipping" is realized. This mechanism avoids the unnecessary edge transitions introduced for forced level alignment, which not only ensures the logical self-consistency and smooth transition of the output waveform, but also effectively reduces the number of unnecessary signal flips, thereby further reducing dynamic power consumption and improving control accuracy.

[0058] In one embodiment, the signal processing module 110 is configured to: if they are not the same, invert the data corresponding to the current phase selection signal in the previous phase data group, and update the data corresponding to the current phase selection signal in the phase data group.

[0059] Specifically, the signal processing module 110 compares the previous bitwise XOR result with the target level. If they are different, it means that the current final hrpwm_out result is different from the previous one. In this case, the data corresponding to the current phase selection signal in the previous phase data group needs to be inverted, and the data corresponding to the current phase selection signal in the phase data group needs to be updated. For example, if the previous bitwise XOR result of the phase data group is 0 and the target level is 1, then the data 1 of the previous phase 2 needs to be changed to data 0, and the data corresponding to phase 2 in de_i[N:1] needs to be updated to 0.

[0060] In this embodiment, if they are different, the data corresponding to the current phase selection signal in the previous phase data group is inverted, and the data corresponding to the current phase selection signal in the phase data group is updated to ensure that the data update is triggered only when necessary, so that the data in the high-resolution PWM signal obtained by the current data is different from the previous one and conforms to the level indicated by the PWM control signal.

[0061] In one embodiment, the signal processing module 110 is further configured to: when the current clock cycle is completed, output the corresponding phase data group as the initial phase data group for the next clock cycle.

[0062] Specifically, when the current clock cycle is finished, the phase data group corresponding to the current clock cycle is output as the initial phase data group for the next clock cycle, and output at the edge of the next clock cycle.

[0063] In this embodiment, when the current clock cycle is completed, the corresponding phase data group is output as the initial phase data group for the next clock cycle, so as to perform the level transition of the next cycle according to the final output result of the current cycle.

[0064] In one embodiment, the delay time of multiple delay chains covers a range from the inherent delay to the inherent delay plus the clock period minus a minimum resolution time, and the delay time interval between adjacent delay chains is equal to the clock period divided by the number of delay chains.

[0065] Specifically, the inherent delay x is the same for all N delay chains, and the value of x depends on the specific implementation of the delay chain. The delays of the N delay chains are different, with a minimum delay of x and a maximum delay of... - / N, and the interval between delay chains is / N.

[0066] In this embodiment, the delay time of multiple delay chains covers the range from the inherent delay to the inherent delay plus the clock period minus a minimum resolution time, and the delay time interval between adjacent delay chains is equal to the clock period divided by the number of delay chains N. Therefore, the resolution of the high-resolution signal is the clock period divided by the number of delay chains N, without any other restrictions.

[0067] In one embodiment, such as Figure 2 The diagram shown is a schematic representation of the processing flow of a signal processing module in one embodiment, including:

[0068] Step 201: Input clock CLK and K groups of PWM signals, including K pwm_ctrl[2:1] and K pwm_sel[M:1].

[0069] Step 202: Temporarily store the previous phase data group de_i[N:1], temporarily store a temporary pwm_sel and set it to zero, sort the K groups of PWM signals according to the pwm_sel in each group from small to large, if the pwm_sel are the same, sort them according to the group number from small to large, if the pwm_ctrl indicator output remains unchanged, then pwm_sel is regarded as zero.

[0070] As one implementation method, if pwm_ctrl indicates that the output remains unchanged, then pwm_sel is an invalid value and is considered zero. After sorting, the K groups of sorted PWM signals are processed sequentially, processing the k-th group of signals each time, where k satisfies 1≤k≤K. The PWM signal indicating that the output remains unchanged will be processed first.

[0071] Step 203: Begin processing the k-th group of signals.

[0072] The first time k=1, the subsequent times k=k+1.

[0073] Step 204: Determine whether pwm_sel[k] is the same as the temporarily stored pwm_sel.

[0074] If yes, do nothing; if no, proceed to step 205.

[0075] As an implementation method, the high-resolution PWM signal can only flip once per phase within each clock cycle CLK. If pwm_sel[k] is the same as the temporary pwm_sel, it indicates that the current phase cannot be flipped again, and the output change indicated by pwm_ctrl[k] will be ignored.

[0076] Step 205: Determine if pwm_ctrl[k] is unchanged in output.

[0077] If yes, do nothing; if no, proceed to step 206.

[0078] Step 206: Determine whether pwm_ctrl[k] is an output flip.

[0079] If yes, proceed to step 208: invert the bit corresponding to pwm_sel[k] in the temporarily stored de_i[N:1], and temporarily store de_i[N:1] and pwm_sel[k]; if no, proceed to step 207.

[0080] Step 207: Determine whether pwm_ctrl[k] indicates a high level output and the previous ^de_i[N:1] was high, or pwm_ctrl[k] indicates a low level output and the previous ^de_i[N:1] was low.

[0081] Here, ^de_i[N:1] refers to the bitwise XOR result of ^de_i[N:1]. If yes, no processing is performed; otherwise, proceed to step 208.

[0082] As one implementation method, the bitwise XOR result of the temporarily stored de_i[N:1] is consistent with the final output hrpwm_out. If the bitwise XOR result is high and pwm_ctrl[k] indicates a high output, then the output does not need to be changed.

[0083] Step 208: Invert the bits corresponding to the phase selected by pwm_sel[k] in the temporarily stored de_i[N:1], and temporarily store de_i[N:1] and pwm_sel[k].

[0084] If pwm_ctrl[k] indicates a high or low output level, and the result of the bitwise XOR operation with the temporarily stored de_i[N:1] is different, the bit corresponding to pwm_sel[k] in the temporarily stored de_i[N:1] is inverted, and pwm_sel[k] is temporarily stored as a temporary pwm_sel, and the next set of sorted PWM signals is processed.

[0085] Step 209: Determine if the traversal has ended (k=K).

[0086] If yes, proceed to step 210; otherwise, return to step 203.

[0087] Step 210: After the K groups of PWM signals have finished traversing, output the processed de_i[N:1] at the next CLK clock edge.

[0088] In this embodiment, the phase data group is updated by determining the type of the PWM control signal. Subsequently, a high-resolution PWM signal matching the PWM control signal can be generated by using a simple delay chain and bitwise XOR processing. This avoids the glitches caused by phase switching through a selector, and there is no need to limit the phase of adjacent cycles to remain unchanged or the shortest pulse width. The implementation method is simple and not prone to errors. Compared with the phase-locked loop scheme, it reduces resident power consumption, locking time and area overhead.

[0089] In one embodiment, such as Figure 3 The diagram shown is a flowchart of a high-resolution signal generation method in one embodiment. This method can be applied to FPGAs (Field-Programmable Gate Arrays), computer devices, etc., and includes the following steps:

[0090] Step 302: Receive multiple signal groups, each signal group including a PWM control signal and a corresponding phase selection signal.

[0091] Step 304: Within the current clock cycle, multiple signal groups are processed sequentially according to priority. For the current signal group to be processed, the current phase data group is determined based on the PWM control signal and the corresponding phase selection signal until all multiple signal groups are processed, thereby obtaining the phase data group within the current clock cycle. The phase data group includes the data corresponding to each phase.

[0092] Step 306: Delay the data corresponding to each phase through the delay chain corresponding to each phase to obtain multi-phase delayed signals; there are multiple delay chains, each delay chain corresponds to a different phase and has a different delay time.

[0093] Step 308: Perform bitwise XOR processing on the multiple phase delay signals to generate a high-resolution PWM signal.

[0094] In this embodiment, multiple signal groups are received, each including a PWM control signal and a phase selection signal. These signal groups are processed within the current clock cycle to generate data corresponding to each phase within the current cycle. By using delay chains with different delay times, the data corresponding to each phase is delayed to obtain multiple phase-delayed signals. This avoids the glitches caused by phase switching via a selector and eliminates the need to restrict the phases of adjacent cycles to remain unchanged or to the minimum pulse width. The multiple phase-delayed signals are then XORed bitwise to generate a single high-resolution PWM signal. This method is simple and error-free. Compared to a phase-locked loop (PLL) solution, it reduces resident power consumption, locking time, and area overhead.

[0095] In one embodiment, receiving multiple signal groups includes: receiving multiple signal groups and processing the multiple signal groups sequentially in priority order within the same clock cycle.

[0096] In one embodiment, multiple signal groups are processed sequentially according to priority, including: within the same clock cycle, sorting the phase selection signals in each signal group from smallest to largest; if the phase selection signals are the same, sorting them from smallest to largest according to the group number.

[0097] In one embodiment, for the current group of signals to be processed, determining the reference data corresponding to the target phase based on the PWM control signal and the corresponding phase selection signal includes:

[0098] For the current group of signals to be processed, if the phase selection signal is the same as the existing phase selection signal, then the current group of signals to be processed is ignored and the next group of signals to be processed is processed.

[0099] In one embodiment, for the current group of signals to be processed, determining the reference data corresponding to the target phase based on the PWM control signal and the corresponding phase selection signal includes:

[0100] For the current group of signals to be processed, when the PWM control signal indicates that the output remains unchanged, the reference data corresponding to the target phase is kept as the data of the corresponding phase in the previous phase data group.

[0101] In one embodiment, for the current group of signals to be processed, determining the reference data corresponding to the target phase based on the PWM control signal and the corresponding phase selection signal includes:

[0102] For the current group of signals to be processed, when the PWM control signal indicates that the output is flipped, the data corresponding to the current phase selection signal in the previous phase data group is inverted, and the data corresponding to the current phase selection signal in the phase data group is updated.

[0103] In one embodiment, for the current group of signals to be processed, determining the reference data corresponding to the target phase based on the PWM control signal and the corresponding phase selection signal includes:

[0104] For the current group of signals to be processed, when the PWM control signal indicates the target output level, the bitwise XOR result of the previous phase data group is compared with the target level. If they are the same, the reference data corresponding to the target phase is kept as the data of the corresponding phase in the previous phase data group.

[0105] In one embodiment, the method further includes:

[0106] If they are different, invert the data corresponding to the current phase selection signal in the previous phase data group, and update the data corresponding to the current phase selection signal in the phase data group.

[0107] In one embodiment, receiving multiple signal groups includes:

[0108] Receive multiple signal groups in the current clock cycle;

[0109] The method also includes:

[0110] When the current clock cycle is completed, the corresponding phase data group is output as the initial phase data group for the next clock cycle; the phase data group includes each phase and its corresponding data.

[0111] In one embodiment, the delay time of multiple delay chains covers a range from the inherent delay to the inherent delay plus the clock period minus a minimum resolution time, and the delay time interval between adjacent delay chains is equal to the clock period divided by N.

[0112] In one embodiment, Figure 4 This is a timing diagram of the signal processing module in one embodiment. For example... Figure 4 As shown, the initial value of de_i[N:1] is 0. In preprocessing cycle 1, the K groups of PWM control signals are first sorted according to pwm_sel[k] (phase), and the sorting result is {1, 2, ..., K}. Initially, pwm_sel=0 and de_i[N:1]=0 are temporarily stored, and then processed sequentially:

[0113] pwm_ctrl[1] indicates a high output level. At this time, the previous XOR result ^de_i[N:1] of de_i[N:1] (initial value is all 0) is low. The target output hrpwm_out result is high and is different from the previous XOR result (0). Moreover, pwm_sel[1] indicates phase 1, which is not equal to the temporary pwm_sel (which is 0 at this time). Therefore, de_i[1] in the previous de_i[N:1] is inverted (changed from 0 to 1), that is, the temporary de_i[1] is updated to 1, and the temporary XOR result is updated, pwm_sel[1] = 1 (phase 1). Finally, the target output hrpwm_out result is high at phase 1.

[0114] pwm_ctrl[2] indicates a low output level. At this time, the bitwise XOR result of the previous de_i[N:1] is high (1). The target output hrpwm_out result is low and is different from the previous XOR result ^de_i[N:1] (high). Moreover, pwm_sel[2] indicates phase 2, which is not equal to the temporary pwm_sel[1]=1. Therefore, the de_i[2] (low level) in the previous de_i[N:1] is inverted (changed from 0 to 1) and de_i[2]=1 is updated, and pwm_sel[2]=2 is updated. Finally, the target output hrpwm_out result is low at phase 2.

[0115] pwm_ctrl[3] indicates a high output level. At this time, the bitwise XOR result of the previous de_i[N:1], ^de_i[N:1], is low (0). The target output hrpwm_out is high and is different from the previous XOR result (0). Moreover, pwm_sel[3] indicates phase 3, which is not equal to the temporary pwm_sel[2]=2. Therefore, the de_i[3] (low level) in the previous de_i[N:1] is inverted (changed from 0 to 1) and de_i[3]=1 and pwm_sel[3]=3 are updated. Finally, the target output hrpwm_out is high at phase 3.

[0116] The subsequent signal groups (k=4...K) are processed. It is assumed that the pwm_ctrl indicator for these groups remains unchanged, and therefore they are ignored. After preprocessing cycle 1 is completed, de_i[N:1] is output on the rising edge of clock CLK. At this time, de_i[3:1] are all 1, and de_i[N] is 0. The hrpwm_out output of preprocessing cycle 1 is also as set by the phase: phase 1 is high, phase 2 is low, and phase 3 is high.

[0117] In preprocessing cycle 2, the K groups of PWM control signals are first reordered according to pwm_sel[k]. Since pwm_ctrl[K] indicates that the output remains unchanged, the sorting result is {K, 1, 2}. pwm_sel is temporarily set to 0, and then processed sequentially:

[0118] pwm_ctrl[K] indicates that the output remains unchanged, so ignore it and proceed to the next group.

[0119] pwm_ctrl[1] indicates a low level output. At this time, the bitwise XOR result of the previous de_i[N:1] is high level (1). The target output hrpwm_out result is low level and is different from the previous XOR result (1). Moreover, pwm_sel[1] indicates phase 2, which is not equal to the temporary pwm_sel(0). Therefore, the de_i[2] (high level) in the previous de_i[N:1] is inverted (changed from 1 to 0) and the temporary is updated, and the temporary pwm_sel is updated to 2. Finally, the target output hrpwm_out result is low level in phase 2.

[0120] pwm_ctrl[2] indicates a low output level. The previous XOR result was also low, so it is ignored.

[0121] After preprocessing cycle 2 is completed, de_i[N:1] is output on the rising edge of clock CLK. At this time, de_i[2] and de_i[N] are 0, and de_i[1] and de_i[3] are 1. The output result of hrpwm_out in preprocessing cycle 2 is also the same as the phase setting. Phase 2 is low, and subsequent phases are maintained.

[0122] In preprocessing cycle 3, the K groups of PWM control signals are first sorted according to pwm_sel[k]. Since pwm_sel[2] and pwm_sel[K] are the same (e.g., both are 3), and both pwm_ctrl[2] and pwm_ctrl[K] indicate output changes, the sorting result is {2, K, 1...} according to the rule of sorting by group number based on the same phase. The pwm_sel is temporarily set to 0, and then processed sequentially:

[0123] Processing the second group of signals: pwm_ctrl[2] indicates output flipping, pwm_sel[2] indicates phase 3, which is not equal to the temporary pwm_sel(0), so the previous de_i[N:1] in de_i[3] is inverted (changed from 1 to 0) and de_i[3]=0 is updated, and pwm_sel[2]=3 is temporarily stored;

[0124] Processing the Kth group of signals: pwm_ctrl[K] indicates output toggling, pwm_sel[K] indicates phase 3, which is equal to the current temporary pwm_sel=3. According to the rule that the same phase can only be toggled once per cycle, it is ignored.

[0125] Processing the first group of signals: pwm_ctrl[1] indicates output flipping, pwm_sel[1] indicates phase N, which is not equal to the temporary pwm_sel, so the previous de_i[N]=0 in de_i[N:1] is inverted (changed from 0 to 1) and de_i[N]=1 is temporarily stored, and pwm_sel[N]=N is temporarily stored;

[0126] After preprocessing cycle 3 is completed, de_i[N:1] is output on the rising edge of clock CLK. At this time, de_i[2] and de_i[3] are 0, and de_i[1] and de_i[N] are 1. The output result of hrpwm_out in preprocessing cycle 3 is also the same as the phase setting, with phase 3 being high and phase N being low.

[0127] Figure 5 This is a timing diagram of the delay module and the XOR module in one embodiment. Figure 5 As shown, the period of clock CLK is The delay module delays the data de_i[N:1] to obtain the delayed data de_o[N:1], and finally obtains a high-resolution PWM output hrpwm_out through the XOR module.

[0128] Figure 5 Let the delay of the first delay chain be x, and the delay of the nth delay chain be x + (n-1) × / N, the delay of the Nth delay chain is - Let's take / N as an example to illustrate.

[0129] For the signal de_i[N: 1], all N bits of data (de_i[1] to de_i[N]) transition (from 0 to 1 or from 1 to 0) on the same rising edge of the clock CLK. This represents a transition within one clock cycle. Inside, the signal processing module calculates the set of instructions that need to be level-flipped at which "phase points".

[0130] Then the signal de_i[N:1] enters the corresponding delay chain, causing the originally aligned de_i transition edges to be "staggered" into a stepped waveform in the de_o part. This subdivides one clock cycle into multiple tiny time slices on the time axis.

[0131] The synthesized output of the XOR module (de_o→hrpwm_out): The characteristic of the XOR operation is that if an odd number of signals in the input change, the output will change; if an even number of changes occur, the output remains unchanged. Since the transition edges of the signals in de_o are staggered in time (they do not overlap), whenever a de_o[n] changes (corresponding to de_i[n]=1), the level of hrpwm_out will immediately toggle once. If de_i[n]=0, the corresponding de_o[n] does not change, and hrpwm_out maintains its original level at that moment.

[0132] Therefore, the transition edge of hrpwm_out is no longer limited to the edge of the clock signal CLK, but can appear at any precise time point. The pulse width is determined by the time difference between two adjacent transition edges, with a minimum precision of [missing information]. .

[0133] Figure 5 As can be intuitively seen, this embodiment can measure a coarse-grained clock cycle. Successfully subdivided into N fine time segments. Arbitrary edge positioning: By controlling which bits in de_i are 1, the rising or falling edge of hrpwm_out can be precisely controlled at any position within the period. Glitch-free synthesis: Since the outputs of each delay chain are strictly serially staggered in time (not simultaneous jumps), the XOR operation will not produce glitches caused by race conditions, resulting in a clean and smooth output waveform.

[0134] This embodiment uses a signal processing module to sort K groups of PWM signals according to phase selection signals, remove collisions, and generate N bits of data. After being delayed in parallel by N delay chains, the data is combined and output through an XOR operation. Since the N delay chains always work in parallel and are finally combined through XOR gate combinational logic, the race conditions (glitch) caused by phase switching in existing delay chain gating output schemes are avoided. At the same time, there is no need to restrict the phase of adjacent cycles to remain unchanged and the minimum pulse width as in gating schemes. Compared with schemes that rely on PLLs to generate multi-phase clocks, this embodiment can achieve equal-interval delays without PLLs, eliminating the resident power consumption, lockout time, and area overhead of PLLs, and delaying the PWM output while keeping it constant. The chain has no dynamic switching power consumption; this embodiment supports independent control of K groups of PWM signals. Each group of signals can specify the output state at any phase position within the same clock cycle, realizing independent control of multiple edges per cycle, breaking through the limitation of existing solutions that can only control 1 to 2 edges per cycle; in addition, the signal processing module has a built-in conflict resolution mechanism based on phase sorting and group number priority, ensuring that the same phase position flips at most once per cycle, and the logic is self-consistent. Moreover, the two design parameters of the number of delay chains N and the number of PWM groups K are decoupled from each other and can be adjusted independently, so that the resolution and the number of edge control can be expanded separately without affecting each other. It has the characteristics of strong scalability, simple structure, pure digital implementation, and easy IP adaptation.

[0135] It should be understood that, although the above Figure 2 and Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the exact order indicated by the arrows or numbers. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 2 and Figure 3At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0136] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0137] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A high resolution signal generating apparatus, characterized by comprising: The device includes: A signal processing module is used to receive multiple signal groups, each of which includes a PWM control signal and a corresponding phase selection signal; within the current clock cycle, the multiple signal groups are processed sequentially according to priority; for the current signal group to be processed, the current phase data group is determined according to the PWM control signal and the corresponding phase selection signal, until all multiple signal groups are processed, and the phase data group within the current clock cycle is obtained; the phase data group includes data corresponding to each phase. The delay module, connected to the signal processing module, includes multiple delay chains, each corresponding to a different phase and having a different delay time; it is used to perform delay processing on the data corresponding to each phase through the delay chain corresponding to each phase to obtain multi-channel phase-delayed signals. An XOR module, connected to the delay module, is used to perform bitwise XOR processing on the multiple phase delay signals to generate a high-resolution PWM signal.

2. The apparatus according to claim 1, characterized in that, The signal processing module is used for: Within the current clock cycle, the phase selection signals in each signal group are processed sequentially from smallest to largest; if the phase selection signals are the same, they are processed sequentially from smallest to largest according to the group number of the signal group.

3. The apparatus according to claim 1, characterized in that, The signal processing module is used for: For the current group of signals to be processed, if the current phase selection signal is the same as the existing phase selection signal, then the current group of signals to be processed is ignored and the next group of signals to be processed is processed.

4. The apparatus according to claim 1, characterized in that, The signal processing module is used for: For the current group of signals to be processed, when the output of the PWM control signal remains unchanged, the data of the corresponding phase in the current phase data group is maintained as the data of the corresponding phase in the previous phase data group.

5. The apparatus according to claim 1, characterized in that, The signal processing module is used for: For the current group of signals to be processed, when the PWM control signal indicates that the output is flipped, the data corresponding to the current phase selection signal in the previous phase data group is inverted, and the data corresponding to the current phase selection signal is updated in the phase data group.

6. The apparatus according to claim 1, characterized in that, The signal processing module is used for: For the current group of signals to be processed, when the PWM control signal indicates the output target level, the bitwise XOR result of the previous phase data group is compared with the target level. If they are the same, the data of the corresponding phase in the current phase data group is kept the same as the data of the corresponding phase in the previous phase data group.

7. The apparatus according to claim 6, characterized in that, The signal processing module is used for: If they are not the same, the data corresponding to the current phase selection signal in the previous phase data group is inverted, and the data corresponding to the current phase selection signal is updated in the phase data group.

8. The apparatus according to claim 1, characterized in that, The signal processing module is also used for: Once the current clock cycle is completed, the corresponding phase data group is output as the initial phase data group for the next clock cycle.

9. The apparatus according to any one of claims 1 to 8, characterized in that, The delay time coverage of the multiple delay chains starts from the inherent delay and extends to the inherent delay plus the clock period minus a minimum resolution time, and the delay time interval between adjacent delay chains is equal to the clock period divided by the number of delay chains.

10. A method for generating high-resolution signals, characterized in that, The method includes: Receives multiple signal groups, each of which includes a PWM control signal and a corresponding phase selection signal; Within the current clock cycle, the multiple signal groups are processed sequentially according to priority. For the current signal group to be processed, the current phase data group is determined based on the PWM control signal and the corresponding phase selection signal until all multiple signal groups are processed, thereby obtaining the phase data group within the current clock cycle. The phase data group includes data corresponding to each phase. By using delay chains corresponding to each phase, the data corresponding to each phase is delayed to obtain multi-phase delayed signals; there are multiple delay chains, each corresponding to a different phase and having a different delay time; The multi-channel phase delay signals are XORed to generate a high-resolution PWM signal.

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