A driving circuit of a power device, circuit system and electronic equipment
By alternately driving power devices with dual power supplies, the auxiliary power supply first provides a low-cost voltage to drive them to the critical value, and then the main power supply completes the conduction. This solves the problems of increased circuit cost and reliability caused by high drive requirements in the existing technology, and achieves cost reduction and reliability improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 格威半导体(厦门)有限公司
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies place high demands on the power supply when driving power devices, leading to increased circuit costs and reliability issues.
The system employs a main power supply drive module, an auxiliary power supply drive module, and a switching module. Power devices are driven alternately by dual power supplies. First, the auxiliary power supply provides a low-cost voltage to drive the device to the critical value, and then the main power supply completes the conduction, reducing the driving requirements of the main power supply.
It effectively reduces circuit costs and improves reliability, avoids long-term high-load and high-current operation of the main power supply, and reduces damage to power devices and sensitive components.
Smart Images
Figure CN122496029A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and in particular to a driving circuit, circuit system and electronic device for a power device. Background Technology
[0002] Drive circuits serve as the bridge for control signals to control power devices. Their applications cover almost all fields involving power devices and actuators, including industrial control, consumer electronics, new energy, automotive electronics, and communication power supplies. Their core function is to convert low-voltage control signals into high-voltage drive signals, ensuring stable and efficient equipment operation. Typical applications include: motor drives, power supplies and energy conversion, automotive electronics, industrial control and automation, consumer electronics and lighting, and specialized and emerging fields.
[0003] However, existing technologies place high demands on the driving power supply when driving power devices, which not only significantly increases circuit costs but also raises reliability issues. Summary of the Invention
[0004] The technical problem solved by this invention is how to reduce the driving requirements of the driving power supply during the driving of power devices, so as to reduce circuit costs and improve circuit reliability.
[0005] To solve the above-mentioned technical problems, the present invention provides a driving circuit for a power device, comprising: The main power drive module is configured to output a first power supply voltage to the gate terminal of the power device according to a first enable signal, and to cut off the first power supply voltage according to a first shutdown signal. An auxiliary power drive module is configured to output a second power supply voltage to the gate terminal of the power device according to a second enable signal, and to cut off the second power supply voltage according to a second shutdown signal, wherein the first power supply voltage is a boost voltage of the second power supply voltage; A switching module is configured to, based on a third enable signal, first output a second enable signal and a first disable signal, and detect a first voltage difference between the second power supply voltage and the gate voltage of the power device. If the first voltage difference is greater than a first threshold, the switching module continues to output the second enable signal and the first disable signal; if the first voltage difference is less than or equal to the first threshold, the switching module switches between outputting the first enable signal and the second disable signal. The first threshold represents a critical value at which the second power supply voltage drives the power device.
[0006] Optionally, it also includes: a pull-down module, configured to pull down the gate terminal of the power device according to a fourth enable signal and a first detection signal to turn off the power device; the pull-down module is further configured to stop pulling down the gate terminal of the power device according to a fourth turn-off signal or a second detection signal; A pull-down detection module is used to detect a second voltage difference between the gate voltage and the source voltage of the power device. If the second voltage difference is less than a second threshold, the pull-down detection module outputs a second detection signal; if the second voltage difference is greater than or equal to the second threshold, the pull-down detection module outputs a first detection signal. The second threshold represents the minimum critical value of the gate-source voltage of the power device.
[0007] Optionally, the pull-down module includes a first NMOS transistor and a first AND gate; the drain of the first NMOS transistor is connected to the gate of the power device, the source of the first NMOS transistor is connected to ground, and the gate of the first NMOS transistor is connected to the output of the first AND gate; the first input of the first AND gate is connected to the fourth enable signal or the fourth disable signal, and the second input of the first AND gate is connected to the first detection signal or the second detection signal.
[0008] Optionally, the pull-down detection module includes a first PMOS transistor, a first resistor, a second resistor, a first diode, a second diode, and a buffer; the source of the first PMOS transistor is connected to the gate of the power device and the cathode of the first diode, the gate of the first PMOS transistor is connected to one end of the first resistor and the anode of the first diode, and the drain of the first PMOS transistor is connected to one end of the second resistor and the input of the buffer; the other end of the first resistor is connected to the source of the power device, and the other end of the second resistor is connected to ground; the output of the buffer outputs the second detection signal or the first detection signal; the anode of the second diode is connected to the gate of the power device, and the cathode of the second diode is connected to the source of the power device and the cathode of the first diode.
[0009] Optionally, the auxiliary power drive module includes a second NMOS transistor, a third resistor, a second PMOS transistor, and a first current source; the gate of the second NMOS transistor receives the second enable signal or the second disable signal, the source of the second NMOS transistor is connected to the input terminal of the first current source, the output terminal of the first current source is connected to ground, and the drain of the second NMOS transistor is connected to one end of the third resistor and the gate of the second PMOS transistor; the drain of the second PMOS transistor is connected to the gate terminal of the power device, and the source of the second PMOS transistor and the other end of the third resistor are both connected to the second power supply voltage.
[0010] Optionally, the auxiliary power drive module further includes a third NMOS transistor, a third PMOS transistor, a fourth resistor, and a second current source; the gate of the third NMOS transistor also receives the second enable signal or the second disable signal, the source of the third NMOS transistor is connected to the input terminal of the second current source, the output terminal of the second current source is connected to ground, the drain of the third NMOS transistor is connected to the gate of the third PMOS transistor and one end of the fourth resistor respectively; the other end of the fourth resistor and the source of the third PMOS transistor are both connected to the gate terminal of the power device, and the drain of the third PMOS transistor is connected to the drain of the second PMOS transistor.
[0011] Optionally, the main power supply drive module includes a fourth NMOS transistor, a fourth PMOS transistor, a third current source, and a fifth resistor; the gate of the fourth NMOS transistor is connected to the first enable signal or the first disable signal, the source of the fourth NMOS transistor is connected to the input terminal of the third current source, and the output terminal of the third current source is connected to ground; the drain of the fourth NMOS transistor is connected to one end of the fifth resistor; the other end of the fifth resistor and the source of the fourth PMOS transistor are both connected to the first power supply voltage, and the drain of the fourth PMOS transistor is connected to the gate terminal of the power device.
[0012] Optionally, the switching module includes a sixth resistor, a seventh resistor, a fifth PMOS transistor, an inverter, a Class D flip-flop, a second AND gate, and a third AND gate. One end of the sixth resistor is connected to the source of the third PMOS transistor and the source of the fifth PMOS transistor, respectively, and the other end of the sixth resistor is connected to the gate of the power device and the gate of the fifth PMOS transistor, respectively. The drain of the fifth PMOS transistor is connected to one end of the seventh resistor and the input of the inverter, respectively. The other end of the seventh resistor is connected to ground. The output of the inverter is connected to the first input of the Class D flip-flop. The Class D input of the Class D flip-flop receives a logic high level. The enable terminal of the Class D flip-flop, the first input of the second AND gate, and the first input of the third AND gate are all connected to a third enable signal or a third disable signal. The inverted output of the Class D flip-flop is connected to the second input of the second AND gate, and the non-inverted output of the Class D flip-flop is connected to the second input of the third AND gate. The output of the second AND gate outputs the second enable signal or the second disable signal. The output of the third AND gate outputs the first enable signal or the first disable signal.
[0013] The present invention also provides a circuit system including a driving circuit for the power device.
[0014] The present invention also provides an electronic device, including the aforementioned circuit system.
[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The power device driving circuit provided by this invention includes a switching module that, based on a third enable signal, first outputs a second enable signal to the auxiliary power drive module and a first shutdown signal to the main power drive module. This drives the gate of the power device using a second power supply voltage output from the auxiliary power drive module until a first voltage difference between the second power supply voltage and the gate of the power device is less than or equal to a first threshold, indicating that the second power supply voltage has provided all the driving capability. The switching module then switches to outputting the first enable signal to the main power drive module and the second shutdown signal to the auxiliary power drive module, switching the first power supply voltage to drive the gate of the power device until the power device is fully turned on. Since the first power supply voltage is obtained by boosting the second power supply voltage, this invention first uses the low-cost second power supply voltage to perform the main task of turning on the power device, and then uses the first power supply voltage to complete the power device's conduction. This significantly reduces the requirement for the first power supply voltage to drive the power device, thereby reducing the circuit cost for boosting the second power supply voltage. In addition, by alternating the power devices through dual power supplies, the output current of the main power drive module can be effectively reduced. This not only avoids the main power drive module from operating under high load and high current conditions for a long time, but also prevents high current from damaging the power devices and other sensitive components, thus improving the reliability of the circuit.
[0016] Furthermore, during the power device shutdown process, a second voltage difference between the gate terminal and the ground terminal of the power device is detected by a pull-down detection module. When the second voltage difference is less than a second threshold, the pull-down module is turned off to stop pulling down the gate terminal of the power device. This avoids damage to the power device caused by the gate-source voltage being pulled down too low during the power device shutdown process, thereby further improving the reliability of the power device. Attached Figure Description
[0017] Figure 1 This is a block diagram of the driving circuit of the power device provided in the first embodiment of the present invention; Figure 2 This is a timing diagram of each signal in the driving circuit of the power device provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the driving circuit of the power device provided in the first embodiment of the present invention; Figure 4 This is a block diagram of the driving circuit of the power device provided in the second embodiment of the present invention; Figure 5This is a schematic diagram of the circuit structure of the driving circuit of the power device provided in the second embodiment of the present invention; Figure 6 This is a timing diagram of each signal in the driving circuit of the power device provided in the second embodiment of the present invention. Detailed Implementation
[0018] As described in the background section, existing technologies place high demands on the driving power supply during the driving of power devices, which not only significantly increases circuit costs but also raises reliability issues.
[0019] Regarding the increased circuit cost: In the driver circuit, the output charge, instantaneous current, and load-carrying capacity of the power supply are directly proportional to the target gate-source voltage required to turn on the power transistor. If the power transistor is driven by a single power supply, the power supply needs to complete the gate charge from 0V to the target gate voltage in one go. Especially in scenarios where NMOS transistors are used for high-side driving, the main power supply must provide a large total charge and meet the instantaneous charging current requirements. This places high demands on the output charge capability, instantaneous drive current, and power load-carrying capacity of the driver power supply. These high demands are an inherent characteristic of single-supply topologies and cannot be avoided through simple optimization.
[0020] If the main power supply is provided by a charge pump, then the capacitance of the pump capacitor needs to be increased, the number of boost stages increased, and larger power switching transistors used, directly increasing the cost of hardware components. If the main power supply is provided by other boost topologies, then the energy storage components need to be enlarged, the heat dissipation design optimized, and the complexity of the power control circuit increased, thus increasing design and manufacturing costs.
[0021] In addition, to meet the requirements of high current drive, the overcurrent and overvoltage protection circuits of the power supply need to be strengthened, which further increases the circuit cost.
[0022] Regarding circuit reliability: Because the main power supply operates under high load and high current conditions for a long time, it will cause the power transistors to overheat, reduce efficiency, and even cause problems such as breakdown of the switching transistors in the power supply topology and accelerated aging of capacitors, which will directly reduce the service life of the power supply circuit.
[0023] In addition, high-current fast charging gates are prone to voltage processes and current spikes, which may cause breakdown of the gate oxide layer of the power transistor. At the same time, it will cause serious electromagnetic interference, leading to false triggering of other sensitive components in the circuit, thereby reducing the stability of the entire drive system, and even causing damage to power devices and circuit failures.
[0024] In view of this, the technical solution of the present invention provides a new driving circuit for power devices, including a main power supply driving module, an auxiliary power supply driving module, and a switching module. The switching module first controls the auxiliary power supply driving module to output a second power supply voltage to drive the gate terminal of the power device until the first voltage difference between the second power supply voltage and the gate terminal of the power device is less than or equal to a first threshold, indicating that the second power supply voltage has provided all the driving capability. Therefore, the switching module switches the main power supply driving module to output the first power supply voltage to drive the gate terminal of the power device until the power device is fully turned on. Since the first power supply voltage is obtained by boosting the second power supply voltage, the present invention first uses the low-cost second power supply voltage to undertake the main task of turning on the power device, and then uses the first power supply voltage to complete the turn-on of the power device, thereby greatly reducing the requirement for the first power supply voltage to drive the power device, and thus reducing the circuit cost of boosting the second power supply voltage. In addition, the alternating use of dual power supplies to turn on the power device can effectively reduce the output current of the main power supply driving module, which not only avoids the main power supply driving module from working under high load and high current conditions for a long time, but also avoids damage to the power device and other sensitive components caused by high current, thus improving the reliability of the circuit.
[0025] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.
[0027] [First Embodiment] Please refer to Figure 1 This embodiment provides a driving circuit for a power device, which includes a main power drive module 10, an auxiliary power drive module 20, and a switch switching module 30.
[0028] The main power drive module 10 is used to output a first power supply voltage V2 to the gate terminal G of the power device according to the first enable signal H1_up, and is also used to cut off the first power supply voltage V2 according to the first shutdown signal H1_down.
[0029] The auxiliary power drive module 20 is configured to output a second power supply voltage V1 to the gate terminal G of the power device according to the second enable signal H2_up, and to cut off the second power supply voltage V1 according to the second shutdown signal H2_down, wherein the first power supply voltage V2 is the boost voltage of the second power supply voltage V1.
[0030] The switching module 30 is configured to, based on the third enable signal H3_up, first output the second enable signal H2_up and the first disable signal H1_down, and detect a first voltage difference between the second power supply voltage V1 and the gate voltage of the power device. If the first voltage difference is greater than a first threshold, the switching module 30 maintains the output of the second enable signal H2_up and the first disable signal H1_down; if the first voltage difference is less than or equal to the first threshold, the switching module 30 switches the output of the first enable signal H1_up and the second disable signal H2_down. The first threshold represents the critical value at which the second power supply voltage V1 drives the power device.
[0031] In this embodiment, the power device is an NMOS transistor and is used for high-side driving. Of course, in other embodiments, the power device may also be a transistor or other conventional power switching transistors in the art, and this is not limited thereto.
[0032] Please refer to Figure 2 The following provides a detailed description of the operation of the power device drive circuit in this embodiment to turn on the power device.
[0033] During the t1 to t3 phase: an external third enable signal H3_up (high level) is input to the switch switching module 30. The switch switching module 30 will output the second enable signal H2_up (high level) to the auxiliary power drive module 20 and the first shutdown signal H1_down (low level) to the main power drive module 10 according to the input third enable signal H3_up.
[0034] Therefore, the main power drive module 10 will cut off the output of the first power supply voltage V2 according to the input low level. Meanwhile, the auxiliary power drive module 20 will output the second power supply voltage V1 to the gate terminal G of the power device according to the input high level, in order to start the power device.
[0035] from Figure 2 It can be seen that during the t1 to t2 stage, the gate-source voltage VGS of the power device is gradually charged from 0V to the threshold voltage of the power device by the second power supply voltage V1.
[0036] During the t2 to t3 phase, the power device enters the Miller plateau period to maintain the gate-source voltage VGS of the power device at the threshold voltage of the power device.
[0037] During stages t3 to t5: the switching module 30 detects the first voltage difference between the second power supply voltage V1 and the gate voltage of the power device. At the node of stage t3, the first voltage difference is less than or equal to the first threshold. Therefore, the switching module 30 switches the output of the first enable signal H1_up (i.e., high level) to the main power drive module 10 and the output of the second shutdown signal H2_down to the auxiliary power drive module 20.
[0038] Therefore, the auxiliary power drive module 20 will cut off the output of the second power supply voltage V1 according to the low input level. Meanwhile, the main power drive module 10 will output the first power supply voltage V2 to the gate terminal G of the power device according to the high input level, so as to take over the conduction of the power device from the second power supply voltage V1.
[0039] from Figure 2 It can be seen that during the t3 to t4 stage, the gate-source voltage VGS of the power device is boosted from the threshold voltage of the power device to the turn-on voltage.
[0040] During the t4 to t5 phase, the power device is fully turned on.
[0041] Since the first power supply voltage V2 is obtained by boosting the second power supply voltage V1, this invention first uses the low-cost second power supply voltage V1 to primarily conduct the power devices, ensuring they are turned on up to the Miller plateau. Then, the first power supply voltage V2 is used to turn on the power devices until they are fully operational. This significantly reduces the requirements on the first power supply voltage V2's ability to drive the power devices, thereby reducing the circuit cost for boosting the second power supply voltage V1. Furthermore, alternating power supply cycles effectively reduce the output current of the main power drive module 10, preventing it from operating under high load and high current conditions for extended periods and avoiding damage to the power devices and other sensitive components from high current, thus improving circuit reliability.
[0042] Taking a 48V system as an example, the sum of the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the NMOS transistor is set to 2nF, and the target gate-source voltage VGS for turning on the NMOS transistor is 18V.
[0043] If the NMOS transistor is to be turned on solely through the main power supply, the main power supply needs to be set to 18V. For the NMOS transistor to be fully turned on, the main power supply's output charge capability must be greater than or equal to 18V * 2nF = 36nC.
[0044] If the NMOS transistor is turned on by both the main power drive module 10 and the auxiliary power drive module 20, and the second power supply voltage is set to 12V, and then the second power supply voltage is reduced to the first power supply voltage of 18V, then to raise the gate-source voltage VGS of the NMOS transistor from 0V to 12V, the output charge capability of the second power supply voltage needs to be greater than or equal to 12V × 2nF = 24nC. Next, to raise the gate-source voltage VGS of the NMOS transistor from 12V to 18V to fully turn on the NMOS transistor, the output charge capability of the first power supply voltage only needs to be greater than or equal to (18V - 12V) × 2nF = 12nC.
[0045] Therefore, it is clear that compared to a single main power supply conducting NMOS transistor, the requirement for the first power supply voltage to output charge capability can be effectively reduced by having the main power supply drive module 10 and the auxiliary power supply drive module 20 jointly conduct the NMOS transistor. Since the requirements for power supply output current and output power are directly related to charge, the requirements for the first power supply voltage output current capability and output power capability are also reduced, thereby effectively reducing the circuit cost required to boost the second power supply voltage to the first power supply voltage.
[0046] Please refer to Figure 3In this embodiment, the auxiliary power drive module 20 includes a second NMOS transistor N2, a third resistor R3, a second PMOS transistor P2, and a first current source I1. The gate of the second NMOS transistor N2 is used to receive the second enable signal H2_up or the second disable signal H2_down. The source of the second NMOS transistor N2 is connected to the input terminal of the first current source I1, and the output terminal of the first current source I1 is connected to ground. The drain of the second NMOS transistor N2 is connected to one end of the third resistor R3 and the gate of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the gate terminal G of the power device, i.e., the gate of the NMOS transistor. The source of the second PMOS transistor P2 and the other end of the third resistor R3 are both connected to the second power supply voltage V1.
[0047] Please continue to refer to this. Figure 3 In this embodiment, the auxiliary power drive module 20 further includes a third NMOS transistor N3, a third PMOS transistor P3, a fourth resistor R4, and a second current source I2. The gate of the third NMOS transistor N3 also receives the second enable signal H2_up or the second disable signal H2_down. The source of the third NMOS transistor N3 is connected to the input terminal of the second current source I2, and the output terminal of the second current source I2 is connected to ground. The drain of the third NMOS transistor N3 is connected to the gate of the third PMOS transistor P3 and one end of the fourth resistor R4. The other end of the fourth resistor R4 and the source of the third PMOS transistor P3 are both connected to the gate terminal G of the power device. The drain of the third PMOS transistor P3 is connected to the drain of the second PMOS transistor P2.
[0048] When the second enable signal H2_up (high level) is input to the gates of the second NMOS transistor N2 and the third NMOS transistor N3, both NMOS transistors N2 and N3 are turned on. The currents output from the first current source I1 and the second current source I2 flow through the third resistor R3 and the fourth resistor R4, respectively, to form a sufficiently large on-state voltage between the source and gate of the second PMOS transistor P2 and the third PMOS transistor P3, thereby turning on the second PMOS transistor P2 and the third PMOS transistor P3. After the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, the second power supply voltage V1 is output to the gate terminal G of the power device through the second PMOS transistor P2 and the third PMOS transistor P3 to start turning on the power device.
[0049] Please continue to refer to this. Figure 2 After the second power supply voltage V1 is applied to the gate terminal G of the power device, the corresponding Figure 2In the t1 stage, from t1 to t2, the gate voltage of the power device gradually rises from 0V to the threshold voltage of the power device, during which the power device remains in the off state.
[0050] During the t2 to t3 phase, the power device begins to conduct after its gate voltage reaches its threshold voltage. Due to the parasitic capacitance between the gate and drain of the power device, the gate-source voltage VGS remains near the threshold voltage for a relatively long period, which is the Miller plateau period during power device conduction.
[0051] During the Miller plateau period, the formula for calculating the gate-source voltage VGS of the power device is: VGS=VTH+√((2×ILOAD) / (μn×Cox×w / l)).
[0052] ILOAD represents the current flowing through the power device during the Miller plateau period; μn is the semiconductor electron mobility of the power device; Cox is the gate oxide capacitance per unit area; w is the total equivalent channel width of the power device; and L is the channel length of the power device.
[0053] As the gate voltage of the power device rises to near the second power supply voltage V1, the current flowing through the second NMOS transistor N2 gradually decreases. When the current flowing through the second NMOS transistor N2 decreases to a first voltage difference between the second power supply voltage V1 and the gate voltage of the power device that is less than or equal to a first threshold, the switching module 30 switches between outputting a first enable signal H1_up and a second disable signal H2_down to turn off the second NMOS transistor N2 and the third NMOS transistor N3, thereby switching the connection between the second power supply voltage and the gate G of the power transistor.
[0054] During the process from t1 to t3, the amount of charge that the second power supply voltage V1 charges at the gate terminal G is: QV1 = VGS × CGS + V1 × CGD.
[0055] QV1 represents the amount of charge applied to the gate terminal G by the second power supply voltage V1; CGD represents the gate-drain parasitic capacitance of the power device; CGS represents the gate-source parasitic capacitance of the power device; V1 represents the second power supply voltage V1.
[0056] When the second shutdown signal H2_down, i.e., a low level input, is applied to the gates of the second NMOS transistor N2 and the third NMOS transistor N3, both the second NMOS transistor N2 and the third NMOS transistor N3 are turned off, cutting off the current flowing through the third resistor R3 and the fourth resistor R4. Therefore, the second PMOS transistor P2 and the third PMOS transistor P3 will be turned off because the voltage across their respective gate and source terminals drops to 0, thereby cutting off the connection between the second power supply voltage V1 and the power devices, i.e., stopping the second power supply voltage V1 from driving the power transistors.
[0057] Furthermore, the third PMOS transistor P3 uses its own body diode to achieve reverse flow of the gate voltage of the power device to the second power supply voltage V1. In other embodiments, the third PMOS transistor P3 can also be replaced by a diode, with the positive terminal of the diode connected to the drain of the third PMOS transistor P3 and the negative terminal of the diode connected to the gate G of the power device; this is not limited here.
[0058] It should be noted that since the third NMOS transistor N3, the second current source I2, and the fourth resistor R4 are all driving circuits for the third PMOS transistor P3, when the third PMOS transistor P3 is replaced by a diode, the third NMOS transistor N3, the second current source I2, and the fourth resistor R4 are no longer needed.
[0059] In other embodiments, if the third PMOS transistor P3 is still used as the anti-reverse current device for the second power supply voltage V1, then the first current source I1 and the second current source I2 can both be replaced with resistors, which is not limited here.
[0060] Please continue to refer to this. Figure 3 The main power drive module 10 includes a fourth NMOS transistor N4, a fourth PMOS transistor P4, a third current source I3, and a fifth resistor R5. The gate of the fourth NMOS transistor N4 is connected to the first enable signal H1_up or the first disable signal H1_down. The source of the fourth NMOS transistor N4 is connected to the input terminal of the third current source I3, and the output terminal of the third current source I3 is connected to ground. The drain of the fourth NMOS transistor N4 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 and the source of the fourth PMOS transistor P4 are both connected to the first power supply voltage V2. The drain of the fourth PMOS transistor P4 is connected to the gate terminal G of the power device.
[0061] When the first enable signal H1_up (high level) is input to the gate of the fourth NMOS transistor N4, the fourth NMOS transistor N4 is turned on. The current output from the third current source I3 flows through the fifth resistor R5 to form a sufficiently large on-state voltage between the source and gate of the fourth PMOS transistor P4, thereby turning on the fourth PMOS transistor P4. After the fourth PMOS transistor P4 is turned on, the first power supply voltage V2 is output through the fourth PMOS transistor P4 to the gate terminal G of the power device, replacing the second power supply voltage V1 to turn on the power device, and correspondingly... Figure 2 At time t3 in the data.
[0062] During the t3 to t4 phase, the gate voltage of the power device increases from the second supply voltage V1 to the first supply voltage V2, further reducing the on-resistance of the power device. At time t4, the power device enters the linear region, and the formula for the on-resistance at this time is as follows: RDSON characterizes the on-resistance of power devices.
[0063] During stages t3 to t4, the total charging charge of the power device's control section due to the first power supply voltage V2 is: .
[0064] QV2 represents the amount of charge applied to the gate terminal G by the first power supply voltage V2; V2 represents the first power supply voltage V2.
[0065] For a typical MOS, if CGS=1nF, CGD=1nF, V1=80V, V2=92V, after adopting the scheme of this embodiment, the total charge provided by the main power supply voltage is about 24nC, which is significantly reduced by 77% compared with the 106nC of the traditional scheme, greatly reducing the requirement for the driving capability of the first power supply voltage V2.
[0066] In other embodiments, the third current source I3 may also be replaced by a resistor, which is not limited here.
[0067] Please continue to refer to this. Figure 3The switching module 30 includes a sixth resistor R6, a fifth PMOS transistor P5, an inverter Inv1, a Class D flip-flop DFF, a second AND gate AND2, and a third AND gate AND3. One end of the sixth resistor R6 is connected to the source of the third PMOS transistor P3 and the source of the fifth PMOS transistor P5, respectively. The other end of the sixth resistor R6 is connected to the gate G of the power device and the gate of the fifth PMOS transistor P5, respectively. The drain of the fifth PMOS transistor P5 is connected to one end of the seventh resistor R7 and the input of the inverter Inv1, respectively. The other end of the seventh resistor R7 is connected to ground. The output of the inverter Inv1 is connected to the first input of the Class D flip-flop DFF. The Class D input of the Class D flip-flop DFF receives a logic high level. The enable terminal of the Class D flip-flop (DFF), the first input terminal of the second AND gate AND2, and the first input terminal of the third AND gate AND3 are all connected to the third enable signal H3_up (high level) or the third disable signal H3_down H2_down (low level). The inverted output terminal of the Class D flip-flop (DFF) is connected to the second input terminal of the second AND gate AND2, and the non-inverted output terminal of the Class D flip-flop (DFF) is connected to the second input terminal of the third AND gate AND3. The output terminal of the second AND gate AND2 outputs the second enable signal H2_up or the second disable signal H2_down. The output terminal of the third AND gate AND3 outputs the first enable signal H1_up or the first disable signal H1_down.
[0068] The charging current from the second power supply voltage V1 to the gate terminal G of the power device flows through the sixth resistor R6, creating a voltage difference across R6. This voltage difference serves as the gate-source voltage of the fifth PMOS transistor P5. Since the voltage difference between the second power supply voltage V1 and the gate voltage of the power device is sufficiently large during the initial conduction phase (i.e., the gate-source voltage of the fifth PMOS transistor P5 is sufficiently large), PMOS transistor P5 operates in the saturation region. According to the formula for PMOS transistor drain current, the gate-source voltage VGS of PMOS transistor P5 is proportionally converted into a corresponding drain current that flows through the seventh resistor R7. The drain current flowing through the seventh resistor R7 generates a high-level input threshold higher than that of the inverter Inv1, causing the inverter Inv1 to output a low level to the first input terminal of the Class D flip-flop DFF.
[0069] Since the enable terminal of the Class D flip-flop (DFF) receives a high level (H3_up), the DFF is reset normally. The Class D input of the DFF is high, and the first input is low (no rising edge). Therefore, according to the working principle of the DFF, its non-inverting output is low, connected to the second input of the third AND gate (AND3), and its inverting output is high, connected to the second input of the second AND gate (AND2). Furthermore, since both the first inputs of the second AND gate (AND2) and the third AND gate (AND3) receive the third enable signal H3_up, the second AND gate (AND2) outputs a high level (H2_up) to the gates of the second NMOS transistor (N2) and the third NMOS transistor (N3), while the third AND gate (AND3) outputs a low level (H1_down) to the gate of the fourth NMOS transistor (N4).
[0070] As the gate voltage of the power device increases, the current flowing through the sixth resistor R6 gradually decreases, causing the voltage across the sixth resistor R6, i.e., the gate-source voltage VGS of the fifth PMOS transistor P5, to continuously decrease. This, in turn, reduces the drain current of the fifth PMOS transistor P5 until the drain voltage of the fifth PMOS transistor P5, i.e., the input voltage of the inverter Inv1, drops below the high-level input threshold. At this point, the inverter Inv1 outputs a high level to the first input of the Class D flip-flop DFF. This also indicates that the voltage difference between the second power supply voltage V1 and the gate voltage of the power device is less than or equal to the first threshold, or it can be understood that they are almost equal.
[0071] Because of the rising edge input, the non-inverting input of the Class D flip-flop (DFF) is reversed from a low output level to a high output level, and the inverting input of the Class D flip-flop (DFF) is reversed from a high output level to a low output level. Therefore, the second AND gate AND2 outputs a low level, which is the second turn-off signal H2_down, and the third AND gate AND3 outputs a high level, which is the first enable signal H1_up.
[0072] [Second Embodiment] This embodiment is a supplementary embodiment to the first embodiment. Please refer to it. Figure 4 In this embodiment, a pull-down module 40 and a pull-down detection module 50 are additionally provided on the basis of the first embodiment to realize the pull-down shutdown of the power device.
[0073] The pull-down module 40 is used to pull down the gate terminal G of the power device according to the fourth enable signal L1_up and the first detection signal D1 to turn off the power device; the pull-down module 40 is also used to stop pulling down the gate terminal G of the power device according to the fourth turn-off signal L1_down or the second detection signal D2.
[0074] The pull-down detection module 50 is used to detect a second voltage difference between the gate voltage and the source voltage S of the power device. If the second voltage difference is less than a second threshold, the pull-down detection module 50 outputs the second detection signal D2; if the second voltage difference is greater than or equal to the second threshold, the pull-down detection module 50 outputs the first detection signal D1. The second threshold represents the minimum critical value of the gate-source voltage VGS of the power device.
[0075] Please refer to Figure 5 In this embodiment, the pull-down module 40 includes a first NMOS transistor and a first AND gate AND1; the drain of the first NMOS transistor is connected to the gate G of the power device, the source of the first NMOS transistor is connected to ground, and the gate of the first NMOS transistor is connected to the output of the first AND gate AND1; the first input of the first AND gate AND1 is connected to the fourth enable signal L1_up or the fourth disable signal L1_down, and the second input of the first AND gate AND1 is connected to the first detection signal D1 or the second detection signal D2.
[0076] Please refer to Figure 6 When the power device is turned off, i.e. Figure 6 At time t5, the first input of the first AND gate AND1 is connected to the fourth enable signal L1_up (high level). If the second input of the first AND gate AND1 is connected to the first detection signal D1 (high level), then the first AND gate AND1 outputs a high level to the gate of the first NMOS transistor to turn on the first NMOS transistor, thereby pulling down the gate G of the power device to ground. If the second input of the first AND gate AND1 is connected to the second detection signal D2 (low level), then the first AND gate AND1 outputs a low level to the first NMOS transistor to turn off the first NMOS transistor, thereby stopping the pull-down of the gate G of the power device to ground.
[0077] Please continue to refer to this. Figure 5In this embodiment, the pull-down detection module 50 includes a first PMOS transistor P1, a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, and a buffer Buf1. The source of the first PMOS transistor P1 is connected to the gate terminal G of the power device and the cathode of the first diode D1, respectively. The gate of the first PMOS transistor P1 is connected to one end of the first resistor R1 and the anode of the first diode D1, respectively. The drain of the first PMOS transistor P1 is connected to one end of the second resistor R2 and the input terminal of the buffer Buf1, respectively. The other end of the first resistor R1 is connected to the source terminal S of the power device, and the other end of the second resistor R2 is connected to ground. The output terminal of the buffer Buf1 outputs the second detection signal D2 or the first detection signal D1. The anode of the second diode D2 is connected to the gate of the power device, and the cathode of the second diode D2 is connected to the source of the power device and the cathode of the first diode D1, respectively.
[0078] When the voltage difference between the gate terminal G and the source terminal S of the power device is greater than or equal to the second threshold, in this embodiment, the second threshold is equal to the sum of the forward voltage of the second diode D2 and the threshold voltage of the first PMOS transistor P1. The source-gate voltage of the first PMOS transistor P1 is greater than or equal to the threshold voltage of the first PMOS transistor P1. Therefore, the first PMOS transistor P1 is turned on, thereby pulling up the drain of the first PMOS transistor P1 so that the buffer Buf1 outputs a high level, i.e., the first detection signal D1.
[0079] When the voltage difference between the gate terminal G and the source terminal S of the power device is less than the second threshold, the source-gate voltage of the first PMOS transistor P1 is less than the threshold voltage of the first PMOS transistor P1. Therefore, the first PMOS transistor P1 is turned off, thereby causing the second resistor R2 to pull down the drain of the first PMOS transistor P1, so that the buffer Buf1 outputs a low level, i.e., the second detection signal D2.
[0080] Please continue to refer to this. Figure 6 During the t5 to t6 phase, the first NMOS transistor is turned on to pull down the gate terminal G of the power device, thus causing the gate-source voltage VGS of the power device to decrease.
[0081] At time t6, the gate-source voltage VGS of the power device is less than the forward voltage of the second diode D2 and the threshold voltage of the second NMOS transistor N2, i.e., less than the second threshold. Therefore, the second NMOS transistor N2 is turned off, causing the buffer Buf1 to output a low level to the first AND gate AND1, thereby turning off the first NMOS transistor and stopping the pull-down of the power device, thus preventing the power device from being damaged due to the excessively low gate-source voltage VGS. Therefore, from t6 to t7, the gate-source voltage VGS of the power device gradually increases. Until time t7, the gate-source voltage VGS of the power device is greater than or equal to the second threshold, then the second NMOS transistor N2 is turned on again, causing the buffer Buf1 to output a high level to the first AND gate AND1, thereby turning on the first NMOS transistor and restoring the pull-down of the gate G of the power device.
[0082] Therefore, during the t7 to t8 phase, the first NMOS transistor is in an alternating cycle of being turned on and off, so that the gate-source voltage VGS of the power device keeps repeating the fluctuations of the t5 to t7 phase until the power device is completely turned off.
[0083] In other embodiments, the buffer may be replaced with a comparator, which is not limited here.
[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A driving circuit of a power device, characterized by comprising: include: The main power drive module is configured to output a first power supply voltage to the gate terminal of the power device according to a first enable signal, and to cut off the first power supply voltage according to a first shutdown signal. An auxiliary power drive module is configured to output a second power supply voltage to the gate terminal of the power device according to a second enable signal, and to cut off the second power supply voltage according to a second shutdown signal, wherein the first power supply voltage is a boost voltage of the second power supply voltage; A switching module is configured to, based on a third enable signal, first output a second enable signal and a first disable signal, and detect a first voltage difference between the second power supply voltage and the gate voltage of the power device. If the first voltage difference is greater than a first threshold, the switching module continues to output the second enable signal and the first disable signal; if the first voltage difference is less than or equal to the first threshold, the switching module switches between outputting the first enable signal and the second disable signal. The first threshold represents a critical value at which the second power supply voltage drives the power device.
2. The driving circuit of a power device according to claim 1, wherein Also includes: A pull-down module is used to pull down the gate terminal of the power device according to a fourth enable signal and a first detection signal to turn off the power device; The pull-down module is also used to stop pulling down the gate terminal of the power device according to the fourth shutdown signal or the second detection signal; A pull-down detection module is used to detect a second voltage difference between the gate voltage and the source voltage of the power device. If the second voltage difference is less than a second threshold, the pull-down detection module outputs the second detection signal. If the second voltage difference is greater than or equal to the second threshold, the pull-down detection module outputs the first detection signal, and the second threshold represents the minimum critical value of the gate-source voltage of the power device.
3. The driving circuit of a power device according to claim 2, wherein The pull-down module includes a first NMOS transistor and a first AND gate; the drain of the first NMOS transistor is connected to the gate of the power device, the source of the first NMOS transistor is connected to ground, and the gate of the first NMOS transistor is connected to the output of the first AND gate; the first input of the first AND gate is connected to the fourth enable signal or the fourth disable signal, and the second input of the first AND gate is connected to the first detection signal or the second detection signal.
4. The driving circuit of a power device according to claim 2, wherein The pull-down detection module includes a first PMOS transistor, a first resistor, a second resistor, a first diode, a second diode, and a buffer. The source of the first PMOS transistor is connected to the gate of the power device and the cathode of the first diode. The gate of the first PMOS transistor is connected to one end of the first resistor and the anode of the first diode. The drain of the first PMOS transistor is connected to one end of the second resistor and the input of the buffer. The other end of the first resistor is connected to the source of the power device, and the other end of the second resistor is connected to ground. The output of the buffer outputs either the second detection signal or the first detection signal. The anode of the second diode is connected to the gate of the power device, and the cathode of the second diode is connected to the source of the power device and the cathode of the first diode.
5. The driving circuit of a power device according to claim 1, wherein The auxiliary power drive module includes a second NMOS transistor, a third resistor, a second PMOS transistor, and a first current source. The gate of the second NMOS transistor receives the second enable signal or the second disable signal. The source of the second NMOS transistor is connected to the input terminal of the first current source, and the output terminal of the first current source is connected to ground. The drain of the second NMOS transistor is connected to one end of the third resistor and the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the gate terminal of the power device. The source of the second PMOS transistor and the other end of the third resistor are both connected to the second power supply voltage.
6. The driving circuit of a power device according to claim 5, wherein The auxiliary power drive module further includes a third NMOS transistor, a third PMOS transistor, a fourth resistor, and a second current source; the gate of the third NMOS transistor also receives the second enable signal or the second disable signal, the source of the third NMOS transistor is connected to the input terminal of the second current source, the output terminal of the second current source is connected to ground, the drain of the third NMOS transistor is connected to the gate of the third PMOS transistor and one end of the fourth resistor respectively; the other end of the fourth resistor and the source of the third PMOS transistor are both connected to the gate terminal of the power device, and the drain of the third PMOS transistor is connected to the drain of the second PMOS transistor.
7. The driving circuit of a power device according to claim 1, wherein The main power drive module includes a fourth NMOS transistor, a fourth PMOS transistor, a third current source, and a fifth resistor. The gate of the fourth NMOS transistor is connected to the first enable signal or the first disable signal. The source of the fourth NMOS transistor is connected to the input terminal of the third current source, and the output terminal of the third current source is connected to ground. The drain of the fourth NMOS transistor is connected to one end of the fifth resistor. The other end of the fifth resistor and the source of the fourth PMOS transistor are both connected to the first power supply voltage, and the drain of the fourth PMOS transistor is connected to the gate terminal of the power device.
8. The driving circuit of a power device according to claim 1, wherein The switching module includes a sixth resistor, a seventh resistor, a fifth PMOS transistor, an inverter, a Class D flip-flop, a second AND gate, and a third AND gate. One end of the sixth resistor is connected to the source of the third PMOS transistor and the source of the fifth PMOS transistor, respectively, and the other end of the sixth resistor is connected to the gate of the power device and the gate of the fifth PMOS transistor, respectively. The drain of the fifth PMOS transistor is connected to one end of the seventh resistor and the input of the inverter, respectively. The other end of the seventh resistor is connected to ground. The output of the inverter is connected to the first input of the Class D flip-flop. The Class D input of the Class D flip-flop receives a logic high level. The enable terminal of the Class D flip-flop, the first input of the second AND gate, and the first input of the third AND gate are all connected to a third enable signal or a third disable signal. The inverted output of the Class D flip-flop is connected to the second input of the second AND gate, and the non-inverted output of the Class D flip-flop is connected to the second input of the third AND gate. The output of the second AND gate outputs the second enable signal or the second disable signal. The output of the third AND gate outputs the first enable signal or the first disable signal.
9. Circuitry, characterized by Includes the circuit system described in any one of claims 1 to 7.
10. An electronic device, comprising: Includes the circuit system described in claim 9.