ESD and ovp cooperative protection circuit and electronic device

Abstract

This application provides an ESD and OVP collaborative protection circuit and electronic device. The ESD and OVP collaborative protection circuit includes: a high-voltage isolation module, with its first and second terminals electrically connected to the protected circuit module, its power supply terminal electrically connected to a voltage source, its third terminal serving as a DM terminal, and its fourth terminal serving as a DP terminal; an OVP detection module, with its first terminal electrically connected to both the DM terminal and a low-speed signal transmitter, its second terminal electrically connected to both the DP terminal and the low-speed signal transmitter, and its third terminal electrically connected to the state machine port inside the chip; and an ESD collaborative protection module. This solves the problem of traditional OVP failure in this state, making it difficult to guarantee ESD and internal circuit safety under overvoltage.

Description

Technical Field

[0001] This application relates to high-speed interface circuit protection, and more specifically, to an ESD and OVP co-protection circuit and electronic device. Background Technology

[0002] For over-voltage protection (OVP) of embedded USB 2.0 (eUSB2) repeaters, the eUSB2 Repeater acts as a voltage and data conversion bridge between eUSB2 (1.2V) and USB 2.0 (3.3V). Since DP and DM are external interface pins that need to be plugged and unplugged from external devices, its external interface DP / DM needs to withstand 5V to cope with the risk of VBUS short circuit. However, the maximum power supply voltage of eUSB2 Repeater is usually 3.3V. Therefore, the device selected for this chip (the semiconductor device used inside the chip) usually also has a withstand voltage of 3.3V.

[0003] Existing OVP (Operational Voltage Detection) solutions are based on operational amplifiers and have two major drawbacks: First, ESD protection devices are prone to thermal runaway during 24-hour stress tests and lack a coordination mechanism with OVP; second, external current can cause backflow through the pins of DP and DM, leading to chip malfunctions, especially when the chip is not powered on. Traditional OVP fails in the event of backflow, making it difficult to guarantee ESD and internal circuit safety during overvoltage. Summary of the Invention

[0004] The main objective of this application is to provide an ESD and OVP collaborative protection circuit and electronic device, so as to at least solve the problem that traditional OVP fails in this state and it is difficult to guarantee the safety of ESD and internal circuits under overvoltage.

[0005] To achieve the above objectives, according to one aspect of this application, an ESD and OVP collaborative protection circuit is provided. The ESD and OVP collaborative protection circuit includes: a high-voltage isolation module having a first terminal, a second terminal, a power supply terminal, a third terminal, and a fourth terminal; the first and second terminals of the high-voltage isolation module are electrically connected to the protected circuit module, the power supply terminal of the high-voltage isolation module is electrically connected to a voltage source, the third terminal of the high-voltage isolation module serves as a DM terminal, and the fourth terminal of the high-voltage isolation module serves as a DP terminal; an OVP detection module having a first terminal, a second terminal, and a third terminal; the first terminal of the OVP detection module is electrically connected to the DM terminal and a low-speed signal transmitting terminal, the second terminal of the OVP detection module is electrically connected to the DP terminal and the low-speed signal transmitting terminal, and the third terminal of the OVP detection module is used for electrical connection to a state machine port inside the chip; and an ESD collaborative protection module having a first terminal, a second terminal, and a power supply terminal; the first terminal of the ESD collaborative protection module is electrically connected to the DM terminal, the ESD collaborative protection module is electrically connected to the DP terminal, and the power supply terminal of the ESD collaborative protection module is electrically connected to the voltage source.

[0006] Optionally, the high-voltage isolation module includes: a first resistor module, a first transistor, and a second transistor. A first terminal of the first resistor module is electrically connected to the voltage source, a second terminal of the first resistor module is electrically connected to the gate of the first transistor, the source of the first transistor and the source of the second transistor are respectively electrically connected to the protected circuit module, the drain of the second transistor serves as the DP terminal, and the drain of the first transistor serves as the DM terminal.

[0007] Optionally, the first resistor module includes: a plurality of resistors connected in parallel or in series.

[0008] Optionally, the OVP detection module includes: a first voltage divider module, a second voltage divider module, a first voltage comparator, a second voltage comparator, and an OR gate. The first terminal of the first voltage divider module is electrically connected to the DM terminal, and the second terminal of the first voltage divider module is electrically connected to the non-inverting input terminal of the first voltage comparator. Reference voltages are respectively input to the inverting input terminals of the first and second voltage comparators. The first terminal of the second voltage comparator is electrically connected to the DP terminal, and the second terminal of the second voltage comparator is electrically connected to the non-inverting input terminal of the second voltage comparator. The output terminal of the first voltage comparator is electrically connected to the first input terminal of the OR gate, and the output terminal of the second voltage comparator is electrically connected to the second input terminal of the OR gate. The output terminal of the OR gate is electrically connected to the state machine port inside the chip.

[0009] Optionally, the first voltage divider module includes a second resistor module and a third resistor module. The first end of the second resistor module is electrically connected to the DM terminal, and the second end of the second resistor module is electrically connected to the first end of the third resistor module and the non-inverting input terminal of the first voltage comparator, respectively. The second end of the third resistor module is used for grounding.

[0010] Optionally, the second voltage divider module includes a fourth resistor module and a fifth resistor module. The first terminal of the fourth resistor module is electrically connected to the DP terminal, and the second terminal of the fourth resistor module is electrically connected to the first terminal of the fifth resistor module and the non-inverting input terminal of the second voltage comparator, respectively. The second terminal of the fifth resistor module is used for grounding.

[0011] Optionally, the ESD collaborative protection module includes: a first diode, a second diode, a third diode, a first voltage regulator module, a second voltage regulator module, and a discharge module. The positive terminal of the third diode is electrically connected to the voltage source. The negative terminals of the first diode and the second diode are respectively used for grounding. The positive terminal of the first diode is electrically connected to the DP terminal and the positive terminal of the first voltage regulator module. The positive terminal of the second diode is electrically connected to the DM terminal and the positive terminal of the second voltage regulator module. The negative terminal of the first voltage regulator module is electrically connected to the negative terminal of the second voltage regulator module, the discharge module, and the negative terminal of the third diode. The first voltage regulator module and the second voltage regulator module each include multiple diodes connected in series.

[0012] Optionally, the discharge module includes: a filter module, an inverter, and a third transistor. The first terminal of the filter module is electrically connected to the negative terminal of the first diode and the drain of the third transistor, respectively. The second terminal of the filter module is electrically connected to the input terminal of the inverter. The output terminal of the inverter is electrically connected to the gate of the third transistor. The source of the third transistor and the third terminal of the filter module are used for grounding.

[0013] Optionally, the filtering module includes a filtering resistor module and a filtering capacitor module. The first end of the filtering resistor module serves as the first end of the filtering module. The second end of the filtering resistor module is electrically connected to the first end of the filtering capacitor module and the input end of the inverter, respectively. The second end of the filtering capacitor module is used for grounding.

[0014] According to another aspect of this application, an electronic device is provided, comprising: any of the ESD and OVP co-protection circuits described herein.

[0015] By applying the technical solution of this application, overvoltage detection and physical protection are separated through structural decoupling: when the chip is not powered on, passive clamping and reverse current blocking are achieved using series diodes and voltage regulator structures, preventing external current from flowing back into the chip without power supply; after the chip is powered on, the OVP detection module starts up, working in conjunction with the isolating switch and protection circuit to actively cut off the overvoltage path. The two work independently and are seamlessly connected, which not only protects against the risk of current backflow in the power-off state, but also achieves intelligent collaborative protection in the power-on state. That is, when OVP_OUT=1, the high-speed TX terminal impedance is cut off, reducing the amplitude of the reverse current; at the same time, the clamping voltage of the ESD module is stabilized in the safe range, avoiding diode thermal failure due to large current surges, thus solving the problem that traditional OVP fails in this state and cannot guarantee the safety of ESD and internal circuits during overvoltage. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic diagram of an ESD and OVP collaborative protection circuit provided in an embodiment of this application is shown;

[0018] Figure 2 A schematic diagram of a high-voltage isolation module provided according to an embodiment of this application is shown;

[0019] Figure 3 A schematic diagram of an OVP detection module provided according to an embodiment of this application is shown;

[0020] Figure 4 A schematic diagram of an ESD collaborative protection module provided according to an embodiment of this application is shown;

[0021] Figure 5 A schematic diagram of the protected structure provided according to an embodiment of this application is shown;

[0022] Figure 6 A schematic diagram of an FS / LS DRV provided according to an embodiment of this application is shown;

[0023] Figure 7 A schematic diagram of a working rate selection module provided according to an embodiment of this application is shown.

[0024] The above figures include the following reference numerals:

[0025] 100. High-voltage isolation module; 200. OVP detection module; 300. ESD collaborative protection module; 310. Discharge module; 400. Protected circuit module; 410. Protected structure; 420. FS / LS DRV. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] As described in the background section, existing OVP (Optical Voltage Detection) schemes are based on operational amplifiers and have two major drawbacks: first, ESD protection devices are prone to thermal runaway during 24-hour stress tests and lack a collaborative mechanism with OVP; second, external current can cause backflow through the pins of DP and DM, leading to chip malfunctions, especially when the chip is not powered on. Traditional OVPs fail under backflow conditions, making it difficult to guarantee ESD and internal circuit safety during overvoltage. To address the problem of traditional OVPs failing in this state and failing to guarantee ESD and internal circuit safety during overvoltage, embodiments of this application provide an ESD and OVP collaborative protection circuit and electronic device.

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] This application provides a collaborative protection circuit for ESD and OVP, such as Figure 1As shown, the ESD and OVP collaborative protection circuit includes: a high-voltage isolation module 100, an OVP detection module 200, an ESD collaborative protection module 300, and a protected circuit module 400. The high-voltage isolation module has a first terminal, a second terminal, a power supply terminal, a third terminal, and a fourth terminal. The first and second terminals of the high-voltage isolation module are electrically connected to the protected circuit module, respectively. The power supply terminal of the high-voltage isolation module is electrically connected to a voltage source. The third terminal of the high-voltage isolation module serves as the DM terminal, and the fourth terminal of the high-voltage isolation module serves as the DP terminal. The OVP detection module 200 has a first terminal, a second terminal, and a fourth terminal. The third terminal of the OVP detection module is electrically connected to the DM terminal and the low-speed signal transmitting terminal, respectively. The second terminal of the OVP detection module is electrically connected to the DP terminal and the low-speed signal transmitting terminal, respectively. The third terminal of the OVP detection module is used to electrically connect to the state machine port inside the chip. The ESD collaborative protection module 300 has a first terminal, a second terminal and a power supply terminal. The first terminal of the ESD collaborative protection module is electrically connected to the DM terminal. The ESD collaborative protection module is electrically connected to the DP terminal. The power supply terminal of the ESD collaborative protection module is electrically connected to the voltage source.

[0032] By decoupling the structure, overvoltage detection and physical protection are separated: when the chip is not powered on, passive clamping and reverse current blocking are achieved using series diodes and voltage regulator structures, preventing external current from flowing back into the chip without power supply; after the chip is powered on, the OVP detection module starts up, working in conjunction with the isolating switch and protection circuit to actively cut off the overvoltage path and enhance ESD discharge. The two work independently and are seamlessly connected, ensuring safety protection in the power-off state and realizing intelligent collaborative protection in the power-on state. That is, when OVP_OUT=1, the high-speed TX termination impedance is cut off, reducing the reverse current amplitude; at the same time, the clamping voltage of the ESD module is stabilized in the safe range, avoiding diode thermal failure due to large current impact, thus solving the problem that traditional OVP fails in this state and cannot guarantee ESD and internal circuit safety during overvoltage.

[0033] Optionally, such as Figure 2 As shown, the high-voltage isolation module 100 includes: a first resistor module R1, a first transistor Mn0, and a second transistor Mn1. The first terminal of the first resistor module is electrically connected to the voltage source VCC, the second terminal of the first resistor module is electrically connected to the gate of the first transistor, the source of the first transistor and the source of the second transistor are respectively electrically connected to the protected circuit module, the drain of the second transistor serves as the DP terminal, and the drain of the first transistor serves as the DM terminal.

[0034] By connecting the sources of the first and second transistors to the DP and DM signal paths of the internal protected circuit module, respectively, and using their drains as external interface terminals (DM and DP), and with the gates uniformly biased to a 3.3V power supply by the first resistor module, the transistor source voltage is naturally clamped below the difference between VDD and Vth (approximately 2.5V) when an external 5V overvoltage occurs. This effectively blocks the high voltage from being conducted to the internal low-voltage circuit, achieving bidirectional isolation protection for sensitive devices inside the eUSB2 chip. This structure uses thick-gate oxide NMOS devices with an on-resistance of less than 3Ω, and the device size and layout are optimized according to the requirements of high-speed differential signal transmission. This ensures good impedance matching, low signal attenuation, and rise / fall times that meet the USB 2.0 specification (e.g., 480Mbps rate) when DP / DM is in the on state, avoiding communication errors caused by delays or reflections introduced by the isolation structure. When the chip is not powered on (VDD=0), the first resistor module disconnects the gate bias path, causing the first and second transistors to turn off naturally, forming a high-resistivity isolation barrier. This completely blocks the reverse current path of the external 5V voltage flowing into the chip through the DP / DM port, solving the problem of traditional OVP failure in the absence of power.

[0035] Optionally, the first resistor module mentioned above includes: multiple resistors connected in parallel or in series.

[0036] Optionally, such as Figure 3 As shown, the OVP detection module 200 includes: a first voltage divider module (composed of a second resistor module R2 and a third resistor module R3), a second voltage divider module (composed of a fourth resistor module R4 and a fifth resistor module R5), a first voltage comparator Q1, a second voltage comparator Q2, and an OR gate Q3. The first terminal of the first voltage divider module is electrically connected to the DM terminal, and the second terminal of the first voltage divider module is electrically connected to the non-inverting input terminal of the first voltage comparator. The inverting input terminals of the first voltage comparator and the second voltage comparator are respectively input with reference voltage Vref. The first terminal of the second voltage comparator is electrically connected to the DP terminal, and the second terminal of the second voltage comparator is electrically connected to the non-inverting input terminal of the second voltage comparator. The output terminal of the first voltage comparator is electrically connected to the first input terminal of the OR gate, and the output terminal of the second voltage comparator is electrically connected to the second input terminal of the OR gate. The output terminal OVP_OUT of the OR gate is electrically connected to the state machine port inside the chip.

[0037] Independent voltage sampling and comparison are performed on the DP and DM signal lines to avoid protection blind spots caused by single-channel failure. This ensures that overvoltage at either port can be detected in a timely manner, significantly improving the system's fault tolerance in single-ended faults or asymmetrical overvoltage scenarios. By setting a unified reference voltage Vref, both channels have the same and stable overvoltage detection threshold (e.g., 4.2V). Combined with a hysteresis mechanism, it can accurately identify real overvoltage events and effectively suppress false actions caused by signal jitter, power supply noise, or common-mode interference. When either channel detects overvoltage, it outputs a high level, which is immediately triggered by an OR gate after merging. This eliminates the need to wait for simultaneous overvoltage at both ends, achieving a "first-come, first-served" rapid response strategy, greatly shortening the protection action delay, especially ensuring chip safety under extreme conditions such as sudden VBUS short circuits. In actual insertion and removal processes, DP or DM may only withstand high voltage at one end due to poor contact, static electricity accumulation, or cable short circuits. Traditional dual-ended linkage detection is prone to failure. This solution can independently respond to anomalies at either end, significantly improving protection coverage in asymmetrical fault environments. Requires only two voltage divider networks, two comparators, and one OR gate, resulting in a simple circuit structure, small footprint, and no need for complex state machines or digital logic processing, thus reducing static power consumption. It is also compatible with CMOS processes, making it suitable for integration into high-density eUSB2 Repeater chips. The OR gate output is directly connected to the chip's internal state machine as a global protection enable signal, which can uniformly control isolating switches, termination impedance cutoff, TX module shutdown, and ESD path activation, achieving an integrated "detection-decision-execution" closed loop and improving system-level protection coordination and response consistency.

[0038] Optionally, such as Figure 3 As shown, the first voltage divider module includes a second resistor module R2 and a third resistor module R3. The first terminal of the second resistor module is electrically connected to the DM terminal, and the second terminal of the second resistor module is electrically connected to the first terminal of the third resistor module and the non-inverting input terminal of the first voltage comparator. The second terminal of the third resistor module is grounded. The second voltage divider module includes a fourth resistor module R4 and a fifth resistor module R5. The first terminal of the fourth resistor module is electrically connected to the DP terminal, and the second terminal of the fourth resistor module is electrically connected to the first terminal of the fifth resistor module and the non-inverting input terminal of the second voltage comparator. The second terminal of the fifth resistor module is grounded.

[0039] By connecting a high-resistance second resistor module and a lower-resistance third resistor module in series to form a voltage divider network, an external high voltage (such as 5V) can be safely and proportionally attenuated to a low level range that the comparator can handle without significantly loading the DP / DM signal path, thereby achieving accurate monitoring of the high voltage state. Simultaneously, this voltage divider structure effectively isolates the direct impact of high voltage on the comparator input, improving circuit reliability and anti-interference capabilities. Furthermore, since the third resistor module is grounded, the voltage divider reference point is stabilized at ground potential, ensuring accurate and drift-free threshold judgment by the comparator, which helps improve the accuracy and consistency of OVP detection. This structure also facilitates the subsequent introduction of a hysteresis mechanism. By dynamically adjusting the equivalent resistance of the second resistor module (e.g., in conjunction with a feedback circuit), precise control of the upper and lower thresholds can be achieved, avoiding frequent false triggers caused by signal ringing or power supply noise, thereby enhancing the system's stability and robustness in complex electromagnetic environments.

[0040] Optionally, such as Figure 4 As shown, the aforementioned ESD collaborative protection module includes: a first diode D1, a second diode D2, a third diode D3, a first voltage regulator module (composed of diodes D4, D5, and D6), a second voltage regulator module (composed of diodes D7, D8, and D9), and a discharge module 310. The positive terminal of the third diode is electrically connected to the voltage source VCC. The negative terminals of the first and second diodes are respectively used for grounding. The positive terminal of the first diode is electrically connected to the DP terminal and the positive terminal of the first voltage regulator module. The positive terminal of the second diode is electrically connected to the DM terminal and the positive terminal of the second voltage regulator module. The negative terminal of the first voltage regulator module is electrically connected to the negative terminal of the second voltage regulator module, the discharge module, and the negative terminal of the third diode. The first and second voltage regulator modules each include multiple diodes connected in series.

[0041] The first and second diodes are connected in series between the DP / DM terminal and ground, forming a unidirectional conduction path to prevent the external 5V high voltage from flowing back into the chip's internal VDD or ground through the DP / DM. Simultaneously, their forward voltage drop (approximately 0.7V / stage), connected in series with the voltage regulator module, completely blocks the current path when the circuit is not powered on or under abnormal power supply conditions, preventing external energy from entering sensitive circuits. The first and second voltage regulator modules consist of multiple series-connected diodes, forming a multi-stage voltage drop structure. When the DP / DM terminal experiences a 5V overvoltage, the cumulative voltage drop of the series diodes effectively limits the clamping node voltage to approximately 2.9V (5V - 3 × 0.7V), far below the breakdown voltage of internal low-voltage devices (such as 3.3V process devices), significantly reducing the risk of transistor failure due to overvoltage breakdown or hot carrier effects. The third diode is connected between VDD and the clamping node. When an ESD event occurs, if the clamping voltage is higher than VDD, this diode conducts, providing a low-impedance discharge path for the ESD current from DP / DM through the voltage regulator module to VDD and then to ground. This prevents current from being forced through an internal high-impedance path, effectively dispersing energy, reducing local temperature rise, and improving ESD immunity. In the chip's off-state, this structure naturally blocks external current due to the unidirectional conductivity of the diodes. After the chip is powered on, the voltage regulator module and the third diode work together to achieve active clamping and energy discharge. A smooth transition from "no-power protection" to "power-on protection" can be achieved without external power supply control, realizing true full-state (Power-Off / Power-On) collaborative protection. By designing the voltage regulator module as a multi-stage series diode instead of a single voltage regulator device, the process compatibility issues of dedicated Zener diodes under high-voltage processes are avoided. This also improves the structure's tolerance to process deviations, temperature drift, and aging effects, enhancing the long-term stability of the circuit under complex environments (such as high temperature, high humidity, and long-term stress).

[0042] Optionally, such as Figure 4 As shown, the discharge module includes: a filter module (composed of a resistor R and a capacitor C), an inverter Q4, and a third transistor Mn2. The first terminal of the filter module is electrically connected to the cathode of the first diode and the drain of the third transistor, respectively. The second terminal of the filter module is electrically connected to the input terminal of the inverter. The output terminal of the inverter is electrically connected to the gate of the third transistor. The source of the third transistor and the third terminal of the filter module are used for grounding.

[0043] This discharge module achieves intelligent dynamic response to ESD clamping node voltage through a collaborative structure of a filter module, inverter, and third transistor. When an ESD event occurs, the clamping node voltage rises rapidly. The filter module smooths out high-frequency transient noise to prevent false triggering. Subsequently, the inverter inverts the filtered voltage signal, driving the third transistor to conduct and providing a low-impedance discharge path to ground for the clamping node, accelerating the release of electrostatic energy. This structure maintains a high-impedance state during normal operation, without affecting signal integrity.

[0044] Optionally, such as Figure 4 As shown, the above-mentioned filtering module includes: a filtering resistor module R and a filtering capacitor module C. The first end of the filtering resistor module serves as the first end of the filtering module. The second end of the filtering resistor module is electrically connected to the first end of the filtering capacitor module and the input end of the inverter, respectively. The second end of the filtering capacitor module is used for grounding.

[0045] like Figure 1 , Figure 5 and Figure 6 As shown, the protected circuit module includes:

[0046] The protected structure 410 includes: USB 2.0 detection circuit Q5, HS / FS / LS RXQ6, P-type transistors Mp1 and Mp2, resistors R6 and R7, and the connection method is as follows. Figure 5 As shown. USB 2.0 detection circuit: determines operating mode (HS / FS / LS), reset, connect, and suspend. HS RX receives 480Mbps high-speed data, FS RX receives 12Mbps full-speed data, and LS RX receives 1.5Mbps low-speed data. 1.3 HS DRV (High-Speed ​​Driver), transmits 480Mbps high-speed data.

[0047] The FS / LS DRV420 includes: P-type transistors Mp3 and Mp4, N-type transistors Mn3, Mn4, Mn5, and Mn6, and resistors R8 and R9, with the connection method as follows: Figure 6 As shown, the FS DRV (full-Speed ​​Driver) sends data at 12Mbps full speed, while the LS DRV (low-Speed ​​Driver) sends data at 1.5Mbps low speed.

[0048] When OVP_OUT=1:

[0049] High-speed TX: Immediately disconnects the 45Ω ground termination impedance, the driver stage enters a high-impedance state, blocking the large current path of 5V / (45Ω+3Ω)≈104mA, preventing the output stage transistor from burning out due to overcurrent;

[0050] High-speed RX: Turn off the input stage terminating resistor and bias current to avoid noise introduction that could cause bit errors;

[0051] Detection circuit: The queue detection and disconnection detection circuits pause operation to avoid misjudgment of abnormal states.

[0052] The ESD and OVP collaborative protection circuit also includes: an operating rate selection module, which includes: P-type transistors Mp5 and Mp6, resistors R10, R11, R12, and R13 (where the second end of R10 is electrically connected to the DP terminal, and the second end of R12 is electrically connected to the DM terminal), and N-type transistors Mn7, Mn8, Mn9, and Mn10, connected as follows: Figure 7 As shown.

[0053] LS / FS TX Protection: Low-speed (1.5Mbps) / Full-speed (12Mbps) TX output requires a 3.3V swing, located outside the high-voltage isolation module, and uses a standard fail-safe structure for overvoltage protection. When OVP_OUT=1, the low-impedance path to ground and VDD is cut off to prevent backflow current. The output terminal has a built-in 1.5kΩ pull-up resistor to 3.3V, and the MP5 / MP6 switches used also adopt a fail-safe structure to prevent backflow current.

[0054] The USB 2.0 speed is determined entirely by the pull-up and pull-down resistors on the DP / DM.

[0055] Low-speed LS (1.5Mbps) DM connected to 1.5k pull-up, DP without pull-up, host detects DM high and DP low, judgment: low-speed device.

[0056] Full-speed FS (12Mbps), DP connected to a 1.5k pull-up switch, DM without a pull-up switch → Host detects high DP and low DM → Determine: Full-speed device.

[0057] High-speed HS (480Mbps) is not determined directly by pull-up. Instead, the device first pretends to be a full-speed device (DP pull-up), then the host sends a Chirp handshake, the device responds with a Chirp, and finally both parties confirm HS support and switch to 480Mbps high speed.

[0058] Seeing a DP pull-up could indicate either a FS or a HS. Ultimately, whether it's an HS or a chirp handshake is determined.

[0059] This application also provides an electronic device, including: any of the above-described ESD and OVP collaborative protection circuits.

[0060] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0061] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A collaborative protection circuit for ESD and OVP, characterized in that, include: A high-voltage isolation module has a first terminal, a second terminal, a power supply terminal, a third terminal, and a fourth terminal. The first and second terminals of the high-voltage isolation module are electrically connected to the protected circuit module, respectively. The power supply terminal of the high-voltage isolation module is electrically connected to a voltage source. The third terminal of the high-voltage isolation module serves as a DM terminal, and the fourth terminal of the high-voltage isolation module serves as a DP terminal. The OVP detection module has a first terminal, a second terminal, and a third terminal. The first terminal of the OVP detection module is electrically connected to the DM terminal and the low-speed signal transmitting terminal, respectively. The second terminal of the OVP detection module is electrically connected to the DP terminal and the low-speed signal transmitting terminal, respectively. The third terminal of the OVP detection module is used to electrically connect to the state machine port inside the chip. The ESD collaborative protection module has a first terminal, a second terminal, and a power supply terminal. The first terminal of the ESD collaborative protection module is electrically connected to the DM terminal, the ESD collaborative protection module is electrically connected to the DP terminal, and the power supply terminal of the ESD collaborative protection module is electrically connected to the voltage source.

2. The ESD and OVP collaborative protection circuit according to claim 1, characterized in that, The high-voltage isolation module includes: a first resistor module, a first transistor, and a second transistor. The first terminal of the first resistor module is electrically connected to the voltage source, and the second terminal of the first resistor module is electrically connected to the gate of the first transistor. The sources of the first transistor and the second transistor are respectively electrically connected to the protected circuit module. The drain of the second transistor serves as the DP terminal, and the drain of the first transistor serves as the DM terminal.

3. The ESD and OVP collaborative protection circuit according to claim 2, characterized in that, The first resistor module includes multiple resistors connected in parallel or in series.

4. The ESD and OVP collaborative protection circuit according to claim 1, characterized in that, The OVP detection module includes: a first voltage divider module, a second voltage divider module, a first voltage comparator, a second voltage comparator, and an OR gate. The first terminal of the first voltage divider module is electrically connected to the DM terminal, and the second terminal of the first voltage divider module is electrically connected to the non-inverting input terminal of the first voltage comparator. Reference voltages are respectively input to the inverting input terminals of the first and second voltage comparators. The first terminal of the second voltage comparator is electrically connected to the DP terminal, and the second terminal of the second voltage comparator is electrically connected to the non-inverting input terminal of the second voltage comparator. The output terminal of the first voltage comparator is electrically connected to the first input terminal of the OR gate, and the output terminal of the second voltage comparator is electrically connected to the second input terminal of the OR gate. The output terminal of the OR gate is electrically connected to the state machine port inside the chip.

5. The ESD and OVP coordinated protection circuit according to claim 4, characterized in that, The first voltage divider module includes a second resistor module and a third resistor module. The first end of the second resistor module is electrically connected to the DM terminal. The second end of the second resistor module is electrically connected to the first end of the third resistor module and the non-inverting input terminal of the first voltage comparator, respectively. The second end of the third resistor module is used for grounding.

6. The ESD and OVP collaborative protection circuit according to claim 4, characterized in that, The second voltage divider module includes a fourth resistor module and a fifth resistor module. The first end of the fourth resistor module is electrically connected to the DP terminal. The second end of the fourth resistor module is electrically connected to the first end of the fifth resistor module and the non-inverting input terminal of the second voltage comparator, respectively. The second end of the fifth resistor module is used for grounding.

7. The ESD and OVP coordinated protection circuit according to claim 1, characterized in that, The ESD collaborative protection module includes: a first diode, a second diode, a third diode, a first voltage regulator module, a second voltage regulator module, and a discharge module. The positive terminal of the third diode is electrically connected to the voltage source. The negative terminals of the first diode and the second diode are respectively used for grounding. The positive terminal of the first diode is electrically connected to the DP terminal and the positive terminal of the first voltage regulator module. The positive terminal of the second diode is electrically connected to the DM terminal and the positive terminal of the second voltage regulator module. The negative terminal of the first voltage regulator module is electrically connected to the negative terminal of the second voltage regulator module, the discharge module, and the negative terminal of the third diode. The first voltage regulator module and the second voltage regulator module each include multiple diodes connected in series.

8. The ESD and OVP collaborative protection circuit according to claim 7, characterized in that, The discharge module includes a filter module, an inverter, and a third transistor. The first terminal of the filter module is electrically connected to the negative terminal of the first diode and the drain of the third transistor, respectively. The second terminal of the filter module is electrically connected to the input terminal of the inverter. The output terminal of the inverter is electrically connected to the gate of the third transistor. The source of the third transistor and the third terminal of the filter module are grounded.

9. The ESD and OVP collaborative protection circuit according to claim 8, characterized in that, The filtering module includes a filtering resistor module and a filtering capacitor module. The first end of the filtering resistor module serves as the first end of the filtering module. The second end of the filtering resistor module is electrically connected to the first end of the filtering capacitor module and the input end of the inverter, respectively. The second end of the filtering capacitor module is used for grounding.

10. An electronic device, characterized in that, include: The ESD and OVP co-protection circuit according to any one of claims 1 to 9.

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