A multi-mode configuration circuit with clock detection function
By using a multi-mode configuration circuit with clock detection, pin reuse and automatic external signal identification of the BUCK converter are achieved, solving the problems of pin resource waste and insufficient flexibility in traditional designs, and improving the stability and efficiency of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-04-30
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional BUCK converters rely on multiple external pins or internal registers for multi-mode selection, resulting in wasted pin resources and insufficient flexibility. Furthermore, they cannot effectively distinguish the type of external input signal, affecting system stability and efficiency.
Design a multi-mode configuration circuit with clock detection function. The circuit automatically identifies the type of external input signal by using the multiplexed mode configuration pin, automatically selects the light-load control mode using logic gate circuits and clock detection circuit, and sends the signal to the phase-locked loop for synchronization control when an AC signal is detected.
It saves pin resources, improves system configuration flexibility and operational reliability, adapts to complex application scenarios, reduces electromagnetic interference, and enhances the performance of power management chips.
Smart Images
Figure CN122496035A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-mode configuration circuit with clock detection function. Background Technology
[0002] In recent years, with the continuous development of integrated circuit technology and the increasing integration of electronic systems, power management chips have increasingly higher requirements for high efficiency, low power consumption, and adaptability to various scenarios. Buck converters, as commonly used step-down switching power supplies, typically employ multiple modulation modes such as PWM, PFM, and Burst to balance heavy-load efficiency and light-load power consumption, switching between them according to load conditions. Therefore, multi-mode configuration technology has become an important means to improve the overall performance of buck converters.
[0003] In traditional designs, multi-mode selection typically relies on multiple external pins or internal registers for configuration. This approach not only consumes significant pin resources but also struggles to meet the flexible configuration requirements of different application scenarios. Furthermore, in some applications, an external clock signal is required for switching frequency synchronization to reduce electromagnetic interference and avoid beat frequency effects between multi-power supply systems. However, if the control circuit cannot effectively distinguish between a DC configuration level and an AC clock signal from the external input signal, it can easily lead to incorrect mode selection or synchronization failure, thus affecting system stability and efficiency.
[0004] Existing solutions typically differentiate functions by adding a dedicated clock input pin or using a simple decision circuit. However, these methods often lead to increased circuit complexity or wasted pin resources. With the development of highly integrated power management chips, traditional solutions can no longer balance flexibility and resource utilization efficiency.
[0005] Therefore, designing a multi-mode configuration circuit with clock detection in a BUCK converter is of great significance. By multiplexing the mode configuration pin, the type of external input signal can be automatically identified. When the input is a DC signal, it is used to select different light-load operating modes, while when an AC signal is detected, it switches to a specific mode and sends it to the phase-locked loop for synchronization control. This method saves pin resources while improving the flexibility and reliability of system configuration, meeting the design requirements of power management chips in complex application scenarios. Summary of the Invention
[0006] The main objective of this invention is to propose a multi-mode configuration circuit to solve the problem of light-load control mode selection in a multi-modulation BUCK converter.
[0007] To achieve the above objectives, the present invention proposes a multi-mode configuration circuit with clock detection function, characterized in that it includes a first circuit mode configuration circuit and a second circuit clock detection circuit.
[0008] The first circuit includes: The first logic gate is configured such that input 1 is connected to the output of comparator COMP1, and input 2 is connected to the output of clock detection circuit CLK_DET. When at least one of the comparator output and the clock detection circuit CLK_DET output is high, the first logic gate outputs a low level.
[0009] The second logic gate is configured such that its input is connected to the output of the first logic gate I1, its output is connected to MODE1, and its output level is opposite to that of the first logic gate.
[0010] The third logic gate is configured such that: the first input terminal is connected to the output terminal of the first logic gate I1, the second input terminal is connected to the drain terminals of transistor MP1 and transistor MN1, and the third logic gate is at a high level when at least one of the output terminal of the first logic gate I1 and the drain terminals of transistor MP1 and transistor MN1 is at a low level.
[0011] The positive input of comparator COMP1 is connected to the reference voltage VREF, the negative input is connected to the external input pin MODE_PLLIN, the MINUS terminal of resistor R1, and the PLUS terminal of resistor R2, and the output is connected to the first input of the first logic gate I1. The source of transistor MP1 is connected to the analog power supply AVDD, the gate is connected to the external input pin MODE_PLLIN, and the drain is connected to the output MODE3. The source of transistor MN1 is connected to reference ground GND, the gate is connected to the fixed bias voltage VBN, and the drain is connected to MODE3. The PLUS terminal of resistor R1 is connected to the analog power supply AVDD, and the MINUS terminal of resistor R2 is connected to the reference ground GND.
[0012] The second circuit includes: The second circuit clock detection circuit CLK_DET is connected to MODE_PLLIN, and its output is connected to the second input of the first logic gate. When the external input is detected as a DC signal, it outputs a low level, and when the external input is detected as an AC signal, it outputs a high level.
[0013] This invention is achieved through the following technical solution: The external input pin MODE_PLLIN has four different connection methods: ground, no connection, AVDD connection, and clock signal connection, corresponding to four different states.
[0014] When MODE_PLLIN is grounded, COMP1 outputs a high level, and outputs MODE1 and MODE2 are configured to high level. Transistor MP1 is turned on. In this invention, the W / L ratio of transistor MP1 is much greater than that of transistor MN1. Transistors MP1 and MN1 can be regarded as a comparator, and the decision threshold is approximately AVDD+V. THP Therefore, the drain terminals of transistors MP1 and MN1 are pulled high. When connected to DC level, output MODE1 will be configured high only when MODE_PLLIN is grounded, and the light load control mode will be configured as MODE1.
[0015] When MODE_PLLIN is unconnected, the voltage at MODE_PLLIN is the result of the voltage division of the analog power supply AVDD by the two resistors, i.e., AVDD / 2. The reference voltage VREF is set to be less than AVDD / 2, COMP1 output is low, and output MODE1 is configured low. Since transistor MP1 is still conducting at this time, output MODE3 is configured high, and output MODE2 is configured low. MODE2 will only be configured low when MODE_PLLIN is unconnected; therefore, the light load control mode will be configured as MODE2.
[0016] When MODE_PLLIN is connected to AVDD, COMP1 outputs a low level, and MODE1 is configured to a low level. Transistor MP1 is turned off, and transistor MN1 pulls output MODE3 low, configuring output MODE2 high. MODE3 will only be configured low when MODE_PLLIN is unconnected, thus the light-load control mode will be configured as MODE3.
[0017] When MODE_PLLIN is connected to an external clock CLK with a frequency greater than the minimum synchronization frequency, since the clock signal is a digital signal, its high level is less than AVDD+V. THP Transistor MP1 remains on, and output MODE3 is configured high. Due to the detection of a clock signal input, the CLK_DET module outputs a high level, output MODE1 is configured high, and output MODE2 is configured high. That is, when the MODE_PLLIN pin is connected to the clock signal CLK, the light-load control mode will be automatically selected as MODE1. In this embodiment, MODE1 is FCCM mode. When a synchronous external clock is selected, this can further reduce output ripple and improve output voltage accuracy.
[0018] As an optional technical solution, the first logic gate is a NOR gate I1.
[0019] As an optional technical solution, the second logic gate is a NOT gate I2.
[0020] As an optional technical solution, the third logic gate circuit is a NAND gate circuit I3.
[0021] As an optional technical solution, the transistor MP1 is a P-type MOS transistor.
[0022] As an optional technical solution, the transistor MN1 is an N-type MOS transistor.
[0023] As an optional technical solution, the second circuit includes logic gates I4, I5, and I6, transistors MP2, MN2, MP3, and MN3, and capacitors C1 and C2.
[0024] The input terminal MODE_PLLIN is connected to the input terminal of the fourth logic gate I4. The output terminal is connected to the gate terminals of transistors MP2 and MN2, and the second input terminal of the fifth logic gate I5. The source terminal of transistor MP2 is connected to the digital power supply DVDD and the PLUS terminal of capacitor C1. The drain terminal is connected to the drain terminal of transistor MN1, the MINUS terminal of capacitor C1, and the first input terminal of logic gate I5. The output terminal of logic gate I5 is connected to the gate terminal of transistor MN3. The source terminal of transistor MN3 is connected to reference ground GND. The drain terminal is connected to the drain terminal of transistor MP3, the MINUS terminal of capacitor C2, and the input terminal of logic gate I6. The gate terminal of transistor MP3 is connected to the fixed bias voltage MBP, and its source terminal is connected to the digital power supply DVDD and the PLUS terminal of capacitor C2. The output terminal of logic gate I6 is connected to OUT.
[0025] The second circuit is implemented through the following technical solution: The second circuit consists of digital logic gates and capacitors. This part of the circuit mainly utilizes the delay effect of capacitor charging and discharging, so that when the MODE_PLLIN signal is a clock signal, the presence of the capacitor prevents the signal from toggling.
[0026] When MODE_PLLIN is at DC level, whether it is high or low, the two inputs of logic gate I5 are at opposite high and low levels, and the output is always low. MN3 is off. At this time, the input of logic gate I6 is pulled high by MP3, and the output OUT is configured to low level.
[0027] When the MODE_PLLIN input is an external clock, it is first shaped by logic gate I4. During the core circuit, the inverter formed by transistors MP2 and MN2 sets the aspect ratio of the PMOS to be much smaller than that of the NMOS. This causes capacitor C1 to charge slowly and discharge quickly, meaning the first input of logic gate I5 transitions slowly from low to high and quickly from high to low. Therefore, when the frequency of MODE_PLLIN is sufficiently high, the first input of logic gate I5 remains low and does not flip. In this case, logic gate I5 acts as an inverter. This causes transistor MN3 to open when its gate is high and discharge capacitor C2. Similarly, for transistors MP3 and MN3, the aspect ratio of MP3 is much smaller than that of MN3. Likewise, the charging current of C2 is much smaller than its discharging current, resulting in the input of logic gate I6 transitioning slowly from low to high and quickly from high to low. In other words, when the frequency of MODE_PLLIN reaches a certain value, the input of logic gate I6 remains at a low level and does not toggle. Therefore, the output OUT is high.
[0028] As an optional technical solution, the fourth logic gate circuit is a Schmitt trigger circuit I4.
[0029] As an optional technical solution, the fifth logic gate circuit is a NOR gate circuit I5.
[0030] As an optional technical solution, the sixth logic gate is a NOT gate I6.
[0031] As an optional technical solution, the transistors MP2 and MP3 are P-type MOS transistors.
[0032] As an optional technical solution, the transistors MN2 and MN3 are N-type MOS transistors.
[0033] One or more technical solutions provided by this invention have at least the following technical effects or advantages: This invention discloses a multi-mode configuration circuit with clock detection function. When the switching power converter is under light load, different light load control modes can be configured according to the external mode configuration pin. This mode configuration circuit has a clock detection function and is suitable for switching power converters with internal integrated phase-locked loop circuits. It can be multiplexed with the mode configuration pin. When an AC signal is detected at the mode configuration pin, the signal can be sent to the phase-locked loop for clock synchronization. At this time, the circuit will automatically select a light load mode. This mode can be selected as a high-precision, low-ripple, and low-noise control mode, thereby improving performance in conjunction with clock synchronization. This circuit is simple to implement, can greatly save chip pin resources, and has high control precision. Attached Figure Description
[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0035] Figure 1 This is a schematic diagram of a multi-mode configuration circuit with clock detection function according to the present invention; Figure 2 This is a schematic diagram of the second circuit in this invention; Figure 3 The simulation results are shown in the figure for the DC level input in this invention. Figure 4 The simulation results of the AC signal input in this invention are shown in the figure. Detailed Implementation
[0036] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, where there is no conflict, the embodiments of the present invention and the features thereof can be combined with each other.
[0037] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below. Example
[0038] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a multi-mode configuration circuit with clock detection function according to the present invention, characterized in that it includes a first circuit mode configuration circuit and a second circuit clock detection circuit.
[0039] The first circuit includes: The first logic gate is configured such that input 1 is connected to the output of comparator COMP1, and input 2 is connected to the output of clock detection circuit CLK_DET. When at least one of the comparator output and the clock detection circuit CLK_DET output is high, the first logic gate outputs a low level.
[0040] The second logic gate is configured such that its input is connected to the output of the first logic gate I1, its output is connected to MODE1, and its output level is opposite to that of the first logic gate.
[0041] The third logic gate is configured such that: the first input terminal is connected to the output terminal of the first logic gate I1, the second input terminal is connected to the drain terminals of transistor MP1 and transistor MN1, and the third logic gate is at a high level when at least one of the output terminal of the first logic gate I1 and the drain terminals of transistor MP1 and transistor MN1 is at a low level.
[0042] The positive input of comparator COMP1 is connected to the reference voltage VREF, the negative input is connected to the external input pin MODE_PLLIN, the MINUS terminal of resistor R1, and the PLUS terminal of resistor R2, and the output is connected to the first input of the first logic gate I1. The source of transistor MP1 is connected to the analog power supply AVDD, the gate is connected to the external input pin MODE_PLLIN, and the drain is connected to the output MODE3. The source of transistor MN1 is connected to reference ground GND, the gate is connected to the fixed bias voltage VBN, and the drain is connected to MODE3. The PLUS terminal of resistor R1 is connected to the analog power supply AVDD, and the MINUS terminal of resistor R2 is connected to the reference ground GND.
[0043] Please refer to Figure 2 . Figure 2 This is a schematic diagram of the second circuit in the present invention, which includes: The second circuit clock detection circuit CLK_DET is connected to MODE_PLLIN, and its output is connected to the second input of the first logic gate. When the external input is detected as a DC signal, it outputs a low level, and when the external input is detected as an AC signal, it outputs a high level.
[0044] This embodiment provides an implementation of a first logic gate circuit, which is a NOR gate circuit I1.
[0045] This embodiment provides an implementation of a second logic gate circuit, which is a NOT gate circuit I2.
[0046] This embodiment provides an implementation of a third logic gate circuit, which is a NAND gate circuit I3.
[0047] This embodiment provides an implementation of a second circuit, which includes logic gates I4, I5, and I6, transistors MP2, MN2, MP3, and MN3, and capacitors C1 and C2.
[0048] This embodiment provides an implementation of a fourth logic gate circuit, which is a Schmitt trigger circuit I4.
[0049] This embodiment provides an implementation of a fifth logic gate circuit, which is a NOR gate circuit I5.
[0050] This embodiment provides an implementation of a sixth logic gate circuit, which is a NOT gate circuit I6.
[0051] The input terminal MODE_PLLIN is connected to the input terminal of the fourth logic gate I4. The output terminal is connected to the gate terminals of transistors MP2 and MN2, and the second input terminal of the fifth logic gate I5. The source terminal of transistor MP2 is connected to the digital power supply DVDD and the PLUS terminal of capacitor C1. The drain terminal is connected to the drain terminal of transistor MN1, the MINUS terminal of capacitor C1, and the first input terminal of logic gate I5. The output terminal of logic gate I5 is connected to the gate terminal of transistor MN3. The source terminal of transistor MN3 is connected to reference ground GND. The drain terminal is connected to the drain terminal of transistor MP3, the MINUS terminal of capacitor C2, and the input terminal of logic gate I6. The gate terminal of transistor MP3 is connected to the fixed bias voltage MBP, and its source terminal is connected to the digital power supply DVDD and the PLUS terminal of capacitor C2. The output terminal of logic gate I6 is connected to OUT.
[0052] The working principle of this embodiment is as follows: The external input pin MODE_PLLIN has four different connection methods: ground, no connection, AVDD connection, and clock signal connection, corresponding to four different states.
[0053] When the MODE_PLLIN input is at a DC level: When MODE_PLLIN is grounded, COMP1 outputs a high level, and outputs MODE1 and MODE2 are configured to high level. Transistor MP1 is turned on. In this invention, the W / L ratio of transistor MP1 is much greater than that of transistor MN1. Transistors MP1 and MN1 can be regarded as a comparator, and the decision threshold is approximately AVDD+V. THP Therefore, the drain terminals of transistors MP1 and MN1 are pulled high. When connected to DC level, output MODE1 will be configured high only when MODE_PLLIN is grounded, and the light load control mode will be configured as MODE1.
[0054] When MODE_PLLIN is unconnected, the voltage at MODE_PLLIN is the result of the voltage division of the analog power supply AVDD by the two resistors, i.e., AVDD / 2. The reference voltage VREF is set to be less than AVDD / 2, COMP1 output is low, and output MODE1 is configured low. Since transistor MP1 is still conducting at this time, output MODE3 is configured high, and output MODE2 is configured low. MODE2 will only be configured low when MODE_PLLIN is unconnected; therefore, the light load control mode will be configured as MODE2.
[0055] When MODE_PLLIN is connected to AVDD, COMP1 outputs a low level, and MODE1 is configured to a low level. Transistor MP1 is turned off, and transistor MN1 pulls output MODE3 low, configuring output MODE2 high. MODE3 will only be configured low when MODE_PLLIN is unconnected, thus the light-load control mode will be configured as MODE3.
[0056] When MODE_PLLIN is connected to an external clock CLK with a frequency greater than the minimum synchronization frequency, since the clock signal is a digital signal, its high level is less than AVDD+V. THP Transistor MP1 remains on, and output MODE3 is configured high. Due to the detection of a clock signal input, the CLK_DET module outputs a high level, output MODE1 is configured high, and output MODE2 is configured high. That is, when the MODE_PLLIN pin is connected to the clock signal CLK, the light-load control mode will be automatically selected as MODE1. In this embodiment, MODE1 is FCCM mode. When a synchronous external clock is selected, this can further reduce output ripple and improve output voltage accuracy.
[0057] Please refer to Figure 3 , Figure 3 The simulation results for the MODE_PLLIN input in this invention are as follows: the analog power supply AVDD is 5V, and the digital power supply DVDD is 2.4V. A DC voltage scan is performed on the input MODE_PLLIN, with a scan range of 0 to 5V. It can be seen that when the input DC voltage is less than 650mV, outputs MODE1, MODE2, and MODE3 are high. When the input DC voltage is between 650mV and 3.85V, outputs MODE1 and MODE2 are low, and output MODE3 is high. When the input DC voltage is greater than 3.85V, outputs MODE1 and MODE3 are low, and output MODE2 is high. The circuit function is correct.
[0058] When an AC signal is input to the circuit: When the MODE_PLLIN input is an external clock, it is first shaped by logic gate I4. During the core circuit, the inverter formed by transistors MP2 and MN2 sets the aspect ratio of the PMOS to be much smaller than that of the NMOS. This causes capacitor C1 to charge slowly and discharge quickly, meaning the first input of logic gate I5 transitions slowly from low to high and quickly from high to low. Therefore, when the frequency of MODE_PLLIN is sufficiently high, the first input of logic gate I5 remains low and does not flip. In this case, logic gate I5 acts as an inverter. This causes transistor MN3 to open when its gate is high and discharge capacitor C2. Similarly, for transistors MP3 and MN3, the aspect ratio of MP3 is much smaller than that of MN3. Likewise, the charging current of C2 is much smaller than its discharging current, resulting in the input of logic gate I6 transitioning slowly from low to high and quickly from high to low. In other words, when the frequency of MODE_PLLIN reaches a certain value, the input of logic gate I6 remains low and does not toggle. Therefore, the output OUT is high. At this time, the MODE output is consistent with the DC level grounded output. Please refer to Figure 4 , Figure 4 This is the simulation result when the AC signal is input to MODE_PLLIN. The input signal frequency is 200KHz, the analog power supply AVDD is 5V, and the digital power supply DVDD is 2.4V. It can be seen that when the gate terminal of transistor MN3 is high, the input terminal of logic gate I6 is quickly pulled to low and maintained at low level. The clock detection module output is high, and at this time, the outputs MODE1, MODE2, and MODE3 are all high.
[0059] Furthermore, transistors MP1, MP2, and MP3 are all P-type MOS transistors.
[0060] Furthermore, transistors MN1, MN2, and MN3 are all N-type MOS transistors.
[0061] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0062] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A multi-mode configuration circuit with clock detection function, characterized in that, Includes a first circuit mode configuration circuit and a second circuit clock detection circuit; The first circuit includes: The first logic gate is configured such that input terminal 1 is connected to the output terminal of comparator COMP1, and input terminal 2 is connected to the output terminal of clock detection circuit CLK_DET. When at least one of the comparator output terminal and the clock detection circuit CLK_DET output terminal is high, the first logic gate outputs a low level. The second logic gate is configured such that its input is connected to the output of the first logic gate I1, its output is connected to MODE1, and the output of the second logic gate is a level opposite to the output potential of the first logic gate. The third logic gate is configured such that: the first input terminal is connected to the output terminal of the first logic gate I1, the second input terminal is connected to the drain terminals of transistor MP1 and transistor MN1, and the third logic gate is at a high level when at least one of the output terminal of the first logic gate I1 and the drain terminals of transistor MP1 and transistor MN1 is at a low level. The comparator COMP1 has its positive input connected to the reference voltage VREF, its negative input connected to the external input pin MODE_PLLIN, the MINUS terminal of resistor R1, and the PLUS terminal of resistor R2, and its output connected to the first input of the first logic gate I1. The transistor MP1 has its source connected to the analog power supply AVDD, its gate connected to the external input pin MODE_PLLIN, and its drain connected to the output MODE3. The transistor MN1 has its source connected to reference ground GND, its gate connected to the fixed bias voltage VBN, and its drain connected to MODE3. The PLUS terminal of resistor R1 is connected to the analog power supply AVDD, and the MINUS terminal of resistor R2 is connected to the reference ground GND. The second circuit includes: The second circuit clock detection circuit CLK_DET is connected to MODE_PLLIN, and its output is connected to the second input of the first logic gate. When the external input is detected as a DC signal, it outputs a low level, and when the external input is detected as an AC signal, it outputs a high level.
2. The multi-mode configuration circuit with clock detection function according to claim 1, wherein, The first logic gate is a NOR gate I1.
3. The multi-mode configuration circuit with clock detection function according to claim 1, wherein, The second logic gate circuit is an inverter circuit I2.
4. The multi-mode configuration circuit with clock detection function according to claim 1, wherein, The third logic gate is a NAND gate I3.
5. The multi-mode configuration circuit with clock detection function according to claim 1, wherein, The transistor MP1 is a P-type MOS transistor.
6. The multi-mode configuration circuit with clock detection function according to claim 1, wherein, The transistor MN1 is an N-type MOS transistor.
7. The multi-mode configuration circuit with clock detection function according to claim 1, wherein, The second circuit includes logic gates I4, I5, and I6, transistors MP2, MN2, MP3, and MN3, and capacitors C1 and C2.
8. The input terminal MODE_PLLIN is connected to the input terminal of the fourth logic gate I4, and the output terminal is connected to the gate terminals of transistors MP2 and MN2, and the second input terminal of the fifth logic gate I5. The source terminal of transistor MP2 is connected to the digital power supply DVDD and the PLUS terminal of capacitor C1, and the drain terminal is connected to the drain terminal of transistor MN1, the MINUS terminal of capacitor C1, and the first input terminal of logic gate I5. The output terminal of logic gate I5 is connected to the gate terminal of transistor MN3. The source terminal of transistor MN3 is connected to reference ground GND, and the drain terminal is connected to the drain terminal of transistor MP3, the MINUS terminal of capacitor C2, and the input terminal of logic gate I6. The gate terminal of transistor MP3 is connected to the fixed bias voltage MBP, and the source terminal is connected to the digital power supply DVDD and the PLUS terminal of capacitor C2. The output terminal of logic gate I6 is connected to OUT.
9. The multi-mode configuration circuit with clock detection function according to claim 8, wherein, The fourth logic gate circuit is a Schmitt trigger circuit I4.
10. A multi-mode configuration circuit with clock detection function according to claim 8, characterized in that, The fifth logic gate is a NOR gate I5.
11. A multi-mode configuration circuit with clock detection function according to claim 8, characterized in that, The sixth logic gate is the NOT gate I6.
12. A multi-mode configuration circuit with clock detection function according to claim 8, characterized in that, The transistors MP2 and MP3 are P-type MOS transistors.
13. A multi-mode configuration circuit with clock detection function according to claim 8, characterized in that, The transistors MN2 and MN3 are N-type MOS transistors.