General-purpose input / output circuit, chip, electronic device

Abstract

This application discloses a general-purpose input / output circuit, chip, and electronic device to avoid electromagnetic interference generated during the transmission of GPIO circuit output signals. The circuit includes: a first output module that outputs a first output signal, and a second output module that outputs a second output signal; an output control module connected to the first and second output modules respectively, configured to: receive the first output signal and output a signal to a first pin outside the GPIO circuit, such that the amplitude of the output signal at the first pin is less than the amplitude of the first output signal; and receive the second output signal and output a signal to a second pin outside the GPIO circuit, such that the amplitude of the output signal at the second pin is less than the amplitude of the second output signal; a first pull-up / pull-down module connected to the first pin, and a second pull-up / pull-down module connected to the second pin; and an input module for receiving signals from the first and second pins and generating an input signal.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to general-purpose input / output circuits, chips, and electronic devices. Background Technology

[0002] GPIO (General-Purpose Input / Output) is a type of input / output that serves as a bridge for interaction between a chip and external devices. The output signal of a GPIO, which is the signal sent to external components through the GPIO port, switches between high and low levels. The difference between the high and low levels is the swing of the output signal (i.e., the signal amplitude). During signal transmission, if the swing of the GPIO module's output signal is too large, it can easily lead to signal energy radiation, i.e., electromagnetic interference (EMI), thus affecting the normal operation of other functional modules. Summary of the Invention

[0003] This application provides general-purpose input / output circuits, chips, and electronic devices to reduce the swing of the GPIO circuit output signal, thereby avoiding EMI generated during the transmission of the GPIO circuit output signal, thus avoiding interference to other modules and ensuring that the normal function of the circuit is not affected.

[0004] This application provides a general-purpose input / output GPIO circuit, including: an output module, an input module, and a pull-up / pull-down module; The output module includes at least: a first output module for outputting a first output signal, and a second output module for outputting a second output signal; The GPIO circuit also includes: An output control module that is connected to the output terminals of the first output module and the second output module, respectively; The output control module is configured to: receive a first output signal output by the first output module and output a signal to a first pin outside the GPIO circuit, such that the amplitude of the output signal at the first pin is less than the amplitude of the first output signal; and receive a second output signal output by the second output module and output a signal to a second pin outside the GPIO circuit, such that the amplitude of the output signal at the second pin is less than the amplitude of the second output signal. The pull-up / pull-down module includes at least: a first pull-up / pull-down module connected to the first pin, and a second pull-up / pull-down module connected to the second pin; The input module includes at least two input terminals, one of which is connected to the first pin and the other is connected to the second pin; the input module is used to receive signals from the first pin and the second pin, and generate an input signal to be output through the output terminal of the input module.

[0005] The GPIO circuit provided in this application embodiment includes a first output module for outputting a first output signal and a second output module for outputting a second output signal; and an output control module connected to the output terminals of the first and second output modules respectively. The output control module can receive the first output signal from the first output module and output a signal to a first pin outside the GPIO circuit, such that the amplitude of the output signal at the first pin is less than the amplitude of the first output signal. Similarly, the output control module can also receive the second output signal from the second output module and output a signal to a second pin outside the GPIO circuit, such that the amplitude of the output signal at the second pin is less than the amplitude of the second output signal. Therefore, by reducing the amplitude of the output signal at the first and second pins, the swing of the GPIO circuit output signal is reduced, thereby preventing EMI from being generated during transmission and thus avoiding interference from the GPIO circuit output signal to other modules, ensuring that the normal function of the entire circuit is not affected. Furthermore, the GPIO circuit provided in this application embodiment implements the pull-up / pull-down functions of the first pin and the second pin respectively through a first pull-up / pull-down module connected to the first pin and a second pull-up / pull-down module connected to the second pin. Additionally, the input module in the GPIO circuit provided in this application embodiment includes at least two input terminals, one connected to the first pin and the other connected to the second pin; thus, the input module can receive signals from the first pin and the second pin, and generate an input signal which is output through the output terminal of the input module.

[0006] In some embodiments, the output control module includes: A first resistor, a second resistor, a first switch, a third resistor, and a fourth resistor are connected in series between the output terminals of the first output module and the second output module; wherein, the first switch is turned on or off under the control of the main control module outside the GPIO circuit.

[0007] In some embodiments, the first resistor, the second resistor, the third resistor, and the fourth resistor are all variable resistors.

[0008] In some embodiments, the output control module further includes: A second switch is connected to the connection point between the first switch and the second resistor, and a third switch is connected to the connection point between the first switch and the third resistor; wherein, the second switch and the third switch are connected to power supply or ground under the control of the main control module outside the GPIO circuit.

[0009] In some embodiments, the second switch and the third switch are controlled by the first output drive signal or the second output drive signal output by the main control module.

[0010] In some embodiments, the input terminals of the first output module and the second output module are respectively connected to the main control module outside the GPIO circuit; The first output module and the second output module are controlled by the same output drive signal or different output drive signals output by the main control module.

[0011] In some embodiments, the output control module includes at least three resistors connected in series between the output terminals of the first output module and the output terminals of the second output module.

[0012] In some embodiments, the second output module includes an inverter and a selector; The inverter's input terminal is connected to the main control module and is used to receive the first output drive signal output by the main control module to the second output module; the inverter's output terminal is connected to the selector. The two input terminals of the selector are respectively connected to the output terminal of the inverter and the main control module. The selector is used to select the inverted signal output of the first output drive signal output by the inverter, or to select the second output drive signal output by the main control module to the second output module.

[0013] In some embodiments, the input module includes at least two output terminals, namely a first output terminal and a second output terminal; The input module further includes: a mode signal control terminal and / or a hysteresis voltage control terminal, which are respectively connected to the main control module outside the GPIO circuit; The mode signal control terminal is used to receive the mode control signal output by the main control module. Under the control of the mode control signal, the input module generates a first input signal and outputs it through the first output terminal; and / or, the input module generates a second input signal and outputs it through the second output terminal. The hysteresis voltage control terminal is used to receive the hysteresis voltage control signal output by the main control module, and to control the magnitude of the hysteresis voltage of the hysteresis comparator in the input module through the hysteresis voltage control signal.

[0014] This application provides a chip including the GPIO circuit described in this application embodiment, and a main control module for controlling the operation of the GPIO circuit.

[0015] Another embodiment of this application provides an electronic device, including the chip provided in the embodiment of this application. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a GPIO circuit provided in an embodiment of this application; Figure 2 A waveform diagram of the output signal of a GPIO circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of another GPIO circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an output control module in a GPIO circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of the third GPIO circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of an input module in a GPIO circuit provided in an embodiment of this application; Figure 7 A schematic diagram of a GPIO circuit divided into upper and lower parts, provided for an embodiment of this application; Figure 8 A waveform diagram of a first output drive signal O (also an output signal of PAD1) provided for an embodiment of this application; Figure 9 A waveform diagram of the output signal of a PAD2 provided in an embodiment of this application; Figure 10 A waveform diagram of the output signal of another PAD1 provided in an embodiment of this application; Figure 11A waveform diagram of the output signal of another PAD2 provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the fourth GPIO circuit provided in the embodiments of this application; Figure 13 A waveform diagram of the output signal of the third type of PAD1 provided in the embodiments of this application; Figure 14 A waveform diagram of the output signal of the fourth type of PAD1 provided in the embodiments of this application; Figure 15 A waveform diagram of the output signal of the third type of PAD2 provided in the embodiments of this application; Figure 16 A waveform diagram of the output signal of the fourth type of PAD2 provided in the embodiments of this application; Figure 17 This is a schematic diagram of the structure of the fifth GPIO circuit provided in the embodiments of this application; Figure 18 This is a schematic diagram of the structure of the pull-up / pull-down module provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] This application provides general-purpose input / output circuits, chips, and electronic devices to reduce the swing of the GPIO circuit output signal, thereby avoiding EMI generated during the transmission of the GPIO circuit output signal, thus avoiding interference to other modules and ensuring that the normal function of the circuit is not affected.

[0020] Among them, the general-purpose input / output circuits, chips, and electronic devices are based on the same application concept. Since the principles of solving the problem are similar, the implementation of the general-purpose input / output circuits, chips, and electronic devices can refer to each other, and the repeated parts will not be described again.

[0021] The terms "first," "second," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] The following examples and embodiments are to be understood as illustrative only. While this specification may refer to "a," "an," or "some" examples or embodiments in several places, this does not mean that every such reference relates to the same example or embodiment, nor does it mean that the feature applies only to a single example or embodiment. Individual features of different embodiments may also be combined to provide other embodiments. Furthermore, terms such as "comprising" and "including" should be understood not to limit the described embodiments to consisting only of those features mentioned; such examples and embodiments may also include features, structures, units, modules, etc., not specifically mentioned.

[0023] The various embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be noted that the order in which the embodiments are presented in this application represents only a chronological order and does not represent the superiority or inferiority of the technical solutions provided by the embodiments.

[0024] like Figure 1As shown, signals from inside the chip (signal O) are output to external components through the output module in the GPIO circuit. The output module outputs signal O to the port of the GPIO circuit (referred to as the GPIO port, i.e., the interface between the GPIO circuit and the external components) according to the output enable (OE) signal and the output drive strength (DS) control signal, and connects to the external components to complete the chip's control and data transmission functions for the external components. Signals from external components are input through the input module of the GPIO circuit, and the input module generates an input signal (signal I) which is then fed back to the inside of the chip. Specifically, the input module converts the signals input to the GPIO circuit from external components into input signals I based on the input enable (IE) signal and the Schmitt trigger control (SE) signal, and feeds them back to the chip (e.g., the main control module) to complete the chip's functions of monitoring signals from external components and transmitting data. The pull-up / pull-down module, under the action of the pull-up (PU) and pull-down (PD) control signals, fixes the signal lines of the GPIO port to the default high level (power supply voltage VCC) or low level (ground GND) through pull-up resistors and pull-down resistors, thus completing the pull-up and pull-down functions of the GPIO port and preventing unstable states caused by floating.

[0025] Among them, the signals output by the GPIO port to external components, such as Figure 2 As shown, the amplitude switches between high and low levels. The low level is typically 0V, and the high level is typically the power supply (VCC) voltage. Therefore, the amplitude of the output signal of the GPIO circuit varies depending on the power supply VCC voltage, such as 5V, 3.3V, 1.8V, etc. That is, the high and low levels of the signal output from the GPIO port to external components switch between VCC and 0, resulting in a relatively large swing. During long-distance transmission, this can easily lead to signal energy radiation, interfering with other modules and causing EMI (Electronic Annoying Syndrome).

[0026] Therefore, to avoid EMI generation during the transmission of GPIO circuit output signals, this application provides a general-purpose input / output GPIO circuit, including: an output module, an input module, and a pull-up / pull-down module; wherein: See Figure 3 The output module includes at least: a first output module 1 for outputting a first output signal, and a second output module 2 for outputting a second output signal; The GPIO circuit also includes: An output control module 3 is connected to the output terminals of the first output module 1 and the second output module 2, respectively. The output control module 3 is configured to: receive a first output signal output by the first output module 1 and output a signal to a first pin 7 outside the GPIO circuit, such that the amplitude of the output signal at the first pin 7 is less than the amplitude of the first output signal; and receive a second output signal output by the second output module 2 and output a signal to a second pin 8 outside the GPIO circuit, such that the amplitude of the output signal at the second pin 8 is less than the amplitude of the second output signal. The pull-up / pull-down module includes at least: a first pull-up / pull-down module 5 connected to the first pin, and a second pull-up / pull-down module 6 connected to the second pin; The input module 4 includes at least two input terminals, one of which is connected to the first pin 7 and the other is connected to the second pin 8; the input module is used to receive signals from the first pin 7 and the second pin 8, and generate an input signal that passes through the output terminal of the input module 4. Figure 3 (Not shown in the diagram) Output, for example, can be output to the main control module inside the chip. The level conversion required for the signals transmitted between the various modules described in this application and the main control module inside the chip adopts conventional methods, which will not be described in detail in the embodiments of this application.

[0027] It should be noted that, in the embodiments of this application, in addition to the first output module and the second output module, more output modules can be similarly set according to actual needs; correspondingly, in addition to the first pull-up / pull-down module and the second pull-up / pull-down module, more pull-up / pull-down modules can be similarly set according to actual needs. In the embodiments of this application, only the GPIO circuit including the first output module, the second output module, the output control module, the input module, the first pull-up / pull-down module, and the second pull-up / pull-down module is used as an example for illustration.

[0028] In some embodiments, see Figure 4 The output control module 3 includes at least three resistors connected in series between the output terminal of the first output module and the output terminal of the second output module; Or see Figure 5 The output control module 3 includes: A first resistor R2, a second resistor R1, a first switch SW1, a third resistor R3, and a fourth resistor R4 are connected in series between the output terminals of the first output module and the second output module; wherein, the first switch SW1 is turned on or off under the control of the main control module (e.g., a CPU, not shown in the figure) outside the GPIO circuit.

[0029] In some embodiments, R2, R1, R3, and R4 are all variable resistors. This allows control over the swing of the GPIO circuit output signal.

[0030] Specifically, for example, by adjusting the resistance ratio of R2 and R1, and the resistance ratio of R4 and R3, the amplitude swing (vol) of the signal output can be changed, so that the high and low levels of the output signals of PAD1 (i.e., the first pin) and PAD2 (i.e., the second pin) are VCC / 2+vol and VCC / 2-vol, respectively. In some embodiments, the resistance values ​​of R2 and R4 can be equal, and the resistance values ​​of R1 and R3 can be equal. The specific resistance values ​​can be set according to actual needs, and are not limited in this embodiment. That is, in this embodiment, the driving capability of the GPIO output signal, i.e., the output current capability, can be adjusted by changing the resistance values ​​of R2, R1, R4, and R3. The larger the resistance, the weaker the output current capability. Assuming the ratio of R2 / R1 is the same, but the resistance values ​​are different, for example, R2=2kΩ and R1=1kΩ, the ratio is 2. If R2=1kΩ and R1=500Ω, the ratio is still 2, so the output current volume is the same, but the output current capability is different, differing by a factor of two.

[0031] In some embodiments, the input terminals of the first output module and the second output module are respectively connected to the main control module outside the GPIO circuit; For example Figure 5 As shown, the first output module and the second output module are controlled by the same output drive signal output by the main control module (e.g., Figure 5 The signal shown (O) or different output drive signals (e.g.) Figure 5 Signals O and O' are shown.

[0032] In some embodiments, the second output module includes an inverter (INV) and a selector (MUX). The input terminal of the inverter is connected to the main control module and is used to receive the first output drive signal (e.g., from the main control module to the second output module) Figure 5 The signal O shown is connected to the selector MUX at the output of the inverter. The two input terminals of the selector MUX are respectively connected to the output terminal of the inverter INV and the main control module. The selector MUX is used to select the inverted signal output of the first output drive signal O output by the inverter INV, or to select the second output drive signal output by the main control module to the second output module (e.g., Figure 5 The signals O and O' shown are output.

[0033] Specifically, for example Figure 5As shown, the first output module includes a CMOS circuit structure, and the input terminal of the first output module is connected to the main control module (e.g., CPU). Figure 5 (Not shown in the diagram), thus the main control module can input the first output drive signal O to the first output module; the output terminal of the first output module is connected to the output control module. The first output module is also provided with two control terminals connected to the main control module, so that the main control module can input the first output enable signal OE and the first drive strength signal DS to the first output module respectively. The CMOS circuit structure described in the embodiments of this application is the same as the conventional CMOS circuit structure, therefore, it will not be described again in the embodiments of this application.

[0034] In other words, the first output module is equivalent to an output module of the GPIO circuit. It is used to output signals to external components through PAD1 under the action of the first output enable signal OE, the first drive strength signal DS, the first output drive signal O, and the control of the output control module. The amplitude of the signal output to the external components can be less than or equal to the amplitude of the first output drive signal O.

[0035] It should be noted that the first output enable signal OE, the first drive strength signal DS, and the first output drive signal O mentioned in the embodiments of this application all originate from the main control module (e.g., CPU). Figure 5 (Not shown in the image).

[0036] The second output module includes: a CMOS circuit structure, a selector MUX, and an inverter INV.

[0037] The input terminal of the second output module is connected to the main control module (e.g., CPU). Figure 5 (Not shown in the diagram), so the main control module can input the first output drive signal O and the second output drive signal O' to the second output module; the output terminal of the second output module is connected to the output control module. The second output module is also provided with four control terminals connected to the main control module, so that the main control module can input the first output enable signal OE, the first drive strength signal DS, the second output enable signal OE', and the second drive strength signal DS' to the second output module respectively.

[0038] In other words, the second output module is equivalent to another output module of GPIO, used to output signals to external components under the action of the first output enable OE signal, the first drive strength DS signal, the first output drive signal O, and the control of the output control module, and the amplitude of the signal output to the external components can be less than or equal to the amplitude of the first output drive signal O; and / or, the second output module is used to output signals to external components under the action of the second output enable OE' signal, the second drive strength DS' signal, the second output drive signal O', and the control of the output control module, and the amplitude of the signal output to the external components can be less than or equal to the amplitude of the second output drive signal O'.

[0039] It should be noted that the second output enable signal OE', the second drive strength signal DS', and the second output drive signal O' mentioned in the embodiments of this application all originate from the main control module (e.g., CPU). Figure 5 (Not shown in the image).

[0040] In some embodiments, the input module includes at least two output terminals, namely a first output terminal and a second output terminal; The input module further includes: a mode signal control terminal (e.g., connected to a main control module external to the GPIO circuit) that is connected to the main control module. Figure 5 The MD signal control terminal shown), and / or the hysteresis voltage control terminal (e.g. Figure 5 (AS signal control terminal shown). The mode signal control terminal is used to receive the mode control signal (MD signal) output by the main control module. Under the control of the mode control signal, the input module generates a first input signal (e.g., Figure 5 The signal I shown is output through the first output terminal; and / or, the input module generates a second input signal (e.g., Figure 5 The signal I' shown is output through the second output terminal; The hysteresis voltage control terminal is used to receive the hysteresis voltage control signal (AS signal) output by the main control module, and to control the magnitude of the hysteresis voltage of the hysteresis comparator in the input module through the hysteresis voltage control signal.

[0041] For example Figure 5 As shown, the input module includes a hysteresis comparator (which may include multiple hysteresis comparators, for example...). Figure 6The two hysteresis comparators shown (or three or more hysteresis comparators, which can be set according to actual needs, and are not limited in this embodiment) are used. The input module has two input terminals, two output terminals, and six control terminals. The first input terminal of the input module is connected to the first pin PAD1; the second input terminal of the input module is connected to the second pin PAD2; the first output terminal of the input module is connected to the main control module and is used to output the first input signal I to the main control module; the second output terminal of the input module is connected to the main control module and is used to output the second input signal I' to the main control module; the six control terminals of the input module are respectively connected to the main control module, so that the main control module can input the first input enable signal IE, the first Schmitt trigger control signal SE, the MD signal, the second input enable signal IE', the second Schmitt trigger control signal SE', and the AS signal to the input module respectively.

[0042] In summary, in this embodiment, the external control module (which can be one or more, and is not limited in this embodiment) can control the opening and closing of SW1, as well as the resistance values ​​of R1, R2, R3, and R4, thereby enabling the following three operating modes of the GPIO circuit: Normal GPIO mode: That is, single-ended high-swing GPIO mode, such as Figure 7 As shown, SW1 is disconnected, and R2 and R4 are set to 0 ohms or a small resistance (the specific values ​​can be determined according to actual needs, and this application embodiment does not impose any restrictions). The GPIO circuit includes two parts, which are unrelated and are two ordinary GPIO circuits. For example, adjust resistor R2 to 0 ohms; the output signal of the upper GPIO circuit is driven by the first output drive signal O and output to PAD1. For example, the first output drive signal O is as follows: Figure 8 As shown, the signal output to PAD1 is also as follows. Figure 8 As shown; the output signal of the lower part of the GPIO circuit is driven by the second output drive signal O' and output to PAD2. For example, the second output drive signal O' is as follows: Figure 9 As shown, the signal output to PAD2 is also as follows. Figure 9 As shown; Regarding input, when the input module's mode MD signal is adjusted to the normal GPIO mode control signal via the MD signal output by the main control module, the input module implements the input function of the normal GPIO circuit. Signals I and I' are converted from signals from PAD1 and PAD2, respectively.

[0043] At this time, the PU and PD control modes are consistent with the PU and PD control modes of ordinary GPIO circuits.

[0044] Differential high-swing GPIO mode: With SW1 disconnected, R2 and R4 are set to 0 ohms or a small resistance (the specific values ​​can be determined according to actual needs, and this embodiment does not impose any restrictions). At this time, signals OE', DS', IE', SE', and O' have no effect (they can be controlled by the main control module). PAD1, PAD2, I, and I' are all controlled by signals OE, DS, IE, SE, and O (they can be controlled by the main control module). The GPIO circuit generates a differential high-swing signal and outputs it to PAD1 and PAD2.

[0045] Differential low-swing GPIO mode: When SW1 is closed, R2 / R1 is set to a certain ratio (the specific ratio can be determined according to actual needs, and this application embodiment does not impose any restrictions). At this time, signals OE', DS', IE', SE', and O' have no effect (they can be controlled by the main control module). PAD1, PAD2, I, and I' are all controlled by signals OE, DS, IE, SE, and O (they can be controlled by the main control module). The GPIO circuit generates a differential low-swing signal output to PAD1 and PAD2.

[0046] In differential low-swing GPIO mode, the amplitude of the output signal of the GPIO circuit can be adjusted and controlled by R1 / R2 / R3 / R4. For example, assuming R2=R4=1000 and R1=R3=500, then vol=1 / 6VCC, so the high and low levels of the output signal of the GPIO circuit are VCC / 2+1 / 6VCC and VCC / 2-1 / 6VCC, respectively.

[0047] As can be seen, the GPIO circuit described in this application embodiment can achieve differential signal output in both differential high-swing GPIO mode and differential low-swing GPIO mode. That is, the output signal of PAD1 and the output signal of PAD2 are out of phase. In other words, the output signal used to transmit PAD1 is out of phase with the output signal used to transmit PAD2. Therefore, when transmitting signals through twisted pair, EMI interference can be greatly reduced.

[0048] When switch SW1 is closed via the main control module, the upper and lower parts are connected through the output control module; both the first output module and the second output module are driven by the first output drive signal O, forming differential output signals, which are output to PAD1 and PAD2 respectively; for example, the first output drive signal O is as follows: Figure 8 As shown, the signal output to PAD1 is as follows: Figure 10 As shown, the signal output to PAD2 is as follows: Figure 11 As shown; When the mode MD signal output by the main control module to the input module is adjusted to the differential low swing GPIO mode control signal, the input signal I is converted from the differential signal of the signals from PAD1 and PAD2, and the input signal I' is not used; In differential low-swing GPIO mode, the PU and PD control modes add CP mode, that is, pull-up and pull-down are enabled together, and the clamping PAD1 and PAD2 are at the intermediate voltage value.

[0049] In some embodiments, when the output control module includes a first resistor, a second resistor, a first switch, a third resistor, and a fourth resistor connected in series between the output terminals of the first output module and the second output module, see [reference needed]. Figure 12 The output control module further includes: A second switch SW2 is connected to the connection point between the first switch SW1 and the second resistor R1, and a third switch SW3 is connected to the connection point between the first switch SW1 and the third resistor R3; wherein, the second switch SW2 and the third switch SW3 are connected to the power supply VCC or ground GND under the control of the main control module outside the GPIO circuit.

[0050] By setting the second switch SW2 and the third switch SW3, the GPIO circuit provided in this application embodiment can further realize a single-ended low-swing GPIO mode.

[0051] Regarding single-ended low-swing GPIO mode: Disconnect switch SW1, both the upper and lower parts (in) Figure 7 Based on the two parts shown, add a second switch SW2 and a third switch SW3 respectively. When there is no connection, that is, the first output module and the second output module are disconnected, at this time... Figure 12 The GPIO circuit structure shown is equivalent to implementing two independent GPIO circuits, one above the other; that is, these two independent GPIO circuits can use the normal GPIO mode or the single-ended low-swing GPIO mode independently.

[0052] Assuming the upper GPIO circuit is used to implement single-ended low-swing GPIO mode, then the second switch SW2 is closed, connected to power supply VCC or ground (GND); when the second switch SW2 is connected to VCC, as... Figure 13 As shown, the signal output from the upper GPIO circuit to PAD1 is a low-swing signal. The high level of this low-swing signal is VCC, and the low level is VCC-vol. When the second switch SW2 is connected to GND, as shown... Figure 14 As shown, the signal output to PAD1 from the upper part of the GPIO circuit is a low-swing signal. The high level of this low-swing signal is GND+vol, i.e., vol, and the low level is GND (i.e., 0V).

[0053] Similarly, assuming the lower part of the GPIO circuit is used to implement single-ended low-swing GPIO mode, then the third switch SW3 is closed, connected to power supply VCC or ground (GND); when the third switch SW3 is connected to VCC, as... Figure 15 As shown, the signal output from the lower GPIO circuit to PAD2 is a low-swing signal. The high level of this low-swing signal is VCC, and the low level is VCC-vol. When the third switch SW3 is connected to GND, as shown... Figure 16 As shown, the signal output to PAD2 from the lower part of the GPIO circuit is a low-swing signal. The high level of this low-swing signal is GND+vol, i.e., vol, and the low level is GND (i.e., 0V).

[0054] In some embodiments, see Figure 17 The second switch SW2 and the third switch SW3 are controlled by the first output drive signal O or the second output drive signal O' output by the main control module.

[0055] Therefore, this embodiment can also generate output signals with high and low levels of VCC / 2+vol and VCC / 2-vol, respectively. The single-ended low-swing signal of PAD1 is generated by signal O, and the single-ended low-swing signal of PAD2 is generated by signal O'. It should be noted that the single-ended scenario described in this embodiment means that the output signals of PAD1 and PAD2 are not related; they are generated by different signals.

[0056] See Figure 17 Assuming the upper GPIO circuit is used to implement single-ended low-swing GPIO mode, then when the second switch SW2 is closed and connected to signal O, then... Figure 10 As shown, the signal output to PAD1 from the upper part of the GPIO circuit is a low-swing signal. The high level of this low-swing signal is VCC / 2+vol, and the low level is VCC / 2-vol.

[0057] Similarly, assuming the lower part of the GPIO circuit is used to implement single-ended low-swing GPIO mode, then when the third switch SW3 is closed and connected to signal O', then... Figure 11 As shown, the signal output to PAD2 from the lower part of the GPIO circuit is a low-swing signal. The high level of this low-swing signal is VCC / 2+vol, and the low level is VCC / 2-vol.

[0058] As can be seen, unlike the differential low-swing GPIO mode described above, in the single-ended low-swing GPIO mode, the output signal of PAD1 is controlled by signal O, and the output signal of PAD2 is controlled by signal O'. Signals O and O' are two unrelated signals. However, in the differential low-swing GPIO mode, both the output signals of PAD1 and PAD2 are controlled by signal O. Therefore, the output signals of PAD1 and PAD2 are out of phase.

[0059] Regarding the input module, the MD signal described in this embodiment can be used to select between single-ended and differential modes. For example, when the MD signal is 0, single-ended mode is implemented, and the upper and lower GPIO circuits are not associated, i.e., SW1 is disconnected. At this time, the signals SE and IE control the signal input to the GPIO circuit by PAD1 to generate the first input signal I through the hysteresis comparator in the input module; the signals SE' and IE' control the signal input to the GPIO circuit by PAD2 to generate the second input signal I' through the hysteresis comparator in the input module. Similarly, for example, when the MD signal is 1, the signals from PAD1 and PAD2 together form a differential signal, which is sent to the differential hysteresis comparator controlled by signals SE and IE in the input module, and generates and outputs the first input signal I at the first output terminal of the input module; at this time, the second output terminal of the input module is not used (i.e., the second input signal I' is not generated), or the second output terminal of the input module generates the inverted signal of the first input signal I or other signals.

[0060] The AS signal in the input module is used to control the hysteresis voltage of the hysteresis comparator. The main control module outputs the corresponding AS signal to the input module according to whether the signal input to the GPIO circuit by PAD1 and PAD2 is a low-swing signal or a high-swing signal. This further controls the hysteresis voltage of the hysteresis comparator to meet the working state of the hysteresis comparator under low-swing or high-swing signals, and avoids the hysteresis comparator operating voltage being too large or too small.

[0061] It should be noted that the MD signal, SE signal, IE signal, SE' signal, IE' signal, and AS signal mentioned in the embodiments of this application all come from the main control module (e.g., CPU, not shown in the figure).

[0062] As can be seen, the input module described in this application embodiment can, under the control of the main control module, convert signals from external components of the chip into input signals (for example, convert signals from PAD1 into first input signal I, signals from PAD2 into second input signal I', or signals from PAD1 and PAD2 into first input signal I), and feed them back to the chip.

[0063] The pull-up / pull-down module described in the embodiments of this application includes at least: a first pull-up / pull-down module connected to the first pin PAD1, and a second pull-up / pull-down module connected to the second pin PAD2; In some embodiments, for example Figure 18 As shown ( Figure 5 , Figure 12 (Similarly, the first pull-up / pull-down module includes: a fifth resistor R5, a fourth switch SW4, a fifth switch SW5, and a sixth resistor R6 connected in series between the power supply VCC and ground GND; similarly, the second pull-up / pull-down module includes: a seventh resistor R7, a sixth switch SW6, a seventh switch SW7, and an eighth resistor R8 connected in series between VCC and GND.)

[0064] The first pull-up / pull-down module realizes the pull-up function of PAD1 under the control of the first pull-up PU signal; and realizes the pull-down function of PAD1 under the control of the first pull-down PD signal.

[0065] The second pull-up / pull-down module realizes the pull-up function of PAD2 under the control of the second pull-up PU' signal; and realizes the pull-down function of PAD2 under the control of the second pull-down PD' signal.

[0066] The fourth switch SW4 can be a PMOS transistor, and the fifth switch SW5 can be an NMOS transistor. The source of the PMOS transistor is connected to resistor R5, the drain is connected to PAD1, and the gate is connected to the PU signal control terminal. The source of the NMOS transistor is connected to resistor R6, the drain is connected to PAD1, and the gate is connected to the PD signal control terminal.

[0067] Similarly, the sixth switch SW6 can be a PMOS transistor, and the seventh switch SW7 can be an NMOS transistor; the source of the PMOS transistor is connected to resistor R7, the drain is connected to PAD2, and the gate is connected to the PU' signal control terminal; the source of the NMOS transistor is connected to resistor R8, the drain is connected to PAD2, and the gate is connected to the PD' signal control terminal.

[0068] It should be noted that the first pull-up PU signal, the first pull-down PD signal, the second pull-up PU' signal, and the second pull-down PD' signal mentioned in the embodiments of this application all come from the main control module (e.g., CPU, not shown in the figure).

[0069] In some embodiments, the first pull-up PU signal and the first pull-down PD signal are output simultaneously, as are the second pull-up PU' signal and the second pull-down PD' signal. The pull-up resistors (R5, R7) and pull-down resistors (R6, R8) are set to have the same resistance value, thereby maintaining the DC level of the output signals of PAD1 and PAD2 at VCC / 2. Since the DC level of the differential low-swing signal is VCC / 2, this function allows PAD1 and PAD2 to maintain the DC level VCC / 2 under all circumstances, thus improving the performance of the low-swing signal.

[0070] This application also provides a chip, including any of the GPIO circuits provided in this application, and a main control module for controlling the operation of the GPIO circuit. The main control module may be one or more, such as a CPU or other main control unit that can output control signals.

[0071] This application also provides an electronic device, including the chip described in this application embodiment.

[0072] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A general-purpose input / output circuit, comprising an output module, an input module, and a pull-up / pull-down module; characterized in that: The output module includes at least: a first output module for outputting a first output signal, and a second output module for outputting a second output signal; The general-purpose input / output circuit also includes: An output control module that is connected to the output terminals of the first output module and the second output module, respectively; The output control module is configured to: receive a first output signal output by the first output module and output a signal to a first pin outside the general-purpose input / output circuit, such that the amplitude of the output signal at the first pin is less than the amplitude of the first output signal; and receive a second output signal output by the second output module and output a signal to a second pin outside the general-purpose input / output circuit, such that the amplitude of the output signal at the second pin is less than the amplitude of the second output signal. The pull-up / pull-down module includes at least: a first pull-up / pull-down module connected to the first pin, and a second pull-up / pull-down module connected to the second pin; The input module includes at least two input terminals, one of which is connected to the first pin and the other is connected to the second pin; the input module is used to receive signals from the first pin and the second pin, and generate an input signal to be output through the output terminal of the input module.

2. The general-purpose input / output circuit according to claim 1, characterized in that, The output control module includes: A first resistor, a second resistor, a first switch, a third resistor, and a fourth resistor are connected in series between the output terminals of the first output module and the second output module; wherein, the first switch is turned on or off under the control of the main control module outside the general-purpose input / output circuit.

3. The general-purpose input / output circuit according to claim 2, characterized in that, The first resistor, the second resistor, the third resistor, and the fourth resistor are all variable resistors.

4. The general-purpose input / output circuit according to claim 2, characterized in that, The output control module also includes: A second switch is connected to the connection point between the first switch and the second resistor, and a third switch is connected to the connection point between the first switch and the third resistor; wherein, the second switch and the third switch are connected to power supply or ground under the control of the main control module outside the general-purpose input / output circuit.

5. The general-purpose input / output circuit according to claim 4, characterized in that, The second switch and the third switch are controlled by the first output drive signal or the second output drive signal output by the main control module.

6. The general-purpose input / output circuit according to claim 1, characterized in that, The output control module includes at least three resistors connected in series between the output terminals of the first output module and the output terminals of the second output module.

7. The general-purpose input / output circuit according to claim 1, characterized in that, The input terminals of the first output module and the second output module are respectively connected to the main control module outside the general-purpose input / output circuit; The first output module and the second output module are controlled by the same output drive signal or different output drive signals output by the main control module.

8. The general-purpose input / output circuit according to claim 7, characterized in that, The second output module includes an inverter and a selector; The inverter's input terminal is connected to the main control module and is used to receive the first output drive signal output by the main control module to the second output module; the inverter's output terminal is connected to the selector. The two input terminals of the selector are respectively connected to the output terminal of the inverter and the main control module. The selector is used to select the inverted signal output of the first output drive signal output by the inverter, or to select the second output drive signal output by the main control module to the second output module.

9. The general-purpose input / output circuit according to any one of claims 1 to 8, characterized in that, The input module includes at least two output terminals, namely a first output terminal and a second output terminal; The input module further includes: a mode signal control terminal and / or a hysteresis voltage control terminal, which are respectively connected to the main control module outside the general-purpose input / output circuit; The mode signal control terminal is used to receive the mode control signal output by the main control module. Under the control of the mode control signal, the input module generates a first input signal and outputs it through the first output terminal; and / or, the input module generates a second input signal and outputs it through the second output terminal. The hysteresis voltage control terminal is used to receive the hysteresis voltage control signal output by the main control module, and to control the magnitude of the hysteresis voltage of the hysteresis comparator in the input module through the hysteresis voltage control signal.

10. A chip, characterized in that, It includes the general-purpose input / output circuit as described in any one of claims 1 to 9, and a main control module for controlling the operation of the general-purpose input / output circuit.

11. An electronic device, characterized in that, Includes the chip described in claim 10.

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