Delayed locking loop device

Abstract

This disclosure provides a delay-locked loop (LLL) device, comprising a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generates a reference clock signal based on the input clock signal. The delay line delays the first signal based on a delay control signal to generate a second signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate a start signal. Upon the start signal, the phase detector detects a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit generates the delay control signal for the delay line based on the phase detection result.

Description

Related applications

[0001] This application is a divisional application of U.S. Patent Application No. 202510416580.0, filed on April 3, 2025, entitled "Delayed Locking Loop Device," which claims priority to U.S. Patent Application No. 18 / 909,128 (priority date October 8, 2024), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to an electronic circuit. In particular, it relates to a delay-locked loop device and its operating method. Background Technology

[0003] Delay-locked loop (LLL) devices are used to delay a clock signal by a specified time to output a corresponding signal. However, LLL devices require an external voltage to operate, and when the external voltage is unstable, the delay time can be affected, potentially causing delay jumps. Therefore, resolving this issue is a priority.

[0004] The prior art description above is merely to provide background information and does not acknowledge that the prior art description above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the prior art above should be considered part of the prior art in this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a delay-locked loop (LLL) device, comprising a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generates a reference clock signal based on the input clock signal. The delay line delays the first signal based on a delay control signal to generate a second signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate a start signal. The phase detector detects a phase difference between the reference clock signal and a feedback clock signal generated by the second signal when the start signal is in a high logic state, to generate a phase detection result. The delay control circuit generates the delay control signal for the delay line based on the phase detection result.

[0006] Another embodiment of this disclosure provides a delay-locked loop (LLL) device, comprising a receiver, a delay line, a frequency detection and control circuit, a first clock divider, a second clock divider, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generates a reference clock signal based on the input clock signal. The delay line delays the first signal based on a delay control signal to generate a second signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate a divider selection signal. The first clock divider divides the reference clock signal based on the divider selection signal using a specific cycle count from a plurality of cycle counts to generate a divided reference clock signal. The second clock divider divides a feedback clock signal generated from the second signal based on the divider selection signal to generate a divided feedback clock signal. The phase detector detects a phase difference between the divided reference clock signal and the divided feedback clock signal to generate a phase detection result. The delay control circuit is used to generate the delay control signal for the delay line based on the phase detection result.

[0007] Another embodiment of this disclosure provides a method for operating a delay-locked loop device, the device including a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The method includes the following steps: comparing an input clock signal with a reference voltage to generate a first signal; generating a reference clock signal based on the input clock signal; detecting an operating frequency of the reference clock signal using the frequency detection and control circuit, and generating a start signal based on a detection result of the operating frequency; when the start signal is in a high logic state, detecting a phase difference between the reference clock signal and a feedback clock signal generated from the first signal through the delay line using the phase detector, to generate a phase detection result; and generating a delay control signal for the delay line using the delay control circuit based on the phase detection result to control a delay time of the first signal.

[0008] In some embodiments, the delay-locked loop (DLL) device can dynamically adjust the startup period of the phase detector based on the operating frequency of the memory device, and is designed to detect the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. Therefore, the DLL device effectively mitigates the delay jump problem caused by timing drift in the delay-locked loop (DLL) due to significant fluctuations in the external power supply voltage (VDD).

[0009] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0011] Figure 1 This is a block diagram illustrating a system for testing memory devices according to some embodiments of this disclosure.

[0012] Figure 2 This is a block diagram illustrating a memory device according to some embodiments of this disclosure.

[0013] Figure 3A This is a block diagram illustrating a delayed locking loop device according to some embodiments of this disclosure.

[0014] Figure 3B This is a block diagram illustrating a delayed locking loop device according to other embodiments of this disclosure.

[0015] Figures 4A-4D It's a waveform diagram, example. Figure 3A Various signals within the medium-delay locking loop device.

[0016] Figure 5A This is a block diagram illustrating a delayed locking loop device according to some embodiments of this disclosure.

[0017] Figure 5B This is a block diagram illustrating a delayed locking loop device according to other embodiments of this disclosure.

[0018] Figures 6A-6D It's a waveform diagram, example. Figure 5A Various signals within the medium-delay locking loop device.

[0019] Figure 7 This is a flowchart illustrating some embodiments of the operation delay locking loop apparatus and method disclosed herein.

[0020] Figure 8 This is a flowchart illustrating an operational delay locking loop apparatus method of other embodiments of this disclosure.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 10: System

[0023] 11: Memory devices

[0024] 12: Signal generating device

[0025] 13: Measuring device

[0026] 14: Computing device

[0027] 15: Display device

[0028] 111: Input signal

[0029] 112: Output signal

[0030] 121: First operating parameter

[0031] 122: Second operating parameter

[0032] 123: Third operating parameter

[0033] 20: Memory device

[0034] 201: Memory Array

[0035] 202: Control Logic

[0036] 203: Synchronization signal generation circuit

[0037] 204: Driver

[0038] 205: Gating signal generator

[0039] 206: Mode control signal

[0040] 207: Address Decoder

[0041] 208: Input reference clock signal

[0042] 209: Data Bus

[0043] 21: Memory controller

[0044] 210: Synchronous output signal

[0045] 211: Instruction Decoder

[0046] 212: Mode Register

[0047] 213: Data Bus

[0048] 215: Address Bus

[0049] 217: Control Signal

[0050] 300A: Delayed Locking Loop Device

[0051] 300B: Delayed Locking Loop Device

[0052] 302: Receiver

[0053] 304: Instruction Decoder

[0054] 306: Delay line

[0055] 308: Amplifier

[0056] 310: Clock Tree

[0057] 312: External driver for the chip

[0058] 314: Solder pad

[0059] 320A: Frequency detection and control circuit

[0060] 320B: Frequency detection and control circuit

[0061] 330: Phase detector

[0062] 340: Delay control circuit

[0063] 500A: Delayed Locking Loop Device

[0064] 500B: Delayed Locking Loop Device

[0065] 502: Receiver

[0066] 504: Instruction Decoder

[0067] 506: Delay Line

[0068] 508: Amplifier

[0069] 510: Clock Tree

[0070] 512: External driver for the chip

[0071] 514: Solder pad

[0072] 520: Frequency detection and control circuit

[0073] 530: Phase detector

[0074] 540: Delay control circuit

[0075] 550A: Clock divider

[0076] 550B: Clock divider

[0077] 552A: Clock Divider

[0078] 552B: Clock divider

[0079] 700: Method

[0080] 710: Steps

[0081] 720: Steps

[0082] 730: Steps

[0083] 740: Steps

[0084] 750: Steps

[0085] 800: Method

[0086] 810: Steps

[0087] 820: Steps

[0088] 830: Steps

[0089] 840: Steps

[0090] 850: Steps

[0091] 860: Steps

[0092] CLK: Clock signal

[0093] DATA: Data

[0094] DIV_SEL: Divider selection signal

[0095] DLL: Delayed Locking Loop

[0096] DL_CTRL: Delay control signal

[0097] DQ: Data bits

[0098] DQS: Data strobe signal

[0099] FB_CLK: Feedback clock signal

[0100] FB_DCLK: Frequency division feedback clock signal

[0101] PD: Phase detection results

[0102] PD_EN: Start signal

[0103] R1: First loop count

[0104] R2: Second cycle count

[0105] R3: Third loop count

[0106] R4: Fourth cycle count

[0107] REF_CLK: Reference clock signal

[0108] REF_DCLK: Frequency division reference clock signal

[0109] S1: Signal

[0110] S2: Signal

[0111] S3: Signal

[0112] S4: Signal

[0113] S5: Signal

[0114] SOUT: Output signal

[0115] t0: Time

[0116] t1: Time

[0117] t2: Time

[0118] t3: Time

[0119] t4: Time

[0120] t5: Time

[0121] t6: Time

[0122] t7: Time

[0123] t8: Time

[0124] t9: Time

[0125] t10: Time

[0126] t11: Time

[0127] t12: Time

[0128] t13: Time

[0129] VDD: Power supply voltage

[0130] VREF: Reference Voltage

[0131] / WE: Write Startup

[0132] / CAS: Row Address Stochastic

[0133] / RAS: Column address strobe Detailed Implementation

[0134] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0135] Terms such as "an embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0136] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0137] Delay-locked loops (LDLs) can be used to maintain a fixed timing relationship between signals in environments where variations in process technology, voltage, clock rate, or temperature can cause this relationship to change over time. A LDL continuously compares the relationship between two signals and provides feedback to adjust and maintain this fixed relationship.

[0138] Lockout time refers to the time interval required for a delayed-lock loop to reach a stable locked state from its initial state. Typically, lockout time is related to the speed of the phase detector in the delayed-lock loop, the magnitude of the charging or discharging current, and the overall bandwidth of the delayed-lock loop.

[0139] Figure 1 This is a block diagram illustrating a system 10 for testing a memory device, representing some embodiments of this disclosure.

[0140] In some embodiments, system 10 is used to determine the target locking time of the delayed locking loop of memory device 11. Memory device 11 is tested after manufacturing and then shipped.

[0141] In some embodiments, system 10 includes hardware and software components that provide a suitable testing operation and functional environment. In some embodiments, system 10 includes a signal generating device 12, a measuring device 13, a computing device 14, and a display device 15.

[0142] In some embodiments, signals, data, instructions, and / or indications are transmitted between one or more of the signal generating device 12, measuring device 13, computing device 14, and display device 15. Furthermore, signals, data, instructions, and / or indications (input signal 111 and output signal 112) are transmitted between system 10 and memory device 11.

[0143] The signal generating device 12 is used to provide an input signal 111 to the memory device 11. In some embodiments, the signal generating device 12 is used to provide a first set of input signals 111 to the memory device 11 according to a first set of operating parameters 121 and a second set of operating parameters 122. In some embodiments, the signal generating device 12 is used to provide a second set of input signals 111 to the memory device 11 according to a second set of first operating parameters 121 and a third set of operating parameters 123.

[0144] according to Figure 1 System 10 is used to determine the target locking time of the delayed locking loop of memory device 11. Memory device 11 is tested after manufacturing and then shipped.

[0145] In some embodiments, system 10 includes hardware and software components that provide a suitable testing operation and functional environment. In some embodiments, system 10 includes a signal generating device 12, a measuring device 13, a computing device 14, and a display device 15.

[0146] Signals, data, instructions, and / or indications are transmitted between one or more of the signal generating device 12, measuring device 13, computing device 14, and display device 15. Signals, data, instructions, and / or indications are transmitted between system 10 and memory device 11.

[0147] The signal generating device 12 is used to provide an input signal 111 to the memory device 11. In some embodiments, the signal generating device 12 is used to provide a first set of input signals 111 to the memory device 11 according to a first set of first operating parameters 121 and a second set of operating parameters 122. In some embodiments, the signal generating device 12 is used to provide a second set of input signals 111 to the memory device 11 according to a second set of first operating parameters 121 and a third set of operating parameters 123.

[0148] In some embodiments, the first operation parameter 121, the second operation parameter 122, or the third operation parameter 123 may be as follows: Figure 1 The inputs shown are given to system 10. These operating parameters are provided by the manufacturer or user of memory device 11. Inputting the minimum, maximum, and step values ​​of these operating parameters enables signal generation device 12 to automatically generate the required operating parameters. Alternatively, these operating parameters are pre-stored in signal generation device 12. The first operating parameter 121 is related to the lock time (tDLLK) of memory device 11. The second operating parameter 122 is related to the clock cycle (tCK) of memory device 11. The third operating parameter 123 is related to the power supply voltage (VDD) of memory device 11. The number of parameters in the third operating parameter group 123 may differ from the number of parameters in the second operating parameter group 122.

[0149] In some embodiments, the measuring device 13 is configured to receive output signals 112 from the memory device 11. In some embodiments, the measuring device 13 is configured to receive and measure a first set of output signals 112 from the memory device 11 in response to a first set of input signals 111. In some embodiments, the measuring device 13 and the computing device 14 are configured to determine whether the delay-locked loop fails under any combination of a first set of first operating parameters 121 and a second set of operating parameters 122. In some embodiments, the measuring device 13 is configured to receive and measure a second set of output signals 112 from the memory device 11 in response to a second set of input signals 111, and, with the assistance of the computing device 14, determine whether the delay-locked loop fails under any combination of a second set of first operating parameters 121 and a third set of operating parameters 123. In some embodiments, the first set of input signals 111 is a data strobe signal (DQS) of the memory device 11. In some embodiments, the determination of whether the delay-locked loop has failed is based on the stability of the DQS.

[0150] In some embodiments, the computing device 14 is configured to determine a first candidate operating parameter from the first set of first operating parameters 121, provided that the delay-locking loop does not fail for each parameter in the second set of operating parameters 122, and subsequently determine a target locking time based on the first candidate operating parameter. In some embodiments, the computing device 14 is further configured to determine a second candidate operating parameter from the second set of first operating parameters 121, provided that the delay-locking loop does not fail for each parameter in the third set of operating parameters 123, and determine a target locking time based on the first candidate operating parameter and the second candidate operating parameter. In some embodiments, the computing device 14 compares the first candidate operating parameter and the second candidate operating parameter to determine the target locking time.

[0151] In some embodiments, the memory device 11 is a double data rate synchronous dynamic random access memory (DDR SDRAM), a second-generation double data rate synchronous dynamic random access memory (DDR2 SDRAM), a third-generation double data rate synchronous dynamic random access memory (DDR3 SDRAM), a fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM), a fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM), or a sixth-generation double data rate synchronous dynamic random access memory (DDR6 SDRAM), but this disclosure is not limited thereto.

[0152] In some embodiments, the display device 15 is used to display one or more two-dimensional drawing areas, including multiple drawing units, each drawing unit corresponding to a combination of a first operation parameter 121 and a second operation parameter 122, or a combination of the first operation parameter 121 and a third operation parameter 123. In some embodiments, one or more two-dimensional drawing areas can help determine candidate operation parameters.

[0153] Figure 2 This is a block diagram illustrating a memory device according to some embodiments of this disclosure.

[0154] For the sake of brevity, Figure 2 A simplified block diagram is presented, showing only the elements relevant to this disclosure. It should be noted that the elements within the memory device 20 are not limited to... Figure 2As shown. In some embodiments, the memory device 20 may include a memory array 201, control logic 202, a synchronization signal generation circuit 203, a driver 204, a strobe signal generator 205, and an address decoder 207.

[0155] In some embodiments, the memory array 201 is used to store data. The memory controller 21 sends address signals to the address decoder 207 via the address bus 215 (ADDR) connected therebetween. The address decoder 207 includes address decoding logic, block control logic, and corresponding logic circuits. The address decoder 207 decodes the received address signals and applies multiple control signals 217 (CTRL) to the memory array 201 according to the decoded address.

[0156] In some embodiments, control logic 202 is used to control read and write operations of memory array 201. Control logic 202 includes an instruction decoder 211 and a mode register 212. The instruction decoder 211 is used to decode multiple signals received from memory controller 21. As shown, these signals include at least write start ( / WE), row address strobe ( / CAS), and column address strobe ( / RAS). Control logic 202 generates multiple mode control signals 206, such as... Figure 2 The signal MODE_CTRL is shown. Control logic 202 stores mode control signals (such as the signal MODE_CTRL) in mode register 212 to control the operation of memory device 20.

[0157] In some embodiments, the synchronization signal generation circuit 203 is used to align the rising / falling edge or leading / trailing edge of the synchronization output signal with the input reference clock signal 208 (REF_CLK) to reduce the offset between the synchronization output signal and the input reference clock signal 208 (REF_CLK). The synchronization signal generation circuit 203 further receives and operates according to the mode control signal 206 (MODE_CTRL), as detailed below.

[0158] In some embodiments, driver 204 drives the data bit (DQ) signal and the data strobe signal (DQS) based on the synchronous output signal 210 (OUT_CLK) generated by synchronous signal generation circuit 203. Driver 204 sequentially receives data DATA from a multiplexer (not shown) via data bus 209, receives the data strobe signal DQS from strobe signal generator 205, and receives the synchronous output signal 210 (OUT_CLK) from synchronous signal generation circuit 203. The data strobe signal DQS has the same frequency as the input reference clock signal 208 (REF_CLK) and is used by memory controller 21 to latch data from memory device 20 during read operations. In response to synchronous output signal 210 (OUT_CLK), driver 204 outputs the received data DATA as the corresponding DQ signal in the DDR configuration and simultaneously outputs the data strobe signal DQS.

[0159] In some embodiments, each DQ signal and data strobe signal DQS collectively define a data bus 213 connected to the memory controller 21. During a read operation, the memory controller 21 latches each bit on the data bus 213 in response to the data strobe signal DQS. The driver 204 includes a latch (not shown) that uses the rising / falling or leading / trailing edge of the synchronization output signal generated by the synchronization signal generation circuit 203 to latch data bits to the DQ signal and latch the data strobe signal DQS to the strobe I / O signal. In this way, the memory array 201 operates based on the synchronization output signal with little or no offset relative to the clock signal applied to the memory array 201.

[0160] In some embodiments, the synchronization signal generation circuit 203 may include a delay locked loop (DLL) device, as described below.

[0161] Figure 3A This is a block diagram illustrating a delayed locking loop device according to some embodiments of this disclosure. Figures 4A-4D It's a waveform diagram, example. Figure 3A Various signals within the medium-delay locking loop device.

[0162] In some embodiments, the delay-locked loop (DLL) device 300A is used to generate an output signal SOUT according to a clock signal CLK, and to provide the output signal SOUT to a pad 314, the pad 314 being configured as follows: Figure 2 The physical input / output pins of the memory device 20 shown. For example... Figure 3AAs shown, the delay-locked loop (DLL) device 300A includes a receiver 302, an instruction decoder 304, a delay line 306, an amplifier 308, a clock tree 310, an off-chip driver (OCD) 312, a frequency detection and control circuit 320A, a phase detector 330, and a delay control circuit 340.

[0163] In some embodiments, receiver 302 is used to receive an input clock signal CLK and a reference voltage VREF, and to generate signal S1 and reference clock signal REF_CLK based on the input clock signal CLK. In some embodiments, the input clock signal CLK may come from an external test device, such as... Figure 1 The system 10 shown includes a signal generation device 12. In some embodiments, the waveforms of signal S1 and reference clock signal REF_CLK are substantially the same as the waveform of input clock signal CLK. In some embodiments, receiver 302 may be implemented using an operational amplifier, but this disclosure is not limited thereto. Instruction decoder 304 is used to receive signal S1 and memory access instructions (not shown) from memory controller (not shown), and generate signal S5 based on the timing of signal S1, such as a memory read instruction or a memory write instruction and a corresponding DQ signal.

[0164] In some embodiments, delay line 306 is a programmable delay line controlled by the control signal DL_CTRL of delay control circuit 340. For example, delay line 306 adjusts (e.g., increases or decreases) the delay of signal S1 to generate signal S2. Therefore, the waveform of signal S2, whose delay time interval is controlled by delay line 306, is similar to the waveform of signal S1. This time interval may be referred to as the delay time of delay-locked loop device 300A (e.g., it may be a positive or negative delay time). For example, a positive delay time indicates that signal S2 lags behind signal S1 by that delay time. A negative delay time indicates that signal S2 leads signal S1 by that delay time.

[0165] In some embodiments, amplifier 308 amplifies signal S2 to generate signal S3. Clock tree 310 performs calculations and generates signal S4 based on signal S3. In some embodiments, the waveform of signal S4 is substantially equal to the waveform of signal S3 or an amplified version of signal S3. Off-chip driver (OCD) 312 generates output signal SOUT based on signals S4 and S5. For example, OCD 312 synchronizes signal S5 (e.g., memory access instructions and corresponding DQ signals) with signal S4, which is the clock signal used by OCD 312, thereby providing output signal SOUT to pad 314. Furthermore, OCD 312 provides a feedback clock signal FB_CLK to phase detector 330. For example, the waveform of feedback clock signal FB_CLK is substantially the same as the waveform of signal S4.

[0166] In some embodiments, the frequency detection and control circuit 320A is used to detect the operating frequency of the reference clock REF_CLK from the receiver 302, and generate a start signal PD_EN for the phase detector 330 based on the detected operating frequency of the reference clock REF_CLK. For example, DDR4 SDRAM supports operating frequencies ranging from 2100MHz to 3600MHz. Figure 2 The memory device 20 described herein utilizes multiple operating frequencies. For illustrative purposes, the reference clock REF_CLK of the DDR4 SDRAM (e.g., memory device 20) includes four operating frequencies: 2100MHz, 2400MHz, 3200MHz, and 3600MHz. However, this disclosure is not limited thereto. The operating frequencies and their number can be adjusted as needed.

[0167] In some embodiments, when the frequency detection and control circuit 320A detects that the operating frequencies of the reference clock signal REF_CLK are 2100MHz, 2400MHz, 3200MHz, and 3600MHz, respectively, the frequency detection and control circuit 320A may activate the phase detector 330 with the start signal PD_EN in each of the first cycle count R1, the second cycle count R2, the third cycle count R3, and the fourth cycle count R4, respectively, for one clock cycle of the reference clock signal REF_CLK. In other words, when the frequency detection and control circuit 320A detects that the operating frequencies of the reference clock signal REF_CLK are 2100MHz, 2400MHz, 3200MHz, and 3600MHz, respectively, the frequency detection and control circuit 320A may divide the frequency of the reference clock signal REF_CLK by (or multiply the period by) the first cycle count R1, the second cycle count R2, the third cycle count R3, and the fourth cycle count R4.

[0168] In some embodiments, for illustrative purposes, the first cycle count R1, the second cycle count R2, the third cycle count R3, and the fourth cycle count R4 may be (but are not limited to) 5, 8, 10, and 12, respectively. It should be noted that the feedback clock signal FB_CLK may be a delayed version of the reference clock signal REF_CLK, therefore a delay or phase difference may exist between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. Accordingly, when the start signal PD_EN is in a high logic state (e.g., "1"), the phase detector 330 can detect the delay or phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK, thereby generating a phase detection result PD, which is sent to the delay control circuit 340.

[0169] For example, when the operating frequency of the reference clock signal REF_CLK is detected to be 2100MHz, the frequency detection and control circuit 320A can activate the start signal PD_EN for one clock cycle every 5 clock cycles of the reference clock signal REF_CLK (e.g., time t0 to t5), as shown. Figure 4A As shown. Furthermore, when the operating frequency of the reference clock signal REF_CLK is detected to be 2400MHz, the frequency detection and control circuit 320A can activate a start signal PD_EN for one clock cycle every eight clock cycles of the reference clock signal REF_CLK (e.g., time t0 to t8), as shown. Figure 4B As shown. Furthermore, when the operating frequency of the reference clock signal REF_CLK is detected to be 3200MHz, the frequency detection and control circuit 320A can activate the start signal PD_EN for one clock cycle every 10 clock cycles of the reference clock signal REF_CLK (e.g., time t0 to t10), as shown. Figure 4C As shown. Furthermore, when the operating frequency of the reference clock signal REF_CLK is detected to be 3600MHz, the frequency detection and control circuit 320A can activate a start signal PD_EN for one clock cycle every 12 clock cycles of the reference clock signal REF_CLK (e.g., time t0 to t12), as shown. Figure 4D As shown.

[0170] In some embodiments, the delay control circuit 340 generates a delay control signal DL_CTRL for the delay line 306, thereby controlling the delay time of the signal S1 based on the delay control signal DL_CTRL to generate the signal S2. Furthermore, the delay control signal DL_CTRL can be between an upper and lower limit, a positive threshold, and a negative threshold, respectively.

[0171] For example, when the phase detector 330 detects that the feedback clock signal FB_CLK lags behind the reference clock signal REF_CLK by a delay time (e.g., a positive phase difference), the phase detection result PD may be positive, causing the delay control circuit 340 to generate a negative delay control signal DL_CTRL, thereby reducing the delay of the feedback clock signal FB_CLK to synchronize with the reference clock signal REF_CLK. Conversely, when the phase detector 330 detects that the feedback clock signal FB_CLK leads the reference clock signal REF_CLK by a delay time (e.g., a negative phase difference), the phase detection result PD may be negative, causing the delay control circuit 340 to generate a positive delay control signal DL_CTRL, thereby increasing the delay of the feedback clock signal FB_CLK to synchronize with the reference clock signal REF_CLK.

[0172] In some traditional methods, Figure 3A The described frequency detection and control circuitry 320A is not used in conventional delay-locked loop (DLL) devices. Instead, the phase detector in the DLL is activated at a fixed number of clock cycles to determine the phase difference between a reference clock signal from an external test device and the feedback clock signal generated by the DLL, regardless of the operating frequency of the memory device. For example, for DDR4 SDRAM, at operating frequencies of 2100MHz (clock cycle = 985.2ps) and 3200MHz (clock cycle = 612.6ps), the phase detector is activated once every 10 clock cycles, which means the phase detector is activated once every 9.85ns and 6.12ns, respectively, to detect the phase difference between the reference clock signal and the feedback clock signal. However, the 9.85ns activation cycle at a 2100MHz operating frequency is approximately 33% slower than the 6.12ns activation cycle at a 3200MHz operating frequency. Therefore, increasing the frequency of the DDR4 SDRAM feedback clock signal at lower operating frequencies becomes increasingly challenging for conventional DLL devices. These problems become even more pronounced in DDR5 SDRAM, which operates at significantly higher frequencies.

[0173] therefore, Figure 3A The delay-locked loop (LLL) device 300A shown can dynamically adjust the activation period of the phase detector 330 according to the operating frequency of the memory device, and is designed to detect the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. In doing so, the LLL device 300A effectively mitigates the delay jump problem caused by timing drift in the delay-locked loop (DLL) that may be caused by significant fluctuations in the external power supply voltage (VDD).

[0174] Figure 3B This is a block diagram illustrating a delayed locking loop device according to other embodiments of this disclosure.

[0175] In some embodiments, Figure 3B The Delay Locked Loop (DLL) device 300B shown may be similar to the Delay Locked Loop device 300A, the difference being that the Delay Locked Loop device 300B is configured for a memory device, specifically DDR5 SDRAM. For example, DDR5 SDRAM can support significantly higher operating frequencies compared to DDR4 SDRAM, such as between 4800MHz and 7200MHz. For illustrative purposes, the reference clock REF_CLK of the DDR5 SDRAM (such as memory device 20) may include four operating frequencies, namely 4800MHz, 5600MHz, 6400MHz, and 7200MHz, although this disclosure is not limited thereto. It should be noted that the operating frequencies and their number can be adjusted as needed.

[0176] In some embodiments, Figure 3B The frequency detection and control circuit 320B in the delay-locked loop device 300B shown is used to detect the operating frequency of the reference clock signal REF_CLK of the DDR5 SDRAM (such as memory device 20), and generate the start signal PD_EN of the phase detector 330 according to the detected operating frequency of the reference clock REF_CLK.

[0177] For example, when the operating frequencies of the reference clock signal REF_CLK are detected to be 4800MHz, 5600MHz, 6400MHz, and 7200MHz, the frequency detection and control circuit 320B can enable the phase detector 330 with a start signal PD_EN for one clock cycle of the reference clock signal REF_CLK every fifth cycle count R5, sixth cycle count R6, seventh cycle count R7, and eighth cycle count R8, respectively. In other words, when the operating frequencies of the reference clock signal REF_CLK are detected to be 4800MHz, 5600MHz, 6400MHz, and 7200MHz, the frequency detection and control circuit 320B can divide the frequency of the reference clock signal REF_CLK by (or multiply the period by) the fifth cycle count R5, sixth cycle count R6, seventh cycle count R7, and eighth cycle count R8, respectively.

[0178] In some embodiments, for illustrative purposes, the fifth cycle count R5, the sixth cycle count R6, the seventh cycle count R7, and the eighth cycle count R8 may be (but are not limited to) 14, 18, 20, and 24, respectively. It should be noted that the feedback clock signal FB_CLK may be a delayed version of the reference clock signal REF_CLK, therefore a delay or phase difference may exist between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. Therefore, when the start signal PD_EN is in a high logic state (e.g., "1"), the phase detector 330 detects the delay or phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK, thereby generating a phase detection result PD, which is sent to the delay control circuit 340.

[0179] It should be noted that the waveforms of the reference clock signal REF_CLK, the feedback clock signal FB_CLK, and the start signal PD_EN at 4800MHz, 5600MHz, 6400MHz, and 7200MHz may be similar to Figures 4A to 4D The waveform shown is so detailed that it will not be repeated here.

[0180] In some embodiments, Figure 3B The frequency detection and control circuit 320B shown can be integrated into Figure 3A In the frequency detection and control circuit 320A shown, it indicates that the frequency detection and control circuit 320A can detect the operating frequency of the reference clock signal REF_CLK compatible with DDR4 SDRAM and DDR5 SDRAM, and generate the start signal PD_EN of the phase detector 330 based on the detection result of the operating frequency.

[0181] Figure 5A This is a block diagram illustrating a delayed locking loop device according to some embodiments of this disclosure. Figures 6A-6D It's a waveform diagram, example. Figure 5A Various signals within the medium-delay locking loop device.

[0182] In some embodiments, the delay-locked loop device 500A is configured to generate an output signal SOUT based on a clock signal CLK and provide the output signal SOUT to a pad 514, which is configured as follows: Figure 2 The physical input / output pins of the memory device 20 shown. For example... Figure 5A As shown, the delay-locked loop device 500A includes a receiver 502, an instruction decoder 504, a delay line 506, an amplifier 508, a clock tree 510, an external chip driver (OCD) 512, a frequency detection and control circuit 520, a phase detector 530, a delay control circuit 540, and clock dividers 550A and 552A.

[0183] In some embodiments, receiver 502 is used to receive an input clock signal CLK and a reference voltage VREF, and to generate signal S1 and reference clock signal REF_CLK based on the input clock signal CLK. In some embodiments, the input clock signal CLK may come from an external test device, such as... Figure 1 The system 10 shown includes a signal generation device 12. In some embodiments, the waveforms of signal S1 and reference clock signal REF_CLK are substantially the same as the waveform of input clock signal CLK. In some embodiments, receiver 502 is implemented using an operational amplifier. Instruction decoder 504 is used to receive signal S1 and signals from memory controller (e.g., Figure 2 The memory controller 21 shown generates memory access instructions and corresponding DQ signals, and generates signals S5 according to the timing of signal S1, such as memory read instructions or memory write instructions and corresponding DQ signals.

[0184] In some embodiments, delay line 506 is a programmable delay line controlled by the control signal DL_CTRL of delay control circuit 540. For example, delay line 506 can adjust (e.g., increase or decrease) the delay of signal S1 to generate signal S2. Therefore, the waveform of signal S2, whose delay time interval is controlled by delay line 506, is similar to that of signal S1. This time interval can be referred to as the delay time of delay-locked loop device 500A (e.g., it may be a positive or negative delay time). For example, when the delay time is positive, it indicates that signal S2 lags behind signal S1 by that delay time. When the delay time is negative, it indicates that signal S2 leads signal S1 by that delay time.

[0185] In some embodiments, amplifier 508 amplifies signal S2 to generate signal S3. Clock tree 510 performs calculations and generates signal S4 based on signal S3. In some embodiments, the waveform of signal S4 is substantially equal to the waveform of signal S3 or an amplified version of signal S3. External chip driver (OCD) 512 generates output signal SOUT based on signals S4 and S5. For example, OCD 512 synchronizes signal S5 (e.g., memory access instructions and corresponding data signals) with signal S4, which is the clock signal used by OCD 512, thereby providing output signal SOUT to pad 514. Furthermore, OCD 512 generates a feedback clock signal FB_CLK from signal S4 to clock divider 552A. For example, the waveform of feedback clock signal FB_CLK is substantially the same as the waveform of signal S4.

[0186] In some embodiments, the frequency detection and control circuit 520 is used to detect the operating frequency of the reference clock REF_CLK from the receiver 502, and generate a divider selection signal DIV_SEL for the clock divider 550A and the clock divider 552A based on the detected operating frequency of the reference clock REF_CLK. For example, DDR4 SDRAM can support operating frequencies ranging from 2100MHz to 3600MHz. Figure 2 The memory device 20 described herein utilizes multiple operating frequencies. For illustrative purposes, the reference clock REF_CLK of the DDR4 SDRAM (e.g., memory device 20) may include four operating frequencies: 2100MHz, 2400MHz, 3200MHz, and 3600MHz. However, this disclosure is not limited thereto. The operating frequencies and their number may be adjusted as needed.

[0187] In some embodiments, when the frequency detection and control circuit 520 detects that the operating frequency of the reference clock signal REF_CLK is 2100MHz, 2400MHz, 3200MHz, and 3600MHz, the frequency detection and control circuit 520 generates a divider selection signal DIV_SEL as a first value, a second value, a third value, and a fourth value, respectively. For descriptive purposes, the first value, second value, third value, and fourth value may be 2'b00, 2'b01, 2'b10, and 2'b11. Clock dividers 550A and 552A generate a divided reference clock signal REF_DCLK and a divided feedback clock signal FB_DCLK from the reference clock signal REF_CLK and the feedback clock signal FB_CLK, respectively, based on the divider selection signal DIV_SEL from the frequency detection and control circuit 520.

[0188] Specifically, when the frequency divider selection signal DIV_SEL is the first value, the second value, the third value, and the fourth value, the clock frequency divider 550A and the clock frequency divider 552A divide the reference clock signal REF_CLK and the feedback clock signal FB_CLK by the first cycle count R1, the second cycle count R2, the third cycle count R3, and the fourth cycle count R4, respectively.

[0189] In some embodiments, for illustrative purposes, the first cycle count R1, the second cycle count R2, the third cycle count R3, and the fourth cycle count R4 may be (but are not limited to) 5, 8, 10, and 12, respectively. It should be noted that the feedback clock signal FB_CLK may be a delayed version of the reference clock signal REF_CLK, therefore there may be a delay or phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. Furthermore, the frequency-divided reference clock signal REF_DCLK is a frequency-divided version of the reference clock signal REF_CLK, and the frequency-divided feedback clock signal FB_DCLK is a frequency-divided version of the feedback clock signal FB_CLK. Moreover, clock dividers 550A and 552A output the frequency-divided reference clock signal REF_DCLK and the frequency-divided feedback clock signal FB_DCLK to the phase detector 530. Therefore, the phase detector 530 detects the delay or phase difference between the frequency divider reference clock signal REF_DCLK and the frequency divider feedback clock signal FB_DCLK in each clock cycle of the frequency divider reference clock signal REF_DCLK, thereby generating a phase detection result PD, which is sent to the delay control circuit 540.

[0190] In some embodiments, when the operating frequency of the reference clock signal REF_CLK is detected to be 2100MHz, the frequency detection and control circuit 520 generates a divider selection signal DIV_SEL with a value of 2'b00. Therefore, the clock divider 550A responds to the divider selection signal DIV_SEL set to 2'b00 and outputs a divided reference clock signal REF_DCLK with a clock period (e.g., from time t0 to t5) that is 5 times longer than the reference clock signal REF_CLK. Figure 6A As shown. Similarly, the clock divider 552A also responds to the divider selection signal DIV_SEL set to 2'b00, outputting a divided feedback clock signal FB_DCLK with a clock period 5 times longer than the feedback clock signal FB_CLK, as shown. Figure 6A As shown.

[0191] Furthermore, when the operating frequency of the reference clock signal REF_CLK is detected to be 2400MHz, the frequency detection and control circuit 520 generates a divider selection signal DIV_SEL with a value of 2'b01. Therefore, the clock divider 550A responds to the divider selection signal DIV_SEL set to 2'b01, outputting a divided reference clock signal REF_DCLK with a clock period (e.g., from time t0 to t8) that is 8 times longer than the reference clock signal REF_CLK. Figure 6B As shown. Similarly, the clock divider 552A also responds to the divider selection signal DIV_SEL set to 2'b01, outputting a divided feedback clock signal FB_DCLK with a clock period 8 times longer than the feedback clock signal FB_CLK, as shown. Figure 6BAs shown.

[0192] Furthermore, when the operating frequency of the reference clock signal REF_CLK is detected to be 3200MHz, the frequency detection and control circuit 520 generates a divider selection signal DIV_SEL with a value of 2'b10. Therefore, the clock divider 550A responds to the divider selection signal DIV_SEL set to 2'b10, outputting a divided reference clock signal REF_DCLK with a clock period (e.g., from time t0 to t10) 10 times longer than the reference clock signal REF_CLK, as shown below. Figure 6C As shown. Similarly, the clock divider 552A also responds to the divider selection signal DIV_SEL set to 2'b10, outputting a divided feedback clock signal FB_DCLK with a clock period 10 times longer than the feedback clock signal FB_CLK, as shown. Figure 6C As shown.

[0193] Furthermore, when the operating frequency of the reference clock signal REF_CLK is detected to be 3600MHz, the frequency detection and control circuit 520 generates a divider selection signal DIV_SEL with a value of 2'b11. Therefore, the clock divider 550A responds to the divider selection signal DIV_SEL with a value of 2'b11, outputting a divided reference clock signal REF_DCLK with a clock period (e.g., from time t0 to t12) that is 12 times longer than the reference clock signal REF_CLK. Figure 6D As shown. Similarly, the clock divider 552A also responds to the divider selection signal DIV_SEL set to 2'b11, outputting a divided feedback clock signal FB_DCLK with a clock period 12 times longer than the feedback clock signal FB_CLK, as shown. Figure 6D As shown.

[0194] In some embodiments, the delay control circuit 540 generates a delay control signal DL_CTRL to the delay line 506, thereby controlling the delay time of the signal S1 based on the delay control signal DL_CTRL to generate the signal S2. Furthermore, the delay control signal DL_CTRL is between the upper and lower limits, and between a positive threshold and a negative threshold, respectively.

[0195] For example, when phase detector 530 detects that the frequency-divided feedback clock signal FB_DCLK lags behind the frequency-divided reference clock signal REF_DCLK by a delay time, the phase detection result PD may be positive, causing delay control circuit 540 to generate a negative delay control signal DL_CTRL, thereby reducing the delay of the feedback clock signal FB_CLK to synchronize with the reference clock signal REF_CLK. Furthermore, when phase detector 330 detects that the frequency-divided feedback clock signal FB_DCLK leads the frequency-divided reference clock signal REF_DCLK by a delay time, the phase detection result PD may be negative, causing delay control circuit 340 to generate a positive delay control signal DL_CTRL, thereby increasing the delay of the feedback clock signal FB_CLK to synchronize with the reference clock signal REF_CLK.

[0196] therefore, Figure 5A The delay-locked loop (LLB) device 500A shown can dynamically adjust the period of the phase detector 530 used to detect the phase difference between the frequency-divided reference clock signal REF_DCLK and the frequency-divided feedback clock signal FB_DCLK according to the detected operating frequency of the memory device. Therefore, the LLB device 500A effectively mitigates the delay jump problem caused by timing drift in the delay-locked loop (DLL) that may be caused by significant fluctuations in the external power supply voltage (VDD).

[0197] Figure 5B This is a block diagram of a delayed locking loop device according to some embodiments of the present disclosure.

[0198] In some embodiments, Figure 5B The Delay Locked Loop (DLL) device 500B shown may be similar to the Delay Locked Loop device 500A, the difference being that the Delay Locked Loop device 500B is configured for a memory device, specifically DDR5 SDRAM. For example, DDR5 SDRAM can support significantly higher operating frequencies compared to DDR4 SDRAM, such as between 4800MHz and 7200MHz. For illustrative purposes, the reference clock REF_CLK of the DDR5 SDRAM (such as memory device 20) includes four operating frequencies: 4800MHz, 5600MHz, 6400MHz, and 7200MHz, although this disclosure is not limited thereto. It should be noted that the operating frequencies and their number can be adjusted as needed.

[0199] In some embodiments, Figure 5BThe frequency detection and control circuit 520 in the delay-locked loop device 500B shown is used to detect the operating frequency of the reference clock signal REF_CLK of the DDR5 SDRAM (such as memory device 20), and generate a divider selection signal DIV_SEL for the clock divider 550B and the clock divider 552B based on the detected operating frequency of the reference clock REF_CLK.

[0200] For example, when the operating frequency of the reference clock signal REF_CLK is detected to be 4800MHz, 5600MHz, 6400MHz, and 7200MHz, the frequency detection and control circuit 520 can generate a divider selection signal DIV_SEL with values ​​of 2'b00, 2'b01, 2'b10, and 2'b11, respectively, so that the clock divider 550B and the clock divider 550A divide the reference clock signal REF_CLK and the feedback clock signal FB_CLK by the fifth cycle count R5, the sixth cycle count R6, the seventh cycle count R7, and the eighth cycle count R8, respectively, to output the divided reference clock signal REF_DCLK and the divided feedback clock signal FB_DCLK.

[0201] In some embodiments, for illustrative purposes, the fifth cycle count R5, the sixth cycle count R6, the seventh cycle count R7, and the eighth cycle count R8 may be (but are not limited to) 14, 18, 20, and 24, respectively. It should be noted that the feedback clock signal FB_CLK may be a delayed version of the reference clock signal REF_CLK, therefore a delay or phase difference may exist between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. Furthermore, the frequency-divided reference clock signal REF_DCLK is a frequency-divided version of the reference clock signal REF_CLK, and the frequency-divided feedback clock signal FB_DCLK is a frequency-divided version of the feedback clock signal FB_CLK. Therefore, the phase detector 530 detects the delay or phase difference between the frequency-divided reference clock signal REF_DCLK and the frequency-divided feedback clock signal FB_DCLK in each clock cycle of the frequency-divided reference clock signal REF_DCLK, thereby generating a phase detection result PD, which is sent to the delay control circuit 540.

[0202] It should be noted that the waveforms of the reference clock signal REF_CLK and the feedback clock signal FB_CLK at 4800MHz, 5600MHz, 6400MHz, and 7200MHz, as well as the start signal PD_EN, may be similar to... Figures 6A to 6D The waveform shown is so detailed that it will not be repeated here.

[0203] In some embodiments, Figure 5AThe frequency detection and control circuit 520 shown can detect the operating frequency of the reference clock signal REF_CLK, which is compatible with both DDR4 SDRAM and DDR5 SDRAM, and generate a divider selection signal DIV_SEL for clock dividers 550A and 552A based on the detected operating frequency. Furthermore, Figure 5B The clock divider 550B and clock divider 552B shown can also be integrated into... Figure 5A In the clock dividers 550A and 552A shown, this integration means that clock dividers 550A and 552A can divide the reference clock signal REF_CLK and the feedback clock signal FB_CLK by a specific cycle count, respectively, according to the divider selection signal DIV_SEL, to output the divided reference clock signal REF_DCLK and the divided feedback clock signal FB_DCLK. Therefore, phase detector 530 can determine the phase difference between the divided reference clock signal REF_DCLK and the divided feedback clock signal FB_DCLK to generate a phase detection result PD.

[0204] In some embodiments, when Figure 5A The delay-locked loop device 500A shown supports eight operating frequencies and eight cycle counts to cover DDR4 SDRAM and DDR5 SDRAM. The frequency detection and control circuit 520 generates a divider selection signal that is a 3-bit signal. For example, when the divider selection signal is 3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, and 3'b111, clock dividers 550A and 552A divide the reference clock signal REF_CLK and the feedback clock signal FB_CLK using the first cycle count, second cycle count, third cycle count, fourth cycle count, fifth cycle count, sixth cycle count, seventh cycle count, and eighth cycle count, respectively, to generate the divided reference clock signal REF_DCLK and the divided feedback clock signal FB_DCLK.

[0205] Figure 7 This is a flowchart illustrating some embodiments of the operation delay locking loop apparatus method disclosed herein. Please refer to... Figure 3A and Figure 7 . Figure 7 The method 700 shown includes steps 710 to 750.

[0206] Step 710: Compare the input clock signal with a reference voltage to generate a first signal. In some embodiments, the receiver 302 receives an input clock signal CLK, which is compared with a reference voltage VREF to generate a signal S1 (e.g., the first signal).

[0207] Step 720: Generate a reference clock signal based on the input clock signal. In some embodiments, the receiver 302 generates a reference clock signal REF_CLK based on the input clock signal CLK. Furthermore, the waveform of the reference clock signal REF_CLK may be similar to the waveform of the input clock signal CLK.

[0208] Step 730: The frequency detection and control circuit detects the operating frequency of the reference clock signal and generates a start signal based on the detection result of the operating frequency. In some embodiments, the frequency detection and control circuit 320A is used to detect the operating frequency of the reference clock signal REF_CLK, which is compatible with DDR4 SDRAM and DDR5 SDRAM, and generates a start signal PD_EN for the phase detector 330 based on the detection result of the operating frequency.

[0209] Step 740: In response to a high logic state start signal, a phase detector is used to detect the phase difference between a reference clock signal and a feedback clock signal generated from a first signal via a delay line, to generate a phase detection result. In some embodiments, the phase detector 330 is used to detect the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK to generate a phase detection result PD, which is sent to the delay control circuit 340.

[0210] Step 750: Using a delay control circuit, based on the phase detection result, a control signal is generated for the delay line to control the delay time of the first signal. In some embodiments, the delay control circuit 340 generates a control signal DL_CTRL for the delay line 306 based on the phase detection result PD. Furthermore, the delay line 306 is a programmable delay line controlled by the control signal DL_CTRL of the delay control circuit 340. For example, the delay line 306 adjusts (e.g., increases or decreases) the delay of signal S1 to generate signal S2. Therefore, the waveform of signal S2, whose delay time interval is controlled by the delay line 306, is similar to the waveform of signal S1.

[0211] Figure 8 This is a flowchart illustrating an operation delay locking loop apparatus method of other embodiments of this disclosure. Please refer to... Figure 5A and Figure 8 . Figure 8 The method 800 shown includes steps 810 to 860.

[0212] Step 810: Compare the input clock signal with a reference voltage to generate a first signal. In some embodiments, the receiver 502 receives an input clock signal CLK, which is compared with a reference voltage VREF to generate a signal S1 (e.g., the first signal).

[0213] Step 820: Generate a reference clock signal based on the input clock signal. In some embodiments, the receiver 502 may generate a reference clock signal REF_CLK based on the input clock signal CLK. Furthermore, the waveform of the reference clock signal REF_CLK may be similar to the waveform of the input clock signal CLK.

[0214] Step 830: The frequency detection and control circuit detects the operating frequency of the reference clock signal and generates a divider selection signal based on the detected operating frequency. In some embodiments, the frequency detection and control circuit 520 is used to detect the operating frequency of the reference clock signal REF_CLK, which is compatible with DDR4 SDRAM and DDR5 SDRAM, and generates a divider selection signal DIV_SEL for clock dividers 550A and 552A based on the detected operating frequency.

[0215] Step 840: In response to the divider selection signal, a frequency-divided reference clock signal and a frequency-divided feedback clock signal are generated by dividing the reference clock signal and the feedback clock signal generated from the first signal via the delay line by a specific period count using a first clock divider and a second clock divider. In some embodiments, the first clock divider and the second clock divider may respectively refer to... Figure 5A The clock divider 550A and clock divider 552A are shown. Furthermore, the specific cycle count can be the first cycle count R1 to the eighth cycle count R8 described in the foregoing embodiments, depending on the operating frequency of the detected reference clock signal REF_CLK.

[0216] Step 850: The phase difference between the frequency division reference clock signal and the frequency division feedback clock signal is detected using a phase detector to generate a phase detection result. In some embodiments, the phase detector 530 is used to detect the phase difference between the frequency division reference clock signal REF_DCLK and the frequency division feedback clock signal FB_DCLK to generate a phase detection result PD, which is sent to the delay control circuit 540.

[0217] Step 860: Using a delay control circuit, based on the phase detection result, a control signal is generated for the delay line to control the delay time of the first signal. In some embodiments, the delay control circuit 540 generates a control signal DL_CTRL for the delay line 506 based on the phase detection result PD. Furthermore, the delay line 506 is a programmable delay line controlled by the control signal DL_CTRL of the delay control circuit 540. For example, the delay line 506 adjusts (e.g., increases or decreases) the delay of signal S1 to generate signal S2. Therefore, the waveform of signal S2, delayed by the time interval controlled by the delay line 506, is similar to the waveform of signal S1.

[0218] One embodiment of this disclosure provides a delay-locked loop device, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generates a reference clock signal based on the input clock signal. The delay line delays the first signal according to a delay control signal to generate a second signal. The frequency detection and control circuit detects the operating frequency of the reference clock signal to generate a start signal. The phase detector, upon receiving the start signal in a high logic state, detects the phase difference between the reference clock signal and a feedback clock signal generated from the second signal to generate a phase detection result. The delay control circuit generates a delay control signal for the delay line based on the phase detection result.

[0219] Another embodiment of this disclosure provides a delay-locked loop device, comprising a receiver, a delay line, a frequency detection and control circuit, a first clock divider, a second clock divider, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generates a reference clock signal based on the input clock signal. The delay line delays the first signal according to a delay control signal to generate a second signal. The frequency detection and control circuit detects the operating frequency of the reference clock signal to generate a divider selection signal. The first clock divider divides the reference clock signal using a specific cycle count from a plurality of cycle counts according to the divider selection signal to generate a divided reference clock signal. The second clock divider divides the feedback clock signal generated from the second signal according to the divider selection signal to generate a divided feedback clock signal. The phase detector detects the phase difference between the divided reference clock signal and the divided feedback clock signal to generate a phase detection result. The delay control circuit generates a delay control signal for the delay line based on the phase detection result.

[0220] Another embodiment of this disclosure provides a method for operating a delay-locked loop device, the delay-locked loop device including a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The method includes the following steps: comparing an input clock signal with a reference voltage to generate a first signal; generating a reference clock signal based on the input clock signal; detecting the operating frequency of the reference clock signal using the frequency detection and control circuit and generating a start signal based on the detection result of the operating frequency; when the start signal is in a high logic state; detecting the phase difference between the reference clock signal and a feedback clock signal generated from the first signal through the delay line using the phase detector to generate a phase detection result; and generating a delay control signal for the delay line using the delay control circuit based on the phase detection result to control the delay time of the first signal.

[0221] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0222] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A delayed-locking loop device, comprising: A receiver is used to compare an input clock signal and a reference voltage to generate a first signal, and to generate a reference clock signal based on the input clock signal; A delay line is used to delay the first signal based on a delay control signal to generate a second signal; A frequency detection and control circuit is used to detect an operating frequency of the reference clock signal to generate a divider selection signal; A first clock divider is used to divide the reference clock signal based on a specific cycle count of a plurality of cycle counts to generate a divided reference clock signal; A second clock divider is used to divide a feedback clock signal generated from the second signal based on the divider selection signal to generate a frequency-divided feedback clock signal. A phase detector is used to detect a phase difference between the frequency division reference clock signal and the frequency division feedback clock signal to generate a phase detection result; as well as A delay control circuit is used to generate the delay control signal for the delay line based on the phase detection result.

2. The delay-locked loop device as claimed in claim 1, wherein the operating frequency of the reference clock signal is compatible with a Double Data Rate (DDR) Generation IV Synchronous Dynamic Random Access Memory and / or a Double Data Rate (DDR) Generation V Synchronous Dynamic Random Access Memory.

3. The delay-locked loop device as claimed in claim 1, wherein the frequency detection and control circuit is configured to generate a first value, a second value, a third value, and a fourth value for the frequency divider selection signal when the detected operating frequencies of the reference clock signal are a first operating frequency, a second operating frequency, a third operating frequency, and a fourth operating frequency, respectively.

4. The delay-locked loop device as claimed in claim 3, wherein... The fourth operating frequency is higher than the third operating frequency. The third operating frequency is higher than the second operating frequency, and The second operating frequency is higher than the first operating frequency.

5. The delay-locked loop device of claim 4, wherein the plurality of cycle counts includes a first cycle count, a second cycle count, a third cycle count, and a fourth cycle count, and the first clock divider and the second clock divider are used to divide the reference clock signal and the feedback clock signal by one of the first cycle count, the second cycle count, the third cycle count, and the fourth cycle count according to the divider selection signal.

6. The delay-locked loop device as claimed in claim 5, wherein... The fourth cycle count is greater than the third cycle count. The third loop count is greater than the second loop count, and The second cycle count is greater than the first cycle count.

7. The delay-locked loop apparatus of claim 6, wherein the frequency detection and control circuit is configured to generate a fifth value, a sixth value, a seventh value, and an eighth value for the frequency divider selection signal when the detected operating frequencies of the reference clock signal are a fifth operating frequency, a sixth operating frequency, a seventh operating frequency, and an eighth operating frequency, respectively.

8. The delay-locked loop apparatus of claim 7, wherein the plurality of cycle counts includes a fifth cycle count, a sixth cycle count, a seventh cycle count, and an eighth cycle count, and the first clock divider and the second clock divider are further configured to divide the reference clock signal and the feedback clock signal by one of the first cycle count, the second cycle count, the third cycle count, the fourth cycle count, the fifth cycle count, the sixth cycle count, the seventh cycle count, and the eighth cycle count according to the divider selection signal.

9. The delay-locked loop device as claimed in claim 8, wherein... The eighth operating frequency is higher than the seventh operating frequency. The seventh operating frequency is higher than the sixth operating frequency. The sixth operating frequency is higher than the fifth operating frequency. The fifth operating frequency is higher than the fourth operating frequency. The eighth cycle count is greater than the seventh cycle count. The seventh cycle count is greater than the sixth cycle count. The sixth cycle count is greater than the fifth cycle count, and The fifth cycle count is greater than the fourth cycle count.

10. The delay-locked loop device as claimed in claim 1, wherein... When the frequency division feedback clock signal lags behind the frequency division reference clock signal, the phase detection result is positive, and When the frequency division feedback clock signal leads the frequency division reference clock signal, the phase detection result is negative.

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