Low power low jitter sub-sampling phase-locked loop based on floating inverter amplifier

Abstract

A low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier includes: a subsampling phase detector, a subsampling charge pump, a low-pass filter, and a voltage-controlled oscillator (VCO) connected in sequence to form the main subsampling loop; and a frequency-locked loop consisting of a phase detector, a dead-time circuit, a charge pump, and a frequency divider. This invention introduces a floating inverter amplifier core into the charge-sampling phase detector structure and employs a combination of reset, sampling, and resampling to convert the phase error between the reference signal and the VCO output signal into a differential sampling voltage. This improves the equivalent phase detection gain, reduces in-band phase noise, reduces the periodic modulation of the VCO load during the sampling phase, and balances low jitter and low-power clock signal output.

Description

Technical Field

[0001] This invention relates to a technology in the field of signal processing, specifically a low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier. Background Technology

[0002] In existing low-jitter subsampling phase-locked loops (PLLs), the removal of the frequency divider in the main loop solves the problem of phase detector and charge pump noise being amplified by the division ratio, thus achieving lower in-band noise. However, its drawbacks are significant. Because the voltage-controlled oscillator (VCO) is sampled directly, the impedance of the VCO resonant cavity changes continuously with the switching of the sampling switch, introducing substantial spurious signals. Improved subsampling PLLs use isolation buffers to reduce reference spurious signals, but the parasitic capacitance clock feedthrough problem persists, and the reference signal duty cycle cannot be less than 5-10 times the VCO period, meaning the reference spurious signal problem remains unresolved. Charge-sampling phase detectors achieve lower reference spurious signals, but suffer from problems such as excessive load and significant common-mode variation. Summary of the Invention

[0003] This invention addresses the challenges of existing technologies in subsampling main loops, such as limited phase detection gain, ripple propagation from sampling nodes to subsequent stages, common-mode voltage fluctuations, and reference spurious emissions caused by sampling disturbances. It aims to simultaneously achieve high phase detection gain, stable common-mode voltage, reduced propagation of transient disturbances from sampling nodes to subsequent stages, and simplified subsampling charge pump interface design at lower power consumption. It also addresses the trade-offs between high phase detection gain, low output ripple, low reference spurious emissions, output common-mode stability, and complex interface design in subsampling phase detectors. The invention proposes a low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier. This subsampling phase detector incorporates a floating inverter amplifier core into the charge-sampling phase detection structure and employs a combination of reset, sampling, and resampling to convert the phase error between the reference signal and the voltage-controlled oscillator (VCO) output signal into a differential sampling voltage. This improves the equivalent phase detection gain, reduces in-band phase noise, reduces periodic modulation of the VCO load during the sampling phase, and balances low jitter and low-power clock signal output.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a low-power, low-jitter subsampling phase-locked loop (PLL) based on a floating inverter amplifier, comprising: a subsampling phase detector, a subsampling charge pump, a low-pass filter, and a voltage-controlled oscillator (VCO) connected in sequence to form the main subsampling loop; and a frequency-locked loop consisting of a phase detector, a dead-time circuit, a charge pump, and a frequency divider. The subsampling phase detector performs subsampling processing on the VCO output signal based on the phase relationship between a reference clock signal and the VCO output signal to obtain a differential output voltage corresponding to the phase error. The subsampling charge pump converts the differential output voltage into a voltage corresponding to the phase error. The subsampling charge pump output current corresponding to the difference is filtered by a low-pass filter and then used by a voltage-controlled oscillator to generate an output clock signal, which is fed back to the subsampling phase detector. The frequency divider performs N-fold frequency division on the clock signal to obtain a frequency division feedback signal. The frequency and phase detector output pull-up and pull-down control signals based on the frequency difference and phase difference between the reference clock signal and the frequency division feedback signal. The dead-time circuit generates an auxiliary adjustment current through the charge pump when the loop frequency approaches the lockout range based on the pull-up and pull-down control signals. When the phase-locked loop starts or loses lockout, the auxiliary adjustment control oscillator output frequency enters the lockout range of the subsampling main loop.

[0006] This invention relates to a phase-locked loop method based on the above-described device, comprising:

[0007] Step 1: Use a frequency-locking loop to assist in capturing the output frequency of the voltage-controlled oscillator (VCO), ensuring the VCO output frequency enters the locking range of the subsampling main loop. Specifically, this includes:

[0008] 1.1 The frequency divider divides the output signal of the voltage-controlled oscillator to obtain a feedback signal for comparison with the reference signal; the frequency and phase detector receives the reference signal and the feedback signal, and generates a corresponding frequency error control signal based on the frequency difference and phase difference between the two.

[0009] 1.2 The dead-zone circuit receives the frequency error control signal output by the frequency and phase detector, and suppresses the frequency-locked loop from continuing to output the adjustment signal when the phase error between the reference signal and the feedback signal is within the preset dead-zone range, so that the frequency-locked loop stops or weakens its effect after the output frequency of the voltage-controlled oscillator approaches the target frequency.

[0010] 1.3 The charge pump adjusts the charge and discharge of the low-pass filter or the voltage-controlled oscillator control node according to the control signal output by the dead-time circuit, so that the output frequency of the voltage-controlled oscillator gradually approaches the target frequency; when the output frequency enters the frequency range that the subsampling main loop can lock, the phase tracking is mainly completed by the subsampling main loop.

[0011] Step 2: The output signal of the voltage-controlled oscillator is phase-sampled using a subsampling phase detector based on a floating inverter amplifier to obtain the differential sampling voltage corresponding to the phase error. Specifically, this includes:

[0012] 2.1 During the reset phase, the reset switch controlled by the reset clock closes, resetting the two ends of the pre-charge capacitor to the power supply voltage and ground respectively, and resetting the sampling node of the sampling capacitor to the common-mode voltage.

[0013] 2.2 During the sampling phase, the sampling switch controlled by the sampling clock is closed, and the differential output signal of the voltage-controlled oscillator is applied to the sampling capacitor through the input stage of the floating inverter amplifier. When there is a phase error between the reference sampling time and the predetermined phase point of the voltage-controlled oscillator output signal, the input stage of the floating inverter amplifier generates a differential charging and discharging current corresponding to the phase error, and forms a differential sampling voltage on the sampling capacitor.

[0014] 2.3 During the resampling stage, the resampling switch controlled by the resampling clock is closed to resample the stable sampling voltage on the sampling capacitor and output the resampled differential voltage to the subsequent subsampling charge pump; wherein: the sampling clock and the resampling clock adopt a non-overlapping timing sequence to reduce the transmission of transient disturbances at the sampling node to the subsequent stage.

[0015] Step 3: Perform error conversion and filtering on the differential sampling voltage using a subsampling charge pump and a low-pass filter, specifically including:

[0016] 3.1 The subsampling charge pump receives the differential sampling voltage output from the subsampling phase detector based on the floating inverter amplifier and converts the differential sampling voltage into a charging and discharging current corresponding to the phase error.

[0017] 3.2 The low-pass filter receives the charging and discharging current, filters and smooths the charging and discharging current, and generates a control voltage for controlling the voltage-controlled oscillator.

[0018] Step 4: Adjust the output frequency and phase of the voltage-controlled oscillator according to the control voltage to lock the phase-locked loop. This specifically includes:

[0019] 4.1 When the subsampling phase detector detects a phase error between the reference sampling time and the predetermined phase point of the voltage-controlled oscillator output signal, the subsampling charge pump and low-pass filter change the control voltage of the voltage-controlled oscillator, so that the output frequency and phase of the voltage-controlled oscillator are adjusted in the direction of reducing the phase error.

[0020] 4.2 When the reference sampling time is aligned with or maintains a predetermined phase relationship with the output signal of the voltage-controlled oscillator, the differential sampling voltage output by the subsampling phase detector approaches zero or remains stable. The control voltage of the voltage-controlled oscillator remains stable, the phase-locked loop enters the locked state and outputs a low-jitter clock signal.

[0021] Technical effect

[0022] This invention combines a floating inverter amplifier structure with a charge-sampling sub-sampling phase detector structure to form a sub-sampling phase detector based on a floating inverter amplifier. This is applied to the main loop of an integer-type sub-sampling phase-locked loop (PLL), maintaining a relatively stable output common-mode voltage without introducing additional common-mode feedback circuitry. Simultaneously, by using a resampling branch to transmit phase error information to the subsequent sub-sampling charge pump after the sampling voltage has stabilized, the transmission of transient disturbances from the sampling node to subsequent stages can be reduced, thereby lowering output ripple and the resulting reference spurious emissions. Furthermore, the DC path between the sub-sampling phase detector and the power supply and ground is shut off during the sampling phase, and the front-end sampling network operates approximately as a passive charge sampling network, resulting in lower static power consumption and a better quality factor (FOM) value. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the system of the present invention;

[0024] Figure 2 This is a circuit diagram of a subsampling phase detector based on a floating inverter amplifier;

[0025] Figure 3 The timing diagram for the subsampling phase detector based on a floating inverter amplifier is shown.

[0026] Figure 4 The input and output waveforms of a subsampling phase detector based on a floating inverter amplifier are shown.

[0027] Figure 5 The simulation results of the gain curve of the subsampling phase detector based on the floating inverter amplifier are shown in the figure.

[0028] Figure 6 The simulation results of the gain curve of the subsampling phase detector and charge pump cascade based on the floating inverter amplifier are shown in the figure.

[0029] Figure 7 The key node waveforms of the subsampling phase detector based on a floating inverter amplifier under steady-state locking conditions are shown.

[0030] Figure 8 This is a simulation result diagram of the phase-locked loop locking process in the embodiment;

[0031] Figure 9 This is a simulation result of the phase-locked loop output spectrum in the embodiment;

[0032] Figure 10 The figure shows the simulation results of the phase noise and integral jitter of the phase-locked loop output in the embodiment. Detailed Implementation

[0033] like Figure 1As shown, this embodiment relates to a low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier, comprising: a subsampling phase detector based on a floating inverter amplifier, a subsampling charge pump, a low-pass filter, and a voltage-controlled oscillator connected in sequence to form the subsampling main loop; and a frequency-locked loop comprising a frequency-locked phase detector, a dead-time circuit, a charge pump, and a frequency divider, wherein: the subsampling phase detector uses a reference clock signal CLK. ref and the voltage-controlled oscillator output signal CLK VCO Based on the phase relationship between the two, the output signal of the voltage-controlled oscillator is subsampled to obtain the differential output voltage V corresponding to the phase error. outp and V outn Subsampling charge pump based on differential output voltage V outp and V outn This is then converted into the subsampled charge pump output current I corresponding to the phase error. sscp The low-pass filter is based on the subsampling charge pump output current I. sscp The voltage-controlled oscillator (VCO) control voltage V is then obtained through filtering. ctrl The voltage-controlled oscillator operates based on the control voltage V. ctrl Adjusting its output frequency and phase generates the output clock signal CLK. VCO The output clock signal is then fed back to a subsampled phase detector based on a floating inverter amplifier; the frequency divider uses the voltage-controlled oscillator output signal CLK. VCO The signal is then divided by N to obtain the frequency-divided feedback signal CLK. div The frequency and phase detector uses the reference clock signal CLK. ref and frequency division feedback signal CLK div Based on the frequency and phase difference between the two signals, a pull-up control signal UP and a pull-down control signal DN are output. The dead-time circuit uses the pull-up control signal UP and the pull-down control signal DN, and performs dead-time processing on them when the loop frequency approaches the locking range to obtain the processed control signal UP. DZ and DN DZ The charge pump operates according to the control signal UP. DZ and DN DZ Generate auxiliary regulating current I cp It is connected to the control node of the subsampling main loop to assist in adjusting the voltage-controlled oscillator control voltage V during phase-locked loop startup or loss of lock. ctrl This allows the voltage-controlled oscillator (VCO) output frequency to enter the locking range of the subsampling main loop. Once the VCO output frequency enters the locking range, the adjustment effect of the auxiliary frequency-locking loop is suppressed by the dead-time circuit, and the phase-locked loop (PLL) mainly completes low-noise phase tracking and stable locking by the subsampling main loop.

[0034] like Figure 2As shown, the subsampling phase detector includes: a charge sampling network and a reset network, a floating inverter amplifier core, and a resampling network connected thereto. Specifically: the charge sampling network converts the phase error between the differential output signal of the voltage-controlled oscillator and the reference sampling time into a differential sampling voltage during the sampling phase; the reset network operates according to the reset clock CLK. rst During the reset phase, the pre-charge capacitor C0 and the sampling node V of the charge sampling network are respectively... sp and V sn Initialize; the resampling network is initialized according to the resampling clock CLK. resamp After the voltage at the sampling node stabilizes, the sampling results from the charge sampling network are transmitted to the output node V. outp and V outn The floating inverter amplifier core adopts a differential structure and reduces the fluctuation of the output common-mode voltage caused by the change of input phase with the charge sampling network.

[0035] The reset network includes: a pre-charge capacitor C0, and a reset clock CLK. rst The control includes a pre-charge reset switch and a sampling node reset switch, wherein: the pre-charge capacitor C0 is connected between the upper pre-charge node and the lower pre-charge node; the pre-charge reset switch is connected between the power supply voltage and the upper pre-charge node of the pre-charge capacitor C0, and between ground and the lower pre-charge node of the pre-charge capacitor C0; the sampling node reset switch is connected to the common-mode voltage V. cm With the first sampling node V sn Between, common-mode voltage V cm With the second sampling node V sp Between. During the reset phase, the reset clock CLK. rst The pre-charge reset switch and the sampling node reset switch are closed to reset the upper pre-charge node of the pre-charge capacitor C0 to the power supply voltage and the lower pre-charge node to ground, thereby storing the initial charge required for the sampling phase on the pre-charge capacitor C0; simultaneously, the first sampling node V... sn Second sampling node V sp Reset to common-mode voltage V cm This ensures that subsequent sampling phases have a defined initial voltage state. After the reset phase ends, the reset clock CLK is activated. rst When the precharge reset switch and the sampling node reset switch are disconnected, the subsampling phase detector based on the floating inverter amplifier enters the sampling preparation state.

[0036] The charge sampling network includes: a sampling clock CLK samp Controlled power supply connection switch, first sampling switch, second sampling switch, first sampling capacitor C sn Second sampling capacitor C spWherein: the power supply connection switch is connected between the upper pre-charge node of the pre-charge capacitor C0 and the upper floating power supply node of the floating inverter amplifier core, and between the lower pre-charge node of the pre-charge capacitor C0 and the lower floating power supply node of the floating inverter amplifier core; the first sampling switch is connected between the internal sampling output node of the first floating inverter unit and the first sampling node V. sn Between, the second sampling switch is connected to the internal sampling output node of the second floating inverter unit and the second sampling node V. sp Between; the first sampling capacitor C sn One end is connected to the first sampling node V sn The other end is grounded, and the second sampling capacitor C sp One end is connected to the second sampling node V sp The other end is grounded. During the sampling phase, the sampling clock CLK... samp The power supply connection switch, the first sampling switch, and the second sampling switch are closed to allow the charge stored in the pre-charge capacitor C0 to provide instantaneous power to the floating inverter amplifier core. The floating inverter amplifier core then supplies power according to the differential output signal CLK of the voltage-controlled oscillator. VCOp and CLK VCOn The instantaneous voltage at the sampling time is respectively applied to the first sampling capacitor C. sn Second sampling capacitor C sp Perform charging and discharging, thereby enabling the first sampling node V sn Second sampling node V sp A differential sampling voltage corresponding to the input phase error is generated. After the sampling phase ends, the sampling clock CLK is activated. samp The above sampling switch is turned off, causing the first sampling node V to... sn Second sampling node V sp The sampled voltage enters a hold state.

[0037] The resampling network includes: a resampling clock CLK resamp The first sampling switch, the second sampling switch, and the first sampling capacitor C are controlled. rsn Second sampling capacitor C rsp Wherein: the first resampling switch is connected to the first sampling node V sn With the first output node V outn Between, the second resampling switch is connected to the second sampling node V. sp With the second output node V outp Between; the first resampling capacitor C rsn One end is connected to the first output node V outn The other end is grounded, and the second resampling capacitor C rsp One end is connected to the second output node V outp The other end is grounded. During the resampling phase, the sampling clock CLK...samp After the control sampling switch is turned off, the resampling clock CLK resamp Controlling the first and second resampling switches to close, causing the first sampling node V to... sn Second sampling node V sp The stable sampling voltages on the first output node V are respectively transmitted to the first output node V. outn Second output node V outp And by the first resampling capacitor C rsn Second sampling capacitor C rsp Because the sampling and resampling phases use non-overlapping timing, the resampling process occurs after the sampling node voltage has stabilized. This reduces the transmission of transient charge and discharge disturbances from the sampling node to the input of the subsequent sub-sampling charge pump, thereby reducing output ripple and the resulting reference spurious emissions.

[0038] The core of the floating inverter amplifier includes: receiving the first differential output signal CLK from the voltage-controlled oscillator. VCOp The first floating inverter unit and the receiving voltage-controlled oscillator second differential output signal CLK VCOn The second floating inverter unit, wherein: the first floating inverter unit and the second floating inverter unit share the floating power supply charge established by the pre-charge capacitor C0, and during the sampling phase according to CLK VCOp and CLK VCOn The instantaneous voltages at sampling node V are respectively sn and V sp The circuit undergoes charging and discharging to generate a differential sampling voltage corresponding to the input phase error. Since the PMOS and NMOS transistors form a complementary input stage and have approximately symmetrical drive capabilities for pull-up and pull-down currents, the fluctuations in the sampled output common-mode voltage caused by changes in the input phase can be reduced.

[0039] like Figure 2 As shown, the first floating inverter unit includes a first PMOS transistor and a first NMOS transistor, wherein the gate terminals of both the first PMOS transistor and the first NMOS transistor receive the first differential output signal CLK from the voltage-controlled oscillator. VCOp The source of the first PMOS transistor is connected to the upper floating power supply node, the source of the first NMOS transistor is connected to the lower floating power supply node, and the drains of the first PMOS transistor and the first NMOS transistor are connected to form the first internal sampling output node. The first internal sampling output node is connected to the sampling clock CLK. samp Controlled sampling switch and sampling node V snConnected. The second floating inverter unit includes a second PMOS transistor and a second NMOS transistor, both of which receive the second differential output signal CLK from the voltage-controlled oscillator. VCOn The source of the second PMOS transistor is connected to the upper floating power supply node, and the source of the second NMOS transistor is connected to the lower floating power supply node. The drains of the second PMOS transistor and the second NMOS transistor are connected to form the second internal sampling output node, which is then connected to the sampling clock CLK. samp Controlled sampling switch and sampling node V sp Connected.

[0040] like Figure 3 As shown, the reset clock CLK rst Sampling clock CLK samp and resampling clock CLK resamp All are reference clock CLK ref Generated by a delay circuit and a pulse shaping circuit, and controlled according to a preset timing sequence for the reset, sampling, and resampling processes, specifically including: during the reset phase, CLK... rst The control reset switch is closed, and the two ends of the pre-charge capacitor C0 are connected to the power supply voltage and ground respectively. At the same time, the first sampling node V... sn Second sampling node V sp Reset to common-mode voltage V cm This allows the core of the floating inverter amplifier and the sampling capacitor to enter a preset initial state; during the sampling phase, CLK rst The control reset switch is off, CLK samp When the controlled sampling switch is closed, the pre-charge capacitor C0 is connected to the core of the floating inverter amplifier. The core of the floating inverter amplifier outputs the differential signal CLK from the voltage-controlled oscillator. VCOp and CLK VCOn The instantaneous voltage at the reference sampling time, relative to the first sampling capacitor C sn Second sampling capacitor C sp Differential charging and discharging are performed to achieve the desired result at the first sampling node V. sn Second sampling node V sp The differential sampling voltage corresponding to the input phase error is formed on the upper part; during the resampling stage, CLK samp The control sampling switch is off, CLK resamp The control resampling switch is closed, and the first sampling node V sn Second sampling node V sp The stable sampled voltages are respectively transmitted to the first output node V. outn Second output node V outp And by the first resampling capacitor C rsnSecond sampling capacitor C rsp Keep.

[0041] The sampling clock CLK samp and resampling clock CLK resamp By employing non-overlapping timing, the resampling process occurs after the sampling node voltage has stabilized, thereby avoiding the direct transfer of charge injection and charge / discharge transients during sampling to the subsequent sub-sampling charge pump. Simultaneously, during the sampling phase, there is no continuously conducting DC path between the floating inverter amplifier core and the fixed power supply and ground. The sampling process mainly relies on the charge stored in the pre-charge capacitor C0. Therefore, the front-end sampling network approximately operates as a passive charge sampling network, which helps reduce the static power consumption of the phase detector.

[0042] In this embodiment, the capacitance value of the pre-charge capacitor C0 is set to 500fF, and the first sampling capacitor C... sn Second sampling capacitor C sp It is implemented using a programmable switched capacitor array with a capacitance of 30fF. The first resampling capacitor is C. rsn Second sampling capacitor C rsp The capacitance value is 10fF. By adjusting the first sampling capacitor C... sn Second sampling capacitor C sp Floating inverter amplifier input stage transistor dimensions and sampling clock CLK samp The pulse width allows configuration of the equivalent phase detection gain of the subsampling phase detector based on the floating inverter amplifier. When the sampling phase error is small, the equivalent phase detection gain is directly proportional to the large-signal equivalent transconductance of the PMOS and NMOS transistors in the input stage of the floating inverter amplifier, the amplitude of the voltage-controlled oscillator output signal, the output angular frequency of the voltage-controlled oscillator, and the sampling pulse width, and inversely proportional to the sampling capacitance value, specifically: , where: K 亚采样鉴相器 G represents the equivalent phase detection gain of a subsampling phase detector based on a floating inverter amplifier. M For the large-signal equivalent transconductance of the PMOS and NMOS transistors in the input stage of the floating inverter amplifier, A VCO ω represents the amplitude of the voltage-controlled oscillator output signal. VCO T is the output angular frequency of the voltage-controlled oscillator. P Sampling clock CLK samp The pulse width, C S The value is the sampling capacitor. As can be seen from the above relationships, increasing the equivalent transconductance of the input stage, the output amplitude of the voltage-controlled oscillator, or the sampling pulse width is beneficial for improving the phase detection gain, while decreasing the sampling capacitor value can also improve the phase detection gain; however, an excessively small sampling capacitor will increase the sampling node ripple and noise sensitivity. Therefore, this embodiment uses a programmable sampling capacitor array and an adjustable sampling pulse width to strike a balance between phase detection gain, sampling ripple, reference spurious emissions, and power consumption.

[0043] like Figure 4 As shown, the sampling clock CLK samp A differential sinusoidal signal CLK with opposite phase used for the differential output of a voltage-controlled oscillator. VCOp and CLK VCOn Sampling is performed, and a differential sampling voltage is generated based on the charge difference between the two differential signals within the sampling window. The red shaded area in the figure represents the voltage relative to CLK. VCOp The corresponding sampled charge Q sp The blue shaded area indicates the relationship with CLK. VCOn The corresponding sampled charge Q sn .like Figure 4 As shown in (a), when the sampling clock CLK samp When the center position of CLK is aligned with the predetermined phase point of the differential output signal of the voltage-controlled oscillator, the sampling window contains CLK. VCOp and CLK VCOn The corresponding effective sampling areas are equal, i.e., Q sp =Q sn The first sampling node V sn With the second sampling node V sp The differential voltage between them satisfies V sn -V sp =0, after resampling, the output differential voltage approaches zero, the subsampling charge pump does not generate significant regulating current, the voltage-controlled oscillator control voltage remains stable, and the phase-locked loop is in a locked state. For example Figure 4 As shown in (b), when the sampling clock CLK samp When the center position of CLK shifts relative to the predetermined phase point of the differential output signal of the voltage-controlled oscillator, the sampling window... VCOp and CLK VCOn The corresponding effective sampling areas are no longer equal; in Figure 4 In the case shown in (b), Q sp Greater than Q sn This makes the first sampling node V sn With the second sampling node V sp V is generated between sn -V sp The differential sampled voltage is greater than 0. This differential sampled voltage is transmitted to the output node V via the resampling network. outn and V outp Subsequently, the sub-sampling charge pump converts the current into a charging / discharging current in the corresponding direction. A low-pass filter then adjusts the voltage-controlled oscillator (VCO) control voltage, causing the VCO output frequency and phase to change in the direction of reducing sampling timing deviation, until the sampling clock CLK is reached. samp The center position is realigned with or maintains the predetermined phase relationship with the differential output signal of the voltage-controlled oscillator.

[0044] After circuit simulation and system-level noise fitting verification, the low-power, low-jitter subsampling phase-locked loop based on the floating inverter amplifier of this invention was run under 40nm CMOS process conditions in an integer subsampling phase-locked loop operation mode with a reference frequency of 40MHz and an output frequency of approximately 5.6GHz. The simulation results are as follows: Figures 5-10 As shown, the phase-locked loop (PLL) can complete frequency acquisition and phase locking, and stably output a clock signal near the target frequency. According to the output spectrum simulation results, the output carrier frequency after locking is approximately 5.602 GHz, and the reference spurious signal is approximately −76.9 dBc. Based on the post-simulation noise results of each module and the MATLAB system-level noise fitting results, the output phase noise in the frequency offset range of 10 kHz to 100 MHz is integrated, and the output integral jitter is 75.14 fs. The frequency tuning range of the voltage-controlled oscillator is close to 600 MHz. The static power consumption of the subsampling main loop after locking is 1.26 mW, and the corresponding quality factor (FOM) is −261.48 dB.

[0045] like Figure 5 The figure shows the simulation results of the output differential voltage varying with the input phase error. This simulation uses the differential output signal of a voltage-controlled oscillator and the sampling clock CLK. samp The input phase error is used as the independent variable, and the differential voltage between the output nodes after resampling by the subsampling phase detector is used as the output quantity to characterize the ability of the subsampling phase detector to convert the phase error into a differential sampling voltage. Figure 5 It can be seen that near zero phase error, the differential voltage output of the subsampling phase detector changes approximately linearly with the input phase error, and its equivalent phase detection gain is 7.85mV / °, corresponding to approximately 0.45V / rad. This result indicates that the subsampling phase detector can provide a high and approximately linear voltage-type phase detection output within the small phase error range corresponding to normal PLL locking, thereby improving the equivalent front-end gain of the subsampling main loop and reducing the in-band phase noise contribution of the phase detector and subsequent subsampling charge pump noise referred to the PLL output.

[0046] like Figure 6 The figure shows the simulation results of the subsampling charge pump output current varying with the input phase error. This simulation uses the differential sampling voltage output from the subsampling phase detector based on a floating inverter amplifier as input and the current output from the subsampling charge pump to the low-pass filter as output, characterizing the subsampling charge pump's ability to convert voltage-type phase error signals into current-type error signals. Figure 6It can be seen that within the input phase error range of −40° to 40°, the output current of the subsampling charge pump changes approximately linearly with the input phase error. The subsampling charge pump is essentially a transconductance amplifier Gm, with a corresponding Gm value of 0.2mS and an equivalent current gain amplitude of 1.571μA / °. This result indicates that the subsequent subsampling charge pump can effectively perform transconductance conversion on the differential sampling voltage output by the subsampling phase detector, thereby outputting a charging and discharging current corresponding to the magnitude and direction of the input phase error. This current is further processed by a low-pass filter to form the control voltage of the voltage-controlled oscillator. Therefore, the cascaded structure of the subsampling phase detector and the subsampling charge pump can provide a high and approximately linear front-end loop gain within the small phase error range corresponding to normal phase-locked loop locking, which is beneficial for improving the phase tracking capability of the subsampling main loop and reducing in-band phase noise.

[0047] like Figure 7 The figure shows the key node waveforms of the subsampling phase detector based on a floating inverter amplifier under steady-state locking conditions, as well as the transient response simulation results when the input phase undergoes a step change. When the input phase is near the locked state, the sampling node V... sp and V sn Glitches and potential fluctuations exist during the reset and sampling processes, therefore the differential voltage V at the sampling node... sp -V sn It still contains some transient disturbances; after processing by the resampling network, the output node differential voltage V outp -V outn The glitches and jitter are significantly reduced, and the differential value is approximately zero near the locked state, indicating that the resampling branch can effectively isolate the influence of transient fluctuations at the sampling node on the final output. At approximately 540 ps, ​​the input phase undergoes a 40° step change, and the subsampling phase detector responds to the input phase error, with the sampling node differential voltage V... sp -V sn After a short period of disturbance, it tends to stabilize, but due to the deviation from the locked state, its transient fluctuations are relatively increased; in contrast, the resampled output differential voltage V outp -V outn The voltage eventually stabilized at approximately −300mV, indicating that the input phase error had been converted into a stable output differential voltage, and the output terminal was almost free of noticeable glitches and periodic fluctuations. Simultaneously, the output common-mode voltage (V...) outp +V outnThe voltage level () / 2 remained stable at approximately 530mV before and after the phase step, indicating that the subsampling phase detector can maintain a relatively stable output common-mode level under different input phase error conditions. This simulation result verifies the effectiveness of the three-stage operation process of the subsampling phase detector—reset, sampling, and resampling—and demonstrates that the resampling branch can suppress the transfer of transient disturbances from the sampling node to the subsequent subsampling charge pump, thereby reducing output bump and improving reference spurious performance.

[0048] like Figure 8 The figure shows the simulation results of the locking process of the low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to the present invention. The vertical axis of the figure represents the control voltage V of the voltage-controlled oscillator. ctrl The horizontal axis represents time. During the initial startup of the phase-locked loop (PLL), the auxiliary frequency-locked loop coarsely adjusts the output frequency of the voltage-controlled oscillator (VCO) to adjust the control voltage V. ctrl The frequency of the voltage-controlled oscillator (VCO) changes rapidly and is pulled into the locking range of the subsampling main loop. Once the output frequency approaches the target frequency, the adjustment effect of the auxiliary frequency-locking loop weakens, and the subsampling main loop continues to fine-tune the phase error through the subsampling phase detector, subsampling charge pump, and LPF. Figure 8 It can be seen that the control voltage Vctrl exhibits significant transient changes during the startup phase and oscillates during loop switching and phase correction. It gradually converges and stabilizes at approximately 0.42V around 3µs. This result demonstrates that the phase-locked loop (PLL) can achieve frequency acquisition and phase locking under the combined action of the auxiliary frequency-locking loop and the subsampling main loop, ultimately entering a stable locked state, providing a foundation for subsequent low-jitter and low-reference-spurious output.

[0049] like Figure 9 The figure shows the simulation results of the output spectrum after locking the low-power, low-jitter subsampling phase-locked loop based on the floating inverter amplifier according to the present invention. Figure 9 It can be seen that the output carrier frequency of the phase-locked loop in the locked state is approximately 5.602 GHz, and the carrier amplitude is approximately -13.2 dB. A reference spurious component exists near the carrier at a position corresponding to the reference frequency offset, with an amplitude of approximately -90.1 dB and a reference spurious component relative to the carrier of approximately -76.9 dB. These results demonstrate that the subsampling phase detector based on a floating inverter amplifier reduces the periodic modulation of the voltage-controlled oscillator load during the sampling stage through a charge sampling structure, and suppresses the transmission of transient disturbances from the sampling node to subsequent stages through a resampling branch. This enables the achievement of a lower reference spurious level in an integer-type subsampling phase-locked loop, thereby improving the spectral purity of the output clock signal.

[0050] like Figure 10The figure shows the MATLAB fitting results of the output phase noise and noise contribution of the low-power, low-jitter subsampling phase-locked loop (PLL) based on a floating inverter amplifier, according to this invention. This figure establishes a system-level noise model based on the post-simulation noise results of each module, and performs fitting analysis on the contributions of the main noise sources, such as the reference signal, the subsampling phase detector and subsampling charge pump based on the floating inverter amplifier, the low-pass filter, and the voltage-controlled oscillator, to the PLL output. Figure 10 It can be seen that within the loop bandwidth, the output phase noise is mainly affected by the reference signal and the noise of the subsampling phase detector and subsampling charge pump; outside the loop bandwidth, the phase noise of the voltage-controlled oscillator gradually becomes the main contributor. The main loop bandwidth of the phase-locked loop in the figure is approximately 4MHz. Integrating the output phase noise within the frequency offset range of 10kHz to 100MHz yields an output integral jitter of approximately 75.14fs. In terms of noise contribution percentage, the voltage-controlled oscillator accounts for approximately 30%, the reference signal for approximately 46%, the subsampling phase detector and subsampling charge pump based on the floating inverter amplifier for approximately 20%, and the low-pass filter for approximately 4%. These results demonstrate that this invention, by increasing the equivalent phase detector gain at the front end of the subsampling main loop, can effectively suppress the contribution of the phase detector and subsequent subsampling charge pump noise to the output in-band phase noise, while simultaneously achieving low integral jitter through a low-noise main loop design.

[0051] In summary, the subsampling phase-locked loop of this invention effectively reduces reference spurious signals, achieves high phase detection gain and extremely low in-band noise, while also ensuring low power consumption and good system feasibility, ultimately meeting the design requirements of high-performance phase-locked loops. Compared with existing technologies, this invention does not merely suppress reference spurious signals in subsampling phase-locked loops through isolation buffers, dummy structures, or traditional sample-and-hold circuits. Instead, it introduces a subsampling phase detector based on a floating inverter amplifier at the front end of the subsampling main loop. Through the coordinated operation of the floating inverter amplifier core, charge sampling network, reset network, and resampling network, the phase error is converted into a stable differential sampling voltage. Compared with subsampling phase-locked loops using high-frequency isolation buffers, this invention does not require a continuously operating high-frequency isolation buffer at the output of the voltage-controlled oscillator, thus reducing the additional power consumption, area, and noise overhead introduced by the buffer.

[0052] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier, characterized in that, include: The subsampling phase detector, subsampling charge pump, low-pass filter, and voltage-controlled oscillator (VCO) are sequentially connected to form the subsampling main loop. The auxiliary frequency-locked loop consists of a frequency detector, dead-time circuit, charge pump, and frequency divider. Specifically: the subsampling phase detector performs subsampling processing on the VCO output signal based on the phase relationship between the reference clock signal and the VCO output signal, obtaining a differential output voltage corresponding to the phase error; the subsampling charge pump converts the differential output voltage into a subsampling charge pump output current corresponding to the phase error, which, after being filtered by the low-pass filter, generates an output clock signal through the VCO and feeds it back to the subsampling phase detector; the frequency divider performs N-fold frequency division processing on the clock signal to obtain a frequency division feedback signal; the frequency detector outputs pull-up and pull-down control signals based on the frequency difference and phase difference between the reference clock signal and the frequency division feedback signal; the dead-time circuit generates an auxiliary regulating current through the charge pump when the loop frequency approaches the locking range based on the pull-up and pull-down control signals, and assists in regulating the VCO output frequency to enter the locking range of the subsampling main loop when the phase-locked loop starts or loses lock. The subsampling phase detector includes: a charge sampling network and a reset network, a floating inverter amplifier core, and a resampling network connected thereto.

2. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to claim 1, characterized in that, The charge sampling network converts the phase error between the differential output signal of the voltage-controlled oscillator and the reference sampling time into a differential sampling voltage during the sampling phase; the reset network uses the reset clock CLK. rst During the reset phase, the pre-charge capacitor C0 and the sampling node V of the charge sampling network are respectively... sp and V sn Initialize; the resampling network is initialized according to the resampling clock CLK. resamp After the voltage at the sampling node stabilizes, the sampling results from the charge sampling network are transmitted to the output node V. outp and V outn The floating inverter amplifier core adopts a differential structure and reduces the fluctuation of the output common-mode voltage caused by the change of input phase with the charge sampling network.

3. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to claim 1, characterized in that, The reset network includes: a pre-charge capacitor C0, and a reset clock CLK. rst The control includes a pre-charge reset switch and a sampling node reset switch, wherein: the pre-charge capacitor C0 is connected between the upper pre-charge node and the lower pre-charge node; the pre-charge reset switch is connected between the power supply voltage and the upper pre-charge node of the pre-charge capacitor C0, and between ground and the lower pre-charge node of the pre-charge capacitor C0; the sampling node reset switch is connected to the common-mode voltage V. cm With the first sampling node V sn Between, common-mode voltage V cm With the second sampling node V sp During the reset phase, the reset clock CLK is used. rst The pre-charge reset switch and the sampling node reset switch are closed to reset the upper pre-charge node of the pre-charge capacitor C0 to the power supply voltage and the lower pre-charge node to ground, thereby storing the initial charge required for the sampling phase on the pre-charge capacitor C0; simultaneously, the first sampling node V... sn Second sampling node V sp Reset to common-mode voltage V cm This ensures that the subsequent sampling phase has a defined initial voltage state. After the reset phase ends, the reset clock CLK is activated. rst When the precharge reset switch and the sampling node reset switch are disconnected, the subsampling phase detector based on the floating inverter amplifier enters the sampling preparation state.

4. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to claim 1, characterized in that, The charge sampling network includes: a sampling clock CLK samp Controlled power supply connection switch, first sampling switch, second sampling switch, first sampling capacitor C sn Second sampling capacitor C sp Wherein: the power supply connection switch is connected between the upper pre-charge node of the pre-charge capacitor C0 and the upper floating power supply node of the floating inverter amplifier core, and between the lower pre-charge node of the pre-charge capacitor C0 and the lower floating power supply node of the floating inverter amplifier core; the first sampling switch is connected between the internal sampling output node of the first floating inverter unit and the first sampling node V. sn Between, the second sampling switch is connected to the internal sampling output node of the second floating inverter unit and the second sampling node V. sp Between; the first sampling capacitor C sn One end is connected to the first sampling node V sn The other end is grounded, and the second sampling capacitor C sp One end is connected to the second sampling node V sp The other end is grounded, and during the sampling phase, the sampling clock CLK is used. samp The power supply connection switch, the first sampling switch, and the second sampling switch are closed to allow the charge stored in the pre-charge capacitor C0 to provide instantaneous power to the floating inverter amplifier core. The floating inverter amplifier core then supplies power according to the differential output signal CLK of the voltage-controlled oscillator. VCOp and CLK VCOn The instantaneous voltage at the sampling time is respectively applied to the first sampling capacitor C. sn Second sampling capacitor C sp Perform charging and discharging, thereby enabling the first sampling node V sn Second sampling node V sp A differential sampling voltage corresponding to the input phase error is generated. After the sampling phase ends, the sampling clock CLK is activated. samp The above sampling switch is turned off, causing the first sampling node V to... sn Second sampling node V sp The sampled voltage enters a hold state.

5. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to claim 1, characterized in that, The resampling network includes: a resampling clock CLK resamp The first sampling switch, the second sampling switch, and the first sampling capacitor C are controlled. rsn Second sampling capacitor C rsp Wherein: the first resampling switch is connected to the first sampling node V sn With the first output node V outn Between, the second resampling switch is connected to the second sampling node V. sp With the second output node V outp Between; the first resampling capacitor C rsn One end is connected to the first output node V outn The other end is grounded, and the second resampling capacitor C rsp One end is connected to the second output node V outp The other end is grounded, and during the resampling phase, the sampling clock CLK... samp After the control sampling switch is turned off, the resampling clock CLK resamp Controlling the first and second resampling switches to close, causing the first sampling node V to... sn Second sampling node V sp The stable sampling voltages on the first output node V are respectively transmitted to the first output node V. outn Second output node V outp And by the first resampling capacitor C rsn Second sampling capacitor C rsp Because the sampling and resampling phases use non-overlapping timing, the resampling process occurs after the sampling node voltage stabilizes. Therefore, it can reduce the transmission of transient charging and discharging disturbances at the sampling node to the input of the subsequent sub-sampling charge pump, thereby reducing output ripple and the reference spurious caused by it.

6. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to claim 1, characterized in that, The core of the floating inverter amplifier includes: receiving the first differential output signal CLK from the voltage-controlled oscillator. VCOp The first floating inverter unit and the receiving voltage-controlled oscillator second differential output signal CLK VCOn The second floating inverter unit, wherein: the first floating inverter unit and the second floating inverter unit share the floating power supply charge established by the pre-charge capacitor C0, and during the sampling phase according to CLK VCOp and CLK VCOn The instantaneous voltages at sampling node V are respectively sn and V sp The charging and discharging process generates a differential sampling voltage corresponding to the input phase error. Since the PMOS transistor and NMOS transistor form a complementary input stage and have approximately symmetrical driving capabilities for pull-up and pull-down currents, the fluctuation of the sampling output common-mode voltage caused by the input phase change can be reduced.

7. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to claim 6, characterized in that, The first floating inverter unit includes a first PMOS transistor and a first NMOS transistor, wherein the gate terminals of both the first PMOS transistor and the first NMOS transistor receive the first differential output signal CLK from the voltage-controlled oscillator. VCOp The source of the first PMOS transistor is connected to the upper floating power supply node, the source of the first NMOS transistor is connected to the lower floating power supply node, and the drains of the first PMOS transistor and the first NMOS transistor are connected to form the first internal sampling output node. The first internal sampling output node is connected to the sampling clock CLK. samp Controlled sampling switch and sampling node V sn The second floating inverter unit is connected in series, comprising a second PMOS transistor and a second NMOS transistor. The gate terminals of both the second PMOS transistor and the second NMOS transistor receive the second differential output signal CLK from the voltage-controlled oscillator. VCOn The source of the second PMOS transistor is connected to the upper floating power supply node, and the source of the second NMOS transistor is connected to the lower floating power supply node. The drains of the second PMOS transistor and the second NMOS transistor are connected to form the second internal sampling output node, which is then connected to the sampling clock CLK. samp Controlled sampling switch and sampling node V sp Connected.

8. The low-power, low-jitter subsampling phase-locked loop based on a floating inverter amplifier according to any one of claims 1-7, characterized in that, The reset clock CLK rst Sampling clock CLK samp and resampling clock CLK resamp All are reference clock CLK ref Generated by a delay circuit and a pulse shaping circuit, and controlled according to a preset timing sequence for the reset, sampling, and resampling processes, specifically including: during the reset phase, CLK... rst The control reset switch is closed, and the two ends of the pre-charge capacitor C0 are connected to the power supply voltage and ground respectively. At the same time, the first sampling node V... sn Second sampling node V sp Reset to common-mode voltage V cm This allows the core of the floating inverter amplifier and the sampling capacitor to enter a preset initial state; during the sampling phase, CLK rst The control reset switch is open, CLK samp When the controlled sampling switch is closed, the pre-charge capacitor C0 is connected to the core of the floating inverter amplifier. The core of the floating inverter amplifier outputs the differential signal CLK from the voltage-controlled oscillator. VCOp and CLK VCOn The instantaneous voltage at the reference sampling time, relative to the first sampling capacitor C sn Second sampling capacitor C sp Differential charging and discharging are performed to achieve the desired result at the first sampling node V. sn Second sampling node V sp The differential sampling voltage corresponding to the input phase error is formed on the upper part; during the resampling stage, CLK samp The control sampling switch is off, CLK resamp The control resampling switch is closed, and the first sampling node V sn Second sampling node V sp The stable sampled voltages are respectively transmitted to the first output node V. outn Second output node V outp And by the first resampling capacitor C rsn Second sampling capacitor C rsp Keep.

9. A phase-locked loop method based on the low-power, low-jitter subsampling phase-locked loop of any one of claims 1-8, characterized in that, include: Step 1: Use a frequency-locking loop to assist in capturing the output frequency of the voltage-controlled oscillator (VCO), ensuring the VCO output frequency enters the locking range of the subsampling main loop. Specifically, this includes: 1.1 The frequency divider divides the output signal of the voltage-controlled oscillator to obtain a feedback signal for comparison with the reference signal; the frequency and phase detector receives the reference signal and the feedback signal, and generates a corresponding frequency error control signal based on the frequency difference and phase difference between the two. 1.2 The dead-zone circuit receives the frequency error control signal output by the frequency and phase detector, and suppresses the frequency-locked loop from continuing to output the adjustment signal when the phase error between the reference signal and the feedback signal is within the preset dead-zone range, so that the frequency-locked loop stops or weakens its effect after the output frequency of the voltage-controlled oscillator approaches the target frequency. 1.3 The charge pump adjusts the charge and discharge of the low-pass filter or the control node of the voltage-controlled oscillator according to the control signal output by the dead-time circuit, so that the output frequency of the voltage-controlled oscillator gradually approaches the target frequency; when the output frequency enters the frequency range that the subsampling main loop can lock, the phase tracking is mainly completed by the subsampling main loop. Step 2: The output signal of the voltage-controlled oscillator is phase-sampled using a subsampling phase detector based on a floating inverter amplifier to obtain the differential sampling voltage corresponding to the phase error. Specifically, this includes: 2.1 During the reset phase, the reset switch controlled by the reset clock closes, resetting the two ends of the pre-charge capacitor to the power supply voltage and ground respectively, and resetting the sampling node of the sampling capacitor to the common-mode voltage. 2.2 During the sampling phase, the sampling switch controlled by the sampling clock is closed, and the differential output signal of the voltage-controlled oscillator is applied to the sampling capacitor through the input stage of the floating inverter amplifier. When there is a phase error between the reference sampling time and the predetermined phase point of the voltage-controlled oscillator output signal, the input stage of the floating inverter amplifier generates a differential charging and discharging current corresponding to the phase error and forms a differential sampling voltage on the sampling capacitor. 2.3 During the resampling stage, the resampling switch controlled by the resampling clock closes, resamples the stable sampling voltage on the sampling capacitor, and outputs the resampled differential voltage to the subsequent subsampling charge pump; wherein: the sampling clock and the resampling clock adopt a non-overlapping timing sequence to reduce the transmission of transient disturbances at the sampling node to the subsequent stage; Step 3: Perform error conversion and filtering on the differential sampling voltage using a subsampling charge pump and a low-pass filter, specifically including: 3.1 The subsampling charge pump receives the differential sampling voltage output from the subsampling phase detector based on the floating inverter amplifier, and converts the differential sampling voltage into a charging and discharging current corresponding to the phase error; 3.2 The low-pass filter receives the charging and discharging current, filters and smooths the charging and discharging current, and generates a control voltage for controlling the voltage-controlled oscillator; Step 4: Adjust the output frequency and phase of the voltage-controlled oscillator according to the control voltage to lock the phase-locked loop. This specifically includes: 4.1 When the subsampling phase detector detects a phase error between the reference sampling time and the predetermined phase point of the voltage-controlled oscillator output signal, the subsampling charge pump and low-pass filter change the control voltage of the voltage-controlled oscillator, so that the output frequency and phase of the voltage-controlled oscillator are adjusted in the direction of reducing the phase error. 4.2 When the reference sampling time is aligned with or maintains a predetermined phase relationship with the output signal of the voltage-controlled oscillator, the differential sampling voltage output by the subsampling phase detector approaches zero or remains stable. The control voltage of the voltage-controlled oscillator remains stable, the phase-locked loop enters the locked state and outputs a low-jitter clock signal.

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