Clock phase alignment circuit, method, fpga chip and laser communication ranging system

Abstract

This application provides a clock phase alignment circuit, method, FPGA chip, and laser communication ranging system, relating to the field of satellite communication technology. The clock phase alignment circuit includes a first D flip-flop, a second D flip-flop, a counter module, and a phase control module. The first D flip-flop is used to sample a first clock signal based on a second clock signal. The second D flip-flop is used to synchronize the initial sampling results. The counter module is used to statistically analyze the target sampling results to obtain a counting result. The phase control module is used to generate a phase adjustment control signal based on the counting result and control the phase interpolation module to perform phase adjustment, so that the phase relationship between the first clock signal and the second clock signal tends to the target phase relationship. This application aims to improve the problem of poor system transmit / receive delay consistency caused by the easy change in processing delay during reinitialization of the transmission link in existing technologies.

Description

Technical Field

[0001] This application relates to the field of satellite communication technology, and in particular to a clock phase alignment circuit, method, FPGA chip, and laser communication ranging system. Background Technology

[0002] With the continuous development of high-speed serial communication technology and high-precision ranging technology, laser communication ranging systems are increasingly being widely used in high-speed data transmission, satellite communication, space ranging, time synchronization, and precision measurement. Compared with traditional wireless communication methods, laser communication has advantages such as high bandwidth, strong directionality, and strong resistance to electromagnetic interference, thus possessing high application value in high-precision ranging and high-precision time synchronization scenarios. A laser communication ranging system typically includes a transmitting link and a receiving link. The transmitting link usually includes multiple processing units such as a buffer module, a parallel-to-serial conversion module, and a high-speed serial transmitting module. These different processing units typically operate in different clock domains, therefore multiple clock signals exist simultaneously within the transmitting link.

[0003] However, during repeated power-on, reset, or reinitialization processes, the initialization states of various modules within the transmission link may differ. Consequently, the edge phase relationship between the user-side clock signal and the transmission output clock signal in the transmission link may change, leading to fluctuations in processing delays. Especially in high-precision ranging or high-precision time synchronization scenarios, changes in processing delays in the transmission link can further cause ranging zero-point drift or time synchronization errors, thus affecting the stability and accuracy of the system's measurement results. Summary of the Invention

[0004] The embodiments disclosed in this application provide a clock phase alignment circuit, method, FPGA chip, and laser communication ranging system, which can improve the problem in the prior art where the processing delay of the transmission link is prone to change during repeated power-on, reset, or reinitialization, resulting in poor consistency of system transmission and reception delays.

[0005] The embodiments of this application adopt the following technical solutions: In a first aspect, a clock phase alignment circuit is provided, comprising: a first D flip-flop, a second D flip-flop, a counter module, and a phase control module. The data input terminal of the first D flip-flop is used to receive a first clock signal, and the clock input terminal of the first D flip-flop is used to receive a second clock signal. The data input terminal of the second D flip-flop is coupled to the output terminal of the first D flip-flop, and the clock input terminal of the second D flip-flop is used to receive the second clock signal. The input terminal of the counter module is coupled to the output terminal of the second D flip-flop, and the input terminal of the phase control module is coupled to the output terminal of the counter module. The output terminal of the phase control module is coupled to a phase interpolation module. The first D flip-flop is used to sample the first clock signal based on the second clock signal. The second D flip-flop is used to perform synchronization processing on the initial sampling result to obtain a target sampling result. The counter module is used to count the number of occurrences of a target level state in the target sampling result within a preset statistical period to obtain a corresponding counting result. The phase control module is used to generate a phase adjustment control signal based on the counting result, and control the phase interpolation module to adjust the phase of the first clock signal and / or the second clock signal based on the phase adjustment control signal, so that the phase relationship between the second clock signal and the first clock signal tends to the target phase relationship.

[0006] In one feasible implementation of the first aspect, the first clock signal is the transmit output clock signal in the transmit link, and the second clock signal is the user-side clock signal in the transmit link; wherein, the user-side clock signal is used to drive the front-end logic circuit of the transmit link, the transmit output clock signal is used to characterize the transmit clock state inside the transmit link, and the clock phase alignment circuit determines the processing delay change in the transmit link by detecting the phase relationship between the user-side clock signal and the transmit output clock signal.

[0007] In one feasible implementation of the first aspect, the phase control module is specifically used to: after the transmission link initialization is completed, control the counter module to release the reset state and start counting statistics on the target sampling results, obtain the counting result output by the counter module, and determine the edge phase offset state between the first clock signal and the second clock signal based on the counting result. According to the edge phase offset state, control the corresponding phase control word to increase, decrease or remain unchanged, so that the phase interpolation module performs phase compensation on the transmission clock signal and / or transmission data signal based on the adjusted phase control word, thereby adjusting the processing delay in the transmission link.

[0008] In one feasible implementation of the first aspect, the counter module is specifically used to: continuously sample and count the target level state output by the second D flip-flop within a preset statistical period, and accumulate the number of outputs corresponding to the target level state to obtain the corresponding counting result. The counting result is used to characterize the edge phase relationship between the first clock signal and the second clock signal. When the edge phase difference between the first clock signal and the second clock signal gradually approaches the target phase relationship, the probability distribution of different level states output by the second D flip-flop gradually approaches the preset ratio, so that the counting result gradually approaches the target count value. The target count value is used to characterize the transmission link being in the target processing delay state.

[0009] In one feasible implementation of the first aspect, the phase control module is specifically configured to: when the counting result is greater than a first threshold, determine that the edge phase relationship between the first clock signal and the second clock signal deviates from the target phase relationship in a first direction, and control the corresponding phase control word to increase, so that the phase interpolation module performs phase adjustment in the first direction; when the counting result is less than a second threshold, determine that the edge phase relationship between the first clock signal and the second clock signal deviates from the target phase relationship in a second direction, and control the corresponding phase control word to decrease, so that the phase interpolation module performs phase adjustment in the second direction; when the counting result is between the first threshold and the second threshold, control the current phase control word to remain unchanged, so as to maintain the processing delay state corresponding to the current transmission link; wherein the first direction and the second direction are opposite.

[0010] In one feasible implementation of the first aspect, the first threshold and the second threshold are determined based on a preset statistical period and a preset protection interval; wherein, the first threshold corresponds to the sum of the target count value and the upper limit of the protection interval, and the second threshold corresponds to the difference between the target count value and the lower limit of the protection interval. When the count result is between the first threshold and the second threshold, it indicates that the edge phase relationship between the second clock signal and the first clock signal satisfies the target phase alignment condition, so that the transmission link maintains the target processing delay state.

[0011] In one feasible implementation of the first aspect, the phase control module is further configured to: accumulate the state count value when the counting result is within the target counting interval; maintain the current phase control word unchanged before the state count value reaches a preset state threshold, and continue to perform edge phase relationship detection between the first clock signal and the second clock signal; and output a phase alignment completion signal when the state count value reaches the preset state threshold to indicate that the processing delay in the current transmission link has entered a stable state and terminate the current phase adjustment process.

[0012] In a second aspect, a clock phase alignment method is provided, applied to the clock phase alignment circuit of any one of the first aspects. The method includes: sampling a second clock signal based on a first clock signal to obtain an initial sampling result; performing synchronization processing on the initial sampling result to obtain a target sampling result; counting the number of occurrences of a target level state in the target sampling result within a preset statistical period to obtain a counting result; generating a phase adjustment control signal based on the counting result; and controlling a phase interpolation module to adjust the phase of the first clock signal and / or the second clock signal based on the phase adjustment control signal.

[0013] Thirdly, an FPGA chip is provided, the FPGA chip including the clock phase alignment circuit provided in any of the first aspects.

[0014] Fourthly, embodiments of this application provide a laser communication ranging system, which includes the FPGA chip provided in the third aspect.

[0015] The clock phase alignment circuit provided in this application detects the edge phase relationship between the transmit output clock signal and the user-side clock signal in the transmit link, and controls the phase interpolation module to perform phase compensation on the transmit clock signal and / or transmit data signal based on the detection result. This makes the processing delay in the transmit link tend to be fixed, thereby reducing the processing delay fluctuation during repeated power-on, reset, or re-initialization processes and improving the consistency of system transmit and receive delays. Furthermore, this application embodiment performs statistical analysis on the target sampling results and performs closed-loop phase adjustment based on the statistical results, making the processing delay in the transmit link gradually tend to the target processing delay state. This improves the ranging zero-point drift or time synchronization error caused by the change in the transmission link processing delay, and enhances the measurement stability and accuracy of laser communication ranging systems, high-precision ranging systems, and high-speed serial transmission systems. Attached Figure Description

[0016] Figure 1 A schematic diagram of the architecture of a laser communication ranging system provided in this application embodiment; Figure 2 A schematic diagram of a transmission link clock phase alignment architecture provided in this application embodiment; Figure 3 A circuit diagram of a clock phase alignment circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of a phase adjustment process provided in an embodiment of this application; Figure 5 A flowchart illustrating the steps of a clock phase alignment method provided in this application embodiment. Detailed Implementation

[0017] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the figures. Obviously, the embodiments described in the specification are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0018] Hereinafter, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units refer to two or more processing units.

[0019] In this application, the term "module" typically refers to a logically divided functional structure. A "module" can be implemented purely in hardware, or a combination of hardware and software. In this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, or both A and B existing simultaneously.

[0020] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being better or more advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0021] With the continuous development of space information technology, precision measurement and control technology, and high-speed digital communication technology, laser communication ranging systems based on optical signal transmission have gradually become an important means of realizing high-precision ranging, space communication, satellite interconnection, airborne measurement, fiber optic sensing, and high-precision time synchronization. Compared with traditional wireless radio frequency communication methods, laser communication has advantages such as high bandwidth, strong directionality, strong resistance to electromagnetic interference, and high transmission accuracy. Therefore, it has been widely used in long-distance high-precision measurement and high-speed data transmission scenarios. Especially in high-precision ranging scenarios, the system usually needs to calculate the distance based on the time difference between the transmitted and received signals. Therefore, the stability of the internal delay of the system directly affects the final ranging accuracy. Under nanosecond or even picosecond level accuracy requirements, even microsecond delay fluctuations in the communication link can cause significant measurement errors. Therefore, how to reduce the uncertainty of the internal link delay has become a key technical problem in current high-precision laser communication ranging systems.

[0022] From a system architecture perspective, laser communication ranging systems typically include an optical transmission link, an optical reception link, and a high-speed digital processing link. (See also...) Figure 1 A laser communication ranging system may include functional modules such as an optical switch, an optical mixer and photoelectric conversion module, a local oscillator light source, an optical modulation module, a high-speed analog-to-digital converter (ADC), a high-speed serial transceiver (GT) module, an analog-to-digital converter (ADC) interface module, and a field-programmable gate array (FPGA). The optical mixer and photoelectric conversion module performs coherent mixing and photoelectric conversion on the received optical signal to output the corresponding electrical signal. The high-speed ADC performs high-speed sampling of the electrical signal based on a sampling clock to output the corresponding digital sampled data. The FPGA performs high-speed data reception, demodulation, and ranging signal processing on the digital sampled data. Simultaneously, the high-speed serial transceiver module in the FPGA can also perform high-speed serial transmission of baseband data and control the laser signal output through drivers and the optical modulation module.

[0023] In the above process, multiple clock domains typically exist within the system. For example, high-speed analog-to-digital converters usually operate in the sampling clock domain, the ADC interface module in an FPGA typically operates in the receiver-side recovery clock domain, while the GT module typically operates in both the transmitter-side user clock domain and the transmitter output clock domain. To ensure stable transmission of high-speed data, the system typically relies on multiple clock signals, such as a reference clock, sampling clock, user-side clock, and transmitter output clock, to achieve synchronization control between different modules.

[0024] However, during repeated power-on, reset, or reinitialization processes, the initialization states of the high-speed analog-to-digital converter, GT module, and high-speed transmission link within the FPGA may differ. This can lead to changes in the edge phase relationship between different clock domains, causing fluctuations in processing delays within the transmission link. Particularly in the GT transmission link, the transmission path typically includes multiple processing units such as a buffer module, clock recovery module, parallel-to-serial conversion module, and phase adjustment module. Therefore, the initialization order, clock locking state, and edge phase relationship of each module may exhibit randomness in different power-on cycles.

[0025] In the GT (Gateway Transmitter) transmission link, baseband data, after entering the transmission link from the user logic side, typically undergoes multiple processing stages, including FIFO buffering, clock domain switching, parallel-to-serial conversion, and serial transmission. Therefore, the edge phase relationship between the user-side clock and the transmit output clock directly affects the overall processing delay from user logic to serial output. When the edge phase relationship between the user-side clock and the transmit output clock differs in different power-on cycles, the overall processing delay in the transmission link will also change. For ordinary data communication scenarios, this type of processing delay fluctuation usually does not significantly affect system functionality. However, for high-precision ranging, high-precision time synchronization, and high-precision phase measurement scenarios, processing delay drift in the transmission link may further cause ranging zero-point drift or time synchronization errors, thus affecting the stability and accuracy of the final measurement results.

[0026] To ensure the accuracy of system measurement results, one feasible implementation in related technologies requires performing a zero-value calibration operation before each system power-on. Zero-value calibration refers to measuring the system's current transmit / receive delay using a preset reference path, standard distance, or internal loopback link before the system formally performs measurements, and using the measured initial delay as a compensation benchmark for subsequent measurements.

[0027] However, re-performing the calibration process after each system startup not only increases system startup time but also raises system control complexity. In applications requiring rapid startup, continuous operation, or unattended operation, frequent zero-value calibration can also negatively impact overall system efficiency. Furthermore, the zero-value calibration process typically relies on additional reference links or standard targets, leading to increased system hardware resource consumption.

[0028] Furthermore, in high-speed laser communication ranging systems, since the transmitting and receiving links typically contain multiple clock domains and multi-level data processing units, the processing delay within the links may change during repeated power-on, reset, or reinitialization. Especially in high-speed serial transmitting links, the edge phase relationship between different clock signals may drift with changes in the system initialization state, leading to uncertainty in the processing delay within the transmitting link.

[0029] In high-precision ranging or high-precision time synchronization scenarios, the aforementioned processing delay variations can further cause zero-point drift in the system measurement, affecting the consistency and accuracy of the measurement results.

[0030] To improve the above problems, this application provides a clock phase alignment circuit. By detecting the edge phase relationship between the first clock signal and the second clock signal in the transmission link, and controlling the phase interpolation module to adjust the phase of the transmission clock signal and / or the transmission data signal based on the edge phase relationship, the processing delay in the transmission link tends to be fixed, thereby reducing the processing delay fluctuation of the system during repeated power-on and improving the consistency of the system's transmission and reception delay.

[0031] First, the clock phase alignment architecture of the transmission link involved in the embodiments of this application will be described.

[0032] See Figure 2 This application provides a schematic diagram of a transmission link clock phase alignment architecture, which can be applied to high-speed serial transmission scenarios, such as laser communication ranging systems, high-precision ranging systems, high-speed data transmission systems, and high-speed serial interface systems.

[0033] like Figure 2As shown, the overall transmission link includes a phase-locked loop (PLL) module, a phase interpolation module, a frequency divider, a multi-modal-to-digital (MMD) divider module, a FIFO module, a parallel-to-serial conversion module, and a clock phase alignment circuit. A reference clock is input to the PLL module, which generates the corresponding transmission link operating clock based on the reference clock and outputs it to the phase interpolation module. The phase interpolation module adjusts the phase of the transmission clock signal in the transmission link to change the processing delay state. Parallel transmission data is input to the FIFO module, which buffers the data to be transmitted and outputs the buffered data to the parallel-to-serial conversion module. The parallel-to-serial conversion module converts the parallel transmission data into serial transmission data to output the corresponding serial transmission data. The operating clock in the transmission link can also be processed by a frequency divider and a MMD divider module to generate the corresponding user-side clock signal; simultaneously, the parallel-to-serial conversion module outputs the corresponding transmission output clock signal. The user-side clock signal drives the front-end logic of the transmission link, and the transmission output clock signal characterizes the transmission clock state in the transmission link. During repeated power-on or re-initialization of the transmission link, the edge phase relationship between the user-side clock signal and the transmission output clock signal may change due to the existence of multiple clock domains and multi-level processing units within the transmission link, resulting in fluctuations in processing delay. Therefore, the clock phase alignment circuit provided in this embodiment is connected to both the user-side clock signal and the transmission output clock signal to detect the edge phase relationship between them and output the corresponding feedback control signal to the phase interpolation module based on the detection result. The phase interpolation module adjusts the phase of the transmission clock signal and / or transmission data signal based on the feedback control signal to compensate for the processing delay in the transmission link, making the processing delay in the transmission link tend to be fixed.

[0034] It is understood that the embodiments of this application do not directly measure the absolute processing delay in the transmission link, but indirectly characterize the processing delay state in the transmission link by detecting the edge phase relationship between the user-side clock signal and the transmission output clock signal, and perform closed-loop phase adjustment based on the edge phase relationship, thereby reducing the processing delay fluctuation of the transmission link during repeated power-on processes and improving the consistency of system transmit and receive delays.

[0035] The following provides an overall description of the topology and function of the clock phase alignment circuit. (See attached document.) Figure 3 The clock phase alignment circuit 100 may include: a first D flip-flop 110, a second D flip-flop 120, a counter module 130, and a phase control module 140.

[0036] The data input terminal of the first D flip-flop 110 is used to receive a first clock signal, and the clock input terminal of the first D flip-flop 110 is used to receive a second clock signal; the data input terminal of the second D flip-flop 120 is coupled to the output terminal of the first D flip-flop 110, and the clock input terminal of the second D flip-flop 120 is used to receive the second clock signal; the input terminal of the counter module 130 is coupled to the output terminal of the second D flip-flop 120; the input terminal of the phase control module 140 is coupled to the output terminal of the counter module 130, and the output terminal of the phase control module 140 is used to connect to the phase interpolation module.

[0037] In one feasible implementation, the first clock signal can be the transmit output clock signal TXOUTCLK, and the second clock signal can be the user-side clock signal TXUSRCLK. The transmit output clock signal characterizes the transmit clock state in the transmit link, and the user-side clock signal drives the front-end logic of the transmit link. Because the transmit link may experience internal clock phase drift during repeated power-on or re-initialization, the edge phase relationship between the transmit output clock signal TXOUTCLK and the user-side clock signal TXUSRCLK may change, leading to fluctuations in processing delay in the transmit link.

[0038] Based on this, the embodiments of this application use a clock phase alignment circuit 100 to detect the edge phase relationship between the transmit output clock signal TXOUTCLK and the user-side clock signal TXUSRCLK, and control the phase interpolation module to perform phase compensation based on the detection result, so that the processing delay in the transmit link tends to be fixed.

[0039] Specifically, the first D flip-flop 110 is used to sample the first clock signal based on the second clock signal to obtain the corresponding initial sampling result. Since there is an edge phase difference between the first clock signal and the second clock signal, the first D flip-flop 110 may output different logic states under different phase relationships.

[0040] The second D flip-flop 120 is used to synchronize the initial sampling results to obtain the target sampling results. It is understood that by adding the second D flip-flop, the impact of metastability on subsequent statistical processes can be reduced, thereby improving the stability of the edge phase relationship detection results.

[0041] The counter module 130 is used to count the number of times the target level state appears in the target sampling results within a preset statistical period, and obtain the corresponding counting result. The counting result is used to characterize the edge phase relationship between the first clock signal and the second clock signal.

[0042] In one feasible implementation, as the edge phase difference between the first clock signal and the second clock signal gradually approaches the target phase relationship, the probability distribution of different output levels of the second D flip-flop 120 gradually becomes more balanced, so that the counting result gradually approaches the target count value; when the counting result deviates from the target count value, it indicates that the edge phase relationship between the current first clock signal and the second clock signal deviates from the target phase relationship.

[0043] The phase control module 140 is used to generate a corresponding phase adjustment control signal based on the counting result, and control the phase interpolation module to adjust the phase of the first clock signal and / or the second clock signal based on the phase adjustment control signal, so as to change the processing delay state in the transmission link.

[0044] For example, when the counting result is greater than the target counting interval, the phase control module 140 can control the corresponding phase control word to increase, so that the phase interpolation module performs phase adjustment along the first direction; when the counting result is less than the target counting interval, the phase control module 140 can control the corresponding phase control word to decrease, so that the phase interpolation module performs phase adjustment along the second direction; when the counting result is within the target counting interval, the phase control module 140 can maintain the current phase control word unchanged, so as to maintain the processing delay state corresponding to the current transmission link.

[0045] Therefore, the embodiments of this application do not directly measure the absolute processing delay in the transmission link, but indirectly characterize the processing delay state in the transmission link by detecting the edge phase relationship between the transmission output clock signal TXOUTCLK and the user-side clock signal TXUSRCLK, and make the processing delay in the transmission link tend to be fixed by using a closed-loop phase adjustment method, thereby reducing the processing delay fluctuation of the system during repeated power-on processes and improving the consistency of system transmission and reception delays.

[0046] To effectively detect processing delay variations in the transmission link and reduce processing delay fluctuations caused by clock edge phase drift during repeated system power-ups, in one feasible implementation, the first clock signal is the transmit output clock signal in the transmission link, and the second clock signal is the user-side clock signal in the transmission link. The user-side clock signal drives the front-end logic circuitry of the transmission link, and the transmit output clock signal characterizes the internal transmit clock state of the transmission link. The clock phase alignment circuit determines the processing delay variations in the transmission link by detecting the phase relationship between the user-side clock signal and the transmit output clock signal.

[0047] Specifically, in a high-speed transmission link, data transmission typically involves multiple processing stages, including buffering, clock domain switching, parallel-to-serial conversion, and serial output. These different stages usually operate under different clock domains, resulting in multiple clock signals existing simultaneously within the transmission link. Although these clock signals generally maintain a fixed frequency relationship, the edge phase relationship between the user-side clock signal and the transmitted output clock signal may change during repeated power-on, reset, or reinitialization processes. This is because the initialization state, clock recovery state, and internal path establishment state of the phase-locked loop module may differ.

[0048] Understandably, the transmit output clock signal is typically located on the side of the transmit link closer to the serial output, thus reflecting the transmit status of the subsequent stages of the transmit link to some extent. Conversely, the user-side clock signal is usually used to drive the preceding logic of the transmit link, therefore reflecting the operating status of that logic to some extent. When the edge phase relationship between the user-side clock signal and the transmit output clock signal changes, it means that the overall processing time for data propagation from the preceding logic to the serial output path within the transmit link changes.

[0049] Therefore, this application embodiment does not directly measure the absolute processing delay in the transmission link, but indirectly characterizes the processing delay state in the transmission link by detecting the edge phase relationship between the user-side clock signal and the transmission output clock signal. Compared with directly constructing an absolute delay measurement circuit, this application embodiment can detect the trend of transmission link processing delay changes without adding a complex time measurement structure, thereby reducing the system implementation complexity.

[0050] As an example, in some repetitive power-on processes, the edge between the user-side clock signal and the transmit output clock signal may be relatively advanced. In other repetitive power-on processes, the edge between the user-side clock signal and the transmit output clock signal may be relatively delayed. Since different edge phase relationships correspond to different data propagation times, this edge phase relationship can be used to characterize the processing delay state in the transmission link.

[0051] To automatically perform phase adjustment after the transmission link initialization is completed, thereby fixing the processing delay in the transmission link, in one feasible implementation, the phase control module is specifically used to: after the transmission link initialization is completed, control the counter module to release the reset state and start counting statistics on the target sampling results; acquire the counting result output by the counter module, and determine the edge phase offset state between the first clock signal and the second clock signal based on the counting result; according to the edge phase offset state, control the corresponding phase control word to increase, decrease, or remain unchanged, so that the phase interpolation module performs phase compensation on the transmission clock signal and / or transmission data signal based on the adjusted phase control word, thereby adjusting the processing delay in the transmission link.

[0052] Specifically, before the transmission link initialization is complete, the phase-locked loop module, multi-modulus divider module, parallel-to-serial converter module, and transmission buffer module may not yet be in a stable working state, so the sampling results obtained at this time may have a large degree of randomness. Based on this, this embodiment of the application controls the counter module to release the reset state after detecting that the transmission link initialization is complete, thereby ensuring the validity of subsequent sampling and statistical results.

[0053] After the reset state is lifted, the counter module begins to continuously count the target sampling results and outputs the results to the phase control module. The phase control module determines the offset direction of the edge phase relationship between the user-side clock signal and the transmitted output clock signal relative to the target phase relationship based on the current counting results.

[0054] If the current edge phase relationship deviates from the target phase relationship, the phase control module adjusts the corresponding phase control word to control the phase interpolation module to perform phase compensation on the transmitted clock signal or transmitted data signal. For example, the phase control module can increase the phase control word to make the phase interpolation module perform phase forward shift along the first direction; or decrease the phase control word to make the phase interpolation module perform phase backward shift along the second direction.

[0055] As the phase interpolation module continues to perform phase adjustment, the edge phase relationship between the user-side clock signal and the transmit output clock signal gradually approaches the target phase relationship, thereby causing the processing delay in the transmission link to gradually approach the target processing delay state.

[0056] As an example, in some implementations, the phase control word can be a multi-bit control code. The phase control module can increment or decrement the phase control word by one each time to gradually approach the target phase state. Of course, in other implementations, the phase control module can also adjust multiple control step sizes at once according to the current offset, and this application does not limit this.

[0057] To convert the edge phase relationship between the first clock signal and the second clock signal into a statistical result that is easy to digitally process, in one feasible implementation, the counter module is specifically used to: continuously sample and statistically analyze the target level state output by the second D flip-flop within a preset statistical period, and accumulate the number of outputs corresponding to the target level state to obtain the corresponding counting result. The counting result is used to characterize the edge phase relationship between the first clock signal and the second clock signal. As the edge phase difference between the first clock signal and the second clock signal gradually approaches the target phase relationship, the probability distribution of different level states output by the second D flip-flop gradually tends to a preset proportion, so that the counting result gradually approaches the target count value. The target count value is used to characterize the transmission link being in a target processing delay state.

[0058] Specifically, the first D flip-flop samples the first clock signal based on the second clock signal. When there is a deviation between the edges of the two clock signals, the output of the first D flip-flop will be affected by the edge position relationship. Since the first D flip-flop may enter the critical sampling state when the edges are close, this embodiment further uses a second D flip-flop to synchronize the initial sampling result, thereby reducing the impact of metastability on the subsequent statistical process.

[0059] Based on this, the counter module counts the target level states output by the second D flip-flop. For example, within a preset statistical period, the counter module can count the number of times the second D flip-flop outputs logic "1" or logic "0". By counting the number of occurrences of different level states, a counting result can be generated to characterize the current edge phase relationship.

[0060] When the edge phase relationship between the first clock signal and the second clock signal is far from the target phase relationship, the probability of the second D flip-flop outputting a certain logic state will be significantly higher than that of the other logic state, thus the counting result will deviate significantly from the target count value. As the edge phase relationship gradually approaches the target phase relationship, the probability of the second D flip-flop outputting different logic states gradually tends to be balanced, thereby causing the counting result to gradually approach the target count value.

[0061] As an example, when the preset statistical period includes N samples, the target count value can correspond to N / 2. If the statistical result is close to N / 2, it indicates that the current edge phase relationship is close to the target phase relationship. If the statistical result is significantly greater than or less than N / 2, it indicates that the current edge phase relationship deviates from the target state.

[0062] To determine the specific phase adjustment direction based on the counting result and achieve closed-loop phase control, in one feasible implementation, the phase control module is specifically used to: when the counting result is greater than a first threshold, determine that the edge phase relationship between the first clock signal and the second clock signal deviates from the target phase relationship along a first direction, and control the corresponding phase control word to increase, so that the phase interpolation module performs phase adjustment along the first direction. When the counting result is less than a second threshold, determine that the edge phase relationship between the first clock signal and the second clock signal deviates from the target phase relationship along a second direction, and control the corresponding phase control word to decrease, so that the phase interpolation module performs phase adjustment along the second direction. When the counting result is between the first threshold and the second threshold, control the current phase control word to remain unchanged, so as to maintain the processing delay state corresponding to the current transmission link. The first direction and the second direction are opposite.

[0063] Specifically, the phase control module determines the direction in which the current edge phase relationship deviates from the target state by comparing the positional relationship between the counting result and the target counting interval. For example, if the counting result is consistently large, it indicates that the current edge phase relationship deviates from the target phase relationship along the first direction. Therefore, it is necessary to increase the phase control word to cause the phase interpolation module to perform a phase forward shift. If the counting result is consistently small, it indicates that the current edge phase relationship deviates from the target phase relationship along the second direction. Therefore, it is necessary to decrease the phase control word to cause the phase interpolation module to perform a phase backward shift.

[0064] As the phase control word is continuously adjusted, the edge phase relationship gradually approaches the target state, and the counting result gradually converges to the target counting interval.

[0065] To avoid frequent adjustments by the phase control module due to sampling jitter or instantaneous fluctuations, in one feasible implementation, the first threshold and the second threshold are determined based on a preset statistical period and a preset protection interval. The first threshold corresponds to the sum of the target count value and the upper limit of the protection interval, and the second threshold corresponds to the difference between the target count value and the lower limit of the protection interval. When the count result is between the first and second thresholds, it indicates that the edge phase relationship between the second clock signal and the first clock signal satisfies the target phase alignment condition, thereby ensuring that the transmission link maintains the target processing delay state.

[0066] Specifically, the preset protection interval is used to establish an allowable fluctuation range near the target count value. When the count result is within this allowable range, the phase control module will no longer adjust the phase control word, thereby avoiding continuous oscillation of the phase control module due to minor jitter.

[0067] As an example, the specific judgment process can be as follows: Figure 4As shown, when the statistical period is N and the target count value is N / 2, the protection interval can be set to ±Δ, where Δ is a pre-set statistical tolerance value based on the system clock jitter characteristics, sampling error, and phase adjustment accuracy, used to characterize the allowable counting fluctuation range near the target count value. In this case, the first threshold can be N / 2+Δ, and the second threshold can be N / 2-Δ. If the counting result is between N / 2-Δ and N / 2+Δ, it indicates that the current edge phase relationship has met the target alignment condition.

[0068] To further confirm that the current edge phase relationship has been stably maintained within the target range, rather than accidentally entering the target counting interval due to instantaneous random fluctuations, in one feasible implementation, the phase control module is further configured to: accumulate the state count value when the counting result is within the target counting interval; maintain the current phase control word unchanged before the state count value reaches a preset state threshold, and continue to perform edge phase relationship detection between the first clock signal and the second clock signal; when the state count value reaches the preset state threshold, output a phase alignment completion signal to indicate that the processing delay in the current transmission link has entered a stable state, and terminate the current phase adjustment process.

[0069] Specifically, the state count value is used to record the number of times the counting result continuously satisfies the target counting interval. When the counting result enters the target counting interval only within a few statistical periods, it does not mean that the current edge phase relationship has stabilized, so the phase control module continues to maintain the detection state; only when the counting result is within the target counting interval for multiple consecutive statistical periods is it considered that the current edge phase relationship has stably satisfied the target phase alignment condition.

[0070] As an example, when the state count value reaches M consecutive times, the phase control module can output a phase alignment completion signal; if the count result of a certain statistical cycle exceeds the target count interval again during the accumulation process, the state count value can be cleared and the phase adjustment process can be re-executed. This method effectively improves the stability and reliability of the phase adjustment results.

[0071] The clock phase alignment circuit provided in this application detects the edge phase relationship between the transmit output clock signal and the user-side clock signal in the transmit link, and controls the phase interpolation module to perform phase compensation on the transmit clock signal and / or transmit data signal based on the detection result. This makes the processing delay in the transmit link tend to be fixed, thereby reducing the processing delay fluctuations of the system during repeated power-on, reset, or reinitialization, and improving the consistency of system transmit and receive delays. Compared with the related technologies that directly measure the absolute processing delay in the transmit link or rely on repeated zero-value calibration, this application indirectly characterizes the processing delay state in the transmit link by detecting the edge phase relationship between the transmit output clock signal and the user-side clock signal, and performs closed-loop phase adjustment based on the edge phase relationship. It can realize the detection and compensation of the processing delay changes in the transmit link without adding a complex absolute time measurement structure, thereby reducing the system implementation complexity and hardware resource overhead.

[0072] This embodiment of the application samples the first clock signal using a first D flip-flop and synchronizes the initial sampling result using a second D flip-flop, thereby reducing the probability of metastability propagating to the subsequent statistical module and improving the stability of the target sampling result and the reliability of the edge phase relationship detection result. Simultaneously, a counter module continuously counts the target level state within a preset statistical period and uses the statistical results to characterize the edge phase relationship between the two clock signals, enabling the clock edge phase relationship to be converted into statistical results that are easy for digital logic processing, thus improving the stability and feasibility of the phase detection process. Furthermore, this embodiment of the application sets a target counting interval and a protection interval, and controls the phase control word to increase, decrease, or remain unchanged based on the relationship between the counting result and the target counting interval, thereby achieving closed-loop adjustment control of the phase interpolation module. This avoids the problem of frequent adjustments to the phase control module due to sampling jitter, clock noise, or instantaneous disturbances, improving the stability of the closed-loop adjustment process and reducing the probability of system adjustment oscillations. Furthermore, in this embodiment of the application, the state count value is accumulated, and the processing delay in the current transmission link is determined to be in a stable state only when the count result is within the target count interval for multiple consecutive statistical periods. This avoids misjudgment due to accidental sampling results or instantaneous fluctuations, thereby improving the reliability and stability of the phase alignment result.

[0073] See Figure 5 This method can be applied to clock phase adjustment scenarios in transmission links, such as laser communication ranging systems, high-speed serial transmission systems, high-precision ranging systems, and high-speed interface systems. The method can be executed by the clock phase alignment circuit in the above embodiments, and specifically may include the following steps: S501: Sample the second clock signal based on the first clock signal to obtain the initial sampling result.

[0074] The first clock signal can be the transmit output clock signal in the transmit link, and the second clock signal can be the user-side clock signal in the transmit link. The transmit output clock signal is used to characterize the transmit clock state of the subsequent stage of the transmit link, and the user-side clock signal is used to drive the preceding logic of the transmit link. Because the initialization state of each module in the transmit link may differ during repeated power-on, reset, or reinitialization processes, the edge phase relationship between the transmit output clock signal and the user-side clock signal may change.

[0075] In this embodiment, the second clock signal is used to sample the first clock signal, and the sampling result is used to indirectly characterize the edge phase relationship between the two clock signals.

[0076] Specifically, a first D flip-flop can be used to sample the first clock signal. The data input of the first D flip-flop receives the first clock signal, and the clock input receives the second clock signal. When the edge of the second clock signal arrives, the first D flip-flop latches the logic state corresponding to the current moment of the first clock signal, thereby obtaining the initial sampling result.

[0077] It is understandable that when the edge phase relationship between the first clock signal and the second clock signal is different, the sampling result output by the first D flip-flop may also be different. Therefore, the initial sampling result can reflect the edge phase relationship between the two clock signals to a certain extent.

[0078] As an example, when the edge of the first clock signal is significantly earlier than the edge of the second clock signal, the output of the first D flip-flop may remain in a fixed logic state for a long time; while when the edge of the first clock signal gradually approaches the edge of the second clock signal, the output of the first D flip-flop may gradually exhibit a random change state.

[0079] S502: Synchronously process the initial sampling results to obtain the target sampling results.

[0080] Specifically, since the first D flip-flop may enter a critical sampling state when the edges of the two clock signals are close, the initial sampling result may be subject to metastability. To reduce the impact of metastability on the subsequent statistical process, embodiments of this application further perform synchronization processing on the initial sampling result.

[0081] Specifically, the initial sampling results can be synchronized using a second D flip-flop. The data input of the second D flip-flop is connected to the output of the first D flip-flop, and the clock input of the second D flip-flop receives a second clock signal.

[0082] The second D flip-flop, driven by the second clock signal, latches the initial sampling result again, thereby outputting the corresponding target sampling result. By adding a second-stage synchronization structure, the stability of the target sampling result can be improved, and the probability of metastability propagating to the subsequent statistical module can be reduced.

[0083] S503: Within a preset statistical period, count the number of times the target level state appears in the target sampling results to obtain the counting result.

[0084] After obtaining the target sampling results, the embodiments of this application further perform statistics on the target level state in the target sampling results, thereby converting the clock edge phase relationship into quantifiable digital statistical results.

[0085] As an example, a counter module can be used to count the number of times the target level state is recorded. For instance, the counter module can count the number of times logic "1" is output in the target sampling result within a preset statistical period; of course, in other embodiments, the number of times logic "0" is output can also be counted, and this application does not limit this.

[0086] The preset statistical period can include multiple sampling periods. For example, the preset statistical period can include N sampling processes. After completing N sampling statistics, the counter module outputs the corresponding counting result. It can be understood that when the edge phase difference between the first clock signal and the second clock signal is large, a certain logic state in the target sampling result may have a significant advantage, so the counting result will deviate significantly from the target count value; while as the edge phase difference between the first clock signal and the second clock signal gradually approaches the target phase relationship, the probability distribution of different logic states in the target sampling result gradually tends to be balanced, so that the counting result gradually approaches the target count value.

[0087] As an example, when the preset statistical period includes N samples, the target count value can be set to N / 2. When the count result is close to N / 2, it can be considered that the edge phase relationship between the current first clock signal and the second clock signal is close to the target phase relationship.

[0088] S504: Generate a phase adjustment control signal based on the counting result, and control the phase interpolation module to adjust the phase of the first clock signal and / or the second clock signal based on the phase adjustment control signal.

[0089] After obtaining the counting result, this embodiment of the application further determines whether the edge phase relationship between the current first clock signal and the second clock signal deviates from the target phase relationship based on the counting result, and generates a corresponding phase adjustment control signal. A target counting interval can be preset. If the counting result is outside the target counting interval, it indicates that the current edge phase relationship deviates from the target phase relationship; if the counting result is within the target counting interval, it indicates that the current edge phase relationship meets the target phase condition.

[0090] As an example, when the count result is greater than a first threshold, it can be determined that the current edge phase relationship deviates from the target phase relationship along a first direction, and a phase adjustment control signal is generated to perform phase adjustment in the first direction. When the count result is less than a second threshold, it can be determined that the current edge phase relationship deviates from the target phase relationship along a second direction, and a phase adjustment control signal is generated to perform phase adjustment in the second direction. The first direction and the second direction are opposite. For example, the first direction may correspond to a phase forward shift direction, and the second direction may correspond to a phase backward shift direction.

[0091] Specifically, the target counting interval can be determined based on the target count value and a preset protection interval. For example, when the target count value is N / 2, the target counting interval can be set to N / 2 ± Δ. By setting a protection interval, frequent phase adjustments by the system due to sampling jitter or instantaneous fluctuations can be avoided.

[0092] Specifically, after generating the phase adjustment control signal, the embodiments of this application further control the phase interpolation module to perform phase adjustment based on the phase adjustment control signal.

[0093] Specifically, the phase control module can control the phase interpolation module to perform phase forward or phase backward shifts by adjusting the corresponding phase control word. For example, when the current edge phase relationship deviates from one side of the target phase relationship, the phase control module can increase the phase control word, causing the phase interpolation module to perform phase adjustment along a first direction. Conversely, when the current edge phase relationship deviates from the other side of the target phase relationship, the phase control module can decrease the phase control word, causing the phase interpolation module to perform phase adjustment along a second direction.

[0094] As the phase interpolation module continuously performs phase compensation, the edge phase relationship between the first clock signal and the second clock signal gradually approaches the target phase relationship, and the processing delay in the transmission link also gradually approaches the target processing delay state. It should be noted that the gradual approach of the edge phase relationship between the first clock signal and the second clock signal to the target phase relationship can refer to the process where, after phase compensation is performed on the transmission clock signal and / or transmission data signal based on the phase adjustment control signal, the edge phase offset between the first clock signal and the second clock signal gradually decreases, causing the counting result characterizing the edge phase relationship to gradually approach the target count value, and ultimately satisfying the preset target phase alignment condition. At this time, the processing delay in the transmission link enters the target processing delay state, enabling the system to adjust the transmission link processing delay to the same or substantially the same delay state after each power-on, reset, or reinitialization, thereby achieving a fixed transmission processing delay after repeated power-on.

[0095] Specifically, when the counting results in multiple consecutive statistical periods are all within the target counting interval, it can be determined that the processing delay in the current transmission link has entered a stable state, and the corresponding phase alignment completion signal is output to end the current phase adjustment process.

[0096] Therefore, the clock phase alignment method provided in this application detects the edge phase relationship between the transmitted output clock signal and the user-side clock signal, and controls the phase interpolation module to perform phase compensation on the transmitted clock signal and / or transmitted data signal based on the detection result, so that the processing delay in the transmission link tends to be fixed, thereby reducing the processing delay fluctuation of the system during repeated power-on processes and improving the consistency and stability of the system's transmit and receive delays.

[0097] In other embodiments, an FPGA chip is provided, which includes a transmission link and the clock phase alignment circuit described in the above embodiments.

[0098] As an example, FPGA chips can be applied to high-speed data transmission equipment, laser ranging equipment, satellite communication equipment, fiber optic communication equipment, radar equipment, and high-speed interface equipment, etc., and this application does not limit them.

[0099] In other embodiments, a laser communication ranging system is provided, which includes a transmitter and a receiver; wherein the transmitter includes the FPGA chip in the above embodiments, and the receiver is used to receive the corresponding laser communication signal.

[0100] Specifically, the FPGA chip in the transmitting end is used to perform high-speed serial transmission processing of the data to be transmitted, and to dynamically adjust the processing delay in the transmission link based on the clock phase alignment circuit; the receiving end is used to acquire, demodulate and recover the received laser communication signal.

[0101] As an example, laser communication ranging systems can be applied to scenarios such as inter-satellite laser communication ranging systems, airborne laser communication ranging systems, ground-based laser communication ranging systems, satellite ranging systems, and high-precision time synchronization systems, and this application does not limit them.

[0102] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application's patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features in the formula. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A clock phase alignment circuit, characterized by, include: The system comprises a first D flip-flop, a second D flip-flop, a counter module, and a phase control module. The data input terminal of the first D flip-flop is used to receive a first clock signal, and the clock input terminal of the first D flip-flop is used to receive a second clock signal; The data input terminal of the second D flip-flop is coupled to the output terminal of the first D flip-flop, and the clock input terminal of the second D flip-flop is used to receive the second clock signal; The input terminal of the counter module is coupled to the output terminal of the second D flip-flop; The input terminal of the phase control module is coupled to the output terminal of the counter module, and the output terminal of the phase control module is used to couple to the phase interpolation module. The first D flip-flop is used to sample the first clock signal based on the second clock signal to obtain an initial sampling result; The second D flip-flop is used to synchronize the initial sampling result to obtain the target sampling result; The counter module is used to count the number of times the target level state appears in the target sampling result within a preset statistical period, and obtain the corresponding counting result; The phase control module is used to generate a phase adjustment control signal based on the counting result, and control the phase interpolation module to adjust the phase of the first clock signal and / or the second clock signal based on the phase adjustment control signal, so that the phase relationship between the second clock signal and the first clock signal tends to the target phase relationship.

2. The clock phase alignment circuit of claim 1, wherein, The first clock signal is the transmit output clock signal in the transmit link, and the second clock signal is the user-side clock signal in the transmit link; wherein, the user-side clock signal is used to drive the front-end logic circuit of the transmit link, and the transmit output clock signal is used to characterize the transmit clock state inside the transmit link; The clock phase alignment circuit determines the processing delay changes in the transmission link by detecting the phase relationship between the user-side clock signal and the transmit output clock signal.

3. The clock phase alignment circuit of claim 2, wherein, The phase control module is specifically used for: After the transmission link initialization is completed, the counter module is released from the reset state and the counting statistics of the target sampling results are started. Obtain the counting result output by the counter module, and determine the edge phase offset state between the first clock signal and the second clock signal based on the counting result; Based on the edge phase offset state, the corresponding phase control word is increased, decreased, or kept unchanged, so that the phase interpolation module performs phase compensation on the transmission clock signal and / or transmission data signal based on the adjusted phase control word, thereby adjusting the processing delay in the transmission link.

4. The clock phase alignment circuit of claim 3, wherein, The counter module is specifically used for: Within a preset statistical period, the target level state output by the second D flip-flop is continuously sampled and statistically analyzed, and the number of outputs corresponding to the target level state is accumulated and counted to obtain the corresponding counting result; wherein, the counting result is used to characterize the edge phase relationship between the first clock signal and the second clock signal; As the edge phase difference between the first clock signal and the second clock signal gradually approaches the target phase relationship, the probability distribution of different level states output by the second D flip-flop gradually approaches the preset ratio, so that the counting result gradually approaches the target count value.

5. The clock phase alignment circuit of claim 3, wherein, The phase control module is specifically used for: When the counting result is greater than the first threshold, it is determined that the edge phase relationship between the first clock signal and the second clock signal deviates from the target phase relationship in the first direction, and the corresponding phase control word is increased so that the phase interpolation module performs phase adjustment in the first direction; When the counting result is less than the second threshold, it is determined that the edge phase relationship between the first clock signal and the second clock signal deviates from the target phase relationship in the second direction, and the corresponding phase control word is reduced so that the phase interpolation module performs phase adjustment in the second direction; When the counting result is between the first threshold and the second threshold, the current phase control word is kept unchanged to maintain the processing delay state corresponding to the current transmission link; wherein the first direction is opposite to the second direction.

6. The clock phase alignment circuit of claim 5, wherein, The first threshold and the second threshold are determined based on a preset statistical period and a preset protection interval; wherein, the first threshold corresponds to the sum of the target count value and the upper limit of the protection interval, and the second threshold corresponds to the difference between the target count value and the lower limit of the protection interval; When the counting result is between the first threshold and the second threshold, it indicates that the edge phase relationship between the second clock signal and the first clock signal satisfies the target phase alignment condition, so that the transmission link maintains the target processing delay state.

7. The clock phase alignment circuit of claim 6, wherein, The phase control module is also used for: When the counting result is within the target counting interval, the state count value is accumulated; Before the state count value reaches the preset state threshold, the current phase control word remains unchanged, and the edge phase relationship detection between the first clock signal and the second clock signal continues to be performed; When the state count value reaches the preset state threshold, a phase alignment completion signal is output to indicate that the processing delay in the current transmission link has entered a stable state and to terminate the current phase adjustment process.

8. A method of clock phase alignment, the method comprising: The method, applied to the clock phase alignment circuit according to any one of claims 1 to 7, comprises: The second clock signal is sampled based on the first clock signal to obtain the initial sampling result; The initial sampling results are processed synchronously to obtain the target sampling results; Within a preset statistical period, the number of times the target level state appears in the target sampling results is counted to obtain a counting result; A phase adjustment control signal is generated based on the counting results; The phase adjustment control signal controls the phase interpolation module to adjust the phase of the first clock signal and / or the second clock signal.

9. An FPGA chip, characterized by The FPGA chip includes the clock phase alignment circuit according to any one of claims 1-7.

10. A laser communication ranging system, characterized by, The laser communication ranging system includes the FPGA chip described in claim 9.

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