Method and apparatus for calibrating voltage-to-delay conversion

Abstract

This patent application relates to methods and apparatus for calibrating voltage-delay conversion. An example apparatus includes: a first amplifier circuit system (204) having a first output and a second output; a second amplifier circuit system (240, 421) having an output; a first transistor circuit system (245, 424) having a first terminal and a control terminal; a second transistor circuit system (250, 427) having a first terminal and a control terminal, the control terminal of the second transistor circuit system being coupled to the output of the second amplifier circuit system and the control terminal of the first transistor circuit system; and a voltage-delay circuit system (220) having a first input and a second input, the first input of the voltage-delay circuit system being coupled to the first output of the first amplifier circuit system and the first terminal of the first transistor circuit system, and the second input of the voltage-delay circuit system being coupled to the second output of the first amplifier circuit system and the first terminal of the second transistor circuit system.

Description

[0001] Cross-references to related applications

[0002] This patent application is incorporated herein by reference in its entirety with U.S. Patent Application No. 18 / 498,358, “Voltage-to-Delay Converter,” which is assigned to the assignee of this application. Technical Field

[0003] This specification generally relates to voltage-delay conversion, and more specifically, to methods and apparatus for calibrating voltage-delay conversion. Background Technology

[0004] Analog-to-digital converter (ADC) circuitry responds to an analog input to produce a digital output. The digital output of an ADC allows digital systems to perform digital signal processing operations using a digital representation of an analog signal. Some ADC circuitry implements a pipelined design to sequentially produce portions representing digital values ​​of analog signals over time. Some pipelined designs convert analog voltage-delay, where the analog voltage-delay represents the analog voltage in the time domain. In such pipelines, a time-to-digital converter (TDC) responds to the timing of a delay in continuous time to produce a digital output. Summary of the Invention

[0005] For a method and apparatus for calibrating a voltage-delay conversion, one example apparatus includes: a first amplifier circuit system having a first output and a second output; a second amplifier circuit system having an output; a first transistor circuit system having a first terminal and a control terminal; a second transistor circuit system having a first terminal and a control terminal, the control terminal of the second transistor circuit system being coupled to the output of the second amplifier circuit system and the control terminal of the first transistor circuit system; and a voltage-delay circuit system having a first input and a second input, the first input of the voltage-delay circuit system being coupled to the first output of the first amplifier circuit system and the first terminal of the first transistor circuit system, and the second input of the voltage-delay circuit system being coupled to the second output of the first amplifier circuit system and the first terminal of the second transistor circuit system. Other examples are described.

[0006] For a method and apparatus for calibrating a voltage-delay conversion, one example apparatus includes: an amplifier circuit system having a first input, a second input, a first output, and a second output; a voltage-delay circuit system having a first input and a second input; a pulse generator circuit system having a first input and a second input; and a calibration circuit system having a first input, a second input, a first output, and a second output, wherein the first input of the calibration circuit system is coupled to the first input of the amplifier circuit system, the second input of the calibration circuit system is coupled to the second input of the amplifier circuit system, the first output of the calibration circuit system is coupled to the first output of the amplifier circuit system, the first input of the voltage-delay circuit system, and the first input of the pulse generator circuit system, and the second output of the calibration circuit system is coupled to the second output of the amplifier circuit system, the second input of the voltage-delay circuit system, and the second input of the pulse generator circuit system. Other examples are described.

[0007] For a method and apparatus for calibrating a voltage-delay conversion, one example apparatus includes: an amplifier circuit system having an input and an output; a voltage-delay circuit system having an input; and a calibration circuit system having an input and an output, the input of the calibration circuit system being coupled to the input of the amplifier circuit system, the output of the calibration circuit system being coupled to the output of the amplifier circuit system and the input of the voltage-delay circuit system, the calibration circuit system being configured to: adjust the common-mode voltage at the output of the amplifier circuit system by an offset correction value; and adjust the common-mode voltage at the output of the amplifier circuit system by a gain correction value. Other examples are described. Attached Figure Description

[0008] Figure 1 This is a block diagram and schematic diagram of an example ADC circuit system, including an example delayed ADC circuit system and an example calibration controller circuit system.

[0009] Figure 2 It includes an example sampling circuit system, an example amplifier circuit system, an example calibration circuit system, an example voltage-delay circuit system, and an example pulse generator circuit system. Figure 1 Block diagrams and schematics of an example delayed ADC circuit system.

[0010] Figure 3 yes Figure 2 A schematic diagram of an example sampling circuit system.

[0011] Figure 4 It includes Figure 2 Amplifier circuit system, Figure 2calibration circuit system, Figure 2 Voltage-delay circuit system and Figure 2 Example of a pulse generator circuit system Figure 2 A schematic diagram of an example of a delayed ADC circuit system.

[0012] Figure 5 yes Figure 2 and 4 Timing diagram of an example operation of a delayed ADC circuit system.

[0013] Figure 6 It includes an example amplifier circuit system. Figure 2 and 4 A schematic diagram of an example calibration circuit system.

[0014] Figure 7 It includes an example offset correction circuit system and an example gain correction circuit system. Figure 1 A block diagram of an example calibration controller circuit system.

[0015] Figure 8 This indicates that it can be used. Figure 2 and 4 The flowchart illustrates an example implementation of a delayed ADC circuit system to demonstrate at least one of the example machine-readable instructions or example operations being implemented, instantiated, or executed.

[0016] Figure 9 This indicates that it can be used. Figure 2 , 4 And the calibration circuit system of 6, Figure 7 Offset correction circuit system or more generally Figure 2 and 4 Delayed ADC circuit system and Figure 1 and 7 The flowchart illustrates an example implementation of a calibration controller circuit system to demonstrate at least one of the example machine-readable instructions or example operations being implemented, instantiated, or executed.

[0017] Figure 10 This indicates that it can be used. Figure 2 , 4 And the calibration circuit system of 6, Figure 7 Gain correction circuit system or more generally Figure 2 and 4 Delayed ADC circuit system and Figure 1 and 7 The flowchart illustrates an example implementation of a calibration controller circuit system to demonstrate at least one of the example machine-readable instructions or example operations being implemented, instantiated, or executed.

[0018] Figure 11 It has and does not have Figure 9 and 10 calibration operation Figure 2 and 4 A graph showing the common-mode rejection ratio of an example voltage-delay circuit system.

[0019] Figure 12 It has and does not have Figure 9 and 10 calibration operation Figure 2 and 4 A graph showing the example sound-to-noise ratio of a delayed ADC circuit system.

[0020] Figure 13 yes Figure 1 A schematic diagram of another example of an ADC circuit system, which includes an amplifier circuit system for implementation in the first stage. Figure 9 and 10 Calibration operation.

[0021] Figure 14 This is a block diagram of an example processing platform containing a programmable circuit system configured to execute, instantiate, or perform example machine-readable instructions or execute... Figure 8 , 9 Example operations of 10 to implement Figure 1 and 7 The calibration controller circuit system.

[0022] Figure 15 yes Figure 14 A block diagram of an example implementation of a programmable circuit system.

[0023] Figure 16 yes Figure 14 A block diagram of another example implementation of a programmable circuit system.

[0024] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and in this specification refer to features and / or parts that are (functionally and / or structurally) the same or similar. Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines or boundaries may be idealized. In reality, boundaries or lines may be unobservable, mixed, or irregular. Detailed Implementation

[0025] Analog-to-digital converter (ADC) circuitry responds to an analog input to produce a digital output. The digital output of an ADC allows digital systems to perform digital signal processing operations using a digital representation of an analog signal. Some ADC circuitry implements a pipelined design to sequentially produce portions representing digital values ​​of analog signals over time. Some pipelined designs convert analog voltage-delay, where the analog voltage-delay represents the analog voltage in the time domain. In such pipelines, a time-to-digital converter (TDC) responds to the timing of a delay in continuous time to produce a digital output.

[0026] The voltage-delay transition occurs in a series of stages. In the first stage of the voltage-delay transition (also known as the reset stage), the first and second capacitors of the voltage-delay circuit system are charged to a reference voltage. During the second stage of the voltage-delay transition, the amplifier circuit system discharges the first and second capacitors at different rates based on the amplitude of the analog input signal. For example, the amplifier circuit system draws a first current from the first capacitor in response to a first analog input signal. Similarly, the amplifier circuit system draws a second current from the second capacitor in response to a second analog input signal. During the second stage, the difference between the positive and negative analog inputs results in different discharge rates of the capacitors in the voltage-delay circuit system. At the end of the second stage, the voltages of the first and second capacitors have shifted in response to the difference between the analog input signals.

[0027] During the third stage of the voltage-to-delay conversion, the voltage-delay circuitry uses a bias current to uniformly discharge the remaining charge from the first and second capacitors. Furthermore, during the third stage, a pulse generator circuitry monitors the discharge of the first and second capacitors. The pulse generator circuitry generates a positive delay signal representing the voltage of the first capacitor and a negative delay signal representing the voltage of the second capacitor. The pulse generator circuitry generates a falling edge on the positive delay signal in response to the voltage of the first capacitor falling below a threshold voltage. Similarly, the pulse generator circuitry generates a falling edge on the negative delay signal in response to the voltage of the second capacitor falling below a threshold voltage. The difference between the falling edges of the positive and negative delay signals is proportional to the difference in discharge rates during the second stage of the voltage-to-delay conversion. Such voltage-delay operation is further described and illustrated in U.S. Patent Application No. 18 / 498,358, "Voltage-to-Delay Converter," which is incorporated herein by reference in its entirety and assigned to the assignee of this application.

[0028] In differential analog-to-digital conversion (ADC), the analog input of an ADC circuit system is represented as the voltage difference between analog input signals, which may be referred to as the positive input signal and the negative input signal. The voltage in the middle of the voltage difference between the analog inputs is called the common-mode voltage. For example, if the positive input signal is four volts and the negative input signal is eight volts, then the analog input voltage of the ADC circuit system is four volts and the common-mode voltage is six volts. In another example, if the positive input signal is eight volts and the negative input signal is twelve volts, then the analog input voltage of the ADC circuit system is four volts and the common-mode voltage is ten volts. Preferably, in both examples, the ADC circuit system produces a digital output representing four volts. However, during conversion, the components of the ADC circuit system cannot completely suppress the effect of the common-mode voltage. In such examples, although the differential voltage is the same, the digital output varies. This variation in the output voltage of the ADC circuit system in response to different common-mode voltages is characterized by the common-mode rejection ratio (CMRR). CMRR represents the ability of the differential circuit system to reduce the effect of the common-mode voltage on the output. An ADC circuit system with a low CMRR produces an output that is susceptible to variations in the common-mode voltage of the analog input.

[0029] In voltage-delay conversion, the midpoint between the positive and negative delayed signals, which are represented differentially as analog voltages, represents the common-mode voltage. During operation, mismatches between components of the voltage-delay circuitry modify the timing of the falling edge of either the positive or negative delayed signal. This modification of the falling edge timing alters the common-mode voltage and reduces CMRR. Furthermore, during voltage-delay conversion, the amplifier circuitry and voltage-delay circuitry can amplify the common-mode voltage through gain, which further reduces the CMRR of the ADC circuitry.

[0030] The examples described herein include methods and apparatus for calibrating voltage-delay conversion using a calibration circuit system. In some examples, the delay-domain ADC circuit system includes a first amplifier circuit system, a second amplifier circuit system, a sampling circuit system, a calibration circuit system, a voltage-delay (V2D) circuit system, a pulse generator circuit system, a time-to-digital converter (TDC) circuit system, and a calibration controller circuit system. The first amplifier circuit system and the sampling circuit system receive a positive analog input signal and a negative analog input signal from an analog signal source. The second amplifier circuit system receives a positive DAC signal and a negative DAC signal from the calibration DAC of the calibration controller circuit system. In non-calibration operation, the sampling circuit system provides the positive analog input signal and the negative analog input signal to the calibration circuit system. In calibration operation, the sampling circuit system provides the positive DAC signal and the negative DAC signal to the calibration circuit system. The calibration circuit system compares the common-mode voltage of the positive and negative input signals with a reference input common-mode voltage from the calibration controller circuit system. During the second stage of the voltage-delay conversion, in response to the difference between the reference input common-mode voltage from the sampling circuit system and the common-mode voltage, the calibration circuit system draws current from the first and second capacitors of the V2D circuit system. Advantageously, the current of the calibration circuit system can correct for one or both of the common-mode voltage offset or the common-mode gain. Advantageously, using the calibration circuit system to reduce the common-mode voltage offset or the common-mode gain improves the CMRR of the voltage-delay conversion.

[0031] In some of the described examples, the calibration controller circuitry performs a calibration operation to determine the reference input common-mode voltage and sets the gain of the calibration circuitry. In the offset calibration operation, the calibration controller circuitry disables the first amplifier circuitry and sets the positive and negative DAC signals to have a common-mode voltage that is approximately equal to zero. The TDC circuitry produces a digital output representing the offset of the voltage-delay conversion. The calibration controller circuitry adjusts the reference input common-mode voltage in response to the digital output. Advantageously, the difference between the digital output and the target common-mode offset represents the offset correction value. Advantageously, adjusting the reference input common-mode voltage with the offset correction value reduces the voltage-delay conversion offset. Advantageously, reducing the voltage-delay conversion offset increases the CMRR of the ADC circuitry.

[0032] In the gain calibration operation, the calibration controller circuitry disables the first amplifier circuitry and sets the positive and negative DAC signals to relatively high differential voltages. The calibration controller circuitry adjusts the common-mode voltages of the positive and negative DAC signals to determine the common-mode voltage with maximum gain. The calibration controller circuitry adjusts its gain to compensate for the determined maximum gain. Advantageously, the gain of the calibration circuitry can be set to cancel the common-mode gain of the amplifier circuitry and the V2D circuitry. Advantageously, adjusting the gain of the calibration circuitry reduces the common-mode gain of the voltage-delay conversion. Advantageously, reducing the common-mode gain of the voltage-delay conversion increases the CMRR of the ADC circuitry.

[0033] Figure 1 This is a block diagram and schematic diagram of an example ADC circuit system 100. Figure 1 In the example, the ADC circuit system 100 includes a first switch 105, a first capacitor 110, a second switch 115, a second capacitor 120, an ADC 125, a capacitor digital-to-analog converter (CDAC) 130, a third switch 135, a fourth switch 140, an example clock circuit system 145, and an example delay domain ADC circuit system 150. Figure 1 The example delay domain ADC circuit system 150 includes a first example delay ADC circuit system 155, a second example delay ADC circuit system 160, a third example delay ADC circuit system 165, and an example calibration controller circuit system 170.

[0034] The ADC circuit system 100 has a first input, a second input, a first output, a second output, a third output, and a fourth output. The first and second inputs of the ADC circuit system 100 are configured to be coupled to an external circuit system that supplies a positive input signal and a negative input signal (INP, INM). Figure 1 In the example, the positive and negative input signals form a pair of differential input signals, which have an analog value equal to the difference between the first and second inputs. The first, second, third, and fourth outputs of the ADC circuit system 100 are configured to be coupled to an external circuit system that receives the first, second, third, and fourth digital values ​​(DOUT0, DOUT1, DOUT2, DOUT3).

[0035] Switch 105 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 105 is coupled to a first input of ADC circuit system 100, which supplies a positive input signal. The second terminal of switch 105 is coupled to a first capacitor 110, ADC 125, and switch 135. The control terminal of switch 105 is coupled to switch 115 and clock circuit system 145.

[0036] Capacitor 110 has a first terminal and a second terminal. The first terminal of capacitor 110 is coupled to switches 105, 135 and ADC 125. The second terminal of capacitor 110 is coupled to a common terminal, which supplies a common potential.

[0037] Switch 115 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 115 is coupled to the second input of ADC circuit system 100, which supplies the negative-side input signal. The second terminal of switch 115 is coupled to capacitor 120, ADC 125, and switch 140. The control terminal of switch 115 is coupled to the control terminal of switch 105 and clock circuit system 145.

[0038] Capacitor 120 has a first terminal and a second terminal. The first terminal of capacitor 120 is coupled to switches 115, 140 and ADC 125. The second terminal of capacitor 120 is coupled to a common terminal, which supplies a common potential.

[0039] ADC 125 has a first input, a second input, and an output. The first input of ADC 125 is coupled to switches 105 and 135 and capacitor 110. The second input of ADC 125 is coupled to switches 115 and 140 and capacitor 120. The output of ADC 125 is coupled to CDAC 130 and the first output of ADC circuit system 100.

[0040] The CDAC 130 has an input, a first output, and a second output. The input of the CDAC 130 is coupled to the ADC 125. The first output of the CDAC 130 is coupled to the switch 135 and the delay domain ADC circuitry 150. The second output of the CDAC 130 is coupled to the switch 140 and the delay domain ADC circuitry 150.

[0041] Switch 135 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 135 is coupled to switch 105, capacitor 110, and ADC 125. The second terminal of switch 135 is coupled to CDAC 130 and delay domain ADC circuitry 150. The control terminal of switch 135 is coupled to the control terminal of switch 140 and clock circuitry 145.

[0042] Switch 140 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 140 is coupled to switch 115, capacitor 120, and ADC 125. The second terminal of switch 140 is coupled to CDAC 130 and delay domain ADC circuitry 150. The control terminal of switch 140 is coupled to the control terminal of switch 135 and clock circuitry 145. In some examples, switches 105, 115, 135, and 140 are implemented as transistors or alternative switching circuitry. Furthermore, in some examples, switches 105, 115, 135, and 140 are shown or described as sample-and-hold circuitry.

[0043] The clock circuit system 145 has a first output and a second output. The first output of the clock circuit system 145 is coupled to the control terminals of switches 105 and 115. The second output of the clock circuit system 145 is coupled to the control terminals of switches 135 and 140.

[0044] The delay-domain ADC circuit system 150 has a first input, a second input, a first output, a second output, and a third output. The first input of the delay-domain ADC circuit system 150 is coupled to a CDAC 130 and a switch 135. The second input of the delay-domain ADC circuit system 150 is coupled to a CDAC 130 and a switch 140. The first and second inputs of the delay-domain ADC circuit system 150 each receive a positive residual voltage (V). RESP ) and negative residual voltage (V RESM The first, second, and third outputs of the delay domain ADC circuit system 150 are coupled to the second, third, and fourth outputs (DOUT1, DOUT2, DOUT3) of the delay domain ADC circuit system 150. The first, second, and third outputs of the delay domain ADC circuit system 150 provide digital values.

[0045] The delayed ADC circuit system 155 has a first input, a second input, a third input, and an output. The first input of the delayed ADC circuit system 155 is coupled to the first input (V) of the delayed ADC circuit systems 160 and 165 and the delayed domain ADC circuit system 150. RESP The second input of the delayed ADC circuit system 155 is coupled to the second input (V) of the delayed ADC circuit systems 160 and 165 and the delayed domain ADC circuit system 150. RESM The third input of the delayed ADC circuit system 155 is coupled to the calibration controller circuit system 170.

[0046] The delayed ADC circuit system 160 has a first input, a second input, a third input, and an output. The first input of the delayed ADC circuit system 160 is coupled to the first input (V) of the delayed ADC circuit systems 155 and 165, as well as the first input (V) of the delayed domain ADC circuit system 150.RESP The second input of the delayed ADC circuit system 160 is coupled to the second input (V) of the delayed ADC circuit systems 155 and 165 and the delayed domain ADC circuit system 150. RESM The third input of the delayed ADC circuit system 160 is coupled to the calibration controller circuit system 170.

[0047] The delayed ADC circuit system 165 has a first input, a second input, a third input, and an output. The first input of the delayed ADC circuit system 165 is coupled to the first input (V) of the delayed ADC circuit systems 155 and 160 and the delayed domain ADC circuit system 150. RESP The second input of the delayed ADC circuit system 165 is coupled to the second input (V) of the delayed ADC circuit systems 155 and 160 and the delayed domain ADC circuit system 150. RESM The third input of the delayed ADC circuit system 165 is coupled to the calibration controller circuit system 170. Figure 2 , 4 Figures 155, 160, and 165 further illustrate and describe examples of delayed ADC circuit systems.

[0048] The calibration controller circuit system 170 has a first input, a second input, a third input, a first output, a second output, and a third output. The first input of the calibration controller circuit system 170 is coupled to the second output of the delayed ADC circuit system 155 and the ADC circuit system 100. The second input of the calibration controller circuit system 170 is coupled to the third output of the delayed ADC circuit system 160 and the ADC circuit system 100. The third input of the calibration controller circuit system 170 is coupled to the fourth output of the delayed ADC circuit system 165 and the ADC circuit system 100. Figure 7 Further examples of the calibration controller circuitry system 170 are shown and described.

[0049] In example operation, clock circuit system 145 closes switches 105 and 115 and opens switches 135 and 140 during the first cycle. During the first cycle, positive and negative input signals charge capacitors 110 and 120. During the second cycle, clock circuit system 145 opens switches 105 and 115 and closes switches 135 and 140. Furthermore, ADC 125 generates a first digital value (DOUT0) in response to the analog voltage of capacitors 110 and 120. In this example operation, CDAC 130 converts the first digital value into an analog approximation of the analog voltage of capacitors 110 and 120. By subtracting the approximation of the analog value of capacitors 110 and 120 from their actual analog value, CDAC 130 generates positive and negative residual voltages. Figure 8Example operation (also referred to as the first stage) of switches 105, 115, 135, 140, capacitors 110, 120, ADC 125, CDAC 130, and clock circuitry 145 is further shown and described.

[0050] In the example operation, the delay domain ADC circuitry 150 receives positive and negative residual voltages from the CDAC 130. The calibration controller circuitry 170 activates at least one of the delay ADC circuitries 155, 160, and 165. The calibration controller circuitry 170 performs a calibration operation on the inactive delay ADC circuitry among the delay ADC circuitries 155, 160, and 165. Figure 9 and 10 Example operation of the calibration controller circuitry 170 is further shown and described. Once calibration is complete, the calibration controller circuitry 170 activates one or more of the delayed ADC circuitries 155, 160, and 165. In some examples, the calibration controller circuitry 170 periodically calibrates the delayed ADC circuitries 155, 160, and 165. Advantageously, the ADC circuitry 100 continues to produce digital values ​​during the calibration of one or more of the delayed ADC circuitries 155, 160, and 165. Advantageously, calibrating the delayed ADC circuitries 155, 160, and 165 improves the CMRR of the ADC circuitry 100.

[0051] Figure 2 These are block diagrams and schematic diagrams of a delayed ADC circuit system 200, which is... Figure 1 Examples of delayed ADC circuit systems 155, 160, and 165. Figure 2 In the example, the delayed ADC circuit system 200 includes a first amplifier circuit system 204, a second amplifier circuit system 208, a sampling circuit system 212, a calibration circuit system 215, a voltage-delay (V2D) circuit system 220, a pulse generator circuit system 225, and an example time-to-digital converter (TDC) circuit system 230. In some examples, such as in Figure 2 In the example, the delayed ADC circuit system 200 further includes an example calibration controller circuit system 235, which is... Figure 1 An example of the calibration controller circuit system 170. In other examples, such as in... Figure 1 In this process, the calibration controller circuit system 235 can be located outside the delay ADC circuit system 200. Figure 2 The example calibration circuit system 215 includes an example amplifier circuit system 240, a first example transistor 245, and a second example transistor 250.

[0052] The delayed ADC circuit system 200 has a first input, a second input, and an output. The first input of the delayed ADC circuit system 200 is configured to be coupled to... Figure 1 CDAC 130 and Figure 1 Switch 135. The first input of the delayed ADC circuit system 200 receives the positive residual voltage (V). RESP The second input of the delayed ADC circuit system 200 is configured to be coupled to... Figure 1 The CDAC 130 and switch 140. The second input of the delayed ADC circuit system 200 receives the negative residual voltage (V). RESM The output of the delayed ADC circuit system 200 is configured to be coupled to an external circuit system. The output of the delayed ADC circuit system 200 provides a digital output (DOUT).

[0053] Amplifier circuit system 204 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of amplifier circuit system 204 is coupled to the first input (V0) of sampling circuit system 212 and delayed ADC circuit system 200. RESP The second terminal of amplifier circuit system 204 is coupled to the second input (V) of sampling circuit system 212 and delay ADC circuit system 200. RESM The third and fourth terminals of amplifier circuit system 204 are coupled to amplifier circuit system 208, calibration circuit system 215, V2D circuit system 220, and pulse generator circuit system 225. In some examples, amplifier circuit system 204 is referred to as a voltage-to-voltage (V2V) circuit system. Furthermore, as... Figure 4 As shown, amplifier circuitry 204 may include a clock input for controlling amplifier circuitry 204. Figure 4 An example of amplifier circuit system 204 is shown and described.

[0054] Amplifier circuit system 208 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of amplifier circuit system 208 are coupled to sampling circuit system 212 and calibration controller circuit system 235. The first and second terminals of amplifier circuit system 208 receive a positive DAC signal and a negative DAC signal (DACP, DACM), respectively, from calibration controller circuit system 235. The positive and negative DAC signals are a pair of differential analog signals that allow calibration controller circuit system 235 to control the inputs of amplifier circuit systems 208 and 240. The third and fourth terminals of amplifier circuit system 208 are coupled to amplifier circuit system 204, calibration circuit system 215, V2D circuit system 220, and pulse generator circuit system 225. In some examples, amplifier circuit system 208 is referred to as a voltage-to-voltage (V2V) circuit system. However, unlike amplifier circuit system 204, amplifier circuit system 208 is configured for calibration operations, which combines... Figure 9 , 10 Figures 1 and 11 show and describe this. Alternatively, in some examples, amplifier circuitry 208 may be replaced by sampling circuitry (e.g., sampling circuitry 212). In such alternative examples, the additional component between the input of the delayed ADC circuitry 200 and amplifier circuitry 204 introduces noise.

[0055] The sampling circuit system 212 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, an eighth terminal, and a ninth terminal. The first terminal of the sampling circuit system 212 is coupled to the first input (V1) of the amplifier circuit system 204 and the delayed ADC circuit system 200. RESP The second terminal of the sampling circuit system 212 is coupled to the second input (V) of the amplifier circuit system 204 and the delay ADC circuit system 200. RESM The third and fourth terminals of sampling circuit system 212 are coupled to amplifier circuit system 208 and calibration controller circuit system 235. The fifth, sixth, and seventh terminals of sampling circuit system 212 are coupled to calibration controller circuit system 235. The eighth and ninth terminals of sampling circuit system 212 are coupled to calibration circuit system 215. Figure 3 Further examples of the sampling circuit system 212 are shown and described.

[0056] The calibration circuit system 215 (also called the correction circuit system) has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, an eighth terminal, a ninth terminal, and a tenth terminal. The first and second terminals of the calibration circuit system 215 are coupled to the sampling circuit system 212. The third and fourth terminals of the calibration circuit system 215 are coupled to the amplifier circuit systems 204 and 208, the V2D circuit system 220, and the pulse generator circuit system 225. The fifth, sixth, seventh, eighth, ninth, and tenth terminals of the calibration circuit system 215 are coupled to the calibration controller circuit system 235. Figure 4 and 6 Further examples of the calibration circuit system 215 are shown and described.

[0057] V2D circuit system 220 has a first terminal and a second terminal. The first and second terminals of V2D circuit system 220 are coupled to amplifier circuit systems 204, 208, calibration circuit system 215, and pulse generator circuit system 225. Figure 4 Further examples of the V2D circuit system 220 are shown and described.

[0058] The pulse generator circuit system 225 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the pulse generator circuit system 225 are coupled to amplifier circuit systems 204 and 208, calibration circuit system 215, and V2D circuit system 220. The third and fourth terminals of the pulse generator circuit system 225 are coupled to TDC circuit system 230. Figure 4 Further examples of the pulse generator circuit system 225 are shown and described.

[0059] TDC circuit system 230 has a first input, a second input, and an output. The first and second inputs of TDC circuit system 230 are coupled to pulse generator circuit system 225. Pulse generator circuit system 225 provides positive and negative delayed signals (PULSE_OUTP, PULSE_OUTM) at the inputs of TDC circuit system 230. The delay between the edges of the positive and negative delayed signals corresponds to the positive and negative residual voltages (V) at the inputs of delayed ADC circuit system 200. RESP V RESM The difference between the two signals is proportional. The output of the TDC circuit system 230 is coupled to the output of the calibration controller circuit system 235 and the delay ADC circuit system 200. The TDC circuit system 230 provides a digital value (TDC) representing the delay of the positive and negative delay signals and the analog voltage at the input of the delay ADC circuit system 200. OUT ).

[0060] The calibration controller circuit system 235 has inputs, a first output, a second output, a third output, a fourth output, a fifth output, a sixth output, a seventh output, an eighth output, a ninth output, a tenth output, and an eleventh output. The inputs of the calibration controller circuit system 235 are coupled to the outputs of the TDC circuit system 230 and the delayed ADC circuit system 200 (TDC...). OUT The first and second outputs of the calibration controller circuit system 235 are coupled to the amplifier circuit system 208 and the sampling circuit system 212. The third, fourth, and fifth outputs of the calibration controller circuit system 235 are coupled to the sampling circuit system 212. The sixth, seventh, eighth, and ninth outputs of the calibration controller circuit system 235 are coupled to the amplifier circuit system 240, or more generally to the calibration circuit system 215. The tenth and eleventh outputs of the calibration controller circuit system 235 are coupled to transistors 245 and 250, respectively, or more generally to the calibration circuit system 215. Figure 7 Further examples of the calibration controller circuitry system 235 are shown and described.

[0061] Amplifier circuit system 240 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal. The first and second terminals of amplifier circuit system 240 are coupled to sampling circuit system 212. The third, fourth, fifth, and sixth terminals of amplifier circuit system 240 are coupled to calibration controller circuit system 235. The seventh terminal of amplifier circuit system 240 is coupled to transistors 245 and 250. In some examples, amplifier circuit system 240 is referred to as a common-mode rejection ratio (CMRR) amplifier. Figure 6 Further examples of amplifier circuit system 240 are shown and described.

[0062] Transistor 245 has a first terminal, a second terminal, a control terminal, and a trimming input. The first terminal of transistor 245 is coupled to amplifier circuit systems 204, 208, V2D circuit system 220, and pulse generator circuit system 225. The second terminal of transistor 245 is coupled to a common terminal supplying a common potential (e.g., ground, AVSS, etc.). The control terminal of transistor 245 is coupled to the control terminals of amplifier circuit system 240 and transistor 250. The trimming input of transistor 245 is coupled to calibration controller circuit system 235. Calibration controller circuit system 235 provides a first gain trimming value (GAIN) at the trimming input of transistor 245. TRIM_T1 The first gain trim value controls the size of transistor 245 by setting at least one of the channel length or width.

[0063] Transistor 250 has a first terminal, a second terminal, a control terminal, and a trimming input. The first terminal of transistor 250 is coupled to amplifier circuit systems 204 and 208, V2D circuit system 220, and pulse generator circuit system 225. The second terminal of transistor 250 is coupled to a common terminal supplying a common potential. The control terminal of transistor 250 is coupled to the control terminals of amplifier circuit system 240 and transistor 245. The trimming input of transistor 250 is coupled to calibration controller circuit system 235. Calibration controller circuit system 235 provides a second gain trimming value (GAIN) at the trimming input of transistor 250. TRIM_T2 The second gain trim value controls the size of transistor 250 by setting at least one of the channel length or width.

[0064] exist Figure 2 In the example, transistors 245 and 250 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 245 and 250 may be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar junction transistors (BJTs), or, with slight modifications, p-type equivalent devices. Transistors 245 and 250 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 245 and 250 may be implemented on / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0065] In the example non-calibration operation (also known as normal operation), amplifier circuitry 204 is active, amplifier circuitry 208 is inactive, and sampling circuitry 212 provides positive and negative residual voltages to calibration circuitry 215. In some examples, for example... Figure 3 , 4 In conjunction with 7, the calibration controller circuit system 235 uses the input control signal (INP_CNTRL), the inverting input control signal (INP_CNTRL_Z), and the calibration control signal (CAL_CNTRL) to control the sampling circuit system 212. Figure 3 Examples of the input control signal (INP_CNTRL), the inverting input control signal (INP_CNTRL_Z), and the calibration control signal (CAL_CNTRL) are further described.

[0066] In this type of example non-calibration operation, amplifier circuitry 240 compares the common-mode voltages of the positive and negative residual voltages with the reference input common-mode voltage (V) from calibration controller circuitry 235. INCM_REFThe comparison is performed. Transistors 245 and 250 draw current from the V2D circuit system 220 in response to the comparison in the amplifier circuit system 240. The pulse generator circuit system 225 generates positive and negative delay signals (PULSE_OUTP, PULSE_OUTM) in response to the voltage in the V2D circuit system 220. Figure 4 , 6 8 further illustrates and describes example operation of transistors 245 and 250. Furthermore, example operation of amplifier circuit system 204, V2D circuit system 220, and pulse generator circuit system 225 is further illustrated and described in U.S. Patent Application No. 18 / 498,358, "Voltage-to-Delay Converter," which is incorporated herein by reference in its entirety and assigned to the assignee of this application. TDC circuit system 230 generates a digital value (TDC) in response to the delay between a positive delay signal and a negative delay signal. OUT Advantageously, drawing current from amplifier circuit systems 204, 208 and V2D circuit system 220 compensates for at least one of the offset or gain of amplifier circuit system 204 and V2D circuit system 220. Advantageously, calibration circuit system 215 improves the CMRR of delayed ADC circuit system 200. Figure 4 , 6 Figures 8 and 9 further illustrate and describe example operations of amplifier circuit system 204, V2D circuit system 220, and pulse generator circuit system 225.

[0067] In the example calibration operation, amplifier circuitry 204 is inactive, amplifier circuitry 208 is active, and sampling circuitry 212 provides positive and negative DAC signals (DACP, DAM) to calibration circuitry 215. In some examples, for instance... Figure 3 , 4 7. The calibration controller circuit system 235 uses the input control signal (INP_CNTRL), the inverting input control signal (INP_CNTRL_Z), and the calibration control signal (CAL_CNTRL) to control the sampling circuit system 212.

[0068] In this type of example calibration operation, the calibration controller circuitry 235 uses positive and negative DAC signals (DACP, DAM) and a positive bias current selection signal (SEL). ICUR_P ) and negative bias current selection signal (SEL) ICUR_M ) and reference input common-mode voltage (V INCM_REF This is used to calibrate the offset of the delayed ADC circuit system 200. Combined with... Figure 6 and 7Examples of the positive bias current selection signal and the negative bias current selection signal are further shown and described. (Combined with...) Figure 9 An example offset calibration operation is further shown and described. Advantageously, the calibration controller circuitry 235 can respond to adjusting the reference input common-mode voltage (V... INCM_REF This reduces the offset of the delayed ADC circuit system 200.

[0069] Furthermore, in such example calibration operations, the calibration controller circuitry 235 uses positive and negative DAC signals (DACP, DAM) and a gain control signal (GAIN). CNTRL ) and the first gain trim value and the second gain trim value (GAIN) TRIM_T1 GAIN TRIM_T2 This is used to calibrate the gain of the delayed ADC circuit system 200. Combined with... Figure 6 and 7 Further examples of gain control signals and gain trim values ​​are provided. Figure 10 Example gain calibration operations are further shown and described. Advantageously, the calibration controller circuitry 235 can reduce the gain of the delayed ADC circuitry 200 in response to adjusting the gain of the calibration circuitry 215. Advantageously, the offset and gain calibration operations improve the accuracy of the calibration circuitry 215.

[0070] Figure 3 yes Figure 2 A schematic diagram of an example of the sampling circuit system 212. Figure 3 The example sampling circuit system 212 includes a first example switch 305, a second example switch 310, a third example switch 315, a fourth example switch 320, a first example capacitor 325, a second example capacitor 330, and a fifth example switch 335. The sampling circuit system 212 has a first input, a second input, a third input, a fourth input, a fifth input, a sixth input, a seventh input, a first output, and a second output. The first input of the sampling circuit system 212 is configured to couple to... Figure 1 CDAC 130 and Figure 1 The switch 135. The second input of the sampling circuit system 212 is configured to be coupled to Figure 1 The CDAC 130 and switch 140. The first and second inputs of the sampling circuit system 212 receive the positive residual voltage (V) respectively. RESP ) and negative residual voltage (V RESM The third, fourth, fifth, sixth, and seventh inputs of the sampling circuit system 212 are configured to be coupled to, respectively. Figure 1 and 2The calibration controller circuit systems 170 and 235. The third, fourth, fifth, sixth, and seventh inputs of the sampling circuit system 212 receive the input control signal (INP_CNTRL), the inverting input control signal (INP_CNTRL_Z), the positive DAC signal, the negative DAC signal (DACP, DAM), and the calibration control signal (CAL_CNTRL), respectively. The first and second outputs of the sampling circuit system 212 are configured to couple to... Figure 2 The calibration circuit system 215. The first and second outputs of the sampling circuit system 212 provide positive and negative input signals (IND). P IND M ).

[0071] Switch 305 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 305 is coupled to the first input (V) of sampling circuit system 212. RESP The second terminal of switch 305 is coupled to switches 315 and 335, capacitor 325, and the first output of sampling circuit system 212. The control terminal of switch 305 is coupled to the control terminal of switch 310 and the third input (INP_CNTRL) of sampling circuit system 212.

[0072] Switch 310 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 310 is coupled to the second input (V) of sampling circuit system 212. RESM The second terminal of switch 310 is coupled to switches 320 and 335, capacitor 330, and the second output of sampling circuit system 212. The control terminal of switch 310 is coupled to the control terminal of switch 305 and the third input (INP_CNTRL) of sampling circuit system 212.

[0073] Switch 315 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 315 is coupled to the fourth input (DACP) of sampling circuit system 212. The second terminal of switch 315 is coupled to switches 305 and 335, capacitor 325, and the first output of sampling circuit system 212. The control terminal of switch 315 is coupled to the control terminal of switch 320 and the sixth input (CAL_CNTRL) of sampling circuit system 212.

[0074] Switch 320 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 320 is coupled to the fifth input (DACM) of sampling circuit system 212. The second terminal of switch 320 is coupled to switches 310, 335, capacitor 330, and the second output of sampling circuit system 212. The control terminal of switch 320 is coupled to the control terminal of switch 315 and the sixth input (CAL_CNTRL) of sampling circuit system 212.

[0075] Capacitor 325 has a first terminal and a second terminal. The first terminal of capacitor 325 is coupled to switches 305, 315, 335 and the first output of sampling circuit system 212. The second terminal of capacitor 325 is coupled to a common terminal that supplies a common potential.

[0076] Capacitor 330 has a first terminal and a second terminal. The first terminal of capacitor 330 is coupled to switches 310, 320, 335 and the second output of sampling circuit system 212. The second terminal of capacitor 330 is coupled to a common terminal that supplies a common potential.

[0077] Switch 335 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 335 is coupled to switches 305 and 315, capacitor 325, and the first output of sampling circuit system 212. The second terminal of switch 335 is coupled to switches 310 and 320, capacitor 330, and the second output of sampling circuit system 212. The control terminal of switch 335 is coupled to the seventh input (INP_CNTRL_Z) of sampling circuit system 212.

[0078] In the example non-calibration operation, the calibration control signal (CAL_CNTRL) opens switches 315 and 320. Additionally, the input control signal (INP_CNTRL) periodically closes switches 305 and 310. In response to the closing of switches 305 and 310, positive and negative residual voltages (V) are generated. RESP and V RESM The capacitors 325 and 330 are charged. During the second part of the cycle, the input control signal (INP_CNTRL) opens switches 305 and 310, and the inverting input control signal (INP_CNTRL_Z) closes switch 335. During the second part of the cycle, the switches short-circuit capacitors 325 and 330 to separate the positive input signal and the negative input signal (IND) at the output of the sampling circuit system 212. P IND M The sampling circuit system 212 provides the positive and negative residual voltages to the calibration circuit system 215 during non-calibration operations.

[0079] In the example calibration operation, the input control signal (INP_CNTRL) opens switches 305 and 310, and the calibration control signal (CAL_CNTRL) closes switches 315 and 320. In response to the closing of switches 315 and 320, the positive and negative DAC signals charge capacitors 325 and 330. In some examples, similar to during non-calibration operations, periodically closing switch 335 will charge the positive and negative input signals (IND) at the output of the sampling circuit system 212. P IND M This is set as the common-mode voltage for the positive and negative DAC signals. Advantageously, during calibration operations, sampling circuit system 212 provides the positive and negative DAC signals (DACP, DAM) to calibration circuit system 215. Combined with... Figure 8 The example operation of the sampling circuit system 212 is further described.

[0080] Figure 4 yes Figure 2 Amplifier circuit system 204 Figure 2 Calibration circuit system 215, Figure 2 V2D circuit system 220, Figure 2 Schematic diagrams of example pulse generator circuit system 225, example master clock circuit system 402, and example calibration clock circuit system 404. Figure 4 The example amplifier circuit system 204 includes a first example transistor 405, a second example transistor 406, a third example transistor 409, a fourth example transistor 412, a fifth example transistor 415, and a sixth example transistor 418. Although in Figure 4 In the example, amplifier circuit system 208 is not shown schematically, but in one example, amplifier circuit systems 204 and 208 are structurally similar. Figure 4 The example calibration circuit system 215 includes an example amplifier circuit system 421 (CMRR amplifier), a first example transistor 424, a second example transistor 427, a third example transistor 430, and a fourth example transistor 433. Figure 4 The example V2D circuit system 220 includes a first example transistor 436, a second example transistor 439, a third example transistor 442, a fourth example transistor 445, a fifth example transistor 448, a first example capacitor 451, a second example capacitor 454, a third example capacitor 457, and a fourth example capacitor 460. Figure 4The example pulse generator circuit system 225 includes a first example transistor 463, a second example transistor 466, a third example transistor 469, a fourth example transistor 472, a fifth example transistor 475, a sixth example transistor 478, a seventh example transistor 481, an eighth example transistor 484, a ninth example transistor 487, a tenth example transistor 490, an eleventh example transistor 493, and a twelfth example transistor 496.

[0081] Amplifier circuit system 204 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first and second inputs of amplifier circuit system 204 are coupled to the first and second inputs (V1, V2) of delayed ADC circuit system 200. RESP V RESM The third and fourth inputs of amplifier circuit system 204 are coupled to master clock circuit system 402, which provides a V2V clock signal (CLK_V2V) and a bias clock signal (CLK_BIAS). The first and second outputs of amplifier circuit system 204 are coupled to amplifier circuit system 208, calibration circuit system 215, V2D circuit system 220, and pulse generator circuit system 225.

[0082] Amplifier circuit system 208 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first and second inputs of amplifier circuit system 208 are configured to couple to calibration controller circuit system 235, which provides a positive DAC signal and a negative DAC signal (DACP, DAM). The third and fourth inputs of amplifier circuit system 208 are coupled to calibration clock circuit system 404, which provides a V2V clock signal (CLK_V2V) and a bias clock signal (CLK_BIAS). The first and second outputs of amplifier circuit system 208 are coupled to amplifier circuit system 204, calibration circuit system 215, V2D circuit system 220, and pulse generator circuit system 225.

[0083] In some examples, clock circuit systems 402, 404 control amplifier circuit systems 204, 208 in response to control of the supply of a V2V clock signal (CLK_V2V). In some examples, for example in Figure 4In this configuration, clock circuit systems 402 and 404 are configured to control the operation of amplifier circuit systems 204 and 208 during either a calibration or non-calibration operation. In such an example, the V2V clock signal (CLK_V2V) of clock circuit system 402 enables amplifier circuit system 204 to perform a non-calibration operation, and the V2V clock signal (CLK_V2V) of clock circuit system 404 enables amplifier circuit system 208 to perform a calibration operation. For example, during a calibration operation, master clock circuit system 402 disables amplifier circuit system 204 by not supplying the V2V clock signal (CLK_V2V), and calibration clock circuit system 404 activates amplifier circuit system 208 by supplying the V2V clock signal (CLK_V2V). In another example, during non-calibration operation, master clock circuitry 402 activates amplifier circuitry 204 by supplying a V2V clock signal (CLK_V2V), and calibration clock circuitry 404 deactivates amplifier circuitry 208 by not supplying a V2V clock signal (CLK_V2V). In other examples, clock circuitry 402 and 404 may be partially or completely combined.

[0084] The calibration circuit system 215 has a first input, a second input, a third input, a first output, and a second output. The first and second inputs of the calibration circuit system 215 are coupled to a sampling circuit system 212, which provides a positive delay input signal and a negative delay input signal (IND). P IND M The third input of calibration circuit system 215 is coupled to clock circuit system 402, which provides a V2V clock signal (CLK_V2V). The first and second outputs of calibration circuit system 215 are coupled to amplifier circuit system 204, V2D circuit system 220, and pulse generator circuit system 225. Figure 6 Another example of the calibration circuit system 215 is further shown and described.

[0085] V2D circuit system 220 has a first input, a second input, a third input, and a fourth input. The first and second inputs of V2D circuit system 220 are coupled to amplifier circuit system 204, calibration circuit system 215, and pulse generator circuit system 225. The third and fourth inputs of V2D circuit system 220 are coupled to clock circuit system 402, which provides a reset clock signal (CLK_RESET) and a V2D clock signal (CLK_V2D).

[0086] The pulse generator circuit system 225 has a first input, a second input, a third input, a first output, and a second output. The first and second inputs of the pulse generator circuit system 225 are coupled to the amplifier circuit system 204, the calibration circuit system 215, and the V2D circuit system 220. The third input of the pulse generator circuit system 225 is coupled to the clock circuit system 402, which supplies a clock pulse reset signal (CLK_PULSE_RESET). The first and second outputs of the pulse generator circuit system 225 are configured to be coupled to... Figure 2 The TDC circuit system 230 receives positive pulses and negative pulses (PULSE_OUTP, PULSE_OUTM).

[0087] The master clock circuit system 402 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal (CLK_V2V) of the master clock circuit system 402 is coupled to the amplifier circuit system 204 and the calibration circuit system 215. The second terminal (CLK_BIAS) of the master clock circuit system 402 is coupled to the amplifier circuit system 204 and the calibration clock circuit system 404. The third and fourth terminals (CLK_RST, CLK_V2D) of the master clock circuit system 402 are coupled to the V2D circuit system 220 and the calibration clock circuit system 404. The fifth terminal (CLK_PULSE_RESET) of the master clock circuit system 402 is coupled to the pulse generator circuit system 225 and the calibration clock circuit system 404. The sixth terminal (EN_CALIB) of the master clock circuit system 402 is coupled to the calibration clock circuit system 404 and is configured to be coupled to the calibration controller circuit system 235. The calibration controller circuit system 235 provides a calibration enable signal (EN_CALIB) at the sixth terminal of the master clock circuit system 402.

[0088] The calibration clock circuit system 404 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal (CLK_V2V) of the calibration clock circuit system 404 is coupled to the amplifier circuit system 208 and the calibration circuit system 215. The second terminal (CLK_BIAS) of the calibration clock circuit system 404 is coupled to the amplifier circuit system 204 and the master clock circuit system 402. The third and fourth terminals (CLK_RST, CLK_V2D) of the calibration clock circuit system 404 are coupled to the V2D circuit system 220 and the master clock circuit system 402. The fifth terminal (CLK_PULSE_RESET) of the calibration clock circuit system 404 is coupled to the pulse generator circuit system 225 and the master clock circuit system 402. The sixth terminal (EN_CALIB) of the calibration clock circuit system 404 is coupled to the master clock circuit system 402 and is configured to be coupled to the calibration controller circuit system 235. The calibration controller circuitry 235 provides a calibration enable signal (EN_CALIB) at terminal six of the calibration clock circuitry 404. Combined with... Figure 5 Example operation of clock circuit systems 402 and 404 is shown and described.

[0089] Transistor 405 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 405 is coupled to transistor 406. The second terminal of transistor 405 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 405 is coupled to a reference terminal, which supplies a V2V bias voltage (NBIAS_V2V). The V2V bias voltage controls the current conduction through transistor 405. In some examples, the V2V bias voltage sets the operating region of transistor 406 in response to transistor 405 pulling down the source voltage of transistor 405. In some such examples, the V2V bias voltage is a constant voltage.

[0090] Transistor 406 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 406 is coupled to transistors 409 and 415. The second terminal of transistor 406 is coupled to transistor 405. The control terminal of transistor 406 is coupled to a master clock circuit system 402, which provides a bias clock signal (CLK_BIAS).

[0091] Transistor 409 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 409 is coupled to transistor 412. The second terminal of transistor 409 is coupled to transistors 406 and 415. The control terminal of transistor 409 is coupled to the first input of amplifier circuit system 204, which supplies a positive residual voltage (V). RESP ).

[0092] Transistor 412 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 412 is coupled to transistors 430, 445, 481, 484 and capacitors 457, 460. The second terminal of transistor 412 is coupled to transistor 409. The control terminal of transistor 412 is coupled to transistors 418, 430, 433 and a master clock circuit system 402, which supplies a V2V clock signal (CLK_V2V).

[0093] Transistor 415 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 415 is coupled to transistors 406 and 409. The second terminal of transistor 415 is coupled to transistor 418. The control terminal of transistor 415 is coupled to the second input of amplifier circuit system 421 and amplifier circuit system 204, the second input being supplied with a negative residual voltage (V). RESM ).

[0094] Transistor 418 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 418 is coupled to transistors 433, 442, 463, 466 and capacitors 451, 454. The second terminal of transistor 418 is coupled to transistor 415. The control terminal of transistor 418 is coupled to transistors 412, 430, 433 and a master clock circuit system 402, which provides a V2V clock signal (CLK_V2V).

[0095] Amplifier circuit system 421 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal. The first and second terminals of amplifier circuit system 421 are coupled to a first input of calibration circuit system 215, which supplies a positive delay input signal and a negative delay input signal (IND). P IND M The third, fourth, fifth, and sixth terminals of amplifier circuit system 421 are configured to couple to calibration controller circuit system 235. Calibration control circuit system 235 supplies a reference input common-mode voltage (V3) at the third, fourth, fifth, and sixth terminals of amplifier circuit system 421, respectively. INCM_REF Gain control signal (GAIN) CNTRL ), positive bias current selection signal (SEL) ICUR_P ) and negative bias current selection signal (SEL) ICUR_M The sixth terminal of amplifier circuit system 421 is coupled to transistors 424 and 427. Amplifier circuit system 421 is... Figure 2An example implementation of amplifier circuit system 240. In some examples, amplifier circuit system 421 includes additional terminals coupled to calibration controller circuit systems 170, 235. (In conjunction with...) Figure 6 Another example of amplifier circuit systems 240, 421 is further shown and described.

[0096] Transistor 424 has a first terminal, a second terminal, a control terminal, and a trimming input. The first terminal of transistor 424 is coupled to transistor 430. The second terminal of transistor 424 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 424 is coupled to amplifier circuitry 421 and transistor 427. The trimming input of transistor 424 is coupled to calibration controller circuitry 235. Calibration controller circuitry 235 provides a first gain trimming value (GAIN) at the trimming input of transistor 424. TRIM_T1 The first gain trim value controls the size of transistor 424 by setting at least one of the channel length or width.

[0097] Transistor 427 has a first terminal, a second terminal, a control terminal, and a trimming input. The first terminal of transistor 427 is coupled to transistor 433. The second terminal of transistor 427 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 427 is coupled to amplifier circuitry 421 and transistor 424. The trimming input of transistor 427 is coupled to calibration controller circuitry 235. Calibration controller circuitry 235 provides a second gain trimming value (GAIN) at the trimming input of transistor 427. TRIM_T2 The second gain trim value controls the size of transistor 427 by setting at least one of the channel length or width.

[0098] Transistor 430 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 430 is coupled to transistors 412, 481, and 484 and capacitors 457 and 460. The second terminal of transistor 430 is coupled to transistor 424. The control terminal of transistor 430 is coupled to transistors 412, 418, and 433 and clock circuit systems 402 and 404, which supply a V2V clock signal (CLK_V2V).

[0099] Transistor 433 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 433 is coupled to transistors 418, 463, 466 and capacitors 451, 454. The second terminal of transistor 433 is coupled to transistor 427. The control terminal of transistor 433 is coupled to transistors 412, 418, 430 and clock circuit systems 402, 404, which supply a V2V clock signal (CLK_V2V).

[0100] Transistor 436 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 436 is coupled to transistor 439. The second terminal of transistor 436 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 436 is coupled to a reference terminal, which supplies a V2D bias voltage (NBIAS_V2D). The V2D bias voltage controls the current conduction through transistor 436. In some examples, the V2D bias voltage sets the operating region of transistor 439 in response to transistor 436 pulling down the source voltage of transistor 439. In some such examples, the V2D bias voltage is a constant voltage.

[0101] Transistor 439 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 439 is coupled to transistor 448 and capacitors 451 and 457. The second terminal of transistor 439 is coupled to transistor 436. The control terminal of transistor 439 is coupled to clock circuit systems 402 and 404, which supply the V2D clock signal (CLK_V2D).

[0102] Transistor 442 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 442 is coupled to a power supply terminal, which supplies a power supply voltage (e.g., VDD, AVDD, etc.). The second terminal of transistor 442 is coupled to transistors 418, 433, 463, 466, and capacitors 451, 454. The control terminal of transistor 442 is coupled to transistors 445, 448, and clock circuit systems 402, 404, which supply a reset clock signal (CLK_RST).

[0103] Transistor 445 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 445 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 445 is coupled to transistors 412, 430, 481, 484 and capacitors 457, 460. The control terminal of transistor 445 is coupled to transistors 442, 448 and clock circuit system 402.

[0104] Transistor 448 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 448 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 448 is coupled to transistor 439 and capacitors 451 and 457. The control terminal of transistor 448 is coupled to transistors 442 and 445 and clock circuit system 402.

[0105] Capacitor 451 has a first terminal and a second terminal. The first terminal of capacitor 451 is coupled to transistors 418, 433, 463, 466 and capacitor 454. The second terminal of capacitor 451 is coupled to transistors 439, 448 and capacitor 457.

[0106] Capacitor 454 has a first terminal and a second terminal. The first terminal of capacitor 454 is coupled to transistors 418, 433, 463, 466 and capacitor 451. The second terminal of capacitor 454 is coupled to a common terminal, which supplies a common potential.

[0107] Capacitor 457 has a first terminal and a second terminal. The first terminal of capacitor 457 is coupled to transistors 412, 430, 445, 481, 484 and capacitor 460. The second terminal of capacitor 457 is coupled to transistors 439, 448 and capacitor 451.

[0108] Capacitor 460 has a first terminal and a second terminal. The first terminal of capacitor 460 is coupled to transistors 412, 430, 445, 481, 484 and capacitor 457. The second terminal of capacitor 460 is coupled to a common terminal, which supplies a common potential.

[0109] Transistor 463 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 463 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 463 is coupled to transistors 466 and 472. The control terminal of transistor 463 is coupled to transistors 418, 433, 466, and capacitors 451 and 454.

[0110] Transistor 466 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 466 is coupled to transistors 463 and 472. The second terminal of transistor 466 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 466 is coupled to transistors 418, 433, 463, and capacitors 451 and 454.

[0111] Transistor 469 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 469 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 469 is coupled to transistors 472, 475, and 478. The control terminal of transistor 469 is coupled to clock circuit systems 402 and 404, which supply a clock pulse reset signal (CLK_PULSE_RESET).

[0112] Transistor 472 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 472 is coupled to transistors 469, 475, and 478. The second terminal of transistor 472 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 472 is coupled to transistors 463 and 466.

[0113] Transistor 475 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 475 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 475 is coupled to transistor 478 and a second output of pulse generator circuit system 225, the second output supplying a negative delay signal (PULSE_OUTM). The control terminal of transistor 475 is coupled to transistors 469, 472, and 478.

[0114] Transistor 478 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 478 is coupled to transistor 475 and a second output of pulse generator circuit system 225, the second output supplying a negative delay signal. The second terminal of transistor 478 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 478 is coupled to transistors 469, 472, and 475.

[0115] Transistor 481 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 481 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 481 is coupled to transistors 484 and 490. The control terminal of transistor 481 is coupled to transistors 412, 430, 484, and capacitors 457 and 460.

[0116] Transistor 484 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 484 is coupled to transistors 481 and 490. The second terminal of transistor 484 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 484 is coupled to transistors 412, 430, 481, and capacitors 457 and 460.

[0117] Transistor 487 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 487 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 487 is coupled to transistors 490, 493, and 496. The control terminal of transistor 487 is coupled to clock circuit systems 402 and 404, which supply a clock pulse reset signal.

[0118] Transistor 490 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 490 is coupled to transistors 487, 493, and 496. The second terminal of transistor 490 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 490 is coupled to transistors 481 and 484.

[0119] Transistor 493 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 493 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 493 is coupled to transistor 496 and a first output of pulse generator circuit system 225, the first output supplying a positive delay signal. The control terminal of transistor 493 is coupled to transistors 487, 490, and 496.

[0120] Transistor 496 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 496 is coupled to transistor 493 and a first output of pulse generator circuit system 225, the first output supplying a positive delay signal. The second terminal of transistor 496 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 496 is coupled to transistors 487, 490, and 493.

[0121] exist Figure 4 In the examples, transistors 405, 406, 409, 412, 415, 418, 424, 427, 430, 433, 436, 439, 466, 472, 478, 484, 490, and 496 are n-channel MOSFETs. Alternatively, transistors 405, 406, 409, 412, 415, 418, 424, 427, 430, 433, 436, 439, 466, 472, 478, 484, 490, and 496 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or, with slight modifications, p-type equivalents. Figure 4In the example, transistors 442, 445, 448, 463, 469, 475, 481, 487, and 493 are p-channel MOSFETs. Alternatively, transistors 442, 445, 448, 463, 469, 475, 481, 487, and 493 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or, with slight modifications, N-type equivalent devices. Transistors 405, 406, 409, 412, 415, 418, 424, 427, 430, 433, 436, 439, 442, 445, 448, 463, 466, 469, 472, 475, 478, 481, 484, 487, 490, 493, and 496 can be depletion-type devices, extended-drain devices, enhancement-type devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 405, 406, 409, 412, 415, 418, 424, 427, 430, 433, 436, 439, 442, 445, 448, 463, 466, 469, 472, 475, 478, 481, 484, 487, 490, 493, and 496 can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0122] Example operation of amplifier circuitry 204, V2D circuitry 220, and pulse generator circuitry 225 is further illustrated and described in U.S. Patent Application No. 18 / 498,358, "Voltage-to-Delay Converter," which is incorporated herein by reference in its entirety and assigned to the assignee of this application. Figure 5 Example operation of amplifier circuit systems 204, 208, calibration circuit system 215, V2D circuit system 220, pulse generator circuit system 225, and clock circuit systems 402, 404 is shown and described.

[0123] Figure 5 yes Figure 4 Clock circuit systems 402, 404, or more generally Figure 2 Timing diagram 500 for example operation of the delayed ADC circuit system 200. Figure 5In the example, timing diagram 500 includes a reset clock signal 510 (CLK_RST), a bias clock signal 520 (CLK_BIAS), a V2V clock signal 530 (CLK_V2V), and a V2D clock signal 540 (CLK_V2D). In non-calibration operation, clock circuit system 402 generates a V2V clock signal 530 that controls amplifier circuit system 204. In calibration operation, clock circuit system 404 generates a V2V clock signal 530 that controls amplifier circuit system 208. In some examples, calibration controller circuit system 235 controls which of clock circuit systems 402, 404 generates the V2V clock signal 530 in response to an enable calibration signal (EN_CALIB). Advantageously, using amplifier circuit system 208 for calibration operations reduces the number of switching components along the main signal path (e.g., via the first and second inputs (V2V and V2D) of the delayed ADC circuit system 200 of pulse generator circuit system 225). RESP V RESM Advantageously, reducing the number of switching components along the main signal path reduces noise and improves the sound-to-noise ratio (SNR).

[0124] At a first time 550, the reset clock signal 510 has a rising edge, initiating the reset stage. During the reset stage, transistors 442, 445, and 448 charge capacitors 451, 454, 457, and 460 in response to the reset clock signal 510. At a second time 560, the reset clock signal 510 has a falling edge, ending the reset stage. At the second time 560, capacitors 451, 454, 457, and 460 are charged to the reset voltage. Furthermore, at the second time 560, the bias clock signal 520 has a rising edge, turning on (enabling, conducting current) transistor 406. Between the second time 560 and the third time 570, transistor 406 biases transistors 409 and 415 for conducting current. Advantageously, biasing transistors 409 and 415 before the third time 570 reduces the on-time of transistors 409 and 415 after the third time 570.

[0125] At the third time 570, transistors 412, 418, 430, and 433 conduct current in response to the V2V clock signal 530. Between the third time 570 and the fourth time 580, transistors 409, 412, and 430 conduct current based on the positive residual voltage (V RESP Capacitors 457 and 460 are discharged. Similarly, between the third time 570 and the fourth time 580, transistors 415, 418, and 433 discharge based on the negative residual voltage (V). RESM The capacitors 451 and 454 are then discharged. In some examples, the operation of discharging capacitors 451, 454, 457, and 460 may be referred to as integration.

[0126] Advantageously, the discharge rates of capacitors 451, 454, 457, and 460 are set by the magnitudes of the positive and negative residual voltages. However, during calibration operations, the corresponding transistors of amplifier circuitry 208 discharge capacitors 451, 454, 457, and 460 in response to the amplitudes of the positive and negative DAC signals (DACP, DAM). Advantageously, transistors 424, 427, 430, and 433 contribute to the discharge rates of capacitors 451, 454, 457, and 460. Advantageously, the currents of transistors 424, 427, 430, and 433 indicate voltage offset and gain. During calibration operations, calibration controller circuitry 235 constructs calibration circuitry 215 to set the currents of transistors 424, 427, 430, and 433. Figure 9 and 10 Further examples of such calibration operations are shown and described.

[0127] At the fifth time 585, the bias clock signal 520 has a falling edge, which turns off (disables, prevents current conduction) transistor 406. Between the fourth time 580 and the fifth time 585, the bias clock signal 520 allows the amplifier circuit system 204 to stabilize. At the sixth time 590, the V2D clock signal 540 has a rising edge to initiate the delayed transition. At the sixth time 590, transistor 439 turns on in response to the V2D clock signal 540. Between the sixth time 590 and the seventh time 595, transistors 436 and 439 discharge capacitors 451, 454, 457, and 460 at the same rate. Furthermore, between the sixth time 590 and the seventh time 595, the voltages of capacitors 451, 454, 457, and 460 exceed the threshold voltages of transistors 463, 466, 481, and 484. In response to the voltages of capacitors 451, 454, 457, and 460 dropping below a threshold voltage, transistors 463, 466, 481, and 484 generate falling edges on the positive and negative delayed signals (PULSE_OUTP and PULSE_OUTM). Advantageously, the time it takes for the voltages of capacitors 451, 454, 457, and 460 to cross the threshold voltage is based on the discharge rate between the third time 570 and the fourth time 580. Advantageously, the TDC circuit system 230 determines the digital value (TDC) in response to the delay between the positive and negative delayed signals. OUT ).

[0128] Figure 6 yes Figure 2 and 4 A schematic diagram of another example of the calibration circuit system 215. Figure 6 In the example, calibration circuit system 215 includes Figure 4 Amplifier circuit system 421 and Figure 4Transistors 424, 427, 430, and 433. Figure 6 The example amplifier circuit system 421 includes a first example transistor 605, a second example transistor 610, a first example current source circuit system 615, a third example transistor 620, a fourth example transistor 625, a fifth example transistor 630, a sixth example transistor 635, a seventh example transistor 640, an eighth example transistor 645, a second example current source circuit system 650, a ninth example transistor 655, a tenth example transistor 660, an eleventh example transistor 665, a third example current source circuit system 670, a first example switch 675, a second example switch 680, a third example switch 685, and a fourth example switch 690.

[0129] Figure 6 The amplifier circuit system 421 has a first input, a second input, a third input, a fourth input, a fifth input, a sixth input, a seventh input, an eighth input, a first output, and a second output. The first and second inputs of the amplifier circuit system 421 are configured to be coupled to... Figure 2 and 3 The sampling circuit system 212 provides a positive delay input signal and a negative delay input signal (IND). P IND M The third, fourth, fifth, sixth, seventh, and eighth inputs of the amplifier circuit system 421 are configured to couple to... Figure 2 The calibration controller circuit system 235 provides a reference input common-mode voltage (V). INCM_REF ), positive bias current selection signal (SEL) ICURR_P Inverting forward bias current selection signal (~SEL) ICURR_P ), negative bias current selection signal (SEL) ICURR_M Inverting negative bias current selection signal (~SEL) ICURR_M ) and gain control signal (GAIN) CNTRL ).exist Figure 6 In the example, the inverting forward bias current selection signal (~SEL) ICURR_P ) is the positive bias selection signal (SEL) at the fourth input of amplifier circuit system 421. ICURR_P An inverted version of the signal. In some examples, amplifier circuitry 421 may include a selection signal (SEL) from the positive bias current. ICURR_P Generates an inverting forward bias current selection signal (~SEL) ICURR_P Circuit systems such as inverters. Similarly, the inverting negative bias current selection signal (~SEL) ICURR_M ) is the negative bias selection signal (SEL) at the sixth input of amplifier circuit system 421.ICURR_M The inverted version of ). In some examples, amplifier circuitry 421 may include a selection signal (SEL) from the negative bias current. ICURR_M Generates an inverting negative bias current selection signal (~SEL) ICURR_M The amplifier circuit system 421 includes circuitry such as an inverter. A first output of the amplifier circuit system 421 is coupled to a transistor 424, which receives a positive correction current (ICURR_P). A second output of the amplifier circuit system 421 is coupled to a transistor 427, which receives a negative correction current (ICURR_M).

[0130] Transistor 605 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 605 is coupled to transistors 610 and 620 and current source circuit system 615. The second terminal of transistor 605 is coupled to transistors 610, 625, and 630. The control terminal of transistor 605 is coupled to the second input (IND) of amplifier circuit system 421. M ).

[0131] Transistor 610 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 610 is coupled to transistors 605 and 620 and current source circuit system 615. The second terminal of transistor 610 is coupled to transistors 625 and 630. The control terminal of transistor 610 is coupled to the first input (IND) of amplifier circuit system 421. P ).

[0132] The current source circuit system 615 has a first terminal, a second terminal, and a control input. The first terminal of the current source circuit system 615 is coupled to a power supply terminal, which supplies a supply voltage. The second terminal of the current source circuit system 615 is coupled to transistors 605, 610, and 620. In some examples, the current source circuit system 615 includes a control terminal that controls the amplitude of the current source circuit system 615. The control input of the current source circuit system 615 is coupled to the eighth input (GAIN) of the amplifier circuit system 421. CNTRL ).

[0133] Transistor 620 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 620 is coupled to transistors 605 and 610 and current source circuit system 615. The second terminal of transistor 620 is coupled to transistors 630, 635, and 645. The control terminal of transistor 620 is coupled to the third input (V) of amplifier circuit system 421. INCM_REF ).

[0134] Transistor 625 has a first terminal, a second terminal, and a control terminal. The first terminal and control terminal of transistor 625 are coupled to transistors 605, 610, and 630. The second terminal of transistor 625 is coupled to a common terminal, which supplies a common potential. Transistor 630 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 630 is coupled to transistors 620, 635, and 645. The second terminal of transistor 630 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 630 is coupled to transistors 605, 610, and 625. Figure 6 In the example, transistors 625 and 635 form a current mirror circuit system that mirrors the current passing through transistors 605 and 610 via transistor 630. Alternatively, transistors 625 and 630 can be replaced by alternative current mirror circuit systems.

[0135] Transistor 635 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 635 is coupled to transistors 620, 630, and 645. The second terminal of transistor 635 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 635 is coupled to transistor 630 and switches 675 and 685.

[0136] Transistor 640 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 640 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 640 is coupled to transistor 635 and switches 675 and 685. The control terminal of transistor 640 is coupled to transistor 645 and current source circuit system 650.

[0137] Transistor 645 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 645 is coupled to transistor 640 and current source circuit system 650. The second terminal of transistor 645 is coupled to transistors 620, 630, and 635. The control terminal of transistor 645 is coupled to a bias terminal, which supplies a bias voltage (BIAS). In some examples, the bias voltage biases the conduction of transistor 645. In some such examples, transistor 645 is a drain-extended transistor.

[0138] The current source circuit system 650 has a first terminal and a second terminal. The first terminal of the current source circuit system 650 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the current source circuit system 650 is coupled to transistors 640 and 645.

[0139] Transistor 655 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 655 is coupled to transistor 665. The second terminal of transistor 655 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 655 is coupled to transistor 660 and switches 680 and 690.

[0140] Transistor 660 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 660 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 660 is coupled to transistor 655 and switches 680 and 690. The control terminal of transistor 660 is coupled to transistor 665 and current source circuit system 670.

[0141] Transistor 665 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 665 is coupled to transistor 660 and current source circuit system 670. The second terminal of transistor 665 is coupled to transistor 655. The control terminal of transistor 665 is coupled to a bias terminal, which supplies a bias voltage. In some such examples, transistor 665 is a drain-extended transistor.

[0142] The current source circuit system 670 has a first terminal and a second terminal. The first terminal of the current source circuit system 670 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the current source circuit system 670 is coupled to transistors 660 and 665.

[0143] Switch 675 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 675 is coupled to transistors 635 and 640 and switch 685. The second terminal of switch 675 is coupled to transistor 424 and switch 680. The control terminal of switch 675 is coupled to the fourth input (SEL) of amplifier circuit system 421. ICURR_P ).

[0144] Switch 680 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 680 is coupled to transistors 655 and 660 and switch 690. The second terminal of switch 680 is coupled to transistor 424 and switch 675. The control terminal of switch 680 is coupled to the fifth input (~SEL) of amplifier circuit system 421. ICURR_P ).

[0145] Switch 685 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 685 is coupled to transistors 635 and 640 and switch 675. The second terminal of switch 685 is coupled to transistor 427 and switch 690. The control terminal of switch 685 is coupled to the sixth input (SEL) of amplifier circuit system 421. ICURR_M ).

[0146] Switch 690 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 690 is coupled to transistors 655 and 660 and switch 680. The second terminal of switch 690 is coupled to transistor 427 and switch 685. The control terminal of switch 690 is coupled to the seventh input (~SEL) of amplifier circuit system 421. ICURR_M ).

[0147] exist Figure 6 In the examples, transistors 424, 427, 430, 433, 625, 630, 635, 640, 645, 655, 660, and 665 are n-channel MOSFETs. Alternatively, transistors 424, 427, 430, 433, 625, 630, 635, 640, 645, 655, 660, and 665 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or, with slight modifications, p-type equivalents. Figure 6 In the examples, transistors 605, 610, and 620 are p-channel MOSFETs. Alternatively, transistors 605, 610, and 620 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or, with slight modifications, N-type equivalent devices. Transistors 424, 427, 430, 433, 605, 610, 620, 625, 630, 635, 640, 645, 655, 660, and 665 may be depletion-mode devices, extended-drain devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 424, 427, 430, 433, 605, 610, 620, 625, 630, 635, 640, 645, 655, 660, and 665 can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0148] In the example operation, transistors 605 and 610 are configured to each have a first width (W), and transistor 620 is configured to have a second width (2W), which is twice the width of the first width. In such examples, the first width and the second width correspond to the channel width or more generally to the size of transistors 605, 610, and 620. Advantageously, setting the sizes of transistors 605 and 610 to be equal will configure transistors 605 and 610 to support positively delayed input signals and negatively delayed input signals (IND) representing the input common-mode voltage. P IND MThe average is then calculated. Advantageously, setting the size of transistors 605 and 610 to half the size of transistor 620 will configure transistors 605, 610, and 620 to be equal to the ratio of the input common-mode voltage to the reference input common-mode voltage from the calibration controller circuitry 235.

[0149] In this type of example operation, transistors 605, 610, and 620 are based on the input common-mode voltage and the reference input common-mode voltage (V). INCM_REF The current is routed from the current source circuit system 615 according to the ratio of the input common-mode voltage of the positive delay input and the negative delay input. For example, if the input common-mode voltage of the positive delay input and the negative delay input is equal to the reference input common-mode voltage, then transistors 605 and 610 conduct the first half of the current of the current source circuit system 615, and transistor 620 conducts the second half of the current of the current source circuit system 615. In another example, transistor 620 conducts more current than transistors 605 and 610 combined in response to the input common-mode voltage being less than the reference input common-mode voltage. Advantageously, amplifier circuit system 421 generates an output in response to the difference between the input common-mode voltage from sampling circuit system 212 and the reference input common-mode voltage from calibration controller circuit system 235. Figure 9 and 10 Example operation of amplifier circuit system 421 is further shown and described.

[0150] Figure 7 yes Figure 1 A block diagram of an example implementation of the calibration controller circuit system 170, which includes Figure 2 The calibration controller circuit system 235. Figure 7 The calibration controller circuitry 170 can be instantiated (e.g., instantiated, generated, materialized, implemented, etc.) by a programmable circuitry system such as a central processing unit (CPU) that executes first instructions. Alternatively, Figure 7 The calibration controller circuit system 170 can be instantiated (e.g., instantiated, generated, materialized, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) or (ii) a field-programmable gate array (FPGA) that is constructed or configured to perform an operation corresponding to the first instruction in response to the execution of the second instruction. Therefore, Figure 7 Some or all of the circuit systems can be instantiated at the same or different times. Figure 7 Some or all of the circuit system can be instantiated, for example, in one or more threads that are implemented simultaneously or in series on the hardware. Furthermore, in some examples, Figure 7 Some or all of the circuitry in the system can be implemented by a microprocessor circuitry that executes instructions or by an FPGA circuitry that performs operations to implement one or more virtual machines or containers.

[0151] exist Figure 7 In the example, calibration controller circuitry 170 includes calibration controller circuitry 235 (which may be specifically designed for...) Figure 2 The delay ADC circuit system 200) and the second calibration controller circuit system 705. In some examples, the calibration controller circuit system 170 may include any number of instances of the calibration controller circuit system 235 to support any number of delay ADC circuit systems, such as Figure 1 The delayed ADC circuit system is 155, 160, 165. Figure 7 The example calibration controller circuit system 235 includes an example sorting circuit system 710, an example offset correction circuit system 715, an example gain correction circuit system 720, an example DAC circuit system 725, an example DAC code circuit system 730, and an example DAC common-mode code circuit system 735. Figure 7 The example offset correction circuit system 715 includes an example offset controller circuit system 740, an example reference generation circuit system 745, an example comparator circuit system 750, a first example offset correction circuit system 755, a second example offset correction circuit system 760, and an example total offset correction circuit system 765. Figure 7 The example gain correction circuit system 720 includes an example gain controller circuit system 770, an example positive DAC code circuit system 775, an example negative DAC code circuit system 780, an example minimum DAC code circuit system 785, and an example gain correction circuit system 790. The calibration controller circuit system 170 is configured to be coupled to... Figure 2 and 3 Sampling circuit system 212, Figure 2 , 4 The calibration circuit system 215 and 6 Figure 2 The TDC circuit system 230.

[0152] The calibration controller circuit system 235 has an input, a first output, a second output, a third output, a fourth output, a fifth output, a sixth output, a seventh output, an eighth output, a ninth output, a tenth output, an eleventh output, and a twelfth output. The input of the calibration controller circuit system 235 is coupled to... Figure 2 The TDC circuit system 230. The TDC circuit system 230 provides digital values ​​(TDC). OUT The first, second, and third outputs of the calibration controller circuit system 235 provide the input control signal (INP_CNTRL), the inverting input control signal (INP_CNTRL_Z), and the calibration control signal (CALIB_CNTRL). The fourth and fifth outputs of the calibration controller circuit system 235 provide the positive DAC signal and the negative DAC signal (DACP, DAM) to... Figure 2 The amplifier circuit system 208 and the sampling circuit system 212. The sixth, seventh, eighth, ninth, tenth, and eleventh outputs of the calibration controller circuit system 235 are directed to... Figure 2 , 4 The calibration circuit system 215 of the 6 provides a reference input common-mode voltage (V). INCM_REF Gain control signal (GAIN) CNTRL ), positive bias current selection signal (SEL) ICUR_P ), negative bias current selection signal (SEL) ICUR_M ), first gain trim value (GAIN) TRIM_T1 ) and second gain trim value (GAIN) TRIM_T2 The twelfth output of the calibration controller circuit system 235 provides the calibration enable signal (EN_CALIB) to... Figure 4 The clock circuit systems 402 and 404.

[0153] The calibration controller circuit system 705 has inputs and outputs. The inputs of the calibration controller circuit system 705 are configured to be coupled to... Figure 2 The TDC circuitry of subsequent instances of the delayed ADC circuitry system 200 (such as delayed ADC circuitry systems 160, 165). The output of the calibration controller circuitry system 705 is configured to be similar to the output of the calibration controller circuitry system 705 and is configured to be coupled to the subsequent instances of the delayed ADC circuitry system 200. Figure 7 In one example, the calibration controller circuit system 235 comprises multiple instances of the calibration controller circuit system 235. In other examples, the calibration controller circuit system 235 may comprise any number of instances of the calibration controller circuit system 235. In some examples, the calibration controller circuit system 705 is instantiated by an application-specific integrated circuit system or a programmable circuit system that implements delayed ADC calibration instructions to perform operations, such as by... Figure 8 , 9 The operations represented by the flowcharts for 10 and 10.

[0154] The sorting circuit system 710 has a first output, a second output, a third output, and a fourth output. The first output of the sorting circuit system 710 provides an input control signal (INP_CNTRL) to the sampling circuit system 212. The second output of the sorting circuit system 710 provides a calibration enable signal (CALIB_EN) to the clock circuit systems 402 and 404. The third output of the sorting circuit system 710 is coupled to an offset correction circuit system 715 and provides an enable offset calibration signal (EN_OFF_CAL). The fourth output of the sorting circuit system 710 is coupled to a gain correction circuit system 720 and provides an enable gain calibration signal (EN_GAIN_CAL). In some examples, the sorting circuit system 710 is instantiated by an application-specific integrated circuit (ASIC) system or a programmable circuit system that implements sorting instructions to perform operations, such as those by... Figure 8 , 9 The operations represented by the flowcharts for 10 and 10.

[0155] The offset correction circuit system 715 has a first input, a second input, a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. The first input of the offset correction circuit system 715 is coupled to the input of the calibration controller circuit system 235, which provides a digital value (TDC). OUT The second input of the offset correction circuit system 715 is coupled to the sorting circuit system 710. The first output of the offset correction circuit system 715 provides the calibration control signal (CAL_CNTRL) to the sampling circuit system 212. The second, third, and fourth outputs of the offset correction circuit system 715 provide a reference input common-mode voltage (V) to the calibration circuit system 215. INCM_REF ), positive bias current selection signal (SEL) ICUR_P ) and negative bias current selection signal (SEL) ICUR_M The fifth output of the offset correction circuit system 715 is coupled to the DAC code circuit system 730. The sixth output of the offset correction circuit system 715 is coupled to the DAC common-mode code circuit system 735. In some examples, the offset correction circuit system 715 is instantiated by an application-specific integrated circuit system or a programmable circuit system that implements offset correction instructions to perform operations, such as by... Figure 8 and 9 The flowchart represents those operations.

[0156] Gain correction circuit system 720 has a first input, a second input, a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. The first input of gain correction circuit system 715 is coupled to the input of calibration controller circuit system 235, the input of which provides a digital value (TDC). OUT The second input of the gain correction circuit system 720 is coupled to the sorting circuit system 710. The first output of the gain correction circuit system 720 provides the calibration control signal (CAL_CNTRL) to the sampling circuit system 212. The second, third, and fourth outputs of the gain correction circuit system 720 transmit the gain control signal (GAIN) to the sampling circuit system 212. CNTRL ), first gain trim value (GAIN) TRIM_T1 ) and second gain trim value (GAIN) TRIM_T2 The fifth output of the gain correction circuit system 720 is coupled to the DAC code circuit system 730. The sixth output of the gain correction circuit system 720 is coupled to the DAC common-mode code circuit system 735. In some examples, the gain correction circuit system 720 is instantiated by an application-specific integrated circuit system or a programmable circuit system that implements gain correction instructions to perform operations, such as those provided by... Figure 8 and 10 The flowchart represents those operations.

[0157] DAC circuit system 725 has a first input, a second input, a first output, and a second output. The first input of DAC circuit system 725 is coupled to DAC code circuit system 730. The second input of DAC circuit system 725 is coupled to DAC common-mode code circuit system 735. The first output of DAC circuit system 725 provides a positive DAC signal (DACP) to amplifier circuit system 208 and sampling circuit system 212. The second output of DAC circuit system 725 provides a negative DAC signal (DACM) to amplifier circuit system 208 and sampling circuit system 212. In some examples, DAC circuit system 725 is instantiated by an application-specific integrated circuit (ASIC) system or a programmable circuit system that implements gain controller instructions to perform operations, such as those provided by... Figure 8 and 10 The flowchart represents those operations.

[0158] The DAC code circuit system 730 has inputs and outputs. The inputs of the DAC code circuit system 730 are coupled to an offset correction circuit system 715 and a gain correction circuit system 720. The outputs of the DAC code circuit system 730 are coupled to a DAC circuit system 725. In some examples, the DAC code circuit system 730 is instantiated by an application-specific integrated circuit (ASIC) system or a programmable circuit system that implements gain control instructions to perform operations, such as those generated by... Figure 8 and 10 The flowchart represents those operations.

[0159] The DAC common-mode code circuit system 735 has inputs and outputs. The inputs of the DAC common-mode code circuit system 735 are coupled to offset correction circuit system 715 and gain correction circuit system 720. The outputs of the DAC common-mode code circuit system 735 are coupled to DAC circuit system 725. In some examples, the DAC common-mode code circuit system 735 is instantiated by an application-specific integrated circuit (ASIC) system or a programmable circuit system that implements gain controller instructions to perform operations, such as those by... Figure 8 and 10 The flowchart represents those operations.

[0160] The offset controller circuit system 740 has an input, a first output, a second output, a third output, a fourth output, a fifth output, a sixth output, a seventh output, an eighth output, and a ninth output. The input of the offset controller circuit system 740 is coupled to a comparator circuit system 750. The first output of the offset controller circuit system 740 provides a calibration control signal (CAL_CNTRL) to the sampling circuit system 212. The second and third outputs of the offset controller circuit system 740 provide a positive bias current selection signal (SEL). ICUR_P ) and negative bias current selection signal (SEL) ICUR_M The offset controller circuit system 740 is provided to calibration circuit system 215. The fourth output of the offset controller circuit system 740 is coupled to DAC code circuit system 730. The fifth output of the offset controller circuit system 740 is coupled to DAC common-mode code circuit system 735. The sixth output of the offset controller circuit system 740 is coupled to reference generation circuit system 745. The seventh output of the offset controller circuit system 740 is coupled to offset correction circuit system 755. The eighth output of the offset controller circuit system 740 is coupled to offset correction circuit system 760. The ninth output of the offset controller circuit system 740 is coupled to total offset correction circuit system 765. In some examples, the offset controller circuit system 740 is instantiated by an application-specific integrated circuit system (ASIC) or a programmable circuit system (Programmable Circuit System), which implements offset controller instructions to perform operations, such as those by... Figure 8 and 9The flowchart represents those operations.

[0161] The reference generation circuit system 745 has inputs and outputs. The inputs of the reference generation circuit system 745 are coupled to the offset controller circuit system 740. The output of the reference generation circuit system 745 references the input common-mode voltage (V). INCM_REF This is provided to the calibration circuit system 215. In some examples, the reference generation circuit system 745 is implemented using a DAC circuit system that sets the reference input common-mode voltage in response to DAC code from the offset controller circuit system 740. In some examples, the reference generation circuit system 745 is instantiated by an application-specific integrated circuit (ASIC) system or a programmable circuit system that implements reference generation instructions to perform operations, such as those provided by... Figure 8 and 9 The flowchart represents those operations.

[0162] The comparator circuit system 750 has inputs and outputs. The input of the comparator circuit system 750 is coupled to the input of the calibration controller circuit system 235, which provides a digital value (TDC). OUT The output of comparator circuit system 750 is coupled to offset controller circuit system 740. In some examples, comparator circuit system 750 is instantiated by application-specific integrated circuit system or programmable circuit system, which implements comparator instructions to perform operations, such as those by... Figure 8 and 9 The flowchart represents those operations.

[0163] Offset correction circuit system 755 has inputs and outputs coupled to offset controller circuit system 740. Offset correction circuit system 760 has inputs and outputs coupled to offset controller circuit system 740. Total offset correction circuit system 765 has inputs and outputs. The input of total offset correction circuit system 765 is coupled to offset controller circuit system 740. The output of total offset correction circuit system 765 is coupled to offset controller circuit system 740. Offset correction circuit systems 755, 760, and 765 store reference offset values. Combined with... Figure 8 and 9 The flowchart illustrates the operation further by providing an example of the reference offset value.

[0164] The gain controller circuit system 770 has an input, a first output, a second output, a third output, a fourth output, a fifth output, a sixth output, a seventh output, an eighth output, a ninth output, and a tenth output. The inputs of the gain controller circuit system 770 are coupled to the inputs of the calibration controller circuit system 235, which provides a digital value (TDC). OUTThe first output of the gain controller circuit system 770 provides the calibration control signal (CALIB_CNTRL) to the sampling circuit system 212. The second, third, and fourth outputs of the gain controller circuit system 770 transmit the gain control signal (GAIN) to the sampling circuit system 212. CNTRL ), first gain trim value (GAIN) TRIM_T1 ) and second gain trim value (GAIN) TRIM_T2 The gain controller circuit system 770 is provided to calibration circuit system 215. The fifth output of gain controller circuit system 770 is coupled to DAC code circuit system 730. The sixth output of gain controller circuit system 770 is coupled to DAC common-mode code circuit system 735. The seventh output of gain controller circuit system 770 is coupled to positive DAC code circuit system 775. The eighth output of gain controller circuit system 770 is coupled to negative DAC code circuit system 780. The ninth output of gain controller circuit system 770 is coupled to minimum DAC code circuit system 785. The tenth output of gain controller circuit system 770 is coupled to gain correction circuit system 790. In some examples, gain controller circuit system 770 is instantiated by an application-specific integrated circuit system or a programmable circuit system that implements gain controller instructions to perform operations, such as those provided by... Figure 8 and 10 The flowchart represents those operations.

[0165] A positive DAC code circuit system 775 has inputs and outputs coupled to a gain controller circuit system 770. A negative DAC code circuit system 780 has inputs and outputs coupled to a gain controller circuit system 770. A minimum DAC code circuit system 785 has inputs and outputs coupled to a gain controller circuit system 770. A gain correction circuit system 790 has inputs and outputs. The input of the gain correction circuit system 790 is coupled to the gain controller circuit system 770. The output of the gain correction circuit system 790 is coupled to the gain controller circuit system 770. DAC code circuit systems 775, 780, 785 and gain correction circuit system 790 store a reference gain value. Figure 8 and 10 The flowchart illustrates an example of the operation for the reference gain value.

[0166] Figure 8 This indicates that it can be used. Figure 1 and 2 Delayed ADC circuit systems 155, 160, 165, 200 and Figure 1 , 2 The calibration controller circuitry system 170, 235 or more generally 7 Figure 1 Delay-domain ADC circuit systems 150 or even more generally Figure 1The flowchart illustrates an example implementation of an ADC circuit system 100, which is used to demonstrate at least one of the example machine-readable instructions or example operations 800 in the implementation, instantiation, or execution of the system.

[0167] Figure 8 Example operation 800 begins at block 805, where ADC circuitry 100 receives an analog input. In this example operation, ADC circuitry 100 receives the analog input in response to clock circuitry 145 closing switches 105 and 115. In this type of example operation, the analog input charges capacitors 110 and 120, which store the analog value after a first duration. After the first duration, capacitors 110 and 120 store the analog input, and clock circuitry 145 opens switches 105 and 115. In some examples, ADC circuitry 100 buffers the analog input before capacitors 110 and 120. In such examples, buffering the analog input before capacitors 110 and 120 increases the drive strength of the analog input.

[0168] Figure 1 The ADC 125 produces a first digital value (DOUT0) as an approximation of the analog input (Box 810). In example operation, the ADC 125 produces a relatively low-resolution digital representation of the analog input at capacitors 110, 120. In this type of example operation, the digital output (DOUT0) of the ADC 125 represents a relatively low-resolution (also known as an approximation) representation of the analog input in digital form.

[0169] Figure 1 The CDAC 130 generates a residual as the difference between an approximation and the actual analog input (Box 815). In example operation, the CDAC 130 generates an approximate analog value in response to the digital output from the ADC 125. In such example operation, the CDAC 130 differentially applies the approximate analog value to a first side of a capacitor circuit system, which is also coupled to the analog input of capacitors 110 and 120 via switches 135 and 140. In such an example, the CDAC 130 sets the voltage across capacitors 110 and 120 as a residual voltage. Advantageously, the voltage difference across capacitors 110 and 120 represents the difference between the analog input and the approximate analog value of the CDAC 130. The CDAC 130 sets the residual voltage (V... RES ) is supplied to the delay domain ADC circuit system 150.

[0170] Figure 1 The delay-domain ADC circuitry 150 uses the delayed ADC to generate a second digital value (DOUT1) of the residual (Box 820). In example operation, the calibration controller circuitry 170 is enabled in response to the calibration enable signal (EN_CALIB). Figure 4 The master clock circuit system 402 activates one of the delayed ADC circuit systems 155, 160, and 165. For example, ADC circuit system 155 generates a second digital value (DOUT1) in response to the calibration controller circuit system 170 activating the master clock circuit system 402 of ADC circuit system 155. In such example operation, amplifier circuit system 204, V2D circuit system 220, and pulse generator circuit system 225 convert the residual voltage into a delay between the rising edges of two signals. In some examples, such as delayed ADC circuit system 200, pulse generator circuit system 225 generates two signals with falling edges timed based on the residual voltage. For example, the delay between the edges of the first and second delayed signals from pulse generator circuit system 225 increases as the analog value of the residual voltage increases. Similarly, the delay between the first and second delayed signals (PULSE_OUTP, PULSE_OUTM) from pulse generator circuit system 225 decreases as the analog value of the residual voltage decreases. The TDC circuit system 230 generates a digital output in response to comparing the delay between delayed signals with a reference delay. For example, the TDC circuit system 230 sets the first bit to logic one in response to determining that the delay between the edges of the delayed signals is greater than a first reference delay. Similarly, the TDC sets the second bit to logic zero in response to determining that the remaining delay between the falling edges of the delayed signals is less than a second reference delay. Advantageously, the TDC circuit system 230 produces a digital output representing the delay between delayed signals from the pulse generator circuit system 225.

[0171] ADC circuitry 100 represents the analog input using a first digital value and a second digital value (Box 825). In example operation, ADC circuitry 100 uses bits from the digital output of ADC 125 and bits from the digital output of delayed ADC circuitry 155 to produce a digital output representing the analog input. In some examples, ADC circuitry 100 may include at least one of latching, alignment, combining, or correction circuitry to logically combine the digital outputs of ADC 125 and delayed-domain ADC circuitry 150. In some such examples, additional circuitry may account for differences between the digital outputs caused by gain, delay, etc.

[0172] The calibration controller circuitry 170, 235 determines whether the delayed ADC circuitry 155 needs to be calibrated (Box 830). In example operation, the calibration controller circuitry 170, 235 may include, for example... Figure 7The sequencing circuit system 710 and other circuit systems are used to sequence the calibration of at least one of the delayed ADC circuit systems 155, 160, and 165. In such examples, the calibration controller circuit systems 170 and 235 may calibrate one of the delayed ADC circuit systems 155, 160, and 165 in response to at least one of periodic intervals, fault detection, or completion of calibration of different delayed ADCs. If the calibration controller circuit systems 170 and 235 determine that the active delayed ADC should not be calibrated (e.g., block 830 returns a negative result), then control proceeds back to block 805.

[0173] If calibration controller circuitry 170, 235 determines that the active delayed ADC needs calibration (e.g., box 830 returns a yes result), then calibration controller circuitry 170, 235 disconnects delayed ADC circuitry 155 (box 835). In example operation, calibration controller circuitry 170, 235 adjusts the calibration enable signal (EN_CALIB) to disable master clock circuitry 402 and enable calibration clock circuitry 404. In this example operation, calibration clock circuitry 404 provides a V2V clock signal (CLK_V2V) to... Figure 2 and 4 The amplifier circuit system 208, and the master clock circuit system 402 stop providing the V2V clock signal (CLK_V2V) to... Figure 2 and 4 The amplifier circuit system 204. Advantageously, the calibration controller circuit systems 170, 235 can use the calibration enable signal (EN_CALIB) to connect the delayed ADC circuit system 200 with the positive residual voltage and the negative residual voltage (V). RESP V RESM Disconnect. Advantageously, the amplifier circuit system 208 receives signals from [unclear - possibly a source] during calibration operations. Figure 7 The input of the DAC circuit system 725.

[0174] In some examples, as shown by the dashed outline, the calibration controller circuitry 170, 235 activates another delayed ADC to produce a subsequent second digital value (box 840). In some examples, such as in... Figure 1 In this example, the delay domain ADC circuitry 150 includes multiple instances of delay ADC circuitry 155, 160, and 165. In such examples, calibration controller circuitry 170 and 235 can activate one of the delay ADC circuitry 160 and 165 to continue providing digital output during calibration of the delay ADC circuitry 155.

[0175] In some examples, as shown by the dashed outline, calibration Figure 2The TDC circuit system 230 (box 845). In some example operations, calibrating the TDC circuit system 230 before calibrating the delayed ADC circuit system 200 improves the accuracy of the calibration operation.

[0176] Figure 7 The offset correction circuit system 715 calibrates the common-mode offset. Figure 9 Operation 900). In example operation, the offset correction circuitry 715 determines the common-mode voltage offset added by the amplifier circuitry 204, the V2D circuitry 220, and the pulse generator circuitry 225 in response to performing operation 900. In this type of example operation, the offset correction value is adjusted by adjusting the reference input common-mode voltage (V2D). INCM_REF To account for common-mode voltage offset. Advantageously, Figure 2 , 4 The calibration circuit system 215 of 6 can take into account the common-mode voltage offset by adjusting the reference input common-mode voltage of the calibration circuit system 215. Combined with Figure 9 Further operation of the offset correction circuit system 715 is shown and described. Advantageously, the calibration circuit system 215 reduces the common-mode voltage offset in response to adjusting the reference input common-mode voltage.

[0177] Figure 7 The gain correction circuit system 720 calibrates the common-mode gain. Figure 10 (Operation 1000). In some examples, the gain of the common-mode voltage across the delayed ADC circuitry 200 depends on the magnitude of the common-mode voltage. For example, a relatively small common-mode voltage (e.g., close to the common potential) may have a relatively high gain, and a relatively large common-mode voltage (e.g., close to the supply voltage) may have a relatively small gain. In such examples, the gain correction circuitry 720 scans a series of common-mode voltages to determine the common-mode voltage with the lowest gain. The gain correction circuitry 720 sets the gain of the calibration circuitry 215 in response to determining the common-mode voltage with the lowest gain. Advantageously, setting the gain of the calibration circuitry 215 based on the lowest common-mode gain improves CMRR. Figure 10 Further operation of the gain correction circuit system 720 is shown and described. Control proceeds to return to block 805.

[0178] refer to Figure 8 The flowchart shown illustrates the example method. However, implementation details may also be used in this specification. Figure 1 and 2 Delayed ADC circuit systems 155, 160, 165, 200 and Figure 1 , 2 And the calibration controller circuitry system 170, 235 or more generally. Figure 1 Delay domain ADC circuit system 150 or even more generally Figure 1 Many other methods exist for the ADC circuit system 100. For example, the execution order of the blocks can be changed, or some of the described blocks can be altered, eliminated, or combined. Similarly, additional operations may be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0179] Figure 9 This indicates that it can be used. Figure 2 , 4 The calibration circuit system of 6, 215, Figure 7 The offset correction circuit system 715 or more generally Figure 1 and 2 Delayed ADC circuit systems 155, 160, 165, 200 and Figure 1 , 2 The flowchart of example machine-readable instructions or example operations 900 for implementing, instantiating, or performing at least one of the example implementations of the calibration controller circuitry systems 170 and 235 of 7.

[0180] Figure 9 Example operation 900 begins at block 905, where the offset correction circuitry 715 initializes the calibration DAC. In example operation, the offset correction circuitry 715 will... Figure 7 DAC code circuit system 730 and Figure 7 The values ​​of the DAC common-mode code circuitry system 735 are set to initial values. In some examples, Figure 7 The DAC circuit system 725 sets the positive and negative DAC signals (DACP, DAM) to initial values ​​in response to the values ​​of the DAC code circuit system 730 and the DAC common-mode code circuit system 735. In some such examples, the DAC circuit system 725 initializes the positive and negative DAC signals (DACP, DAM) to have differential voltages that are approximately equal to zero (e.g., the positive and negative DAC signals (DACP, DAM) are equal). In such example operation, the offset correction circuit system 715 adjusts the calibration control signal (CAL_CNTRL) to close. Figure 3 Switches 315 and 320. In response to closing switches 315 and 320, sampling circuitry 212 provides positive and negative DAC signals (DACP, DAM) to calibration circuitry 215. In this example, in response to closing switches 315 and 320, the positive and negative input signals (IND) of switching circuitry 212 are... P IND M It is roughly equal to the positive DAC signal and the negative DAC signal (DACP, DAM).

[0181] Figure 2 and3 The amplifier circuitry 240, 421 drives the positive-side calibration transistor with a correction bias (Box 910). In example operation, the offset controller circuitry 740 uses a positive bias current selection signal and a negative bias current selection signal (SEL). ICURR_P SEL ICURR_M To control the direction Figure 4 and 6 Transistors 424 and 427 supply CMRR correction bias (CMRR_CORR_BIAS). Transistors 635 and 640 generate CMRR correction bias in response to the current in the current source circuit system 650 and the current in transistor 630. In this example operation, Figure 6 The switch 675 responds to the offset controller circuitry 740 by setting a positive bias current selection signal (SEL). ICURR_P A CMRR correction bias is supplied to transistor 424. The CMRR correction bias is a control signal set in response to the difference in current conduction by transistors 605, 610, and 620. Advantageously, the CMRR correction bias is based on the difference between the input common-mode voltage at the input of amplifier circuit system 204 and the reference input common-mode voltage from calibration controller circuit system 235.

[0182] Amplifier circuitry 240, 421 drives the negative-side calibration transistor with a calibration bias (Box 915). In example operation, offset controller circuitry 740 uses a positive bias current selection signal and a negative bias current selection signal (SEL). ICURR_P SEL ICURR_M This controls the supply of CMRR calibration bias (CMRR_CALIB_BIAS) to transistors 424 and 427. Transistors 655 and 660 generate the CMRR calibration bias in response to the current in the current source circuit system 670 and the current in transistor 655. In this example operation, Figure 6 Switch 690 responds to offset controller circuitry 740 to clear the negative bias current selection signal (SEL). ICURR_M Or set the inverting negative bias current selection signal (~SEL) ICURR_M A CMRR calibration bias is supplied to transistor 427. The CMRR calibration bias is a control signal that serves as a fixed bias signal. Unlike the CMRR correction bias, the CMRR calibration bias does not change in response to variations in the common-mode voltage at the inputs of amplifier circuit systems 240 and 421. Advantageously, the CMRR calibration bias provides a fixed reference bias independent of the voltage at the inputs of amplifier circuit systems 240 and 421.

[0183] Figure 7The reference generation circuit system 745 sets the reference common-mode voltage (Box 920). In example operation, the reference generation circuit system 745 sets the reference input common-mode voltage (V). INCM_REF The reference input common-mode voltage is set as the initial voltage, which represents the target common-mode voltage. For example, if the inputs of amplifier circuit system 204 are equal, then reference generation circuit system 745 sets the reference input common-mode voltage to zero volts.

[0184] Figure 7 The comparator circuit system 750 determines whether the TDC output is zero (box 925). In example operation, the amplifier circuit system 208, V2D circuit system 220, and pulse generator circuit system 225 generate positive and negative delay signals (PULSE_OUTP, PULSE_OUTM) in response to the input voltage of the amplifier circuit system 204 and the current from the calibration circuit system 215. In this example operation, the TDC circuit system 230 outputs a digital value representing the delay between the positive and negative delay signals (PULSE_OUTP, PULSE_OUTM). The comparator circuit system 750 compares the digital value from the TDC circuit system 230 with a target output of zero. Advantageously, if the inputs to the amplifier circuit system 204 are equal, the digital value at the output of the TDC circuit system 230 represents the offset of the calibration circuit system 215. Advantageously, the CMRR correction bias control transistor 424 and the CMRR calibration bias control transistor 427 will cause a common-mode shift at the input of the V2D circuit system 220 based on the offset of the amplifier circuit systems 240, 421.

[0185] If comparator circuitry 750 determines that the TDC output is not zero (e.g., block 925 returns a negative result), then Figure 7 The offset controller circuitry 740 adjusts a first offset correction value to adjust the reference common-mode voltage (box 930). In example operation, the comparator circuitry 750 detects a voltage offset in response to a non-zero digital value from the TDC circuitry 230. In this example operation, the offset controller circuitry 740 adjusts the reference generation circuitry 745 based on the digital value from the TDC circuitry 230. For example, the comparator circuitry 750 increases the input reference common-mode voltage in response to a digital value from the TDC circuitry 230 corresponding to a voltage less than zero. Similarly, the comparator circuitry 750 decreases the input reference common-mode voltage in response to a digital value from the TDC circuitry 230 corresponding to a voltage greater than zero. In some examples, such as in... Figure 7In this example, the offset correction circuit system 755 stores a first offset correction value (OFF_CORR1). In this type of example, the first offset correction value represents the adjustment of the reference input common-mode voltage when the CMRR correction bias control transistor 424 is applied.

[0186] If comparator circuitry 750 determines that the TDC output is zero (e.g., box 925 returns a yes result), then amplifier circuitry 240, 421 drives the positive-side calibration transistor with a calibration bias (box 935). In example operation, Figure 6 Switch 680 responds to offset controller circuitry 740 to clear the positive bias current selection signal (SEL). ICURR_P Or set the inverting forward bias current selection signal (~SEL) ICURR_P ) and supply CMRR calibration bias to transistor 424.

[0187] Amplifier circuitry 240, 421 drives the negative-side calibration transistor with a corrective bias (box 940). In example operation, Figure 6 The switch 685 responds to the offset controller circuitry 740 by setting the negative bias current selection signal (SEL). ICURR_M ) and supply CMRR correction bias to transistor 427.

[0188] Reference generation circuitry 745 sets a reference common-mode voltage (box 945). In example operation, reference generation circuitry 745 sets the reference input common-mode voltage to an initial voltage, which represents the target common-mode voltage. For example, if the inputs of amplifier circuitry 204 are equal, then reference generation circuitry 745 sets the reference input common-mode voltage to zero volts.

[0189] Comparator circuitry 750 determines whether the TDC output is zero (box 950). In example operation, amplifier circuitry 204, 208, V2D circuitry 220, and pulse generator circuitry 225 generate positive and negative delay signals (PULSE_OUTP, PULSE_OUTM) in response to the input voltage of amplifier circuitry 204 and the current from calibration circuitry 215. In this example operation, TDC circuitry 230 outputs a digital value representing the delay between the positive and negative delay signals (PULSE_OUTP, PULSE_OUTM). Comparator circuitry 750 compares the digital value from TDC circuitry 230 with a target output of zero. Advantageously, if the inputs to amplifier circuitry 204 are equal, the digital value at the output of TDC circuitry 230 represents the offset of calibration circuitry 215. Advantageously, the CMRR correction bias control transistor 427 and the CMRR calibration bias control transistor 424 will cause a common-mode shift at the input of the V2D circuit system 220 based on the offset of the amplifier circuit systems 240, 421.

[0190] If comparator circuitry 750 determines that the TDC output is not zero (e.g., block 950 returns a negative result), then offset controller circuitry 740 adjusts a second offset correction value to adjust the reference common-mode voltage (block 955). In example operation, comparator circuitry 750 determines the presence of a voltage offset in response to a non-zero digital value from TDC circuitry 230. In such example operation, offset controller circuitry 740 adjusts reference generation circuitry 745 based on the digital value from TDC circuitry 230. In some examples, such as in... Figure 7 In this example, the offset correction circuit system 760 stores a second offset correction value (OFF_CORR2). In this type of example, the second offset correction value represents the adjustment of the reference input common-mode voltage when the CMRR correction bias control transistor 427 is activated.

[0191] If comparator circuitry 750 determines that the TDC output is zero (e.g., block 950 returns a yes result), then Figure 7The total offset correction circuit system 765 determines an offset correction value based on a first offset correction value and a second offset correction value (box 960). In example operation, the total offset correction circuit system 765 determines the offset correction value in response to the first and second offset correction values ​​from offset correction circuit systems 755 and 760. In some examples, the total offset correction circuit system 765 determines the final offset correction value in response to averaging the first and second offset correction values. In such examples, the offset correction value of the total offset correction circuit system 765 represents the common-mode voltage offset of the calibration circuit system 215 or more generally the delay ADC circuit system 200. Advantageously, averaging the first and second offset correction values ​​provides offset correction for the calibration circuit system 215. Advantageously, both the first and second offset correction values ​​take into account the offsets of the amplifier circuit system 204, the V2D circuit system 220, the pulse generator circuit system 225, and the TDC circuit system 230.

[0192] Offset controller circuitry 740 sets a reference common-mode voltage based on the offset correction value (Box 965). In example operation, after the total offset correction circuitry 765 determines the offset correction value, offset controller circuitry 740 constructs a CMRR correction bias (CMRR_CORR_BIAS) and a CMRR calibration bias (CMRR_CALIB_BIAS) to close switches 675 and 685 and open switches 680 and 690. Furthermore, reference generation circuitry 745 references the input common-mode voltage (V... INCM_REF Set to the determined offset correction value.

[0193] In this type of example operation, the calibration controller circuitry 170, 235 responds to supplying a reference input common-mode voltage (V) to the amplifier circuitry 240, 421. INCM_REF And control Figure 6 Transistor 620. In this example operation, transistor 620 conducts the common-mode voltage of the reference input and... Figure 6 The current of transistors 605 and 610 is proportional to the ratio of their input common-mode voltages. The current mirror circuit system of transistors 625 and 630 generates a current proportional to the difference in current conduction between transistors 605, 610, and 620. Transistors 645 and 635 subtract this current difference from the bias current from the current source circuit system 650 to control the conduction of transistor 640, which drives transistors 245, 250, 424, and 427. Control proceeds to operation 1000.

[0194] In this type of example operation, the delay period (T) between the positive and negative delay edges at the output of the V2D circuit system 220 d ) and the gain of amplifier circuit system 204 ), input common-mode voltage of positive residual voltage and negative residual voltage ( ), the gain of V2D circuit system 220 ( The output common-mode voltage at the input of the V2D circuit system 220 ( ) and input voltage (V RES The delay period is proportional to equation (1). Example operations of calculating the gain of amplifier circuit systems 204, 208 and V2D circuit system 220 are further illustrated and described in U.S. Patent Application No. 18 / 498,358, "Voltage-to-Delay Converter," which is incorporated herein by reference in its entirety and assigned to the assignee of this application. Advantageously, Figure 2 , 4 The calibration circuit system of 6, 215, Figure 7 The offset correction circuit system 715 improves the CMRR of the delay domain ADC circuit system 150 by reducing the contribution of the output common-mode voltage at the input of the V2D circuit system 220. The CMRR of the delay domain ADC circuit system 150 is proportional to the contribution of the common-mode gain on the differential gain or the CMRR of the amplifier circuit systems 204, 208, the CMRR of the V2D circuit system 220, and the gain of the amplifier circuit systems 204, 208. The CMRR of the delay domain ADC circuit system 150 can be obtained using equation (2). Advantageously, improving the CMRR of the amplifier circuit systems 204, 208 increases the total CMRR of the delay domain ADC circuit system 150. Advantageously, as combined with Figure 10 As described, operation 1000 further improves the CMRR of the delay domain ADC circuit system 150 by using calibration circuit system 215 to reduce the common-mode gain of amplifier circuit systems 204, 208.

[0195] Equation (1)

[0196] Equation (2)

[0197] Advantageously, transistors 245, 250, 424, and 427 conduct correction current based on the difference between the input common-mode voltage at the input of amplifier circuit system 204 and the reference input common-mode voltage from calibration controller circuit systems 170 and 235. Advantageously, transistors 245, 250, 424, and 427 draw current for replication, as if the input common-mode voltage at the input of amplifier circuit system 204 were the reference input common-mode voltage. Advantageously, setting the common-mode voltage to the determined reference input common-mode voltage reduces the common-mode offset across delayed ADC circuit systems 155, 160, 165, and 200. Advantageously, reducing the common-mode offset improves the CMRR of delayed ADC circuit systems 155, 160, 165, and 200. Advantageously, improving the CMRR of delayed ADC circuit systems 155, 160, 165, and 200 improves the overall accuracy of ADC circuit system 100.

[0198] refer to Figure 9 The flowchart shown illustrates the example method. However, implementation details may also be used in this specification. Figure 2 , 4 The calibration circuit system of 6, 215, Figure 7 The offset correction circuit system 715 or more generally Figure 1 and 2 Delayed ADC circuit systems 155, 160, 165, 200 and Figure 1 , 2 And many other methods of the calibration controller circuitry systems 170, 235 of 7. For example, the execution order of the blocks can be changed, or some of the blocks described can be changed, eliminated, or combined. Similarly, additional operations may be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0199] Figure 10 This indicates that it can be used. Figure 2 , 4 The calibration circuit system of 6, 215, Figure 7 Gain correction circuit system 720 or more generally Figure 1 and 2 Delayed ADC circuit systems 155, 160, 165, 200 and Figure 1 , 2 The flowcharts of example machine-readable instructions or example operations 1000 for implementing, instantiating, or executing at least one of the example implementations, instantiations, or executions of the calibration controller circuit systems 170 and 235 of 7.

[0200] Figure 10 Example operation 1000 begins in box 1005. Figure 7The DAC code circuitry 730 sets the DAC code of the calibrating DAC as a reference value. In example operation, the DAC code circuitry 730 controls the analog output of the DAC circuitry 725 in response to the supply of a DAC code. In such example operation, the DAC circuitry 725 produces an analog output having a voltage corresponding to the DAC code of the DAC code circuitry 730. In some examples, the reference DAC code corresponds to an analog output having a voltage close to the maximum voltage of the DAC circuitry 725. For example, the reference value corresponds to an analog voltage that is 90% of the maximum differential voltage between the positive DAC signal and the negative DAC signal (DACP, DAM).

[0201] Figure 7 The DAC common-mode code circuitry 735 sets the DAC common-mode code of the calibrating DAC to an initial value (Box 1010). In example operation, the DAC common-mode code circuitry 735 controls the common-mode voltage of the DAC circuitry 725. In such example operation, the DAC circuitry 725 produces an analog output having a common-mode voltage corresponding to the DAC common-mode code of the DAC common-mode code circuitry 735. In some examples, the initial value of the DAC common-mode code circuitry 735 corresponds to the lowest possible common-mode voltage of the DAC circuitry 725. In other examples, the initial value of the DAC common-mode code circuitry 735 corresponds to the highest possible common-mode voltage of the DAC circuitry 725. In yet another example, the initial value of the DAC common-mode code circuitry 735 corresponds to a common-mode voltage in the middle of the range of the DAC circuitry 725.

[0202] Figure 7 The gain controller circuitry 770 determines a first digital value at the output of the TDC in response to the DAC common-mode code (Box 1015). In example operation, amplifier circuitry 208, V2D circuitry 220, and pulse generator circuitry 225 generate positive and negative delay signals (PULSE_OUTP, PULSE_OUTM) in response to the analog output of DAC circuitry 725. In this example operation, TDC circuitry 230 outputs a digital value representing the delay between the positive and negative delay signals (PULSE_OUTP, PULSE_OUTM). Ideally, the digital value corresponds to the DAC code of DAC common-mode code circuitry 735. However, at least one of amplifier circuitry 208, V2D circuitry 220, pulse generator circuitry 225, and TDC circuitry 230 amplifies the common-mode voltage. Gain controller circuitry 770 stores the first digital value.

[0203] The DAC common-mode code circuitry 735 increments the DAC common-mode code by a step size (Box 1020). In some examples, the gain of at least one of the amplifier circuitry 208, V2D circuitry 220, pulse generator circuitry 225, and TDC circuitry 230 may depend on the common-mode voltages of the positive and negative DAC signals (DACP, DAM). In some examples, the DAC common-mode code circuitry 735 scans the possible common-mode voltages of the positive and negative DAC signals (DACP, DAM). In such examples, during the scan of possible common-mode voltages, the DAC common-mode code circuitry 735 increments the DAC common-mode code by a step size across a range of possible common-mode voltages. For example, the DAC common-mode code circuitry 735 may decrease the DAC common-mode code by ten millivolts (mV).

[0204] Gain controller circuitry 770 determines a second digital value at the output of the TDC in response to the DAC common-mode code (Box 1025). In example operation, amplifier circuitry 208, V2D circuitry 220, and pulse generator circuitry 225 generate positive and negative delay signals (PULSE_OUTP, PULSE_OUTM) in response to the analog output of DAC circuitry 725. In this example operation, TDC circuitry 230 outputs a digital value representing the delay between the positive and negative delay signals (PULSE_OUTP, PULSE_OUTM). Ideally, the digital value corresponds to the DAC code of DAC common-mode code circuitry 735. However, at least one of amplifier circuitry 208, V2D circuitry 220, pulse generator circuitry 225, and TDC circuitry 230 amplifies the common-mode voltage. Gain controller circuitry 770 stores the second digital value.

[0205] The DAC common-mode code circuitry 735 reduces the original DAC common-mode code by a step value (Box 1030). In some examples, the DAC common-mode code circuitry 735 scans the possible common-mode voltages of the positive and negative DAC signals (DACP, DAM). In such examples, during the scan of possible common-mode voltages, the DAC common-mode code circuitry 735 increments the DAC common-mode code by a step value across a range of possible common-mode voltages. For example, the DAC common-mode code circuitry 735 may reduce the DAC common-mode code by ten millivolts.

[0206] Gain controller circuitry 770 determines a third digital value at the output of the TDC in response to the DAC common-mode code (Box 1035). In example operation, amplifier circuitry 208, V2D circuitry 220, and pulse generator circuitry 225 generate positive and negative delay signals (PULSE_OUTP, PULSE_OUTM) in response to the analog output of DAC circuitry 725. In this example operation, TDC circuitry 230 outputs a digital value representing the delay between the positive and negative delay signals (PULSE_OUTP, PULSE_OUTM). Ideally, the digital value corresponds to the DAC code of DAC common-mode code circuitry 735. However, at least one of amplifier circuitry 208, V2D circuitry 220, pulse generator circuitry 225, and TDC circuitry 230 amplifies the common-mode voltage. Gain controller circuitry 770 stores the third digital value.

[0207] Figure 7 The positive DAC code circuitry 775 determines a first difference between the second digital value and the first digital value (box 1040). In example operation, the positive DAC code circuitry 775 determines the first difference between the digital value from box 1015 and the digital value from box 1025 as a first change in gain. The first difference represents a change in the output of the TDC circuitry 230 in response to the DAC common-mode code circuitry 735 increasing the step size of the DAC common-mode code from box 1015.

[0208] Figure 7 The negative DAC code circuitry 780 determines a second difference between the third digital value and the first digital value (box 1045). In example operation, the negative DAC code circuitry 780 determines the second difference between the digital value from box 1015 and the digital value from box 1035 as a second change in gain. The second difference represents a change in the output of the TDC circuitry 230 in response to the DAC common-mode code circuitry 735 reducing the step size of the DAC common-mode code from box 1015.

[0209] Figure 7 The minimum DAC code circuitry 785 determines the absolute value of the larger of a first difference or a second difference (box 1050). In example operation, the minimum DAC code circuitry 785 takes the absolute values ​​of the first difference from box 1040 and the second difference from box 1045. The minimum DAC code circuitry 785 determines the minimum common-mode DAC code in response to determining which of the differences is greater. In this example operation, the common-mode gain of the delay-domain ADC circuitry 150 has a convex characteristic. Advantageously, a large variation at the output of the TDC circuitry 230 corresponds to a local minimum of the common-mode gain curve.

[0210] Gain controller circuitry 770 determines whether the determined absolute value is greater than a previously determined absolute value (box 1055). In example operation, gain controller circuitry 770 compares the determined minimum common-mode DAC code with a previously determined minimum DAC code. In such example operation, gain controller circuitry 770 may determine the true minimum DAC code across the range of DAC circuitry 725.

[0211] If the gain controller circuitry 770 determines that the determined absolute value is not greater than the previously determined absolute value (e.g., block 1055 returns a negative result), then Figure 7 The gain correction circuit system 790 updates the gain correction value based on the determined absolute value (box 1060). In example operation, the gain correction circuit system 790 adjusts the gain control signal (GAIN). CNTRL ), first gain trim value (GAIN) TRIM_T1 ) or second gain trim value (GAIN) TRIM_T2 At least one of the following is used to adjust the gain of the calibration circuit system 215. In some examples, the gain control signal (GAIN) CNTRL )Adjustment Figure 6 The current source circuit system 615 adjusts the current to adjust the gain of the amplifier circuit system 421. In other examples, the gain trim value is adjusted in response to the magnitude of transistors 245, 250, 424, and 427, thereby adjusting the gain of the calibration circuit system 215. In yet another example, the gain correction circuit system 790 adjusts the gain control signal (GAIN)... CNTRL ) and gain trimming value. Advantageously, adjust the gain control signal (GAIN) CNTRL One or more of the gain trim values ​​will adjust the gain of calibration circuit system 215. Advantageously, as shown in equation (2), adjusting the common-mode gain of amplifier circuit systems 204, 208 using calibration circuit system 215 allows calibration controller circuit system 235 to control the CMRR of delay domain ADC circuit system 150.

[0212] If the gain controller circuitry 770 determines that the determined absolute value is greater than the previously determined absolute value (e.g., block 1055 returns a yes result), then control proceeds from block 1060, and the DAC common-mode code circuitry 735 determines whether all DAC common-mode codes have been tested (block 1065).

[0213] If the DAC common-mode code circuitry 735 determines that not all DAC common-mode codes have been tested (e.g., box 1065 returns a negative result), then the DAC common-mode code circuitry 735 adjusts the DAC common-mode code of the calibration DAC (box 1070). In some examples, the DAC common-mode code circuitry 735 scans for all possible DAC common-mode codes during calibration. In such examples, the DAC common-mode code circuitry 735 continues calibrating the delay domain ADC circuitry 150 until the ideal CMRR is achieved. Control proceeds to return to box 1015. If the DAC common-mode code circuitry 735 determines that all DAC codes have been tested (e.g., box 1065 returns a positive result), then control proceeds to return.

[0214] Advantageously, setting the common-mode voltage to a calibrated reference input common-mode voltage reduces common-mode offset and decreases the common-mode gain across the delayed ADC circuit systems 155, 160, 165, and 200. Advantageously, reducing common-mode offset and common-mode gain improves the common-mode rejection ratio (CMRR) of the delayed ADC circuit systems 155, 160, 165, and 200. Advantageously, improving the CMRR of the delayed ADC circuit systems 155, 160, 165, and 200 improves the overall accuracy of the ADC circuit system 100.

[0215] refer to Figure 9 The flowchart shown illustrates the example method. However, implementation details may also be used in this specification. Figure 2 , 4 The calibration circuit system of 6, 215, Figure 7 The gain correction circuit system 720 or more generally Figure 1 and 2 Delayed ADC circuit systems 155, 160, 165, 200 and Figure 1 , 2 And many other methods of the calibration controller circuitry systems 170, 235 of 7. For example, the execution order of the blocks can be changed, or some of the blocks described can be changed, eliminated, or combined. Similarly, additional operations may be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0216] Figure 11 It has and does not have Figure 9 and 10 Calibration operations 900, 1000 Figure 2 and 4 The example common-mode rejection ratio (CMRR) curve of the V2D circuit system 220 is shown in Figure 1100. Figure 11Example graph 1100 shows the uncalibrated CMRR 1110 and calibrated CMRR 1120 across different common-mode voltages (INCM). The uncalibrated CMRR 1110 represents the noise caused by the CMRR of the delay domain ADC circuitry 150 without calibration circuitry 215. The calibrated CMRR 1120 represents the noise caused by the CMRR of the delay domain ADC circuitry 150 without calibration circuitry 215. Figure 9 and 10 The noise caused by the CMRR of the delay domain ADC circuit system 150 with calibration circuit system 215 after operations 900 and 1000. The uncalibrated CMRR 1110 has higher noise across different common-mode voltage ranges compared to the calibrated CMRR 1120. Advantageously, calibration circuit system 215 and operations 900 and 1000 reduce the noise caused by different common-mode voltages.

[0217] Figure 12 It has and does not have Figure 9 and 10 Calibration operations 900, 1000 Figure 2 and 4 Figure 1200 shows an example performance curve of the delayed ADC circuit system. Figure 12 Graph 1200 shows the first calibrated sound-to-noise ratio (SNR) 1210, the second calibrated SNR 1220, and the uncalibrated SNR 1230 across different common-mode voltages (INCM). Figure 12 In the example, the Y-axis represents the sound-to-noise ratio (SNR) in decibels, and the X-axis represents the input common-mode voltage (INCM). Calibrated SNR 1210, 1220 represent the operation of the delay-domain ADC circuit system 150 with calibration circuit system 215 and operations 900, 1000. Uncalibrated SNR 1230 represents the operation of the delay-domain ADC circuit system 150 without calibration circuit system 215 or operations 900, 1000. Advantageously, calibration circuit system 215 and operations 900, 1000 reduce noise caused by different common-mode voltages.

[0218] Figure 13 This is a schematic diagram of an example ADC circuit system 1300, which shows... Figure 2 , 4 Alternative implementation schemes for calibration circuit system 215 of 6. Figure 13 The example ADC circuit system 1300 includes a first example switch 1305, a first example capacitor 1310, a second example switch 1315, a second example capacitor 1320, an example amplifier circuit system 1325, a third example switch 1330, a fourth example switch 1335, a fifth example switch 1340, a sixth example switch 1345, a third example capacitor 1350, a fourth example capacitor 1355, and an example CDAC 1360. Figure 2 , 4 Unlike the calibration circuit system 215 of the 6th amplifier, the amplifier circuit system 1325 achieves CMRR correction by controlling the voltage between capacitors 1350 and 1355. Figure 13 In the example, amplifier circuit system 1325 is Figure 4 and 6 An embodiment of amplifier circuit system 421 is shown below. Example operation of amplifier circuit system 1325 is further illustrated and described below.

[0219] The ADC circuit system 1300 has a first input, a second input, a third input, a first output, and a second output. The first input (INP) of the ADC circuit system 1300 is configured to be coupled to an external circuit system that supplies an analog signal. The second input (INM) of the ADC circuit system 1300 is configured to be coupled to the external circuit system. The third input of the ADC circuit system 1300 is configured to be coupled to an ADC (e.g., ADC 125) that provides digital bits. The first and second outputs (V...) of the ADC circuit system 1300... RESP V RESM ) is constructed to be coupled to Figure 1 The delay domain ADC circuit system 150. In Figure 13 In the example, the ADC circuit system 1300 includes a first stage of analog-to-digital conversion. Specifically, in the first stage, the amplifier circuit system 421 of the calibration circuit system 215 is used as a diagram of the amplifier circuit system 1325.

[0220] Switch 1305 has a first terminal and a second terminal. The first terminal of switch 1305 is coupled to switch 1340 and the first input (INP) of ADC circuit system 1300. The second terminal of switch 1305 is coupled to capacitor 1310 and switch 1315.

[0221] Capacitor 1310 has a first terminal and a second terminal. The first terminal of capacitor 1310 is coupled to switches 1305 and 1315. The second terminal of capacitor 1310 is coupled to capacitor 1320 and amplifier circuit system 1325.

[0222] Switch 1315 has a first terminal and a second terminal. The first terminal of switch 1315 is coupled to switch 1305 and capacitor 1310. The second terminal of switch 1315 is coupled to a common terminal, which provides a common potential.

[0223] Capacitor 1320 has a first terminal and a second terminal. The first terminal of capacitor 1320 is coupled to capacitor 1310 and amplifier circuit system 1325. The second terminal of capacitor 1320 is coupled to switches 1330 and 1335.

[0224] Amplifier circuit system 1325 has a first input, a second input, and an output. The first input of amplifier circuit system 1325 is coupled to capacitors 1310 and 1320. The second input of amplifier circuit system 1325 is configured to couple to calibration controller circuit system 235, which provides a reference input common-mode voltage (V). INCM_REF The output of amplifier circuit system 1325 is coupled to capacitors 1350 and 1355. Amplifier circuit system 1325 is an example implementation of amplifier circuit system 421 in the first stage of ADC circuit system 1300.

[0225] Switch 1330 has a first terminal and a second terminal. The first terminal of switch 1330 is coupled to capacitor 1320 and switch 1335. The second terminal of switch 1330 is coupled to a common terminal that provides a common potential.

[0226] Switch 1335 has a first terminal and a second terminal. The first terminal of switch 1335 is coupled to capacitor 1320 and switch 1330. The second terminal of switch 1335 is coupled to switch 1345 and the second input (INM) of ADC circuit system 1300.

[0227] Switch 1340 has a first terminal and a second terminal. The first terminal of switch 1340 is coupled to switch 1305 and the first input (INP) of ADC circuit system 1300. The second terminal of switch 1340 is coupled to capacitor 1355, CDAC 1360 and the first output (V) of ADC circuit system 1300. RESP ).

[0228] Switch 1345 has a first terminal and a second terminal. The first terminal of switch 1345 is coupled to switch 1335 and the second input (INM) of ADC circuit system 1300. The second terminal of switch 1345 is coupled to capacitor 1350, CDAC 1360 and the second output (V) of ADC circuit system 1300. RESM ).

[0229] Capacitor 1350 has a first terminal and a second terminal. The first terminal of capacitor 1350 is coupled to amplifier circuit system 1325 and capacitor 1355. The second terminal of capacitor 1350 is coupled to switch 1345, CDAC 1360, and the second output (V) of ADC circuit system 1300. RESM ).

[0230] Capacitor 1355 has a first terminal and a second terminal. The first terminal of capacitor 1355 is coupled to amplifier circuit system 1325 and capacitor 1350. The second terminal of capacitor 1355 is coupled to switch 1340, CDAC 1360, and the first output (V) of ADC circuit system. RESP ).

[0231] The CDAC 1360 has an input, a first output, and a second output. The input of the CDAC 1360 is coupled to the third input of the ADC circuit system 1300. The first output of the CDAC 1360 is coupled to switch 1340, capacitor 1355, and the first output (V) of the ADC circuit system 1300. RESP The second output of the CDAC 1360 is coupled to the switch 1345, the capacitor 1350, and the second output (V) of the ADC circuit system 1300. RESP ).

[0232] In the example operation, switches 1305, 1315, 1330, 1335, 1340, and 1345 sample and hold the first and second inputs (INP, INM) of the ADC circuit system 1300 across capacitors 1310 and 1320. Capacitors 1310 and 1320 divide the voltages of the first and second inputs of the ADC circuit system 1300 to provide an input common-mode voltage to the amplifier circuit system 1325. The amplifier circuit system 1325 compares the input common-mode voltage from capacitors 1310 and 1320 with a reference input common-mode voltage from the calibration controller circuit system 235. Capacitors 1350 and 1355 set the common-mode voltages (V1) of the first and second outputs of the ADC circuit system 1300 in response to the comparison by the amplifier circuit system 1325. RESP V RESM In the example described above, transistors 245 and 250 compensate for errors caused by the input common-mode voltage by sinking current. This type of correction, occurring after the input common-mode voltage passes through amplifier 204, can be referred to as correction that occurs after the introduction of an error. Figure 13 In the example, amplifier circuitry 1325 compensates for errors caused by the input common-mode voltage in response to adjusting the input common-mode voltage set by capacitors 1350 and 1355. This type of correction can be considered preemptive compensation. Advantageously, amplifier circuitry 1325 improves the CMRR of ADC circuitry 1300 by correcting the input common-mode voltage based on a reference input common-mode voltage. Advantageously, amplifier circuitry 1325 and capacitors 1350 and 1355 correct the output common-mode voltage of CDAC 1360.

[0233] Figure 14This is a block diagram of an example programmable circuit system platform 1400, which is configured to respond to example machine-readable instructions or... Figure 8 , 9 And one or more of the example operations in 10 are implemented or one or a combination of them are instantiated to implement. Figure 1 and 7 The calibration controller circuit system 170. The programmable circuit system platform 1400 can be used for, for example, servers, personal computers, workstations, self-learning machines (e.g., neural networks), mobile devices (e.g., mobile phones, smartphones, e.g., iPads). TM Tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices, or any other type of computing or electronic device.

[0234] The illustrated programmable circuit system platform 1400 includes a programmable circuit system 1412. The illustrated programmable circuit system 1412 is hardware. For example, the programmable circuit system 1412 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired series or manufacturer. The programmable circuit system 1412 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1412 implements calibration controller circuit system 235, or more generally, calibration controller circuit system 170. In another example, a block in the programmable circuit system platform 1400 may participate in controlling or interfacing at least one of the delayed ADC circuit systems 155, 160, 165, 200 to implement calibration controller circuit system 170. In yet another example, a block in the programmable circuit system platform 1400 that participates in controlling or interfacing at least one of the delayed ADC circuit systems 155, 160, 165, 200 implements… Figure 8 , 9 Some or all of the machine-readable instructions in the flowchart of 10.

[0235] The illustrated programmable circuit system 1412 includes local memory 1413 (e.g., cache, registers, etc.). The illustrated programmable circuit system 1412 communicates via bus 1418 with main memories 1414 and 1416, which include volatile memory 1414 and non-volatile memory 1416. The volatile memory 1414 may be implemented using one or more synchronous dynamic random access memories (SDRAM), dynamic random access memories (DRAM), RAMBUS® dynamic random access memories (RDRAM®), or any other type of RAM device. The non-volatile memory 1416 may be implemented using flash memory or any other desired type of memory device, or a combination thereof. Access to the illustrated main memories 1414 and 1416 is controlled by a memory controller 1417. In some examples, the memory controller 1417 may be implemented by one or more integrated circuits, logic circuits, microcontrollers or any other type of circuit system from any desired series or manufacturer to manage the data flow to and from the main memory 1414, 1416.

[0236] The programmable circuit system platform 1400 shown in the example also includes an interface circuit system 1420. The interface circuit system 1420 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect High Speed ​​(PCIe) interface.

[0237] In the illustrated example, one or more input devices 1422 are connected to the interface circuitry 1420. The input devices 1422 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry 1412. The input devices 1422 may be implemented using, for example, an audio sensor, microphone, camera (still or video), keyboard, buttons, mouse, touchscreen, touchpad, trackball, dot device, or a voice recognition system, or a combination thereof.

[0238] One or more output devices 1424 are also connected to the interface circuitry 1420 illustrated in the example. The output devices 1424 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuitry 1420 illustrated in the example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuitry system such as a GPU.

[0239] The interface circuit system 1420 shown in the example also includes communication devices, such as one or a combination of a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 1426. Communication can be carried out via, for example, Ethernet connection, Digital Subscriber Line (DSL) connection, telephone line connection, coaxial cable system, satellite system, line-of-sight wireless system, line-of-sight wireless system, cellular telephone system, optical connection, etc.

[0240] The programmable circuit system platform 1400 shown in the example also includes one or more mass storage disks or devices 1428 for storing one or more of firmware, software, or data. Examples of such mass storage disks or devices 1428 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0241] can be Figure 8 , 9 The machine-readable instructions 1432 implemented by the machine-readable instructions of 10 may be stored in one or a combination of mass storage device 1428, volatile memory 1414, and non-volatile memory 1416, or stored on at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0242] Figure 15 yes Figure 14 A block diagram of an example embodiment of the programmable circuit system 1412. In this example, Figure 14 The programmable circuit system 1412 is implemented by the microprocessor 1500. For example, the microprocessor 1500 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit system). The microprocessor 1500 executes... Figure 8 , 9 Some or all of the machine-readable instructions in the flowchart of 10, in order to effectively translate Figure 2 The circuit system is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such examples, Figure 1 and 7The circuit system is instantiated by the hardware circuitry of the microprocessor 1500 in conjunction with machine-readable instructions. For example, the microprocessor 1500 may be implemented by a multi-core hardware circuitry system such as a CPU, DSP, GPU, or XPU. While it may contain any number of example cores 1502 (e.g., one core), this example microprocessor 1500 is a multi-core semiconductor device containing N cores. The cores 1502 of the microprocessor 1500 may operate independently or collaboratively to execute machine-readable instructions. For example, machine code corresponding to firmware, embedded software, or software programs may be executed by one of the cores 1502, or by multiple cores 1502 at the same or different times. In some examples, the machine code corresponding to firmware, embedded software, or software programs is split into threads and executed in parallel by two or more of the cores 1502. Software programs may correspond to... Figure 8 , 9 The flowcharts of 10 represent part or all of the machine-readable instructions or operations.

[0243] Core 1502 can communicate via a first example bus 1504. In some examples, the first bus 1504 can be implemented as a communication bus to enable communication associated with one or more of the cores 1502. For example, the first bus 1504 can be implemented via at least one of an Interconnect Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Alternatively, the first bus 1504 can be implemented by any other type of computing or electrical bus. Core 1502 can obtain data, instructions, and signals from one or more external devices via example interface circuitry 1506. Core 1502 can output data, instructions, and signals to one or more external devices via interface circuitry 1506. While the core 1502 of this example includes example local memory 1520 (e.g., a Level 1 (L1) cache, which can be split into an L1 data cache and an L1 instruction cache), the microprocessor 1500 also includes example shared memory 1510 (e.g., a Level 2 (L2) cache) that can be shared by the cores for high-speed access to data and instructions. Data and instructions can be transferred (e.g., shared) by writing to or reading from shared memory 1510. The local memory 1520 and shared memory 1510 of each of the cores 1502 may be multi-level cache memory and main memory (e.g., Figure 14 The cache is part of the storage device hierarchy of main memories (1414, 1416). Typically, higher-level memories in the hierarchy exhibit shorter access times and smaller storage capacities compared to lower-level memories. Changes to the various levels of the cache hierarchy are managed by cache coherence strategies (e.g., reconciliation).

[0244] Each core 1502 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuitry. Each core 1502 includes a control unit circuitry 1514, an arithmetic and logic (AL) circuitry (sometimes called an ALU) 1516, multiple registers 1518, local memory 1520, and a second example bus 1522. Other structures may exist. For example, each core 1502 may include a vector unit circuitry, a single instruction multiple data (SIMD) unit circuitry, a load / store unit (LSU) circuitry, a branch / jump unit circuitry, a floating-point unit (FPU) circuitry, etc. The control unit circuitry 1514 includes semiconductor-based circuitry configured to control (e.g., coordinate) the movement of data within the corresponding core 1502. The AL circuitry 1516 includes semiconductor-based circuitry configured to perform one or more mathematical or logical operations on the data within the corresponding core 1502. Some example AL circuitry 1516 performs integer-based operations. In other examples, the AL circuit system 1516 also performs floating-point operations. In still other examples, the AL circuit system 1516 may include a first AL circuit system that performs integer-based operations and a second AL circuit system that performs floating-point operations. In some examples, the AL circuit system 1516 may be referred to as an arithmetic logic unit (ALU).

[0245] Register 1518 is a semiconductor-based structure used to store data and instructions, such as the results of one or more operations performed by the AL circuitry 1516 corresponding to core 1502. For example, register 1518 may contain vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 1518 can be arranged in groups, such as... Figure 15 As shown in the diagram. Alternatively, register 1518 can be organized in any other arrangement, format, or structure, for example, by distributing it throughout core 1502 to reduce access time. The second bus 1522 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0246] Each core 1502, or more generally, the microprocessor 1500, may include additional or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergent / common grid stoppers (CMS), one or more shifters (e.g., barrel shifters), or other circuitry may be present. The microprocessor 1500 is a semiconductor device manufactured to include a number of transistors interconnected in one or more integrated circuits (ICs) contained in one or more packages to implement the structures described above.

[0247] Microprocessor 1500 may include or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks faster and more efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, or other programmable devices may also serve as accelerators. Accelerators may be mounted on microprocessor 1500, in the same chip package as microprocessor 1500, or in one or more separate packages with microprocessor 1500.

[0248] Figure 16 yes Figure 14 A block diagram of another example embodiment of the programmable circuit system 1412 is shown. In this example, the programmable circuit system 1412 is implemented by an FPGA circuit system 1600. For example, the FPGA circuit system 1600 may be implemented by an FPGA. The FPGA circuit system 1600 can be used, for example, to execute machine-readable instructions that can be implemented by corresponding machine-readable instructions. Figure 15 The example microprocessor 1500 performs operations in other ways. However, once configured, the FPGA circuit system 1600 instantiates operations and functions corresponding to machine-readable instructions in hardware, and therefore can generally perform operations / functions faster than those that can be performed by a general-purpose microprocessor implementing the corresponding software.

[0249] More specifically, as described above Figure 15 The microprocessor 1500 (which is programmable to perform operations by...) Figure 8 , 9 Compared to the flowchart in 10, which represents some or all of the general-purpose devices in machine-readable instructions, but whose interconnections and logic circuitry are fixed once manufactured, Figure 16 The example FPGA circuit system 1600 includes interconnects and logic circuit systems, which can be configured, constructed, programmed, and interconnected in different ways or in combination after manufacturing to instantiate, for example, with... Figure 8 , 9The flowchart in Figure 10 represents some or all of the machine-readable instructions corresponding to the operations / functions. Specifically, the FPGA circuit system 1600 can be considered as an array of logic gates, interconnects, and switches. Switches can be programmed to change how logic gates are interconnected via interconnects to effectively form one or more dedicated logic circuits (unless and until the FPGA circuit system 1600 is reprogrammed). The logic circuits are configured so that logic gates can cooperate in different ways to perform different operations on data received from the input circuit system. Those operations can correspond to... Figure 8 , 9 The flowcharts 10 and 10 represent some or all of the instructions (e.g., software and / or firmware). Therefore, the FPGA circuit system 1600 can be configured or constructed in at least one of the following ways to effectively integrate with... Figure 8 , 9 Some or all of the operations / functions corresponding to the machine-readable instructions in the flowchart 10 are instantiated as dedicated logic circuits to execute the operations / functions corresponding to those software instructions in a dedicated manner similar to that of an ASIC. Therefore, the FPGA circuit system 1600 can be coupled with a general-purpose microprocessor to perform operations / functions corresponding to those software instructions. Figure 8 , 9 The operation / function is performed faster than some or all of the machine-readable instructions in 10.

[0250] exist Figure 16 In some examples, the FPGA circuit system 1600 is configured or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled or generated based on instructions in a hardware description language (HDL) such as Lucid, a Very High Speed ​​Integrated Circuit (VHSIC) hardware description language (VHDL), or Verilog, or both. For example, a user (e.g., a human user, a machine user, etc.) may write code or programs corresponding to one or more operations / functions in the HDL; the code / program may be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be translated into a binary file (e.g., by a compiler, software application, etc.). In some examples, Figure 16 The FPGA circuit system 1600 can access or load at least one of the binary files, so that... Figure 16 The FPGA circuit system 1600 is configured or constructed to perform one or more operations / functions. For example, a binary file can be generated by... Figure 16 The FPGA circuit system 1600 can access one or a combination of bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) or machine-readable instructions to perform operations on... Figure 16 At least one of the FPGA circuit system 1600 or a portion thereof is configured or constructed.

[0251] In some examples, the binary file is compiled, generated, transformed, or otherwise output from a unified software platform used for programming FPGAs. For example, the unified software platform can transform first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in HDL. In some such examples, the binary file is compiled, generated, or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 16 The FPGA circuit system 1600 can access or load at least one of the binary files, so that... Figure 16 The FPGA circuit system 1600 is configured or constructed to perform one or more operations / functions. For example, a binary file can be generated by... Figure 16 The FPGA circuit system 1600 can access one or a combination of bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) or machine-readable instructions to perform operations on... Figure 16 At least one of the FPGA circuit system 1600 or a portion thereof is configured or constructed.

[0252] Figure 16 The FPGA circuit system 1600 includes an example input / output (I / O) circuit system 1602 to perform at least one of the following operations: obtaining data from or outputting data to at least one of the example configuration circuit system 1604 or the external hardware 1606. For example, the configuration circuit system 1604 may be implemented by an interface circuit system that provides a binary file, which may be implemented by one or more of bitstreams, data, or machine-readable instructions to configure the FPGA circuit system 1600 or a portion thereof. In some such examples, the configuration circuit system 1604 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), or any combination thereof. In some examples, the external hardware 1606 may be implemented by an external hardware circuit system. For example, the external hardware 1606 may be implemented by... Figure 15 The microprocessor 1500 is implemented.

[0253] The FPGA circuit system 1600 also includes an array of example logic gate circuit systems 1608, multiple example configurable interconnects 1610, and example memory circuit systems 1612. The logic gate circuit system 1608 and the configurable interconnects 1610 are configurable to instantiate corresponding to... Figure 8 , 9 One or more operations / functions and / or other desired operations in at least some of the machine-readable instructions of 10. Figure 16 The logic gate system 1608 shown is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures configurable into logic circuits. In some examples, the electrical structures contain logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for the logic circuits. Electrically controlled switches (e.g., transistors) are present in each of the logic gate system 1608 to enable the configuration of one or a combination of electrical structures or logic gates to form a circuit for performing a desired operation / function. The logic gate system 1608 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0254] The configurable interconnect 1610 shown in the example may include conductive paths, traces, vias, etc., of electrically controlled switches (e.g., transistors), the states of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit system 1608 to program the desired logic circuit.

[0255] The storage circuit system 1612 shown in the example is configured to store the result of one or more of the operations performed by the corresponding logic gates. The storage circuit system 1612 may be implemented by registers, etc. In the example shown, the storage circuit system 1612 is distributed within the logic gate circuit system 1608 to facilitate access and improve execution speed.

[0256] Figure 16The example FPGA circuit system 1600 also includes an example dedicated operating circuit system 1614. In this example, the dedicated operating circuit system 1614 includes a dedicated circuit system 1616 that can be invoked to implement common functions to avoid the need for field programming of those functions. Examples of such dedicated circuit systems 1616 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory and multiplier-accumulator circuit systems. Other types of dedicated circuit systems may be present. In some examples, the FPGA circuit system 1600 may also include an example general-purpose programmable circuit system 1618, such as an example CPU 1620 or an example DSP 1622. Other general-purpose programmable circuit systems 1618 that can be programmed to perform other operations, such as GPUs, XPUs, etc., may also be present, either additionally or alternatively.

[0257] although Figure 15 and 16 Show Figure 14 Two example implementations of the programmable circuit system 1412 are provided, but many other approaches are envisioned. For example, the FPGA circuit system may include an onboard CPU, such as... Figure 15 One or more of the example CPUs 1620. Therefore, Figure 14 The programmable circuit system 1412 can also be configured by at least combining Figure 15 Example microprocessor 1500 and Figure 16 The example FPGA circuit system 1600 is used for implementation. In some such hybrid examples, Figure 15 One or more core 1502 can be implemented by Figure 8 , 9 The flowchart of 10 represents the first part of the machine-readable instructions to perform a first operation / function. Figure 16 The FPGA circuit system 1600 can be configured or constructed to perform operations similar to those performed by... Figure 8 , 9 The second operation / function corresponding to the second part of the machine-readable instructions represented in the flowchart of 10, and / or at least one of which can be configured or constructed by the ASIC to perform the operation / function corresponding to the second part of the machine-readable instructions represented in the flowchart of 10, and / or the second ... operation / function corresponding to the second operation / function corresponding to the second operation / function corresponding to Figure 8 , 9 The flowchart of 10 represents the third operation / function corresponding to the third part of the machine-readable instruction.

[0258] therefore, Figure 1 and 7 Some or all of the circuitry in a system can be instantiated at the same or different times. For example, Figure 15One or more identical and / or different parts of the microprocessor 1500 can be programmed to execute machine-readable instructions at the same and / or different times. In some examples, Figure 16 The same and / or different parts of the FPGA circuit system 1600 can be configured or constructed to perform operations / functions corresponding to machine-readable instructions at the same and / or different times.

[0259] In some examples, Figure 1 and 7 Some or all of the circuit system can be instantiated, for example, in one or more threads that are executed simultaneously and / or in series. For example, Figure 15 The microprocessor 1500 can execute machine-readable instructions in one or more threads, simultaneously and / or in series. In some examples, Figure 16 The FPGA circuit system 1600 can be configured or constructed to perform operations / functions simultaneously and / or in series. Furthermore, in some examples, Figure 1 and 7 Some or all of the circuit systems can be in Figure 15 It is implemented within one or more virtual machines or containers on a microprocessor 1500.

[0260] In some examples, Figure 14 The programmable circuit system 1412 can be housed in one or more packages. For example, Figure 15 microprocessor 1500 or Figure 16 At least one of the FPGA circuitry systems 1600 may be housed in one or more packages. In some examples, the XPU may be derived from... Figure 14 The programmable circuit system 1412 is implemented, and the programmable circuit system may be in one or more packages. For example, the XPU may be contained within a CPU in one package (e.g., Figure 15 Microprocessor 1500, Figure 16 CPU1620, etc.), and DSP in another package (e.g., Figure 16 DSP 1622), GPU in another package, and FPGA in yet another package (e.g., Figure 16 FPGA circuit system 1600).

[0261] Although Figure 1 and 7 The implementation is shown in the figure. Figure 1 The calibration controller circuit system 170 is an example of a certain method, but Figure 1 and 7 One or more of the elements, processes, or devices shown may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, the calibration controller circuit system 235, or more generally... Figure 1 and 7 The calibration controller circuitry 170 can be implemented by a single piece of hardware or by a combination of hardware, software, and firmware. Therefore, for example, either the calibration controller circuitry 235 or more generally the calibration controller circuitry 170 can be implemented by a programmable circuitry system in combination with one or more machine-readable instructions (e.g., firmware or software), a processor circuitry system, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), or a field-programmable logic device (FPLD) (e.g., an FPGA). Furthermore, Figure 1 and 7 Example calibration controller circuit system 170 may include as Figure 1 and 7 The elements, processes, or devices shown may be supplemented or replaced by one or more elements, processes, or devices, or may include more than one of any or all of the elements, processes, and devices shown.

[0262] Figure 8 , 9 Figures 1 and 10 illustrate flowcharts representing example machine-readable instructions or example operations, which can be implemented by a programmable circuit system to... Figure 1 and 7 At least one of the calibration controller circuitry 170 is implemented or instantiated, and the example operation can be performed by a programmable circuitry system to... Figure 1 and 7 The calibration controller circuitry 170 is implemented or instantiated in at least one of these ways. Machine-readable instructions may be provided for programmable circuitry systems (e.g., as described below in conjunction with...). Figure 14 The programmable circuit system 1412 shown in the example processor platform 1400 described herein implements one or more executable programs or portions thereof, and may be incorporated herein by reference. Figure 15 Or, as discussed in example 16, a programmable circuit system (e.g., an FPGA) performs one or more functions or portions of functions. In some examples, machine-readable instructions cause operations, tasks, etc., to be performed or executed in a real-world manner. As used herein, “automatic” means without human intervention.

[0263] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disks (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, optical discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated by one or more hardware devices other than the programmable circuit system or embodied in dedicated hardware. Machine-readable instructions can be distributed across multiple hardware devices or implemented by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices can be implemented by endpoint client hardware devices (e.g., hardware devices associated with human and / or machine users) or intermediate client hardware device gateways (e.g., radio access networks (RAN)) that facilitate communication between the server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media can contain one or more media. Furthermore, although references... Figure 8 , 9The flowchart shown in Figure 10 describes an example program, but many other methods of implementing the example calibration controller circuit system 170 can be used alternatively. For example, the execution order of the flowchart blocks can be changed, or some of the described blocks can be changed, eliminated, or combined. Furthermore or alternatively, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete, integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without implementing software or firmware. The programmable circuit system can be distributed across different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, a programmable circuit system can be one or a combination of the following: a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers across server racks, multiple processors distributed across one or more server racks, or any combination thereof.

[0264] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, encapsulated format, etc. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., as parts of instructions, code, code representations, etc.), which can be used to create, manufacture, or generate machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations within a network or network set (e.g., in the cloud, at an edge device, etc.). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, decapsulated, allocated, reassigned, compiled, etc., to make them directly readable, interpretable, or executable by a computing device or other machine. For example, machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, or stored on separate computing devices, wherein the parts, when decrypted, decompressed, or combined, form a set of one or more computer-executable or machine-executable instructions, the execution of which may together form one or more functions or operations of a program, such as those described herein.

[0265] In another example, machine-readable instructions may be stored in a state that allows them to be read by a programmable circuit system, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., need to be added to enable the execution of the machine-readable instructions on a specific computing device or other device. In another example, the machine-readable instructions (e.g., stored settings, data inputs, recorded network addresses, etc.) may need to be configured before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable, or machine-readable media may contain one or a combination of instructions and programs, regardless of the specific format or state of the machine-readable instructions or programs.

[0266] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0267] As mentioned above, Figure 8 , 9The example operations of 10 can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are explicitly defined as containing any type of computer-readable storage device or disk that does not contain propagation signals and does not contain transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk where information is stored for any duration (e.g., a prolonged period of time, permanently, temporarily, temporarily buffered, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware for retaining information for a period of time, but excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of the following: mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured by, or manufactured to execute, computer-readable instructions, machine-readable instructions, etc.

[0268] "Including" and "comprises" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a technical solution adopts any form of "including" or "comprises" (e.g., including, encompassing, including, having, etc.) as a preamble or in any type of technical solution description, additional elements, terms, etc., may be present without exceeding the scope of the corresponding technical solution or description. As used herein, when the phrase "at least" is used as a transitional term in, for example, a preamble of a technical solution, it is open in the same way as the terms "including" and "comprises" are open-ended. The term "and / or," when used, for example, in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A and B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation scheme that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0269] As used herein, singular references (e.g., "a(a)", "an(an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a(a)" or "an(an)" refers to one or more of the objects mentioned. The terms "a(a)" (or "an(an)"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Moreover, while individual features may be included in different examples or technical solutions, these features may be combined, and inclusion in different examples or technical solutions does not imply that the combination of features is not feasible or advantageous.

[0270] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. The first part is above the second part if the second part has at least one portion between it and the earth. Similarly, as used herein, the first part is "below" the second part when it is closer to the earth than the second part. As mentioned above, the first part may be above or below the second part, having one or more of the following: having other portions between it, having no other portions between it, the first and second parts in contact, or the first and second parts not in direct contact with each other.

[0271] As used in this patent, stating that any part (e.g., layer, film, region, area, or plate) is on another part in any way (e.g., located on it, positioned on it, placed on it, or formed on it, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0272] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate member between elements referenced by the connection reference between those elements or by at least one of the elements in relative movement. Thus, a connection reference does not necessarily imply that two elements are directly connected to each other or are in a fixed relationship. As used herein, the statement that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.

[0273] Unless otherwise specifically stated, descriptive terms such as “first,” “second,” and “third” are used herein without intending or otherwise indicating any meaning of priority, physical order, arrangement, or sorting in the list, but only as markers or arbitrary names to distinguish elements for the purpose of understanding the described examples. In some examples, the descriptive term “first” may be used to refer to an element in a detailed description, while the same element may be referred to in a technical solution by different descriptive terms such as “second” or “third.” In such cases, such descriptive terms are used only to clearly identify those elements within the context of the discussion (e.g., within the technical solution), in which elements may otherwise share the same name.

[0274] As used herein, “approximately” and “about” modify their subject / value to identify the potential for variation in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified herein, “approximately” and “about” may indicate that such dimensions are within tolerances of + / - 10%.

[0275] As used herein, the phrase “communication” includes variations thereof, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication carried out at at least one of periodic intervals, predetermined intervals, non-periodic intervals or one-off events.

[0276] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., special-purpose circuits (ASICs)) configured to perform a particular operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits programmable by instructions to perform one or more particular functions or operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include: programmable microprocessors, such as central processing unit (CPU) that can execute first instructions to perform one or more operations or functions; field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure or construct at least one of the FPGAs, thereby instantiating one or more operations or functions corresponding to the first instructions; graphics processing unit (GPU) that can execute first instructions to perform one or more operations or functions; digital signal processor (DSP) that can execute first instructions to perform one or more operations or functions; XPU; network processing unit (NPU); one or more microcontrollers that can execute first instructions to perform one or more operations or functions; or integrated circuits, such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes a variety of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs)) that can distribute computing tasks to any one or more programmable circuit systems that are suitable and can be used to perform the computing tasks.

[0277] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0278] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0279] A device “configured to” perform a task or function may be configured (e.g., programmed or hardwired at least one of) during manufacturing by the manufacturer to perform at least one of the following operations: perform the function, or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the device’s hardware components and interconnects, or by a combination thereof.

[0280] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnects or their terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0281] In this specification and claims, the “circuit system” described may include one or more circuits. A circuit or device described herein as including certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources and / or current sources) may substantially include only semiconductor elements within a single physical device (e.g., at least one in a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled to at least some passive elements or sources to form the described structure during or after manufacturing, for example, by at least one of an end user or a third party.

[0282] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. For example, a transistor shown and described herein as a single component may actually be multiple transistors. In some such examples, a transistor circuit system may correspond to one or more transistor components. While some elements in the described examples are included in an integrated circuit and others are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as outside the integrated circuit may be included in the integrated circuit, and some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that perform at least one of the following operations: (i) incorporating in / on a semiconductor substrate; (ii) incorporating in a single semiconductor package; (iii) incorporating in the same module; or (iv) incorporating in / on the same printed circuit board.

[0283] The use of the phrase “ground” in the foregoing description includes at least one of the following: chassis ground, ground wire ground, floating ground, virtual ground, digital ground, general ground, or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “generally” preceding a value means + / - 10% of the stated value, or, if the value is zero, indicates a reasonable range of values ​​near zero.

[0284] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An apparatus comprising: A first amplifier circuit system having a first output and a second output; The second amplifier circuit system has an output; A first transistor circuit system having a first terminal and a control terminal; A second transistor circuit system having a first terminal and a control terminal, wherein the control terminal of the second transistor circuit system is coupled to the output of the second amplifier circuit system and the control terminal of the first transistor circuit system; as well as A voltage-delay circuit system having a first input and a second input, wherein the first input of the voltage-delay circuit system is coupled to a first output of a first amplifier circuit system and a first terminal of a first transistor circuit system, and the second input of the voltage-delay circuit system is coupled to a second output of the first amplifier circuit system and a first terminal of the second transistor circuit system.

2. The device of claim 1, wherein the first transistor circuit system comprises: A first transistor having a first terminal and a control terminal, the control terminal of the first transistor being coupled to the output of the second amplifier circuit system and the control terminal of the second transistor circuit system; and The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the first output of the first amplifier circuit system and the first input of the voltage-delay circuit system, and the second terminal of the second transistor is coupled to the first terminal of the first transistor.

3. The device of claim 2, wherein the control terminal of the second transistor circuit system is a first control terminal, the second transistor circuit system further includes a second control terminal, and the first amplifier circuit system includes: A third transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the first input of the voltage-delay circuit system and the first terminal of the second transistor; A fourth transistor having a first terminal and a second terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the third transistor; A fifth transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth transistor is coupled to the second input of the voltage-delay circuit system and the first terminal of the second transistor circuit system. The control terminal of the fifth transistor is coupled to the control terminal of the second transistor, the second control terminal of the second transistor circuit system, and the control terminal of the third transistor. as well as A sixth transistor having a first terminal and a second terminal, the first terminal of the sixth transistor being coupled to the second terminal of the fifth transistor, and the second terminal of the sixth transistor being coupled to the second terminal of the fourth transistor.

4. The device of claim 1, wherein the voltage-delay circuit system comprises: A first capacitor has a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the first output of the first amplifier circuit system and the first terminal of the first transistor circuit system. A second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the second output of the first amplifier circuit system and the first terminal of the second transistor circuit system. as well as A transistor having a terminal coupled to the second terminal of the first capacitor and the second terminal of the second capacitor.

5. The device of claim 1, wherein the first amplifier circuit system has a first input and a second input, and the second amplifier circuit system comprises: A first transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first transistor is coupled to the first input of the first amplifier circuit system; A second transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal of the second transistor is coupled to the second input of the first amplifier circuit system; A current mirror circuit system having an input and an output, wherein the input of the current mirror circuit system is coupled to a first terminal of a first transistor and a first terminal of a second transistor; The third transistor has a first terminal and a second terminal; A current source circuit system having terminals coupled to the second terminal of the first transistor, the second terminal of the second transistor, and the first terminal of the third transistor; as well as A fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor being coupled to the output of the current mirror circuit system and the second terminal of the third transistor, and the control terminal of the fourth transistor being coupled to the control terminal of the first transistor circuit system and the control terminal of the second transistor circuit system.

6. The device of claim 5, wherein the current source circuit system is a first current source circuit system, and the second amplifier circuit system further comprises: The fifth transistor has a first terminal and a control terminal; The second current source circuit system has terminals coupled to the output of the current mirror circuit system, the second terminal of the third transistor, the first terminal of the fourth transistor, and the control terminal of the fifth transistor; A first switch having a first terminal and a second terminal, the first terminal being coupled to the control terminal of the fourth transistor and the first terminal of the fifth transistor; The sixth transistor has a first terminal and a control terminal; The third current source circuit system has terminals; A seventh transistor having a first terminal and a control terminal, the control terminal of the seventh transistor being coupled to the first terminal of the sixth transistor and the terminal of the third current source circuit system; as well as A second switch having a first terminal and a second terminal, the first terminal of the second switch being coupled to the control terminal of the sixth transistor and the first terminal of the seventh transistor, and the second terminal of the second switch being coupled to the control terminal of the first transistor circuit system and the second terminal of the first switch.

7. The device of claim 1, wherein the second amplifier circuit system further has an input, and the device further comprises: A pulse generator circuit system includes a first input, a second input, a first output, and a second output. The first input of the pulse generator circuit system is coupled to the first output of the first amplifier circuit system, the first terminal of the first transistor circuit system, and the first input of the voltage-delay circuit system. The second input of the pulse generator circuit system is coupled to the second output of the first amplifier circuit system, the first terminal of the second transistor circuit system, and the second input of the voltage-delay circuit system. A time-to-digital converter (TDC) circuit system has a first input, a second input, and an output, wherein the first input of the TDC circuit system is coupled to the first output of the pulse generator circuit system, and the second input of the TDC circuit system is coupled to the second output of the pulse generator circuit system. as well as A calibration controller circuit system having an input and an output, the input of the calibration controller circuit system being coupled to the output of the TDC circuit system, and the output of the calibration controller circuit system being coupled to the input of the second amplifier circuit system.

8. The device of claim 7, wherein the first amplifier circuit system further has a first input and a second input, the input of the second amplifier circuit system is the first input, the second amplifier circuit system further has a second input and a third input, and the device further comprises: The sampling circuit system includes: The first switch has a first terminal, a second terminal, and a control terminal; The second switch has terminals; The third switch has a first terminal, a second terminal, and a control terminal; The fourth switch has terminals; as well as A fifth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth switch is coupled to the first terminal of the first switch, the terminal of the second switch, the first input of the first amplifier circuit system, and the second input of the second amplifier circuit system; and the second terminal of the fifth switch is coupled to the first terminal of the third switch, the terminal of the fourth switch, the second input of the first amplifier circuit system, and the third input of the second amplifier circuit system; and The calibration controller circuit system described herein includes: An offset correction circuit system having an input, a first output, a second output, and a third output, wherein the first output of the offset correction circuit system is coupled to the third input of the second amplifier circuit system, and the second output of the offset correction circuit system is coupled to the control terminal of the fifth switch; as well as A gain correction circuit system has an input, a first output, a second output, and a third output. The input of the gain correction circuit system is coupled to the output of the TDC circuit system and the input of the offset correction circuit system. The first output of the gain correction circuit system is coupled to the second terminal of the first switch. The second output of the gain correction circuit system is coupled to the second terminal of the third switch. The third output of the gain correction circuit system is coupled to the control terminal of the first switch and the control terminal of the third switch.

9. An apparatus comprising: An amplifier circuit system having a first input, a second input, a first output, and a second output; A voltage-delay circuit system having a first input and a second input; A pulse generator circuit system having a first input and a second input; as well as A calibration circuit system has a first input, a second input, a first output, and a second output. The first input of the calibration circuit system is coupled to the first input of the amplifier circuit system. The second input of the calibration circuit system is coupled to the second input of the amplifier circuit system. The first output of the calibration circuit system is coupled to the first output of the amplifier circuit system, the first input of the voltage-delay circuit system, and the first input of the pulse generator circuit system. The second output of the calibration circuit system is coupled to the second output of the amplifier circuit system, the second input of the voltage-delay circuit system, and the second input of the pulse generator circuit system.

10. The device of claim 9, wherein the amplifier circuit system is a first amplifier circuit system, and the calibration circuit system comprises: A second amplifier circuit system has a first input, a second input, and an output, wherein the first input of the second amplifier circuit system is coupled to the first input of the first amplifier circuit system, and the second input of the second amplifier circuit system is coupled to the second input of the first amplifier circuit system. A first transistor circuit system having a first terminal and a control terminal, wherein the first terminal of the first transistor circuit system is coupled to the first output of the first amplifier circuit system, the first input of the voltage-delay circuit system and the first input of the pulse generator circuit system; as well as A second transistor circuit system has a first terminal and a control terminal. The first terminal of the second transistor circuit system is coupled to the second output of the first amplifier circuit system, the second input of the voltage-delay circuit system, and the second input of the pulse generator circuit system. The control terminal of the second transistor circuit system is coupled to the output of the second amplifier circuit system and the control terminal of the first transistor circuit system.

11. The device of claim 10, wherein the second amplifier circuit system comprises: A first transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first transistor is coupled to the first input of the first amplifier circuit system; A second transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal of the second transistor is coupled to the second input of the first amplifier circuit system; A current mirror circuit system having an input and an output, wherein the input of the current mirror circuit system is coupled to a first terminal of a first transistor and a first terminal of a second transistor; The third transistor has a first terminal and a second terminal; A current source circuit system having terminals coupled to the second terminal of the first transistor, the second terminal of the second transistor, and the first terminal of the third transistor; as well as A fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor being coupled to the output of the current mirror circuit system and the second terminal of the third transistor, and the control terminal of the fourth transistor being coupled to the control terminal of the first transistor circuit system and the control terminal of the second transistor circuit system.

12. The device of claim 11, wherein the current source circuit system is a first current source circuit system, and the second amplifier circuit system further comprises: The fifth transistor has a first terminal and a control terminal; The second current source circuit system has terminals coupled to the output of the current mirror circuit system, the second terminal of the third transistor, the first terminal of the fourth transistor, and the control terminal of the fifth transistor; A first switch having a first terminal and a second terminal, the first terminal being coupled to the control terminal of the fourth transistor and the first terminal of the fifth transistor; The sixth transistor has a first terminal and a control terminal; The third current source circuit system has terminals; A seventh transistor having a first terminal and a control terminal, the control terminal of the seventh transistor being coupled to the first terminal of the sixth transistor and the terminal of the third current source circuit system; as well as A second switch having a first terminal and a second terminal, the first terminal of the second switch being coupled to the control terminal of the sixth transistor and the first terminal of the seventh transistor, and the second terminal of the second switch being coupled to the control terminal of the first transistor circuit system and the second terminal of the first switch.

13. The device of claim 9, wherein the amplifier circuit system comprises: A first transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the first output of the calibration circuit system and the first input of the voltage-delay circuit system; The second transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first transistor, and the control terminal of the second transistor is coupled to the first input of the calibration circuit system; A third transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second output of the calibration circuit system and the second input of the voltage-delay circuit system, and the control terminal of the third transistor is coupled to the control terminal of the first transistor. as well as A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, the second terminal of the fourth transistor is coupled to the second terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the second input of the calibration circuit system.

14. The device of claim 9, wherein the voltage-delay circuit system comprises: A first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first output of the amplifier circuit system and the first output of the calibration circuit system; A second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the second output of the amplifier circuit system and the second output of the calibration circuit system; as well as A transistor having a terminal coupled to the second terminal of the first capacitor and the second terminal of the second capacitor.

15. The device of claim 9, wherein the calibration circuit system further has a third input, and the device further comprises: A time-to-digital converter (TDC) circuit system has a first input, a second input, and an output, wherein the first input of the TDC circuit system is coupled to the first output of the pulse generator circuit system, and the second input of the TDC circuit system is coupled to the second output of the pulse generator circuit system. as well as A calibration controller circuit system having an input and an output, the input of the calibration circuit system being coupled to the output of the TDC circuit system, and the output of the calibration circuit system being coupled to the third input of the calibration circuit system.

16. The device according to claim 15, further comprising: The sampling circuit system includes: The first switch has a first terminal, a second terminal, and a control terminal; The second switch has terminals; The third switch has a first terminal, a second terminal, and a control terminal; The fourth switch has terminals; as well as A fifth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth switch is coupled to the first terminal of the first switch, the terminal of the second switch, and the first input of the calibration circuit system; and the second terminal of the fifth switch is coupled to the first terminal of the third switch, the terminal of the fourth switch, and the second input of the calibration circuit system; and The calibration controller circuit system described herein includes: An offset correction circuit system having an input, a first output, a second output, and a third output, wherein the first output of the offset correction circuit system is coupled to the third input of the calibration circuit system, and the second output of the offset correction circuit system is coupled to the control terminal of the fifth switch; as well as A gain correction circuit system has an input, a first output, a second output, and a third output. The input of the gain correction circuit system is coupled to the output of the TDC circuit system and the input of the offset correction circuit system. The first output of the gain correction circuit system is coupled to the second terminal of the first switch. The second output of the gain correction circuit system is coupled to the second terminal of the third switch. The third output of the gain correction circuit system is coupled to the control terminal of the first switch and the control terminal of the third switch.

17. An apparatus comprising: An amplifier circuit system that has input and output; Voltage-delay circuit system, which has an input; A calibration circuit system having an input and an output, the input of the calibration circuit system being coupled to the input of the amplifier circuit system, and the output of the calibration circuit system being coupled to the output of the amplifier circuit system and the input of the voltage-delay circuit system, the calibration circuit system being configured to: The common-mode voltage at the output of the amplifier circuit system is adjusted accordingly to the offset correction value; and The common-mode voltage at the output of the amplifier circuit system is adjusted in accordance with the gain correction value.

18. The device of claim 17, wherein the voltage-delay circuit system further has an output, and the device further comprises: A pulse generator circuit system having an input and an output, wherein the input of the pulse generator circuit system is coupled to the output of the voltage-delay circuit system; as well as A time-to-digital converter (TDC) circuit system having an input coupled to the output of the pulse generator circuit system.

19. The device of claim 18, wherein the input of the calibration circuit system is a first input, the calibration circuit system further has a second input, the TDC circuit system further has an output, and the device further includes a calibration controller circuit system having an input and an output, the input of the calibration controller circuit system being coupled to the output of the TDC circuit system, the output of the calibration controller circuit system being coupled to the second input of the calibration circuit system, the calibration controller circuit system being configured to: The common-mode voltage offset of the amplifier circuit system and the voltage-delay circuit system is determined based on the output of the TDC circuit system. The common-mode voltage offset is adjusted using the reference common-mode voltage of the calibration circuit system; and The offset correction value is determined based on the reference common-mode voltage.

20. The device of claim 17, wherein the amplifier circuit system is a first amplifier circuit system, the device further comprising: The second amplifier circuit system has input and output; and The calibration circuit system is further configured to: The common-mode voltage of the output of the second amplifier circuit system is adjusted based on the input of the second amplifier circuit system.

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