High-precision digital-to-analog converter testing system and method

Abstract

This invention provides a high-precision digital-to-analog converter (DAC) testing system and method. The system includes a control module, a DAC timing generation module, an analog-to-digital converter (ADC) timing generation module, a timing delay adjustment module, and an ADC data acquisition module. The DAC timing generation module generates a read memory signal and a conversion signal; the ADC timing generation module generates a serial clock signal and a start conversion signal; the timing delay adjustment module adjusts the delay of the serial clock signal and the start conversion signal so that the start conversion signal is within the stable sampling time window of the DAC's output voltage; the ADC data acquisition module acquires the analog signal triggered by the delayed start conversion signal. This application, through refined delay compensation in the digital domain, avoids level switching glitches in sampling, significantly improving the testing accuracy of dynamic and static indicators.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a high-precision digital-to-analog converter testing system and method. Background Technology

[0002] In general testing schemes for digital-to-analog converters (DACs), whether it's automated test equipment (ATE) wafer testing or package-level testing, conversion glitches in the DAC can significantly impact the test results. Although filtering is typically used at the DAC output, it cannot completely eliminate glitches.

[0003] During dynamic testing, waveform generators typically output single-tone sine waves. Currently, there are two main approaches to dynamic testing: one is direct measurement using a spectrum analyzer; the other is data acquisition via a high-precision analog-to-digital converter (ADC) followed by analysis. To reduce the energy of glitches in the ADC output signal, a buffer or filter (usually an active filter) is typically added to the ADC output to remove out-of-band noise and high-order harmonics, thereby reducing aliasing interference to the subsequent high-precision sampling by the ADC.

[0004] However, existing testing methods have the following drawbacks: First, while glitches can be reduced by filters, they cannot be completely eliminated, and filtering also affects the effective signal level. Second, because spectrum analyzers use high sampling rates, it is difficult to achieve precise synchronization between the sampling points and the digital-to-analog converter (DAC) output using clock synchronization methods. Finally, although using an DAC acquisition system facilitates system integration, variations in semiconductor manufacturing processes result in clock deviations between different process corners and between different chips, leading to varying delays and energy levels in glitches. These problems severely restrict the accuracy and reliability of DAC testing.

[0005] Therefore, there is an urgent need in this field for a new system synchronization method and a high-precision testing system to eliminate the adverse effects of glitches generated by digital-to-analog converters on testing accuracy. Summary of the Invention

[0006] The technical problem this application aims to solve is that during the testing of digital-to-analog converters (DACs), conversion glitches in the DAC can significantly affect the test results, and traditional filtering methods cannot completely eliminate glitches. Furthermore, due to process variations, the delay and energy of glitches differ between different chips, and existing sampling systems struggle to achieve high-precision synchronization with the DAC output sampling, resulting in inaccurate test performance.

[0007] This application provides a high-precision digital-to-analog converter testing system, including:

[0008] Control module;

[0009] The digital-to-analog converter timing generation module is connected to the control module and is used to generate a read memory signal. The read memory signal is used to trigger waveform data output to the digital-to-analog converter under test. After delay processing, the read memory signal generates a conversion signal to the digital-to-analog converter under test.

[0010] The analog-to-digital converter timing generation module is connected to the control module and is used to generate a serial clock signal and a start conversion signal.

[0011] The timing delay adjustment module is connected to the analog-to-digital converter timing generation module. It is used to adjust the delay of the serial clock signal and the start conversion signal so that the start conversion signal is within the stable sampling time window of the output voltage of the digital-to-analog converter under test.

[0012] The analog-to-digital converter (ADC) data acquisition module is connected to the timing delay adjustment module and the ADC under test. It is used to acquire the analog signal output by the ADC under test when triggered by the start conversion signal after the delay adjustment.

[0013] Preferably, the timing delay adjustment module includes a first delay adjustment unit and a second delay adjustment unit connected in series, wherein the adjustment accuracy of the first delay adjustment unit is lower than that of the second delay adjustment unit.

[0014] Preferably, the first delay adjustment unit includes a counter.

[0015] Preferably, the second delay adjustment unit includes an adjustable delay unit in a field-programmable gate array.

[0016] Preferably, the delay adjustment formula of the adjustable delay unit is: tDelay = m*(1 / f)+n*Δt, where tDelay is the total delay time, m is the upward count value of the counter, f is the input clock frequency, n is the delay control input value, and Δt is the single-step adjustment accuracy of the adjustable delay unit.

[0017] Preferably, the input clock frequency is 400MHz and the single-step adjustment accuracy is 78ps.

[0018] Preferably, the adjustment step of the first delay adjustment unit is 2ns.

[0019] Preferably, the adjustable delay unit includes 32 taps, with a maximum delay of 2.469 ns.

[0020] Preferably, the delay time of the start conversion signal relative to the read memory signal is greater than the minimum delay time and less than the maximum delay time. The minimum delay time is the time from the rising edge of the conversion signal to the stabilization of the output voltage glitches of the digital-to-analog converter under test, and the maximum delay time is the rising edge time of the next conversion signal.

[0021] Preferably, it also includes a digital-to-analog converter waveform memory module, which is connected to the control module and the digital-to-analog converter timing generation module, and is used to store waveform data and output waveform data when triggered by a read memory signal.

[0022] Preferably, it also includes a host computer, which is connected to the control module and the analog-to-digital converter data acquisition module, and is used to send control commands and receive data acquired by the analog-to-digital converter data acquisition module.

[0023] Preferably, the control module includes a microcontroller.

[0024] This application also provides a high-precision digital-to-analog converter (DAC) testing method, applied to the high-precision DAC testing system described above, including:

[0025] Step 1: Generate a read memory signal, trigger waveform data output to the digital-to-analog converter under test (DAC) through the read memory signal, and generate a conversion signal to the DAC after delay processing.

[0026] Step 2: Generate a serial clock signal and a start conversion signal;

[0027] Step 3: Adjust the delay of the serial clock signal and the start conversion signal so that the start conversion signal is within the stable sampling time window of the output voltage of the digital-to-analog converter under test; Step 4: Under the trigger of the start conversion signal after the delay adjustment, acquire the analog signal output by the digital-to-analog converter under test.

[0028] Preferably, in step three, the delay adjustment of the serial clock signal and the start conversion signal includes: performing delay adjustment through a first delay adjustment unit and a second delay adjustment unit connected in series, wherein the adjustment accuracy of the first delay adjustment unit is lower than that of the second delay adjustment unit.

[0029] Preferably, in step three, the delay adjustment of the first delay adjustment unit is performed by a counter.

[0030] Preferably, in step three, the delay of the second delay adjustment unit is adjusted by the adjustable delay unit in the field-programmable gate array.

[0031] Preferably, in step three, the total delay time of the delay adjustment satisfies the formula: tDelay = m*(1 / f)+n*Δt, where tDelay is the total delay time, m is the upward count value of the counter, f is the input clock frequency, n is the delay control input value, and Δt is the single-step adjustment accuracy of the adjustable delay unit.

[0032] Preferably, in step three, the delay time of the start conversion signal relative to the read memory signal is greater than the minimum delay time and less than the maximum delay time. The minimum delay time is the time from the rising edge of the conversion signal to the stabilization of the output voltage spike of the digital-to-analog converter under test, and the maximum delay time is the rising edge time of the next conversion signal.

[0033] Preferably, in step three, before adjusting the delay of the serial clock signal and the start conversion signal, the method further includes: detecting the rising and falling edges of the serial clock signal and the start conversion signal to generate serial clock rising and falling edge signals and start conversion rising and falling edge signals.

[0034] Preferably, in step three, the delay time is manually adjusted by the controller to calibrate the sampling window.

[0035] As described above, the high-precision digital-to-analog converter testing system and method of the present invention have the following beneficial effects:

[0036] By constructing a cascaded delay compensation link consisting of a first delay adjustment unit and a second delay adjustment unit in the digital domain, sub-nanosecond-level fine adjustment of the sampling timing of the analog-to-digital converter (ADC) is achieved. This scheme enables the sampling action to precisely avoid the nonlinear glitches generated by the ADC at the moment of level transition, thereby significantly reducing the interference of out-of-band noise and high-order harmonics on the test results without the need for complex analog filters. Since the sampling points are locked within the stable window of the output voltage, the reconstructed waveform has extremely high fidelity and can more realistically and accurately reflect the chip's key performance indicators such as signal-to-noise ratio, total harmonic distortion, and integral nonlinearity. In addition, the system has good process compatibility and flexibility, effectively compensating for timing offsets introduced by individual chip differences, circuit board trace delays, and environmental temperature drift, greatly improving the reliability of testing and the accuracy of yield assessment in mass production testing. Attached Figure Description

[0037] Figure 1 The diagram shows the synchronous test timing of the high-precision digital-to-analog converter test system of the present invention.

[0038] Figure 2 The diagram shows the functional modules of the high-precision digital-to-analog converter testing system of the present invention.

[0039] Figure 3The diagram shown is a schematic diagram of the timing delay adjustment module of the high-precision digital-to-analog converter test system of the present invention.

[0040] Figure 4 The diagram shown is a schematic representation of the overall implementation scheme of the high-precision digital-to-analog converter testing system of the present invention.

[0041] Figure 5 The diagram shown is a flowchart illustrating the high-precision digital-to-analog converter testing method of the present invention.

[0042] Figure 6 The diagram shows the sampling window calibration process of the high-precision digital-to-analog converter test system of the present invention. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] This application provides a high-precision digital-to-analog converter testing system, such as... Figure 2 and Figure 4 As shown, it includes:

[0045] Control module 101;

[0046] The digital-to-analog converter timing generation module 106 is connected to the control module 101 and is used to generate a read memory signal RD_MEM. The read memory signal RD_MEM is used to trigger waveform data output to the digital-to-analog converter under test 109. After delay processing, the read memory signal RD_MEM generates a conversion signal CONV to the digital-to-analog converter under test 109.

[0047] The analog-to-digital converter timing generation module 103 is connected to the control module 101 and is used to generate the serial clock signal SCLK and the start conversion signal STC.

[0048] The timing delay adjustment module 104 is connected to the analog-to-digital converter timing generation module 103 and is used to adjust the delay of the serial clock signal SCLK and the start conversion signal STC so that the start conversion signal STC is within the stable sampling time window tSW of the output voltage VOUT of the digital-to-analog converter under test 109.

[0049] The analog-to-digital converter data acquisition module 105 is connected to the timing delay adjustment module 104 and the digital-to-analog converter under test 109. It is used to acquire the analog signal output by the digital-to-analog converter under test 109 when triggered by the start conversion signal STC_d2 after delay adjustment.

[0050] This system achieves high-precision alignment between the sampling phase of the analog-to-digital converter (ADC) and the output waveform of the digital-to-analog converter (DAC) by constructing a multi-level delay compensation link at the digital logic level. This synchronous architecture effectively avoids dynamic glitches generated during quantization level switching in the DAC, thus significantly improving the test system's ability to capture signal integrity without relying on complex analog filtering networks. Through this precise timing control, the system can capture dynamic performance indicators closer to the chip's physical limits, resulting in more accurate parameters such as signal-to-noise ratio (SNR) and total harmonic distortion (THD).

[0051] In some embodiments, such as Figure 3 As shown, the timing delay adjustment module 104 includes a first delay adjustment unit 1041 and a second delay adjustment unit 1042 connected in series. The adjustment accuracy of the first delay adjustment unit 1041 is lower than that of the second delay adjustment unit 1042. The first delay adjustment unit 1041 is mainly responsible for covering a large time span, while the second delay adjustment unit 1042 is responsible for picosecond-level phase fine-tuning at the microscopic level. This cascaded design with hierarchical precision ensures that the system can adapt to the long-period delay requirements under low sampling rates and also meet the stringent requirements for sampling point positions under high sampling rates. The delay adjustment module 104 can also integrate automatic calibration logic to dynamically correct the delay parameters by monitoring the phase drift of the system clock in real time, thereby offsetting the impact of ambient temperature changes on circuit propagation delay. Figure 3 The calibration module requires a 200MHz clock input to ensure accurate precision unit delay of 78ps under different operating conditions, such as different voltages and temperatures.

[0052] In some embodiments, the first delay adjustment unit 1041 includes a counter. The counter increments or decrements based on a high-speed reference clock provided by the system, adjusting the logic delay of the signal in the digital domain by changing the count value. In some embodiments, the adjustment step of the first delay adjustment unit 1041 is 2ns. Besides a synchronous counter, the first delay adjustment unit 1041 can also be implemented using a delay line array based on multiplexer switching, a carry chain structure within a programmable logic device, or a shift register chain. A shift register chain can provide discrete and stable delay steps by adjusting the number of register stages through which the data flows. Another alternative is to use a phase-locked loop to generate a set of clock clusters with a fixed phase difference, and to achieve the first delay adjustment by switching these clock phases using a high-speed switch.

[0053] In some embodiments, the second delay adjustment unit 1042 includes an adjustable delay unit within a field-programmable gate array (FPGA). The adjustable delay unit can be implemented using dedicated hardware primitives within the FPGA, such as the ODELAYE2 cell. Besides dedicated primitives, the second delay adjustment unit 1042 can also be implemented using a voltage-controlled delay line composed of an inverter chain, a phase interpolator based on a phase-locked loop (PLL), or a charge pump delay circuit with high-resolution characteristics. The phase interpolator can generate a continuously adjustable output signal by weighting and mixing two adjacent master clock phases, thereby providing a time resolution far exceeding the system clock frequency limit. In an analog front-end implementation, the second delay adjustment unit 1042 can also employ a current-starved delay unit, linearly controlling the signal propagation delay by adjusting the magnitude of the bias current.

[0054] In some embodiments, the delay adjustment formula for the adjustable delay unit is: tDelay = m*(1 / f)+n*Δt, where tDelay is the total delay time, m is the up-count value of counter 1041, f is the input clock frequency, n is the delay control input value, and Δt is the single-step adjustment accuracy of the adjustable delay unit. In some embodiments, the input clock frequency f is 400MHz, and the single-step adjustment accuracy Δt is 78ps. This formula provides a precise configuration model for the control module 101, enabling the system to automatically calculate and issue hardware register parameters according to the preset sampling target. In actual deployment, this formula can also introduce a calibration factor to compensate for the fixed phase offset introduced by parasitic inductance and capacitance of the circuit board traces. In addition, the system can periodically measure the actual single-step adjustment accuracy Δt through a self-test program and dynamically update the formula parameters to ensure the linearity of delay control under different process angles and voltage conditions.

[0055] In some embodiments, the adjustment step of the first delay adjustment unit 1041 is 2 ns, the adjustable delay unit includes 32 taps, and the maximum delay is 2.469 ns. These parameters are designed to ensure that the adjustment range of the second delay adjustment unit 1042 can cover at least one complete step cycle of the first delay adjustment unit 1041, thereby achieving seamless delay adjustment. The number of taps can be expanded to 64 or more according to actual accuracy requirements to further improve the fineness of phase control.

[0056] In some embodiments, such as Figure 1As shown, the delay time of the start-up conversion signal STC relative to the read memory signal RD_MEM is greater than the minimum delay time but less than the maximum delay time. The minimum delay time is the time from the rising edge of the conversion signal CONV to the stabilization of the output voltage glitches of the digital-to-analog converter 109 under test, and the maximum delay time is the rising edge time of the next conversion signal CONV. By precisely positioning the sampling action in the stable segment of the voltage waveform, the system can effectively avoid charge injection glitches and clock feedthrough noise caused by the internal switching of the digital-to-analog converter. This timing strategy ensures that the analog-to-digital converter captures the steady-state value of the quantization level, thereby significantly reducing the interference of nonlinear distortion on the test results. The width of the stable sampling time window tSW depends on the setup and hold time specifications of the chip under test. The system adjusts the delay parameters to place the sampling point as close to the center of the window as possible to obtain the maximum anti-clock jitter margin.

[0057] In some embodiments, a digital-to-analog converter (DAC) waveform memory module 108 is also included. The DAC waveform memory module 108 is connected to the control module 101 and the DAC timing generation module 106, and is used to store waveform data and output waveform data D[N:0] triggered by the read memory signal RD_MEM. The memory module 108 can be a dual-port random access memory, a first-in-first-out buffer, or a synchronous dynamic random access memory. The read memory signal RD_MEM serves as the synchronization clock for data outflow, ensuring that the digital signal is transmitted to the chip under test at a constant rate. The memory module 108 can also support various waveform modes, such as single-tone sine waves, two-tone signals, or arbitrary function waveforms.

[0058] In some embodiments, a host computer 110 is also included. The host computer 110 is connected to the control module 101 and the analog-to-digital converter data acquisition module 105, and is used to send control commands and receive data acquired by the analog-to-digital converter data acquisition module 105. The host computer 110 can be a personal computer, an industrial control host, or an automated testing device. The host computer 110 interacts with the testing hardware through a high-speed communication link, such as the Peripheral Component Interconnect Standard Extension Interface (PCIe). It is responsible not only for configuring test parameters and procedures, but also for performing fast Fourier transforms, spectrum analysis, and performance index calculations on massive amounts of acquired data. The software of the host computer 110 can provide an intuitive graphical interface, allowing engineers to observe waveform quality in real time and manually fine-tune delay parameters to achieve optimal test results.

[0059] In some embodiments, the control module 101 includes a microcontroller. The microcontroller can be integrated within a field-programmable gate array (FPGA) or a separate processor chip. The control module 101 is responsible for parsing instructions from the host computer 110, coordinating the enable states of various timing modules within the system, and executing delay calibration algorithms. Besides a microcontroller, the control module 101 can also be implemented using a hard-wired finite state machine, providing faster response speeds through pure hardware logic. In multi-channel testing applications, the control module 101 can also manage synchronization and data arbitration between multiple acquisition channels.

[0060] This application also provides a high-precision digital-to-analog converter testing method, such as... Figure 5 As shown, it includes:

[0061] Step 1: Generate a read memory signal RD_MEM. This signal triggers waveform data output to the digital-to-analog converter (DAC) under test (DUT) 109. After a delay, the read memory signal RD_MEM is used to generate a conversion signal CONV, which is then sent to the DUT 109. In Step 1, the generation of the read memory signal RD_MEM is controlled by the state machine within the DUT timing generation module 106. The waveform data can be pre-loaded into a cache. The delay ensures that the levels on the data bus are fully stable before the conversion signal CONV arrives, thus meeting the setup and hold time requirements of the DUT. The pulse width and polarity of the conversion signal CONV can be programmed and configured according to the interface protocol of the DUT to ensure optimal conversion efficiency.

[0062] Step 2: Generate the serial clock signal SCLK and the start conversion signal STC. In step 2, these signals can be generated by the phase-locked loop or frequency divider inside the field-programmable gate array (FPGA) to ensure extremely low clock jitter. The frequency of the serial clock signal SCLK can be dynamically adjusted according to the maximum transmission rate of the analog-to-digital converter (ADC).

[0063] Step 3: Adjust the delay of the serial clock signal SCLK and the start conversion signal STC so that the start conversion signal STC falls within the stable sampling time window tSW of the output voltage VOUT of the digital-to-analog converter under test 109. In step 3, the delay adjustment is jointly completed by the cascaded first delay adjustment unit 1041 and second delay adjustment unit 1042. The system achieves full coverage of the sampling phase by adjusting the counter value m and the tap value n. To improve calibration efficiency, step 3 can employ an automatic search algorithm to automatically lock the optimal delay position by monitoring the signal-to-noise ratio of the acquired data.

[0064] In some embodiments, such as Figure 6As shown, the timing calibration process in step three specifically includes: First, after the chip under test is powered on, the data in the waveform memory module 108 of the digital-to-analog converter is set, for example, to alternating values ​​such as 0x100, 0x200, 0x100, and 0x200, so that the digital-to-analog converter outputs a square wave signal that is easy to observe. Next, the delay control value of the second delay adjustment unit 1042 (such as ODELAYE2) in the delay adjustment module 104 based on the field-programmable gate array is initialized to 0, and the module is enabled. After the digital-to-analog converter is started, the waveforms of the start conversion signal STC, the conversion signal CONV, and the output voltage VOUT are observed using an oscilloscope. By observation, the start conversion signal STC is first set to the leftmost starting position of the stable sampling time window tSW, the initial total delay time tDelay is measured, and the initial count value m of the counter 1041 is calculated accordingly. Then, a coarse adjustment loop is entered, by increasing the counter value m and restarting the delay adjustment module, until the start conversion signal STC approaches the target sampling area. After coarse adjustment, the fine adjustment cycle begins, gradually increasing the tap value n of the second delay adjustment unit 1042 until the start conversion signal STC is precisely within the stable sampling time window tSW, finally ending with sequential correction. This left-to-right scanning strategy ensures the monotonicity and reliability of the calibration process and can effectively handle complex trace delay situations.

[0065] In some embodiments, before adjusting the delay of the serial clock signal SCLK and the start transition signal STC in step three, the method further includes: detecting the rising and falling edges of the serial clock signal SCLK and the start transition signal STC to generate serial clock rising and falling edge signals SCLK_P and SCLK_N, and start transition rising and falling edge signals STC_P and STC_N. The edge detection process can utilize high-speed sampling logic to capture transient transitions in the signal, providing a precise time reference for subsequent delay alignment. To eliminate high-frequency noise interference on the transmission line, the edge detection logic can also integrate digital filtering or hysteresis comparison functions.

[0066] Step 4: Triggered by the delayed start conversion signal STC_d2, the analog signal output by the digital-to-analog converter under test (DAC) 109 is acquired. In step 4, the acquired analog signal is converted into a digital sequence by a high-precision DAC. The acquisition process can use either continuous stream mode or burst mode. To improve data throughput, the system can use multiple DACs to acquire data in parallel and perform data interleaving. The acquired data is stored in a local high-speed buffer in real time and then uploaded in batches to the host computer 110 via a high-speed bus for in-depth analysis. Because the sampling points avoid the glitches with severe nonlinear distortion, the reconstructed waveform has extremely high fidelity, thus enabling a more accurate evaluation of key static indicators such as integral nonlinearity and differential nonlinearity of the DAC 109 under test.

[0067] like Figure 4 As shown, the entire system consists of a computer host 110, a field-programmable gate array (FPGA), a digital-to-analog converter (DAC) test board, and an DAC data acquisition module 105. The FPGA can be internally divided into multiple clock domains, and cross-clock domain data exchange is performed through an asynchronous first-in-first-out (FIFO) buffer to ensure the integrity of high-speed signals. The DAC test board can include a precision voltage reference source and a low-noise linear regulator to provide clean operating power to the chip under test. The DAC data acquisition module 105 can integrate high-performance front-end conditioning circuitry, including a programmable gain amplifier and an anti-aliasing filter, to further improve measurement accuracy under small signals. The system uses a 10MHz external reference clock input to the clock module 102. The clock module 102 uses phase-locked loop (PLL) technology to output mutually synchronized high-frequency clock signals such as 200MHz and 400MHz, providing a unified time reference for the entire system. Since the system uses two frequency-doubled clocks in phase, the asynchronous FIFO buffer can be omitted.

[0068] In some embodiments, the read memory signal RD_MEM generated by the digital-to-analog converter timing generation module 106 is directly connected to the digital-to-analog converter waveform memory module 108, outputting waveform data D[N:0] to the digital-to-analog converter test board (the digital-to-analog converter under test 109). The read memory signal RD_MEM generates a conversion signal CONV through the delay unit 107, ensuring that the conversion signal CONV and the waveform data D[N:0] meet the timing requirements of the digital-to-analog converter test board. The delay amount of the delay unit 107 can be pre-compensated according to the physical trace length on the test board. The duty cycle of the conversion signal CONV can be optimized according to the characteristics of the sample-and-hold circuit inside the digital-to-analog converter under test to reduce the charge injection effect at the moment of sampling. The bit width of the waveform data D[N:0] can be flexibly configured according to the quantization accuracy of the chip under test, supporting a full range of tests from low-resolution high-speed digital-to-analog converters to high-resolution precision digital-to-analog converters.

[0069] In some embodiments, the analog-to-digital converter (ADC) data acquisition module 105 is connected to the computer host 110 via a high-speed interface such as the Peripheral Component Interconnect (PCI) standard expansion interface. After calibration, the ADC data acquisition module 105 is controlled and data is acquired. Data is received at the computer host 110 and saved as a data file for back-end data analysis software to perform data analysis. The data file can be stored using an efficient binary compression format to handle the large amount of data generated by long-term high-frequency sampling. The back-end analysis software can provide rich visualization tools, such as real-time spectrum graphs, integral nonlinearity curves, and eye diagrams, to help test engineers comprehensively evaluate various performance indicators of the chip. The analysis software can also integrate automated test report generation functions, directly exporting test results as standardized technical documents.

[0070] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-precision digital-to-analog converter testing system, characterized in that, include: Control module; A digital-to-analog converter timing generation module, connected to the control module, is used to generate a read memory signal. The read memory signal is used to trigger waveform data output to the digital-to-analog converter under test. After delay processing, the read memory signal generates a conversion signal to the digital-to-analog converter under test. An analog-to-digital converter timing generation module, connected to the control module, is used to generate a serial clock signal and a start conversion signal; A timing delay adjustment module, connected to the analog-to-digital converter timing generation module, is used to adjust the delay of the serial clock signal and the start conversion signal so that the start conversion signal is within the stable sampling time window of the output voltage of the digital-to-analog converter under test; The analog-to-digital converter data acquisition module is connected to the timing delay adjustment module and the digital-to-analog converter under test, and is used to acquire the analog signal output by the digital-to-analog converter under test when triggered by the start conversion signal after delay adjustment.

2. The high-precision digital-to-analog converter testing system according to claim 1, characterized in that: The timing delay adjustment module includes a first delay adjustment unit and a second delay adjustment unit connected in series. The adjustment accuracy of the first delay adjustment unit is lower than that of the second delay adjustment unit.

3. The high-precision digital-to-analog converter testing system according to claim 2, characterized in that: The coarse delay adjustment unit includes a counter.

4. The high-precision digital-to-analog converter testing system according to claim 3, characterized in that: The fine delay adjustment unit includes an adjustable delay unit in a field-programmable gate array.

5. The high-precision digital-to-analog converter testing system according to claim 4, characterized in that: The delay adjustment formula of the adjustable delay unit is: tDelay = m*(1 / f)+n*Δt, where tDelay is the total delay time, m is the upward count value of the counter, f is the input clock frequency, n is the delay control input value, and Δt is the single-step adjustment accuracy of the adjustable delay unit.

6. The high-precision digital-to-analog converter testing system according to claim 5, characterized in that: The input clock frequency is 400MHz, and the single-step adjustment accuracy is 78ps.

7. The high-precision digital-to-analog converter testing system according to claim 6, characterized in that: The adjustment step of the coarse delay adjustment unit is 2ns.

8. The high-precision digital-to-analog converter testing system according to claim 7, characterized in that: The adjustable delay unit includes 32 taps, with a maximum delay of 2.469 ns.

9. The high-precision digital-to-analog converter testing system according to claim 1, characterized in that: The delay time of the start-up conversion signal relative to the read memory signal is greater than the minimum delay time and less than the maximum delay time. The minimum delay time is the time from the rising edge of the conversion signal to the stabilization of the output voltage glitches of the digital-to-analog converter under test. The maximum delay time is the time of the next rising edge of the conversion signal.

10. The high-precision digital-to-analog converter testing system according to claim 1, characterized in that: It also includes a digital-to-analog converter waveform memory module, which is connected to the control module and the digital-to-analog converter timing generation module, and is used to store waveform data and output the waveform data when triggered by the read memory signal.

11. The high-precision digital-to-analog converter testing system according to claim 1, characterized in that: It also includes a host computer, which is connected to the control module and the analog-to-digital converter data acquisition module, and is used to send control commands and receive data acquired by the analog-to-digital converter data acquisition module.

12. The high-precision digital-to-analog converter testing system according to claim 1, characterized in that: The control module includes a microcontroller.

13. A high-precision digital-to-analog converter (DAC) testing method, applied to the high-precision DAC testing system as described in any one of claims 1 to 12, characterized in that, include: Step 1: Generate a read memory signal, trigger waveform data output to the digital-to-analog converter under test (DAC) through the read memory signal, and generate a conversion signal to the DAC after delay processing. Step 2: Generate a serial clock signal and a start conversion signal; Step 3: Adjust the delay of the serial clock signal and the start-up conversion signal so that the start-up conversion signal is within the stable sampling time window of the output voltage of the digital-to-analog converter under test; Step 4: Under the triggering of the start conversion signal after delay adjustment, the analog signal output by the digital-to-analog converter under test is acquired.

14. The high-precision digital-to-analog converter testing method according to claim 13, characterized in that: In step three, the delay adjustment of the serial clock signal and the start conversion signal includes: performing delay adjustment through a first delay adjustment unit and a second delay adjustment unit connected in series, wherein the adjustment accuracy of the first delay adjustment unit is lower than that of the second delay adjustment unit.

15. The high-precision digital-to-analog converter testing method according to claim 14, characterized in that: In step three, the delay of the first delay adjustment unit is adjusted using a counter.

16. The high-precision digital-to-analog converter testing method according to claim 15, characterized in that: In step three, the delay of the second delay adjustment unit is adjusted by the adjustable delay unit in the field programmable gate array.

17. The high-precision digital-to-analog converter testing method according to claim 17, characterized in that: In step three, the total delay time of the delay adjustment satisfies the formula: tDelay = m*(1 / f)+n*Δt, where tDelay is the total delay time, m is the upward count value of the counter, f is the input clock frequency, n is the delay control input value, and Δt is the single-step adjustment accuracy of the adjustable delay unit.

18. The high-precision digital-to-analog converter testing method according to claim 13, characterized in that: In step three, the delay time of the start conversion signal relative to the read memory signal is greater than the minimum delay time and less than the maximum delay time. The minimum delay time is the time from the rising edge of the conversion signal to the stabilization of the output voltage glitches of the digital-to-analog converter under test, and the maximum delay time is the time of the next rising edge of the conversion signal.

19. The high-precision digital-to-analog converter testing method according to claim 13, characterized in that: In step three, before adjusting the delay of the serial clock signal and the start-up conversion signal, the method further includes: detecting the rising and falling edges of the serial clock signal and the start-up conversion signal to generate serial clock rising and falling edge signals and start-up conversion rising and falling edge signals.

20. The high-precision digital-to-analog converter testing method according to claim 13, characterized in that: In step three, the delay time is manually adjusted via the controller to calibrate the sampling window.

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