High linearity phase interpolator based on digital predistortion technique
By optimizing the control weights of the phase interpolator in the digital domain and employing digital predistortion technology, the linearity problem of the four-phase input PI was solved, resulting in a phase interpolator with high energy efficiency and high reliability. The peak integral nonlinearity and differential nonlinearity are both less than 0.5 LSB.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI JIAOTONG UNIV
- Filing Date
- 2026-05-09
- Publication Date
- 2026-07-31
AI Technical Summary
Existing four-phase input phase interpolators have inherent integral nonlinearity in linearity, which leads to increased power consumption and chip area. At the same time, the control algorithm is limited by traditional complementary weight constraints and lacks sufficient degrees of freedom to compensate for the non-ideal characteristics of the circuit.
A high-linearity phase interpolator based on digital predistortion technology is adopted. By optimizing the PI control weights in the digital domain, and utilizing a multi-phase clock generator, a digital predistortion decoder, and an analog interpolation core, independent control of non-complementary weights is achieved, generating two completely independent weight combinations for phase vector synthesis.
Without increasing the complexity of analog circuitry or the input clock phase, it suppresses noise coupling, ensures extremely low clock jitter and excellent signal purity, and provides a highly energy-efficient and highly reliable phase interpolator with peak integral nonlinearity and differential nonlinearity both less than 0.5 LSB.
Smart Images
Figure CN122496047A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a technology in the field of digital signal processing, specifically a phase interpolator based on digital predistortion technology with a maximum absolute deviation not exceeding 0.5 LSB. Background Technology
[0002] As a core component of digital-to-analog phase conversion, the phase interpolator (PI) directly determines the timing margin of the data link. Existing four-phase input PIs, when using linear weight control, exhibit severe inherent integral nonlinearity (INL), typically reaching 3.0 LSB peak-to-peak values. To improve linearity, current technologies often increase the number of input phases (e.g., 8 phases) or employ complex cancellation architectures, such as twin-phase PIs. However, this inevitably leads to a significant increase in power consumption and chip area. Furthermore, the control algorithm remains constrained by traditional complementary weight constraints, meaning the sum of the I / Q control weights is a fixed value. This limits the phase search space to a one-dimensional path, lacking sufficient degrees of freedom to compensate for the circuit's inherent non-ideal characteristics. Summary of the Invention
[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes a high-linearity phase interpolator based on digital predistortion technology. By optimizing the PI control weights in the digital domain, it suppresses noise coupling without increasing the complexity of analog circuits or the input clock phase, ensuring extremely low clock jitter and excellent signal purity. This provides a core technology solution for ultra-high-speed wired data links that combines high energy efficiency and high reliability.
[0004] This invention is achieved through the following technical solution:
[0005] This invention relates to a high linearity phase interpolator based on digital predistortion technology, comprising: a multi-phase clock generator, a digital predistortion decoder, and an analog interpolation core, wherein: the multi-phase clock generator uses a current-mode divider to generate four mutually orthogonal clock signals; the digital predistortion decoder employs an approximately sinusoidal weight allocation strategy in a two-dimensional N×N discrete lattice space, accurately mapping the input K-bit phase control code to an integer weight combination that most closely approximates the ideal circular motion through a lookup table (LUT), generating two sets of completely independent non-complementary weights; the analog interpolation core synthesizes vectors of corresponding phases in the complex plane based on the non-complementary weights and the clock signals.
[0006] The lookup table is obtained in the following way:
[0007] Step 1: Obtain the phase constellation diagram by scanning the weight matrix: Through simulation, traverse and obtain the actual synthesized phase and amplitude corresponding to all weight combinations in this two-dimensional space, and establish an N × N (e.g., 63 × 63) two-dimensional discrete weight combination for independently controlled I-channel and Q-channel DACs, specifically including:
[0008] 1.1 Based on the resolution m of the underlying digital-to-analog converter (DAC), the range N of the values of the aforementioned independent control variables is set, and a two-dimensional discrete weight search space WT of size N × N is constructed, whose elements are weight combinations, i.e., wt ij = <wt i ,wt q >, where: wt i With wt q These represent the weight control codes for the in-phase path and the quadrature path DAC, respectively. Their values are discrete integers within the closed interval [0, N], and the minimum step size is set to 1.
[0009] The range of the parameter values is N = 2 m -1.
[0010] 1.2 Through circuit simulation, each weight combination in the two-dimensional discrete weight search space is driven by a phase interpolator and the phase and amplitude of the corresponding output clock signal are recorded. Then, a two-dimensional basic state matrix containing the non-ideal error of the underlying simulation is obtained.
[0011] The second step involves iterating through the ideal phase of each target at a K-bit resolution (e.g., 8-bit, corresponding to 256 states), calculating the difference between the actual synthesized phase at each discrete point and the current ideal phase of the target. This includes:
[0012] 2.1 Calculate the target ideal phase corresponding to the current state based on the input K-bit phase control code n and preset the phase error tolerance, specifically: target ideal phase θ target (n) = n × 360° / 2 K Where: n ∈ [0, 2] K -1].
[0013] The preferred phase error tolerance is 0.5 LSB.
[0014] 2.2 Extract all discrete weighted coordinate points whose phase difference satisfies the phase error tolerance. Specifically, this includes: calculating the absolute difference between each synthetic phase and the target ideal phase in the basic state matrix, and extracting the coordinate points in the basic state matrix corresponding to the phases that satisfy the phase error tolerance.
[0015] 2.3 Cluster all coordinate points to form a candidate weight set, which serves as the data basis for subsequent magnitude optimization.
[0016] Step 3, Amplitude Approximation Optimization: A second screening is performed on the candidate weight set obtained in Step 2, specifically including:
[0017] 3.1 Calculate the amplitude deviation between each synthesized amplitude in the basic state matrix and the ideal target amplitude limit value.
[0018] The ideal target amplitude limit value is preferably 63, which is the maximum range of a single DAC.
[0019] 3.2 The coordinate point in the basic state matrix corresponding to the amplitude with the smallest amplitude deviation is locked, and this point is used as the optimal predistortion weight combination.
[0020] The fourth step is to store all the best weight combinations in order into the on-chip static random access memory (SRAM) to build a complete predistortion lookup table (LUT).
[0021] The precise mapping refers to the following: In the online phase, using the real-time input K-bit phase control code as the index address, a single-cycle lookup is performed in the LUT generated in the offline phase to obtain the corresponding optimal independent weights. These two sets of weights independently drive the underlying I-channel and Q-channel DAC arrays, respectively, to complete high-precision phase vector synthesis. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the structure of the present invention;
[0023] Figure 2 A constellation diagram for a 6-bit DAC with digital predistortion;
[0024] Figure 3 A schematic diagram of digital predistortion IQ weighted codes;
[0025] Figure 4 This is a schematic diagram of the nonlinear results;
[0026] Figure 5 This is a schematic diagram of the output amplitude envelope. Detailed Implementation
[0027] like Figure 1 As shown, this embodiment relates to a high linearity phase interpolator based on digital predistortion technology, including: a multi-phase clock generator for generating four phase signals with orthogonal phase relationships, a digital predistortion decoder for realizing nonlinear mapping in the digital domain and underlying error precompensation, and an analog interpolation core.
[0028] In this embodiment, the multi-phase clock generator is implemented by a current-mode quadrature frequency divider. The current-mode quadrature frequency divider performs a two-way frequency division based on the input differential clock signal using a current-mode logic frequency division architecture to obtain four phase signals with orthogonal phase relationships.
[0029] The aforementioned nonlinear mapping and underlying error pre-compensation refer to: receiving the K-bit target phase control code input from the system and parsing it into a data addressing index; according to the addressing index, calling a pre-configured predistortion lookup table in the internal static memory. This lookup table pre-stores the optimal weight combination extracted by a two-dimensional optimization algorithm; subsequently, these two sets of independent weight signals are sent to the subsequent analog interpolation core.
[0030] like Figure 1 As shown, in this embodiment, the core of the analog interpolation includes: a quadrant selection multiplexer (MUX), two sets of current-mode logic-based digital-to-analog converters (DACs), and a current synthesis node. Specifically: the MUX performs clock path switching based on an 8-bit phase control code, selecting two adjacent clock signals corresponding to the current quadrant from the four input quadrature reference clocks as the input sources for the I and Q paths, respectively; the two DACs correspond to the in-phase (I) and quadrature (Q) paths, respectively, with each DAC consisting of N unit current elements. By independently controlling the number of DACs on, current vectors of corresponding phases are synthesized in the complex plane; the current synthesis node performs current-weighted summation on the load resistor based on the controlled current outputs of the I and Q DACs to obtain the synthesized analog vector signal in the complex plane.
[0031] Through practical application experiments, in a hardware design based on CMOS standard technology and a high-precision mixed-signal post-simulation environment, the high linearity phase interpolator based on digital predistortion technology of this invention was run. The system power supply voltage was set to 0.8V, and the core operating clock frequency was set to 14GHz to receive 8-bit phase control code addressing the predistortion lookup table. The resulting peak INL was less than 0.5LSB. Figure 4 As shown.
[0032] Based on a target control code range of 0~255 (corresponding to 8-bit phase resolution), and a digital predistortion PI architecture using 6-bit resolution digital-to-analog converters (DACs) for the underlying in-phase and quadrature paths.
[0033] like Figure 3As shown, in the generation and configuration stage of the predistortion weight code, this invention uses a built-in digital decoder or lookup table (LUT) to independently map the input 8-bit phase control code (Code n, range 0~255) into two sets of non-complementary discrete weight signals. The I-path weight (blue line in the figure) and Q-path weight (red line in the figure) are precisely mapped to quantization step-level values that approximate ideal cosine and sine curves, respectively. To adapt to the underlying hardware, these digital weight values are strictly clamped within the maximum dynamic operating range of the 6-bit DAC (i.e., the value 63). Through this independent nonlinear mapping performed in the digital domain beforehand, this invention possesses the ability to compensate for structural errors at the analog end from the source.
[0034] Based on the aforementioned independent and approximately sinusoidal predistortion weight configuration, this invention performs a two-dimensional vector synthesis operation of the phase at the analog circuit level. For example... Figure 2 As shown, when the I-channel and Q-channel DACs receive the aforementioned predistortion control code and output corresponding current drives, the equivalent output vector endpoint trajectories synthesized on the complex plane exhibit a perfect "circular" geometric envelope. The color gradient of the scattered points from cold to warm in the figure clearly records the complete evolution of the control code from step 0 to 255. Compared to the unavoidable non-ideal "diamond" trajectory under existing complementary constraints, this invention achieves high geometric symmetry in the generated circular constellation diagram through global optimization in a 63x63 two-dimensional discrete quantization grid. This performance physically demonstrates that this scheme can ensure highly uniform phase stepping, thereby eliminating the phase jump distortion caused by existing one-dimensional trajectory limitations.
[0035] To accurately verify the effectiveness of the aforementioned predistortion scheme and the final performance of the invention, this invention performs rigorous data extraction and comparison tests on the phase nonlinearity and amplitude envelope of the output signal. On one hand, in the core phase linearity test, such as... Figure 4 Test data shows that the INL and DNL of this invention are extremely strictly limited to a very small range throughout the entire 0~255 control code sweep cycle. Specifically, the maximum absolute deviation of INL (blue line) and DNL (pink / red line) does not exceed 0.5 LSB. This is far superior to the periodic error peak of up to 3 LSB in existing linear architectures.
[0036] On the other hand, such as Figure 5As shown, in the amplitude robustness test of the output signal, the test data reveals the amplitude modulation phenomenon that occurs when approximating the ideal circle using a discrete grid. The data shows that the actual output amplitude of the synthesized vector (solid black line) exhibits a certain regular fluctuation around the target ideal amplitude (parameter value 63, dashed red line), with its actual amplitude envelope fluctuating approximately between 57 and 69. In this test of operating parameters, this approximately 10% amplitude is the closest result to the target ideal amplitude while ensuring the tolerance of search phase matching, greatly avoiding nonlinear problems caused by AM-PM modulation. This complete data comparison and testing process fully demonstrates that the present invention not only achieves extremely high-precision linear calibration in the phase domain but also possesses robustness in the amplitude domain.
[0037] Compared to existing technologies, this invention breaks through the long-standing "weighted complementary physical constraint" that has limited phase interpolators from the underlying architecture. By shifting the core task of nonlinear compensation from the power-intensive analog domain to the area-efficient digital predistortion logic, it achieves or even surpasses the extreme phase accuracy of complex hardware architectures with only basic orthogonal four-phase inputs, resolving the contradiction between high performance, low power consumption, and high integration in clock systems. When the resolution is increased from K bits to K+1 bits, only a very small number of DAC units need to be added to each of the I / Q paths. The phase point that meets the higher accuracy requirements can be found through the reconfiguration of the digital lookup table, making full use of the scaling benefits of digital logic circuits under advanced processes. While maintaining 14G broadband operation capability, the overall power consumption is controlled at around 4.0mW.
[0038] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.
Claims
1. A high linearity phase interpolator based on digital predistortion technology, characterized in that, include: A multi-phase clock generator for generating four-channel phase signals with orthogonal phase relationship, a digital predistortion decoder for realizing nonlinear mapping in the digital domain and low-level error precompensation, and an analog interpolation core, wherein: the multi-phase clock generator uses a current-mode divider to generate four mutually orthogonal clock signals. The digital predistortion decoder employs an approximate sinusoidal weight allocation strategy in a two-dimensional N×N discrete dot matrix space. It accurately maps the input K-bit phase control code to the integer weight combination that most closely approximates the ideal circular motion through a lookup table (LUT), generating two completely independent non-complementary weights. The analog interpolation core synthesizes the corresponding phase vector in the complex plane based on the non-complementary weights and the clock signal.
2. The high linearity phase interpolator based on digital predistortion technology according to claim 1, characterized in that, The lookup table is obtained in the following way: Step 1: Scan the weight matrix to obtain the phase constellation diagram: Through simulation, traverse and obtain the real synthesized phase and amplitude corresponding to all weight combinations in the two-dimensional space, and establish an N×N two-dimensional discrete weight combination for the I-channel and Q-channel DACs that are independently controlled. The second step is to iterate through the ideal phase of each target at K-bit resolution and calculate the difference between the actual composite phase of each discrete point and the current ideal phase of the target. Step 3, Amplitude Approximation Optimization: Perform a second screening on the candidate weight set obtained in Step 2; The fourth step is to store all the best weight combinations in order into the on-chip static random access memory (SRAM) to build a complete predistortion lookup table (LUT).
3. The high linearity phase interpolator based on digital predistortion technology according to claim 2, characterized in that, The first step, specifically include: 1.1 Based on the resolution m of the underlying digital-to-analog converter (DAC), the range N of the values of the aforementioned independent control variables is set, and a two-dimensional discrete weight search space WT of size N×N is constructed, whose elements are weight combinations, i.e., wt ij = <wt i ,wt q >, where: wt i With wt q These represent the weight control codes for the in-phase path and the quadrature path DAC, respectively. Their values are discrete integers within the closed interval [0, N], and the minimum step size is set to 1. 1.2 Through circuit simulation, each weight combination in the two-dimensional discrete weight search space is driven by a phase interpolator and the phase and amplitude of the corresponding output clock signal are recorded. Then, a two-dimensional basic state matrix containing the non-ideal error of the underlying simulation is obtained.
4. The high linearity phase interpolator based on digital predistortion technology according to claim 3, characterized in that, The range of the parameter values is N=2. m -1.
5. The high linearity phase interpolator based on digital predistortion technology according to claim 2, characterized in that, The second step specifically includes: 2.1 Calculate the target ideal phase corresponding to the current state based on the input K-bit phase control code n and preset the phase error tolerance, specifically: target ideal phase θ target (n) = n × 360° / 2 K Where: n ∈ [0, 2] K -1]; 2.2 Extract all discrete weighted coordinate points whose phase difference satisfies the phase error tolerance. Specifically, this includes: calculating the absolute difference between each synthetic phase and the target ideal phase in the basic state matrix, and extracting the coordinate points in the basic state matrix corresponding to the phases that satisfy the phase error tolerance. 2.3 Cluster all coordinate points to form a candidate weight set, which serves as the data basis for subsequent magnitude optimization.
6. The high linearity phase interpolator based on digital predistortion technology according to claim 2, characterized in that, The third step specifically includes: 3.1 Calculate the amplitude deviation between each synthesized amplitude in the basic state matrix and the ideal target amplitude limit value; 3.2 The coordinate point in the basic state matrix corresponding to the amplitude with the smallest amplitude deviation is locked, and this point is used as the optimal predistortion weight combination.
7. The high linearity phase interpolator based on digital predistortion technology according to claim 1, characterized in that, The precise mapping refers to the following: In the online stage, based on the real-time input K-bit phase control code as the index address, a single-cycle lookup is performed in the LUT generated in the offline stage to obtain the corresponding optimal independent weights. These two sets of weights independently drive the underlying I-channel and Q-channel DAC arrays to complete high-precision phase vector synthesis.
8. The high linearity phase interpolator based on digital predistortion technology according to claim 1, characterized in that, The multi-phase clock generator is implemented by a current-mode quadrature frequency divider. The current-mode quadrature frequency divider performs a two-way frequency division based on the input differential clock signal using a current-mode logic frequency division architecture to obtain four phase signals with orthogonal phase relationship.
9. The high linearity phase interpolator based on digital predistortion technology according to claim 1, characterized in that, The aforementioned nonlinear mapping and underlying error pre-compensation refer to: receiving the K-bit target phase control code input by the system and parsing it into a data addressing index; according to the addressing index, calling a pre-configured predistortion lookup table in the internal static memory, which pre-stores the optimal weight combination extracted by the two-dimensional optimization algorithm; subsequently, these two sets of independent weight signals are then sent to the subsequent analog interpolation core.
10. The high linearity phase interpolator based on digital predistortion technology according to claim 1, characterized in that, The analog interpolation core includes: a quadrant selection multiplexer (MUX), two sets of current-mode logic-based digital-to-analog converters (DACs), and a current synthesis node. Specifically: the MUX performs clock path switching based on an 8-bit phase control code, selecting two adjacent clock signals corresponding to the current quadrant from four input quadrature reference clocks as the input sources for the I and Q paths, respectively; the two DACs correspond to the in-phase (I) and quadrature (Q) paths, respectively, with each DAC consisting of N unit current elements. By independently controlling the number of DACs on, current vectors of corresponding phases are synthesized in the complex plane; the current synthesis node performs current-weighted summation on the load resistor based on the controlled current outputs of the I and Q DACs to obtain the synthesized analog vector signal in the complex plane.