FPGA-based MIM-FAID LDPC decoder and implementation method

Abstract

This invention discloses an FPGA-based MIM-FAID LDPC decoder and its implementation method, belonging to the field of channel decoding and integrated circuit implementation technology. The method includes: receiving 3-bit quantized channel information from the front-end demodulation output, reconstructing it into 7-bit fixed-point values ​​through a lookup table, and concatenating it into a 1792-bit parallel data block using 256 nodes; performing hierarchical iterative decoding based on 7 sub-layers under the scheduling of the master control finite state machine; using a forward / backward shift network to complete data alignment and write-back corresponding to the quasi-cyclic parity check matrix; employing an RCQ node update architecture in the core processing engine to complete message updates between variable nodes and parity check nodes, minimum / sub-minimum value search, and saturation truncation; simultaneously detecting decoding convergence in real time through a companion parity check and early stopping unit, and outputting a hard decision result with a 64-bit bus width after decoding. This invention effectively solves problems such as complex wiring of wide-bit data paths, difficulty in addressing irregular matrices, and numerous invalid iterations, and has advantages such as high throughput, low latency, and high resource utilization efficiency.

Description

Technical Field

[0001] This invention belongs to the field of channel decoder hardware implementation and integrated circuit design technology, specifically relating to an FPGA-based MIM-FAID LDPC decoder and its implementation method. Background Technology

[0002] With the continuous development of high-density storage systems and high-speed digital communication systems, long code length, high code rate, low-density parity-check (LDPC) codes are widely used in flash memory controllers, data center interconnects, and high-reliability transmission links due to their error correction performance approaching the Shannon limit. To meet engineering requirements such as high throughput, low latency, and low power consumption, decoders typically need to implement hierarchical iterative scheduling and fixed-point message updates on the hardware platform.

[0003] On the one hand, existing LDPC decoding hardware implementations mostly employ belief propagation or minimum sum-type algorithms. While these schemes offer good decoding performance, they are prone to problems such as high message storage overhead, complex nonlinear operations, and difficulty in timing closure of wide-bit data paths in low-bit-width quantization scenarios. In particular, in the implementation of quasi-cyclic LDPC codes, cyclic shift alignment, irregular matrix addressing, and early stopping control often become bottlenecks for improving system performance.

[0004] On the other hand, the Mutual Information-Maximizing Finite Alphabet Iterative Decoding (MIM-FAID) method has good performance potential under low quantization bit width conditions, but without a matching Reconstruction-Computation-Quantization (RCQ) node update architecture design, it is still difficult to fully realize the advantages of this algorithm in engineering implementation.

[0005] Therefore, it is necessary to propose a MIM-FAID LDPC decoder structure for Field-Programmable Gate Array (FPGA) implementation, and to coordinately optimize its data organization method, core operation process, RCQ node update mechanism and control mechanism. Summary of the Invention

[0006] To address the problems of complex wide-bit data routing, difficulty in addressing irregular parity-check matrices, numerous invalid iterations, and low resource utilization efficiency in existing technologies, this invention proposes an FPGA-based MIM-FAID LDPC decoder and its implementation method to achieve layered decoding with high throughput, low latency, and low resource overhead.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] An FPGA-based MIM-FAID LDPC decoder includes a channel data loading and reconstruction unit, a dual-port memory, a master control state machine unit, an address generation unit, a forward shift network, a reverse shift network, a core processing engine, and a companion check and early stop unit, wherein:

[0009] The channel data loading and reconstruction unit receives 3 bits of quantized channel information for a quasi-cyclic low-density parity-check (QC-LDPC) code with a spread factor Z of 256 and parameters of (18432, 16640), and reconstructs it into 7 bits of signed fixed-point value through a lookup table; the reconstructed fixed-point value is then concatenated into a 1792-bit parallel data block by 256 nodes and sequentially written into the dual-port memory;

[0010] The master control state machine unit is used to control the data loading, hierarchical iteration, accompanying verification early stopping, and result output process;

[0011] Address generation unit, used to map layer number and column offset to physical memory access address;

[0012] Forward shifting network and backward shifting network are used to perform cyclic shifting, alignment and recovery of quasi-cyclic LDPC data;

[0013] The core processing engine uses the RCQ architecture to reconstruct the old messages from the previous round of verification nodes to variable nodes, update the messages of variable nodes and verification nodes, and complete amplitude quantization, sign accumulation, and minimum / second minimum value search.

[0014] The accompanying verification and early stop unit is used to detect decoding convergence in real time and feed back a global verification pass signal to the main control state machine;

[0015] The codeword readout and streaming output interface unit is used to output the hard decision result on a 64-bit wide bus after decoding is completed.

[0016] Furthermore, the channel data loading and reconstruction unit adopts a data organization method with an expansion factor Z of 256, uses an intra-block counter to concatenate 256 input nodes, and uses a block counter to sequentially write 72 cyclic blocks of the full codeword; when all 72 cyclic blocks have been written, a loading completion signal is output.

[0017] Furthermore, it is reconstructed into a 7-bit signed fixed-point value using a lookup table:

[0018]

[0019] in The reconstructed 7-bit signed message is llr_in, which is the 3-bit quantized channel message, and b represents binary.

[0020] Furthermore, the master control finite state machine includes an idle state, a search state, an update state, and a completion state. In the search state and the update state, the master control finite state machine is cyclically scheduled according to 7 sub-layers, where the search phase and update phase of each sub-layer occupy 42 clock cycles respectively. When the verification pass feedback is received, the master control finite state machine directly jumps to the completion state.

[0021] Furthermore, both the forward shift network and the reverse shift network adopt a logarithmic cascaded barrel shift structure, decomposing the cyclic shift in the range of 0~255 into 8-level combined shift operations with steps of 1, 2, 4, 8, 16, 32, 64 and 128 respectively, and performing timing optimization through a 2-level pipelined cut register.

[0022] Furthermore, the core processing engine includes 256 parallel processing units for simultaneously processing 256 nodes in a single quasi-cyclic block; the RCQ architecture satisfies the following relationship:

[0023]

[0024]

[0025]

[0026] Where phi is the reconstruction mapping, M is a finite alphabet set, D is the computational domain, u is the computed value, PHI is the computational function, and Gamma is the quantization mapping based on the quantization lookup table.

[0027] Furthermore, the core processing engine reconstructs the old messages from the previous round of verification nodes to variable nodes as follows:

[0028]

[0029] in The message is a 7-bit message reconstructed from the old message, and msg is a 3-bit quantized message, where b represents binary.

[0030] The amplitude quantization is performed by quantizing a 7-bit message into a 3-bit message using a quantization lookup table, which is:

[0031]

[0032] in The first part is a quantized 3-bit message, and the second part is a 7-bit message.

[0033] Furthermore, the updates to the variable node and verification node messages specifically include:

[0034] For either side The variable node update satisfies:

[0035]

[0036]

[0037] in For external information to be calculated, For retrospective information, For refactoring functions, For quantified messages, The message after the variable node is updated. Let m be the quantization function, m be the index of the check node, and n_k be the index of the k-th variable node connected to the check node.

[0038] For any check node outputting edge j, the check node update satisfies:

[0039]

[0040] in To verify the updated messages of the verification node, It is a mapping function that will Mapped to , for inverse function, for A is an abbreviation for qm, where A_j is the set of variable node indices connected to the check node j, and qm is the number of message quantization bits.

[0041] Furthermore, the accompanying verification and early stop unit uses a 256-bit XOR accumulator to store the hard decision verification result of the current sub-layer. Specifically, when the first quasi-cyclic block of a certain sub-layer arrives, the current 256-bit hard decision result is written into the XOR accumulator; when subsequent blocks arrive, bitwise XOR accumulation is performed; when the current layer verification result is detected to be zero at the end of the last sub-layer and the verification status of all other layers has passed, a global verification pass signal is output.

[0042] A method for implementing an FPGA-based MIM-FAID LDPC decoder includes the following steps: Step S1: For a QC-LDPC code with a spreading factor Z of 256 and parameters (18432, 16640), receive the 3-bit quantized channel information output from the front-end demodulator and reconstruct it into a 7-bit signed fixed-point value using a lookup table; concatenate the reconstructed fixed-point value into 256 nodes to form 1792. Step S2: Under the scheduling of the master finite state machine, the parity check matrix is ​​divided into 7 sub-layers and hierarchical iterative decoding is performed. Each sub-layer includes a search phase and an update phase. The address generation unit maps the layer number and column offset provided by the master finite state machine to the physical memory access address. Step S3: In the search phase, the data of the relevant nodes in the current sub-layer is cyclically shifted and aligned through the forward shift network. In the core processing engine, the old message from the parity check node to the variable node in the previous round is reconstructed and calculated to generate a new message from the variable node to the parity check node, and the amplitude quantization, sign accumulation and minimum / second minimum search are completed. Step S4: In the update phase, the core processing engine generates the message from the parity check node to the variable node according to the minimum search result, and synthesizes it with the variable node message to obtain the updated posterior probability. After restoring the original node arrangement through the reverse shift network, it is written back to the dual-port memory. Step S5: During the hierarchical iteration process, the posterior probability sign bit is extracted synchronously to form 256. The bit hard decision block, the accompanying check and early stop unit performs the accompanying check, and when all check equations are satisfied, the early stop mechanism is triggered and the current decoding task is directly terminated; Step S6: After decoding is completed, the code word readout and streaming output interface unit reads out the hard decision result in segments and streams it according to the 64-bit bus width.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] (1) By constructing a 3-bit quantized channel information to a 7-bit fixed-point value reconstruction mechanism based on the (18432, 16640) QC-LDPC code, and combining it with the 1792-bit wide closed-loop data path design, the internal calculation precision required by the algorithm is matched with the granularity of FPGA parallel processing, reducing the conversion overhead between external serial input and internal wide-bit operation.

[0045] (2) By introducing the RCQ node update architecture into the core processing engine, efficient mapping and write-back of finite alphabet messages to computation domain messages can be achieved, and the reliability accumulation capability can still be maintained under low exchange bit width.

[0046] (3) Through the collaborative design of the master control finite state machine, address generation unit and dual-port memory, efficient addressing and inter-layer pipelined control for irregular QC-LDPC parity check matrices are realized, avoiding the waste of resources caused by additional cache copying;

[0047] (4) By using a logarithmic cascaded shift network and its pipeline cutting method, the wiring pressure and critical path problem caused by the 1792-bit ultra-wide cyclic shift are effectively alleviated, and the system timing closure capability is enhanced.

[0048] (5) By using the folded MIM-FAID core processing engine and the accompanying early stop mechanism, the invalid iterations are reduced while maintaining a high degree of parallelism, which improves the efficiency of resource reuse and reduces the average decoding latency and power consumption. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments are briefly described below; obviously, the accompanying drawings described below are only some embodiments of the present invention.

[0050] Figure 1 This is a general architecture diagram of the MIM-FAID LDPC decoder provided in an embodiment of the present invention.

[0051] Figure 2 This is a diagram of a 1792-bit logarithmic cascaded shift network architecture provided in an embodiment of the present invention.

[0052] Figure 3 This is a flow diagram of the internal microstructure of a single processing unit provided in an embodiment of the present invention.

[0053] Figure 4 This is a circuit diagram of the underlying comparison and update circuit of the minimum value finder provided in the embodiment of the present invention.

[0054] Figure 5 This is a diagram of the underlying hardware logic structure for accompanying verification and early stopping provided in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of this invention.

[0056] The parity check matrix of the QC-LDPC code is denoted as: Its structure consists of several cyclic submatrices, and can be represented as:

[0057]

[0058] Each sub-block Let Z be a Z × Z cyclic matrix, where Z is called the expansion factor. A basis matrix is ​​introduced for ease of hardware implementation. in: .when At that time, the corresponding sub-block It is a zero matrix; when When the corresponding sub-block is an identity matrix The cyclic permutation submatrix obtained by cyclically shifting p bits to the right. By combining the basis matrix and the expansion factor Z, the complete parity check matrix can be uniquely determined, and the storage problem of large-scale sparse matrices is transformed into the storage problem of basis matrix elements and shift parameters, thereby reducing storage complexity.

[0059] Based on this, this embodiment focuses on a QC-LDPC code with parameters (18432, 16640) commonly used in storage systems. The parity check matrix of the QC-LDPC code consists of several Z×Z cyclic submatrices. This embodiment provides an FPGA-based MIM-FAID LDPC decoder, such as... Figure 1 As shown.

[0060] Regarding the code type used in this embodiment, there are , Therefore, the number of verification equations When the expansion factor Z = 256, the corresponding , Therefore, the complete code can be divided into 72 quasi-cyclic blocks, and the parity-check matrix can be organized into 7 sub-layers, thus providing a structural foundation for parallel processing of 256 nodes per block, a 1792-bit wide closed-loop data path, and hierarchical scheduling. Based on this, the decoder constructs a 1792-bit wide high-speed closed-loop data path around a dual-port memory, mainly composed of a channel data loading and reconstruction unit, a dual-port memory, a master control finite state machine, an address generation unit, a forward shift network, a reverse shift network, a MIM-FAID core processing engine, and a companion-type parity-check unit.

[0061] The channel data loading and reconstruction unit is used to receive 3-bit quantized channel information for QC-LDPC code with parameters (18432, 16640) and reconstruct it into 7-bit fixed-point values, and write it into the dual-port memory in 1792-bit parallel data blocks.

[0062] The master control state machine unit is used to control the data loading, hierarchical iteration, accompanying verification early stopping, and result output process;

[0063] Address generation unit, used to map layer number and column offset to physical memory access address;

[0064] Forward shifting network and backward shifting network are used to perform cyclic shifting, alignment and recovery of quasi-cyclic LDPC data;

[0065] The core processing engine is used to perform message updates for variable nodes and check nodes in the RCQ architecture, minimum value search, and posterior probability updates.

[0066] The accompanying verification and early stop unit is used to detect decoding convergence in real time and feed back a global verification pass signal to the main control state machine;

[0067] The codeword readout and streaming output interface unit is used to output the hard decision result on a 64-bit wide bus after decoding is completed.

[0068] The QC-LDPC code is applied to the storage system, and its parity check matrix consists of several Z×Z cyclic submatrices. For a code pattern with parameters (18432, 16640), when the spread factor Z is 256, the complete code corresponds to 72 quasi-cyclic blocks and 7 sub-layers. Based on this structure, the channel data loading stage employs coordinated control of intra-block counters and block counters. The intra-block counter is used to count the 256 nodes within a single 1792-bit data block, while the block counter is used to count the 72 quasi-cyclic blocks of the complete codeword. Once all 72 quasi-cyclic blocks have been written, a loading completion signal is output to the master finite state machine.

[0069] During the data loading phase, the external interface serially inputs 3-bit quantized channel information `llr_in`, and enters the preprocessing logic when `llr_in_valid` is valid. Considering the balance between internal accuracy and resource consumption in the hardware implementation of the MIM-FAID algorithm, this embodiment uses a 7-bit fixed-point number to represent the reconstructed channel value. Preferably, a non-uniform mapping is performed using a lookup table, mapping the 3-bit quantized channel information to a 7-bit fixed-point value as follows:

[0070]

[0071] in The 7-bit signed message is the reconstructed message, and llr_in is the 3-bit quantized channel message.

[0072] The reconstructed 7-bit data is entered into a high-order shift register for concatenation. The block counter `bit_cnt` counts the number of nodes in the range 0-255. When `bit_cnt` reaches 255, it indicates that a complete 1792-bit data block has been formed; at this point, a write enable pulse is output to write the data block to the dual-port memory. The block counter `block_cnt` counts the 72 quasi-cyclic blocks of the complete codeword. When all blocks have been written, the `load_done` signal is output to drive the system into the iterative decoding stage.

[0073] During the decoding phase, the master finite state machine acts as the global control center, including at least the IDLE state, SEARCH state, UPDATE state, and DONE state. The system enters the IDLE state after a reset; when load_done is detected as valid and start_decode is high, the master finite state machine enters the SEARCH state. Preferably, the processing of each sub-layer consists of a 42-clock-cycle SEARCH phase and a 42-clock-cycle UPDATE phase. For a sub-layer containing 42 non-zero blocks, clock cycles 0-41 correspond to each quasi-cyclic block; for a sub-layer containing 41 non-zero blocks, the same timing organization can be achieved through internal column counting boundary control.

[0074] The address generation unit maps the two-dimensional logical coordinates given by the master finite state machine to the physical access addresses of the dual-port memory. Since the parity check matrix used in this embodiment has irregular characteristics—the 5th sublayer contains 42 non-zero blocks, and the remaining sublayers each contain 41 non-zero blocks—the address generation unit preferably uses a dimensionality reduction mapping combined with a hard-wired lookup table to generate addresses. More preferably, the lookup table depth is 294, and the conversion from logical coordinates to physical addresses can be completed within one clock cycle.

[0075] like Figure 2 As shown, the forward shift network and the reverse shift network are key data routing modules for shift alignment of the quasi-cyclic LDPC structure. Both the forward shift network and the reverse shift network adopt an 8-stage logarithmic cascaded barrel shift structure, and use a 2-stage pipelined cut register to optimize the timing of the 1792-bit wide data path to reduce critical path latency and improve clock frequency reachability. Since the (18432, 16640) QC-LDPC code spread factor Z in this embodiment is 256, and a single node uses a 7-bit fixed-point representation, the shift network needs to process 256 × 7 = 1792 bits of ultra-wide data. Preferably, the barrel shift in the range of 0~255 is decomposed into 8 stages of combinational logic shift with steps of 1, 2, 4, 8, 16, 32, 64 and 128, and a 2-stage pipelined cut register is inserted in the middle to shorten the critical path and increase the system clock frequency.

[0076] like Figure 3 As shown, the MIM-FAID core processing engine is the core module for performing message updates and nonlinear operations. To match the parallelism of Z=256, this embodiment instantiates 256 identical processing units within the engine. Each processing unit processes the 256 nodes in a single quasi-cyclic block in parallel in space, and in time, the master-controlled finite state machine performs folded reuse in a 42-cycle search and 42-cycle update manner, significantly reducing the scale of the computational logic and the pressure on memory ports while ensuring the basic parallelism. Furthermore, the core processing unit adopts an RCQ architecture, which includes three steps: reconstruction, computation, and quantization. The reconstruction mapping is used to map compressed messages in a finite alphabet to the computation domain, the computation function is used to complete the construction of external information and the propagation of verification constraints in the computation domain, and the quantization mapping is used to re-compress the computation domain results into finite alphabet messages to meet the low-bit-width iteration transmission requirements. The specific RCQ architecture satisfies the following relationship:

[0077]

[0078]

[0079]

[0080] Where phi is the reconstruction mapping, M is a finite alphabet set, D is the computational domain, u is the calculated value, PHI is the computation function, and Gamma is the quantization mapping. During the search phase, each processing unit first reconstructs the compressed verification message into a 7-bit signed fixed-point value using the lookup table phi_v. The lookup table phi_v maps the 3-bit compressed verification message to 7-bit information as follows:

[0081]

[0082] in The reconstructed 7-bit message is represented by a 3-bit quantized message named `msg`. Subsequently, the reconstructed value is subtracted from the posterior probability of the current input to obtain the variable node to check node message. To reduce the resource consumption of subsequent minimum value searches, the 7-bit variable node message can be further quantized into a 3-bit compressed state using a lookup table. The specific quantization lookup table is as follows:

[0083]

[0084] in The quantized 3-bit message has a sum of 7 bits. The sign bit and 2 bits of amplitude information are extracted from it. For either side... The variable node update satisfies:

[0085]

[0086]

[0087] in For external information to be calculated, For retrospective information, For refactoring functions, For quantified messages, The message after the variable node is updated. This is the quantization function. Therefore, the variable node can accumulate reliability using the 7-bit computational domain posterior message Q while maintaining a 3-bit swap width.

[0088] like Figure 4 As shown, each processing unit internally sets up a first minimum value register min1, a second minimum value register min2, and an index register min1_idx for the first minimum value. When the first quasi-cyclic block in the layer arrives, min1 is initialized with the current amplitude, and min2 is set to the preset maximum value. When subsequent quasi-cyclic blocks arrive, the current amplitude is compared with min1 and min2 to synchronously update the minimum value, the second minimum value, and their indices.

[0089] During the update phase, each processing unit selects either min1 or min2 as the return amplitude based on the comparison result between the current quasi-cyclic block index and min1_idx; if the current quasi-cyclic block corresponds to the position of the first minimum value, then the second minimum value min2 is returned; otherwise, the first minimum value min1 is returned. The check node update adopts the minimum sum rule. For any check node outputting edge j, the check node update satisfies:

[0090]

[0091] in To verify the updated messages of the verification node, It is a mapping function that will Mapped to , for The inverse function of the function. This structure avoids complex hyperbolic function operations and is easy to implement on an FPGA using comparators, selectors, and lookup tables. To prevent accumulation overflow, a 7-bit saturation truncation logic can be set at the output to limit results greater than 63 to 63 and results less than -64 to -64.

[0092] like Figure 5As shown, the accompanying check and early stopping unit is used to determine in real time during the decoding process whether the current hard decision result has satisfied all check equations. Decoding convergence detection is achieved through intra-layer XOR accumulation and inter-layer state arbitration, and the global check is fed back to the master finite state machine via a signal, thereby avoiding unnecessary residual iterations. Specifically, the posterior probability of each node output by the core processing engine is a 7-bit signed fixed-point value. The accompanying check and early stopping unit directly extracts its highest bit as the hard decision result and concatenates the sign bits of 256 nodes into a 256-bit parallel check block.

[0093] When the first quasi-cyclic block of a sublayer arrives, the current 256-bit hard decision block is directly written to the XOR accumulator layer_acc. In subsequent clock cycles, bitwise XOR accumulation is performed on newly arriving hard decision blocks. When the XOR result is zero at the end of the sublayer, the check status of that layer is set. Only when the check result of the last sublayer is zero and the check status of all other layers passes, the accompanying check and early stop unit outputs the global check pass signal all_pass and feeds it back to the master finite state machine to interrupt the remaining iterations.

[0094] After decoding, the codeword readout and streaming output interface unit is responsible for converting the internal 1792-bit wide a posteriori probability data into a 64-bit hard decision output. Since the (18432, 16640) QC-LDPC code consists of 72 quasi-cyclic blocks, this interface unit can be configured with a 9-bit readout counter, readout_cnt. When decode_done and decode_success are both valid, the readout process is started, and the results of the 72 cyclic blocks are read out sequentially, with one cyclic block output every 4 clock cycles, thus achieving full codeword streaming output.

[0095] Through the above structural design, this invention achieves efficient hardware mapping of the MIM-FAID LDPC decoder under limited FPGA resources. This scheme is particularly suitable for engineering implementation scenarios involving long code lengths and high code rates of quasi-cyclic LDPC codes.

[0096] The implementation method of the decoder based on the above design includes the following steps:

[0097] Step S1: For a QC-LDPC code with a spread factor Z of 256 and parameters (18432, 16640), receive the 3-bit quantized channel information output from the front-end demodulator and reconstruct it into a 7-bit signed fixed-point value through a lookup table; concatenate the reconstructed fixed-point value into a 1792-bit parallel data block according to 256 nodes and write it sequentially into the dual-port memory;

[0098] Step S2: Under the scheduling of the master finite state machine, the parity check matrix is ​​divided into 7 sub-layers and hierarchical iterative decoding is performed. Each sub-layer includes a search phase and an update phase. The maximum number of iterations is set to 10.

[0099] Step S3: During the search phase, the forward shift network performs cyclic shift alignment on the relevant node data of the current sub-layer. In the core processing engine, the RCQ architecture is used to reconstruct and calculate the old messages from the previous round of check nodes to variable nodes to generate new messages from variable nodes to check nodes, and complete amplitude quantization, sign accumulation, and minimum / second minimum value search.

[0100] Step S4: In the update phase, a check node to variable node message is generated based on the minimum value search result, and the updated posterior probability is obtained by combining it with the variable node message. After restoring the original node arrangement through the reverse shift network, it is written back to the dual-port memory.

[0101] Step S5: During the hierarchical iteration process, the posterior probability symbol bits are extracted synchronously to form a 256-bit hard decision block, and the accompanying verification is performed; when all verification equations are satisfied, the early stopping mechanism is triggered, and the current decoding task is terminated directly.

[0102] Step S6: After decoding, the hard decision result is read out in segments and streamed according to the 64-bit bus width.

[0103] This invention can effectively solve problems such as complex wiring of wide-bit data paths, difficulty in addressing irregular matrices, and a large number of invalid iterations, and has the advantages of high throughput, low latency, and high resource utilization efficiency.

[0104] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various equivalent substitutions or modifications can be made without departing from the spirit and essence of the present invention, and all such modifications should fall within the protection scope of the present invention.

Claims

1. An FPGA-based MIM-FAID LDPC decoder, characterized in that, It includes a channel data loading and reconstruction unit, a dual-port memory, a master control state machine unit, an address generation unit, a forward shift network, a reverse shift network, a core processing engine, and a companion check and early stop unit, wherein: The channel data loading and reconstruction unit receives 3 bits of quantized channel information for a QC-LDPC code with a spread factor Z of 256 and parameters of (18432, 16640), and reconstructs it into 7 bits of signed fixed-point value through a lookup table; the reconstructed fixed-point value is then concatenated into a 1792-bit parallel data block by 256 nodes and sequentially written into the dual-port memory. The master control state machine unit is used to control the data loading, hierarchical iteration, accompanying verification early stopping, and result output process; Address generation unit, used to map layer number and column offset to physical memory access address; Forward shifting network and backward shifting network are used to perform cyclic shifting, alignment and recovery of quasi-cyclic LDPC data; The core processing engine uses the RCQ architecture to reconstruct the old messages from the previous round of verification nodes to variable nodes, update the messages of variable nodes and verification nodes, and complete amplitude quantization, sign accumulation, and minimum / second minimum value search. The accompanying verification and early stop unit is used to detect decoding convergence in real time and feed back a global verification pass signal to the main control state machine; The codeword readout and streaming output interface unit is used to output the hard decision result on a 64-bit wide bus after decoding is completed.

2. The FPGA-based MIM-FAID LDPC decoder according to claim 1, characterized in that, The channel data loading and reconstruction unit adopts a data organization method with an expansion factor Z of 256. It uses an intra-block counter to concatenate 256 input nodes and uses a block counter to sequentially write 72 cyclic blocks of the full codeword. When all 72 cyclic blocks have been written, a loading completion signal is output.

3. The FPGA-based MIM-FAID LDPC decoder according to claim 1, characterized in that, Reconstructing it into a 7-bit signed fixed-point value using a lookup table: in The reconstructed 7-bit signed message is llr_in, which is the 3-bit quantized channel message, and b represents binary.

4. The FPGA-based MIM-FAID LDPC decoder according to claim 1, characterized in that, The master control finite state machine includes an idle state, a search state, an update state, and a completion state. In the search and update states, the master control finite state machine is scheduled in a cyclic manner according to 7 sub-layers, where the search phase and update phase of each sub-layer each occupy 42 clock cycles. When the verification pass feedback is received, the master control finite state machine directly jumps to the completion state.

5. The FPGA-based MIM-FAID LDPC decoder according to claim 1, characterized in that, Both the forward shift network and the reverse shift network adopt a logarithmic cascaded barrel shift structure, which decomposes the cyclic shift in the range of 0 to 255 into 8-stage combined shift operations with steps of 1, 2, 4, 8, 16, 32, 64 and 128, and optimizes the timing through a 2-stage pipelined cut register.

6. The FPGA-based MIM-FAID LDPC decoder according to claim 1, characterized in that, The core processing engine comprises 256 parallel processing units, used to process 256 nodes in a single quasi-cyclic block simultaneously; the RCQ architecture satisfies the following relationship: Where phi is the reconstruction mapping, M is a finite alphabet set, D is the computational domain, u is the computed value, PHI is the computational function, and Gamma is the quantization mapping based on the quantization lookup table.

7. The FPGA-based MIM-FAID LDPC decoder according to claim 6, characterized in that, The core processing engine reconstructs the old messages from the previous round of verification nodes to variable nodes as follows: in The message is a 7-bit message reconstructed from the old message, and msg is a 3-bit quantized message, where b represents binary. The amplitude quantization is performed by quantizing a 7-bit message into a 3-bit message using a quantization lookup table, which is: in The first part is a quantized 3-bit message, and the second part is a 7-bit message.

8. The FPGA-based MIM-FAID LDPC decoder according to claim 6, characterized in that, The updates to the variable node and verification node messages specifically include: For either side The variable node update satisfies: in For external information to be calculated, For retrospective information, For refactoring functions, For quantified messages, The message after the variable node is updated. Let m be the quantization function, m be the index of the check node, and n_k be the index of the k-th variable node connected to the check node. For any check node outputting edge j, the check node update satisfies: in To verify the updated messages of the verification node, It is a mapping function that will Mapped to , for inverse function, for A is an abbreviation for qm, where A_j is the set of variable node indices connected to the check node j, and qm is the number of message quantization bits.

9. The FPGA-based MIM-FAID LDPC decoder according to claim 1, characterized in that, The accompanying verification and early stop unit uses a 256-bit XOR accumulator to store the hard decision verification result of the current sub-layer. Specifically, when the first quasi-cyclic block of a certain sub-layer arrives, the current 256-bit hard decision result is written into the XOR accumulator; when subsequent blocks arrive, bitwise XOR accumulation is performed; when the current layer verification result is detected to be zero at the end of the last sub-layer and the verification status of all other layers has passed, a global verification pass signal is output.

10. A method for implementing the FPGA-based MIM-FAID LDPC decoder according to any one of claims 1-9, characterized in that, The steps include: Step S1: For a QC-LDPC code with a spreading factor Z of 256 and parameters (18432, 16640), receive the 3-bit quantized channel information output from the front-end demodulator and reconstruct it into a 7-bit signed fixed-point value using a lookup table; then concatenate the reconstructed fixed-point value into 256 nodes to form 1792. Step S2: Under the scheduling of the master finite state machine, the parity check matrix is ​​divided into 7 sub-layers and hierarchical iterative decoding is performed. Each sub-layer includes a search phase and an update phase. The address generation unit maps the layer number and column offset provided by the master finite state machine to the physical memory access address. Step S3: In the search phase, the data of the relevant nodes in the current sub-layer is cyclically shifted and aligned through the forward shift network. In the core processing engine, the old message from the parity check node to the variable node in the previous round is reconstructed and calculated to generate a new message from the variable node to the parity check node, and the amplitude quantization, sign accumulation and minimum / second minimum search are completed. Step S4: In the update phase, the core processing engine generates the message from the parity check node to the variable node according to the minimum search result, and synthesizes it with the variable node message to obtain the updated posterior probability. After restoring the original node arrangement through the reverse shift network, it is written back to the dual-port memory. Step S5: During the hierarchical iteration process, the posterior probability sign bit is extracted synchronously to form 256. The bit hard decision block, the accompanying check and early stop unit performs the accompanying check, and when all check equations are satisfied, the early stop mechanism is triggered and the current decoding task is directly terminated; Step S6: After decoding is completed, the code word readout and streaming output interface unit reads out the hard decision result in segments and streams it according to the 64-bit bus width.

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