FPGA-based reconfigurable ground test system for scientific satellite payload

Abstract

This invention relates to a reconfigurable scientific satellite payload ground testing system based on FPGA, belonging to the field of spacecraft ground testing. The system consists of a host computer and a hardware platform. The host computer is responsible for human-computer interaction, test logic control, and data management; the hardware platform is responsible for protocol conversion, instruction execution, data acquisition, and forwarding. The two are connected via two physical links, UART and USB 2.0, achieving separation of control flow and data flow, ensuring that the real-time upload of high-bandwidth scientific data is unaffected by instruction interaction. This invention achieves full-duplex communication capability, supporting simultaneous transmission and reception; is compatible with multiple communication interfaces; allows flexible configuration of communication protocols through FPGA to adapt to different payloads; features parameterized data routing for easy configuration; integrates power management, status monitoring, and host computer interaction functions to form a one-stop testing platform; and provides extended I / O interfaces for easy integration with other customized circuits, enhancing system applicability.

Description

Technical Field

[0001] This invention belongs to the field of spacecraft ground testing, specifically relating to a ground testing system for reconfigurable scientific satellite payloads based on FPGA. Background Technology

[0002] During the spacecraft's ground testing phase, each payload unit (such as the pointing system, spectrometer, and radiation detector) needs to communicate with the payload management unit to complete functions such as command issuance, data transmission, and status monitoring. However, different payloads have different communication interfaces (such as RS422 level, LVDS level, and UART) and communication protocols (frame format, baud rate, and verification method), and the same payload also needs to simulate different operating modes when testing different functions.

[0003] Currently, ground testing mostly utilizes customized, specialized testing equipment. This type of equipment suffers from the following technical drawbacks: (1) Poor versatility and flexibility: A system can often only adapt to a specific load or a single protocol and cannot be compatible with multiple interfaces and protocol standards. When the test object or test requirements change, it is usually necessary to redesign or significantly modify the hardware, resulting in a long development cycle and high cost.

[0004] (2) Limited communication mode: Most existing systems use half-duplex communication, which cannot support the concurrent transmission of instructions and the real-time transmission of high-speed scientific data in full-duplex mode, making it difficult to meet the test scenarios with high real-time requirements.

[0005] (3) Single function and low integration: The test system usually only has communication function and lacks integrated power management, status monitoring and flexible command parsing and data routing capabilities. During the test, multiple independent devices often need to work together, which increases the complexity of the system and the difficulty of joint debugging.

[0006] (4) Inflexible configuration: Adjusting test parameters (such as the length of communication protocol configuration instructions, channel enable, threshold voltage, etc.) usually requires modifying hardware or recompiling firmware, which cannot achieve dynamic and real-time configuration during the test process, thus limiting test efficiency.

[0007] Therefore, there is an urgent need for a general-purpose, flexible, highly integrated ground testing system that supports full-duplex communication to solve the above problems. Summary of the Invention

[0008] To address the shortcomings of existing aerospace payload ground testing systems, such as poor versatility, insufficient protocol compatibility, and inability to flexibly support full-duplex communication, this invention provides a reconfigurable scientific satellite payload ground testing system based on FPGA. This system aims to: achieve full-duplex communication capability, supporting simultaneous transmission and reception; be compatible with multiple communication interfaces including RS422 (master / backup) level, LVDS (master / backup) level, UART, and USB; flexibly configure communication protocols via FPGA to adapt to different payloads; implement parameterized data routing for easy configuration; integrate power management, status monitoring, and host computer interaction functions to form a one-stop testing platform; and provide extended I / O interfaces for easy integration with other customized circuits, enhancing system applicability.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A ground testing system for a reconfigurable scientific satellite payload based on FPGA includes: a host computer and a hardware platform; instructions from the host computer are sent to the hardware platform via UART, and the hardware platform parses the instructions and completes the specified operations; the hardware platform includes an FPGA module, a communication interface module, a power management module, and an expansion interface module; the FPGA module dynamically loads or switches the corresponding communication protocol core according to the command frames issued by the host computer, and configures the corresponding operating parameters to perform full-duplex communication for payloads with different interfaces and protocols; the communication interface module provides a UART serial interface and a USB 2.0 high-speed data interface for connection to the host computer, as well as an RS422 full-duplex level interface and an LVDS high-speed differential signal receiving interface for communication with the payload; the power management module monitors the voltage and current of the nodes in real time, and the FPGA module reads the monitoring data through the serial peripheral interface; the power management module also provides multiple regulated power supplies; the expansion interface module reserves multiple FPGA general-purpose I / O to connectors to support the connection of custom circuits or sensors.

[0010] Optionally, the host computer is developed using Python and PyQt5, combined with the QtSerialPort and ftd2xx libraries to form a graphical testing platform.

[0011] Optionally, the data port of the host computer can be selected from serial port mode and FTDI synchronous FIFO mode via a drop-down box; The serial port mode opens the selected COM port via QSerialPort to read data in real time; when recording data, a recording flag is set in serial port mode, and the received data is appended to the received_data.bin file; after recording stops, the serial port mode writes the memory buffer to the file. The FTDI synchronous FIFO mode starts an independent thread, which continuously reads data blocks and sends them back to the main thread via signals. When recording data, the FTDI synchronous FIFO mode calls the independent thread, passing in a filename with a timestamp, and the independent thread writes subsequent data to the file. After stopping recording, the FTDI synchronous FIFO mode calls to close the file handle.

[0012] Optionally, the host computer supports batch configuration of registers via a configuration file. Specifically, the host computer software parses the contents of the user-selected txt configuration file, extracts all register values ​​and calculates the checksum. The calculated value is displayed in the corresponding input box, and the complete configuration data is stored in memory. The host computer software sends configuration data through the configuration serial port and displays the sent hexadecimal data in the log.

[0013] Optionally, the host computer is equipped with a readback data display switch. Only after the readback data display switch is clicked will the data received by the configuration serial port and data serial port be displayed in hexadecimal format in the log interface. Otherwise, it will only be cached or written to a file and will not be displayed in the log interface.

[0014] Optionally, the FPGA module is internally configured with a parameterized UART module for receiving the input clock frequency and the target baud rate, and generating a sampling clock.

[0015] Optionally, when the command frame issued by the host computer indicates "switch to RS422 mode", the cmd_parser module inside the FPGA module parses the command and sets the control signal to an active state; at the same time, it writes the baud rate and data bit parameters into the corresponding configuration register, and the BAUD_GEN_PAR module inside the FPGA module recalculates and outputs the baud rate clock according to the parameters.

[0016] Optionally, the FPGA module receives the differential signal through the IBUFDS primitive and performs edge detection and serial-to-parallel conversion through the EDGE_DET module; the 10-bit parallel data after serial-to-parallel conversion is sent to the DEC_8B10B decoder to complete 8b / 10b decoding and output 8 bits of valid data and a "K code" indicator signal.

[0017] Optionally, the cmd_parser module inside the FPGA module implements a finite state machine (FSM) to parse rx_data from the parameterized UART module; upon receiving a complete command frame, the FSM enters the following different branches based on the opcode: If it is a configuration command, then parse the subsequent data and write it to the corresponding internal configuration register; If it is a payload data write command, the FSM writes the data to be sent into a dedicated transmit FIFO. At the same time, it continuously checks the FIFO through an independent state machine. Once the FIFO is not empty, it sends the data out byte by byte according to the pre-configured RS422 protocol. If it is a payload data readback command, the FSM will generate a special read request signal. This signal will interrupt the current operation and occupy the channel to send the readback request signal to the payload in the highest priority manner. When the payload returns data, it will store the data in the receive FIFO through the RS422 receiving module and notify the FSM. The FSM will then package the data and send it back to the host computer through the UART interface to complete the read operation.

[0018] Optionally, during the writing process, the host computer packages the configuration data into a write command frame and sends it to the FPGA module; during the loading process, the cmd_parser module inside the FPGA module parses the command and writes the configuration data into the internal register of the FPGA module or into an external analog device via the SPI interface; during the verification process, the host computer automatically generates a specific read-back verification command frame and sends it to the FPGA module, instructing the FPGA module to read the data just written from a specific register or state memory of the payload; during the readback process, the FPGA module performs a read operation and transmits the read data back to the host computer via the UART serial interface; during the comparison process, the host computer compares the readback data bit by bit with the locally cached data and displays the result on the interface.

[0019] The beneficial effects of this invention are: it features full-duplex communication and multi-protocol compatibility, supports simultaneous transmission and reception, improves communication efficiency, and is suitable for test scenarios with high real-time requirements; through flexible FPGA configuration, a single system can be adapted to RS422, LVDS circuits and UART protocols, and can be configured with data routing to improve the versatility and reusability of the test system.

[0020] This invention features high reliability and scalability. The RS422 master-slave design enhances the reliability of the communication link; the status monitoring module monitors the system current and voltage in real time; and the reserved expansion I / O and modular design facilitate secondary development and functional integration, as well as troubleshooting sudden failures.

[0021] This invention enables one-stop testing, and its integrated and user-friendly design simplifies the testing process. Polling and verification configuration reduces the complexity of multi-device joint debugging, effectively shortening the ground testing cycle and cost. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the hardware platform of the present invention.

[0023] Figure 2 This is a diagram of the interface of the host computer of this invention.

[0024] Figure 3 This is a block diagram of the reconfigurable protocol processing logic of the present invention.

[0025] The attached diagram is labeled as follows: 1-Power management module; 2-LVDS level receiving circuit; 3-RS422 transceiver; 4-Current and voltage monitoring; 5-Expansion interface module; 6-FPGA core module; 7-UART serial port module and USB 2.0 data interface module. Detailed Implementation

[0026] The invention will now be described in further detail with reference to the accompanying drawings.

[0027] In the communication interaction between aerospace satellites and ground control centers, the payload management unit system of the ground control center plays a major role in communication interaction. This invention relates to a full-duplex, multi-protocol compatible ground test operating system based on a field-programmable gate array (FPGA) for the ground testing phase of aerospace payloads during the experimental process of payload ground verification. This system can simulate a spacecraft payload management unit, enabling full-duplex or half-duplex communication with various payloads, and supports real-time data acquisition, protocol adaptation, and status monitoring. It is suitable for comprehensive ground testing of spacecraft such as satellites and space probes.

[0028] This system consists of two parts: a host computer (PC) and a hardware platform (test board). The host computer is responsible for human-computer interaction, test logic control, and data management; the hardware platform is responsible for protocol conversion, instruction execution, data acquisition, and forwarding. The two are connected via two physical links: UART (for low-speed instructions / telemetry) and USB 2.0 (for high-speed scientific data), to separate the control flow from the data flow, ensuring that the real-time upload of high-bandwidth scientific data is not affected by instruction interaction.

[0029] The hardware platform is based on the Xilinx Artix-7 series FPGA, such as Figure 1 As shown, the circuit board measures 16cm x 20cm and mainly includes the following modules: FPGA Core Module 6: Employs Xilinx Artix-7 series FPGAs (such as XC7A35T), responsible for overall system control, protocol parsing, data packing / unpacking, timing generation, and logic scheduling.

[0030] Communication interface module: including UART serial port module and USB 2.0 data interface module 7 (LT231X chip and FT232H chip), RS422 transceiver 3 (DS26LV31 transmit, DS26LV32 receive), LVDS level receiving circuit 2 (DS90LV032 chip).

[0031] The communication interface module provides a UART serial interface and a USB 2.0 high-speed data interface for connection to the host computer, as well as an RS422 full-duplex level interface and an LVDS high-speed differential signal receiving interface for communication with the payload, enabling data interaction of multi-protocol heterogeneous links.

[0032] Power Management Module 1: The system integrates a status monitoring module implemented through an analog-to-digital converter (ADC), which collects the voltage and current of key nodes in real time. The FPGA core module reads the monitoring data through the serial peripheral interface (SPI) for system status monitoring and fault early warning, i.e., current and voltage monitoring 4. At the same time, the power management module provides multiple regulated power supplies for the system and external loads.

[0033] Expansion Interface Module 5: Reserves multiple FPGA general-purpose I / O to connectors, supporting the connection of other custom circuits or sensors.

[0034] Meanwhile, a reconfigurable protocol processing logic is implemented within the FPGA module using a hardware description language. This logic includes multiple parameterized communication protocols (such as UART and LVDS reception). The command frames issued by the host computer contain protocol selection fields and parameter configuration fields. Based on the parsed command frames, the FPGA core module dynamically loads or switches the corresponding communication protocol cores and configures their operating parameters (such as baud rate, data bits, stop bits, and parity mode), thereby enabling full-duplex communication of payloads from different interfaces and protocols.

[0035] Command parsing and data routing mechanism: The FPGA core module contains a command parsing and routing unit for receiving and parsing command frames from the host computer. Based on the instruction type field in the command frame, this unit performs at least one of the following operations: a) writing configuration data to the internal configuration register to adjust the system's operating state; b) sending the data to be sent to the target payload via the currently active communication protocol; c) transmitting the scientific observation data received from the payload back to the host computer via a high-speed data interface (USB 2.0) or reading status parameters back to the host computer via a low-speed telemetry interface (UART) according to preset routing rules.

[0036] Closed-loop testing and data verification mechanism: The command frames generated by the host computer include write command frames and read-back verification command frames. For the write command frame, the hardware platform writes data to the payload according to the instruction; for the read-back verification command frame, the hardware platform reads data from the specified address of the payload, packages it, and sends it back to the host computer. The host computer automatically compares the written data with the read-back data to complete the closed-loop testing and functional verification of the payload.

[0037] The parameterized communication code in the reconfigurable protocol processing logic employs a baud rate generator based on a pulse uniform distribution parameterized design. By inputting the clock frequency and target baud rate parameters, it automatically calculates and generates a sampling clock with optimal uniformity. The routing unit contains multiple first-in-first-out (FIFO) buffers to isolate different data streams, enabling parallel and non-blocking processing of commands, telemetry data, and high-speed scientific data.

[0038] Specifically, this invention uses a Xilinx Artix-7 series FPGA as its core to build a ground test system for simulating a satellite payload management unit.

[0039] I. System Overall Architecture The ground testing system of this invention consists of two parts: a host computer (PC) and a hardware platform (test board). The host computer is responsible for human-computer interaction, test logic control, and data management; the hardware platform is responsible for protocol conversion, instruction execution, data acquisition, and forwarding. The two are connected by two physical links: UART (for low-speed instructions / telemetry) and USB 2.0 (for high-speed scientific data), which separates the control flow from the data flow, ensuring that the real-time upload of high-bandwidth scientific data is not affected by instruction interaction.

[0040] II. Details and Workflow of the Host Computer Software The host computer interface is as follows Figure 2 As shown, the host computer software was developed using Python and PyQt5, combined with the QtSerialPort and ftd2xx libraries, to implement a graphical testing platform. The software supports two data acquisition modes: standard serial port mode (via a USB-to-serial chip) and FTDI synchronous FIFO mode (via the high-speed USB transmission of the FT232H chip), which can be selected according to testing requirements.

[0041] Graphical User Interface: The interface integrates multiple areas including data port selection, serial port configuration, data logging control, command configuration, mode selection, and status display. The data port can be selected via a dropdown menu as a standard serial port or an FTDI device (scanned by the ftd2xx library). Clicking "Open Serial Port" initiates data acquisition in the corresponding mode. The serial port configuration is independently set up for sending commands to the payload and receiving readback data. The log display area records all operations and received data, supporting clearing and automatic saving when the window is closed.

[0042] Dual data source support and data recording control: The software enables seamless switching between two data acquisition modes. In standard serial port mode, the selected COM port is opened via QSerialPort with parameters including baud rate, 8 data bits, no parity, and 1 stop bit for real-time data reading. In FTDI synchronous FIFO mode, an independent thread is started. The device is opened using the ftd2xx library and configured as an FT245 synchronous FIFO, USB transmission parameters are set to optimize throughput, and data blocks are continuously read in the independent thread and transmitted back to the main thread via signals. Data recording is controlled by the "Store Data" button. Clicking this button processes the data according to the current data source type: in FIFO mode, a thread is invoked, passing in a filename with a timestamp (a binary file named with the current time), and the thread writes subsequent data to the file; in serial port mode, a recording flag is set, and received data is appended to the received_data.bin file. Clicking the button again stops recording; in FIFO mode, the file handle is closed, while in serial port mode, the memory buffer is written to the file. A separate thread is added to cut the file every 10 minutes for easy saving and backtracking of experimental data.

[0043] Configuration File Parsing and Configuration Sending: The software supports batch configuration of registers via configuration files. The user clicks the "Select Configuration File" button to choose a .txt file, where each line can have a random format and arbitrary length. The software parses the file content, extracts all register values, and calculates the checksum. The calculated value is displayed in the corresponding input box, and the complete configuration data (including all registers and the calculated ADD_HIGH / ADD_LOW) is stored in memory. After clicking the "Send Configuration" button, the software sends the byte array via the configuration serial port and displays the sent hexadecimal data in the log.

[0044] Data Replay and Log Management: To meet the control requirements for data display, the software features a data replay switch. Only after clicking the read / display button will data received from the configuration serial port and data serial port be displayed in hexadecimal format in the log interface. Before this, all serial port data is only cached or written to a file and is not displayed on the UI to avoid interference from a large amount of useless data. When the read / display button is clicked, the software sets a display flag and clears the buffer. Subsequent received data is then appended to the log in hexadecimal format one by one. Furthermore, comprehensive log management functionality is provided, saving all contents of the log display area to the log folder in the current directory for easy traceability of the testing process.

[0045] III. Hardware Platform Details and Workflow After the host computer interface commands are sent to the hardware platform via UART, the hardware platform parses the commands and completes the specified operations. The hardware platform is based on an FPGA, such as... Figure 3As shown, its top-level module (such as Ground_test_board_top) integrates the following functional units: 1. Multi-protocol reconfigurable communication architecture This architecture is a hardware language compiled with Verilog, and its internal implementation is highly parameterized, enabling "hot switching" of hardware functions through software commands.

[0046] Parameterized UART: As shown in modules UART_BYTE_RX and UART_BYTE_TX, the stop bits and parity are configurable through parameters. Baud rate generation is performed by the independent BAUD_GEN_PAR module. This module receives the input clock frequency (CLK_FREQ_HZ) and the target baud rate (TARGET_BAUD), calculates it using an algorithm (CHOSEN_TOTAL_CLKS = (CLK_FREQ_HZ + TARGET_BAUD / 2 ) / TARGET_BAUD), and uses a pulse uniform distribution strategy to generate the sampling clock with minimal jitter and the most uniform distribution.

[0047] Reconfigurable RS422 full-duplex communication: The physical layer of RS422 level is implemented in hardware using DS26LV31 (transmit) and DS26LV32 (receive) chips. Internally, the FPGA implements full-duplex communication through a state machine-controlled transmit / receive logic. When a command frame from the host computer indicates "switch to RS422 mode," the cmd_parser module inside the FPGA parses the command and sets the control signals (fpga_data_en_m / s, fpga_cmd_en_m / s) to active status, thus activating the master / backup switch. Simultaneously, parameters such as baud rate and data bits are written to the corresponding configuration registers. The BAUD_GEN_PAR module then recalculates based on the new parameters and outputs the baud rate clock, completing the dynamic reconfiguration of the communication protocol.

[0048] LVDS High-Speed ​​Data Reception: Since there is no clock during onboard LVDS data transmission, all data recovery relies on decoding, primarily accomplished using the DEC_8B10B module. The LVDS interface is used to receive high-speed serial scientific data from the payload. The FPGA receives the differential signal via the IBUFDS primitive and performs edge detection and serial-to-parallel conversion via the EDGE_DET module. The received 10-bit parallel data is fed into the DEC_8B10B decoder for 8b / 10b decoding, outputting 8 bits of valid data and a "K code" indicator signal. This process is executed entirely in parallel within the hardware platform's code logic, achieving real-time data processing.

[0049] 2. Integrated command parsing and data routing mechanism The core of this mechanism is the cmd_parser code module.

[0050] Command frame structure: All commands in the host computer software are prefixed with "0x0055AA" and followed by different opcodes (such as 0x00 for "write" and 0xEE for "read verification").

[0051] Command parsing and routing: The cmd_parser module internally implements a finite state machine (FSM) responsible for parsing rx_data from the UART. Upon receiving a complete command frame, the FSM enters different branches based on the opcode: If it is a configuration command, the subsequent data is parsed and written to the corresponding internal configuration registers. These registers directly control the core operating mode of the system, including protocol selection, channel enable, threshold voltage, etc.

[0052] If it is a payload data write command, the FSM writes the data to be sent into a dedicated transmit FIFO. At the same time, a separate state machine (such as UART_BYTE_TX) continuously checks the FIFO, and once it is not empty, it sends the data byte by byte according to the pre-configured RS422 protocol.

[0053] If it's a payload data readback command, the FSM generates a special read request signal. This signal interrupts the current operation and occupies the channel, sending the readback request signal to the payload with the highest priority. When the payload returns data, the RS422 receiver module (UART_BYTE_RX) stores it in the receive FIFO and notifies the FSM. The FSM then packages this data and transmits it back to the host computer via the UART interface, completing the read operation.

[0054] Multi-FIFO data isolation: such as Figure 3 As shown, the system internally incorporates multiple FIFOs, such as fifo_lvds_data for caching high-speed scientific data, and fifo_daq_tx and fifo_daq_rx for isolating command responses from payload data. The writing and reading of high-speed scientific data are completely asynchronous and do not block each other, while low-speed command interactions are also isolated from the high-speed data stream.

[0055] 3. Closed-loop testing and data verification mechanism This mechanism determines the operation that the instruction needs to perform.

[0056] Write: Configure the parameters on the host computer interface and click the send button. The host computer packages these configurations into a write command frame (prefixed with 0x0055aa) and sends it to the hardware platform.

[0057] Loading: The cmd_parser command of the hardware platform parses the configuration data and writes it to the FPGA's internal registers or to an external analog device via the SPI interface.

[0058] Verification: Subsequently, the host computer automatically generates a specific read-back verification command frame (e.g., prefixed with 0x0055aaee) and sends it to the hardware platform. This command instructs the hardware platform to read the data just written from a specific register or state memory of the payload.

[0059] Readback: The hardware platform performs a read operation and transmits the read data back to the host computer via UART.

[0060] Comparison: The host computer software compares the read-back data bit by bit with the locally cached data and displays the results on the interface to verify the correctness of the communication link, register read / write function, and parameter configuration.

[0061] 4. Integrated monitoring and power management Status Monitoring: The hardware platform integrates an ADC128S102 analog-to-digital converter, whose control logic, the ADC128S module, communicates with the FPGA via the SPI protocol. The FPGA's internal state machine controls the ADC's sampling channels and timing, and stores the acquired voltage / current data in internal registers. The host computer can query this monitoring data at any time by sending command frames, enabling real-time perception of the system's health status and fault early warning.

[0062] Power Management: The hardware design offers multiple power supply options. One is through an external +12V input, which, via DC-DC conversion and LDO regulation, provides a stable power supply to all chips. Another option is dual +12V and +5V power supply, facilitating independent monitoring of current at critical nodes and improving power management flexibility.

[0063] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An FPGA-based reconfigurable scientific satellite payload ground test system, characterized in that, It includes: a host computer and a hardware platform; the host computer sends instructions to the hardware platform via UART, the hardware platform parses the instructions and completes the specified operation; the hardware platform includes an FPGA module, a communication interface module, a power management module and an expansion interface module, the FPGA module dynamically loads or switches the corresponding communication protocol core according to the command frame issued by the host computer, and configures the corresponding working parameters to perform full-duplex communication for payloads of different interfaces and protocols; The communication interface module provides a UART serial interface and a USB 2.0 high-speed data interface for connection to the host computer, as well as an RS422 full-duplex level interface and an LVDS high-speed differential signal receiving interface for communication with the payload. The power management module monitors the voltage and current of the nodes in real time, and the FPGA module reads the monitoring data through the serial peripheral interface. The power management module also provides multiple regulated power supplies. The expansion interface module reserves multiple FPGA general-purpose I / O ports to the connector, supporting the connection of custom circuits or sensors.

2. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: The host computer is developed using Python and PyQt5, and combined with the QtSerialPort and ftd2xx libraries to form a graphical testing platform.

3. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: The data port of the host computer can be selected from serial port mode and FTDI synchronous FIFO mode via a drop-down box; The serial port mode opens the selected COM port via QSerialPort to read data in real time; when recording data, a recording flag is set in serial port mode, and the received data is appended to the received_data.bin file; after recording stops, the serial port mode writes the memory buffer to the file. The FTDI synchronous FIFO mode starts an independent thread, which continuously reads data blocks and sends them back to the main thread via signals. When recording data, the FTDI synchronous FIFO mode calls the independent thread, passing in a filename with a timestamp, and the independent thread writes subsequent data to the file. After stopping recording, the FTDI synchronous FIFO mode calls to close the file handle.

4. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: The host computer supports batch configuration of registers via configuration files. Specifically, the host computer software parses the contents of the user-selected txt configuration file, extracts all register values ​​and calculates the checksum. The calculated value is displayed in the corresponding input box, and the complete configuration data is stored in memory. The host computer software sends configuration data through the configuration serial port and displays the sent hexadecimal data in the log.

5. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: The host computer is equipped with a readback data display switch. Only after clicking the readback data display switch will the data received by the configuration serial port and data serial port be displayed in hexadecimal format on the log interface. Otherwise, it will only be cached or written to a file and will not be displayed on the log interface.

6. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: The FPGA module is internally configured with a parameterized UART module, which is used to receive the input clock frequency and the target baud rate, and generate a sampling clock.

7. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: When the host computer sends a command frame indicating "switch to RS422 mode", the cmd_parser module inside the FPGA module parses the command and sets the control signal to the valid state; at the same time, it writes the baud rate and data bit parameters into the corresponding configuration register, and the BAUD_GEN_PAR module inside the FPGA module recalculates and outputs the baud rate clock according to the parameters.

8. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: The FPGA module receives differential signals through the IBUFDS primitive and performs edge detection and serial-to-parallel conversion through the EDGE_DET module. The 10-bit parallel data after serial-to-parallel conversion is sent to the DEC_8B10B decoder to complete 8b / 10b decoding and output 8 bits of valid data and a "K code" indicator signal.

9. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 6, characterized in that: The cmd_parser module inside the FPGA module implements a finite state machine (FSM) to parse rx_data from the parameterized UART module. Upon receiving a complete command frame, the FSM enters the following different branches based on the opcode: If it is a configuration command, then parse the subsequent data and write it to the corresponding internal configuration register; If it is a payload data write command, the FSM writes the data to be sent into a dedicated transmit FIFO. At the same time, it continuously checks the FIFO through an independent state machine. Once the FIFO is not empty, it sends the data out byte by byte according to the pre-configured RS422 protocol. If it is a payload data readback command, the FSM will generate a special read request signal. This signal will interrupt the current operation and occupy the channel to send the readback request signal to the payload in the highest priority manner. When the payload returns data, it will store the data in the receive FIFO through the RS422 receiving module and notify the FSM. The FSM will then package the data and send it back to the host computer through the UART interface to complete the read operation.

10. The FPGA-based reconfigurable scientific satellite payload ground test system as described in claim 1, characterized in that: During the writing process, the host computer packages the configuration data into a write command frame and sends it to the FPGA module. During the loading process, the cmd_parser module inside the FPGA module parses the command and writes the configuration data into the internal register of the FPGA module or into an external analog device via the SPI interface. During the verification process, the host computer automatically generates a specific readback verification command frame and sends it to the FPGA module, instructing the FPGA module to read the data just written from a specific register or state memory of the payload. During the readback process, the FPGA module performs a read operation and transmits the read data back to the host computer via the UART serial interface. During the comparison process, the host computer compares the read-back data with the locally cached data bit by bit and displays the results on the interface.

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