Non-linear mitigation interleaver for forward error correction encoder with probabilistic constellation shaping

Abstract

Embodiments of this disclosure relate to a nonlinear mitigation interleaver for a forward error correction encoder with probabilistic constellation shaping (PCS). Systems and methods for mitigating nonlinear effects are provided in high-speed optical communication systems using quadrature amplitude modulation (QAM) with probabilistic constellation shaping (PCS) and forward error correction (FEC). The transmitter includes a nonlinear mitigation (NLM) interleaver that permutes amplitude bits after FEC encoding to reduce the energy variance in the transmitted signal. This targeted interleaving minimizes the effects of optical channel nonlinearity, thereby supporting various interleaving modes and advanced FEC schemes. At the receiver, a corresponding NLM deinterleaver restores the original bit order, resulting in robust error correction and improved transmission performance.

Description

Technical Field

[0001] This disclosure relates to the field of electronics, and more specifically, to a nonlinear mitigation interleaver for a forward error correction encoder with probabilistic constellation shaping. Background Technology

[0002] High-speed, high-bandwidth communication systems are indispensable for modern computing and networking applications. These systems are designed to facilitate efficient and reliable data transmission over various media, including fiber optics, copper cables, and wireless channels. Forward error correction (FEC) schemes are commonly used in high-speed coherent optical communication systems. Probabilistic constellation shaping (PCS) technology is being used in conjunction with FEC schemes to increase channel capacity. Summary of the Invention

[0003] According to a first aspect of this disclosure, a method for reducing nonlinear effects in coded quadrature amplitude modulation (QAM) signals is provided. The method includes: dividing a bit sequence into a first sequence and a second sequence; encoding the second sequence using a distributed matching encoder; performing a first interleaving operation on the first sequence and the encoded second sequence; encoding the output of the first interleaving operation using a forward error correction (FEC) encoder; performing a second interleaving operation based on a signal output by the FEC encoder; and performing a third interleaving operation based on a signal output by the second interleaving operation, wherein the second interleaving operation outputs an amplitude signal and a symbol signal, and the third interleaving operation reduces the energy variance in the amplitude signal.

[0004] According to a second aspect of this disclosure, an encoding apparatus is provided for reducing nonlinear effects in coded quadrature amplitude modulation (QAM) signals. The encoding apparatus includes: a forward error correction (FEC) encoder; a distributed matching encoder, wherein the FEC encoder and the distributed matching encoder are arranged in a reverse cascaded scheme, wherein the distributed matching encoder is configured to operate on an input data stream prior to the FEC encoder; a first interleaver following the FEC encoder, wherein the first interleaver interleaves distributed matching amplitude bits; and a nonlinear mitigation nonlinearity interleaver following the FEC encoder, wherein the NLM interleaver is configured to: buffer the amplitude bits output by the first interleaver; and permutate the buffered amplitude bits to reduce the energy variance in the coded QAM signal.

[0005] According to a third aspect of this disclosure, a decoding apparatus for decoding a coded quadrature amplitude modulation (QAM) signal with reduced nonlinear effects is disclosed. The apparatus includes: a demapper configured to output symbol bits and amplitude bits from a received QAM signal; a nonlinear mitigation NLM deinterleaving unit following the demapper, the NLM deinterleaving unit being configured to: buffer the amplitude bits output by the demapper; and replace the buffered amplitude bits based on interleaving performed at an encoding device for reducing nonlinear effects; a forward error correction (FEC) decoder following the NLM deinterleaving unit; and a distributed matching decoder following the FEC decoder. Attached Figure Description

[0006] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For ease of description, the same reference numerals designate the same structural elements. The embodiments are illustrated in the figures by way of example rather than limitation.

[0007] Figure 1 The diagram illustrates a block diagram pair for encoding and decoding signals using FEC and distributed matching.

[0008] Figure 2 The diagram illustrates a block diagram pair for encoding and decoding signals using FEC, distributed matching, and additional interleaving and deinterleaving steps.

[0009] Figure 3 The diagram illustrates a block diagram pair illustrating the use of FEC and distributed matching, along with nonlinear deinterleaving and deinterleaving, to encode and decode signals according to some embodiments of the present disclosure.

[0010] Figure 4 The illustration shows example interleaved codewords before and after FEC encoding according to some embodiments of the present disclosure.

[0011] Figure 5 The figures illustrate some embodiments according to the present disclosure. Figure 4 An example of interleaved codewords after further interleaving.

[0012] Figure 6 An example of codewords following a further interleaving step according to some embodiments of the present disclosure is illustrated.

[0013] Figure 7 The contents of an NLM interleaver buffer according to some embodiments of the present disclosure are illustrated.

[0014] Figure 8 The illustration shows a first example amplitude channel mapping for an NLM interleaver according to some embodiments of the present disclosure.

[0015] Figure 9 An example symbol channel mapping for an NLM interleaver according to some embodiments of the present disclosure is illustrated.

[0016] Figure 10 The illustration shows a second amplitude channel mapping for an NLM interleaver according to some embodiments of the present disclosure.

[0017] Figure 11 The diagram illustrates a block diagram pair for encoding and decoding signals using FEC and distributed matching along with nonlinearity mitigation interleavers and deinterleavers, as well as payload error decorcorrelation and parity check interleavers, according to some embodiments of the present disclosure.

[0018] Figure 12 The illustrations depict some embodiments of the present disclosure. Figure 11 Example FEC encoder output of the encoder.

[0019] Figure 13 The illustrations depict some embodiments of the present disclosure. Figure 11 Example output codewords of the encoder.

[0020] Figure 14 The diagram illustrates a block diagram pair illustrating the use of FEC and distributed matching, along with a nonlinear deinterleaver and deinterleaver, to encode and decode signals according to some embodiments of the present disclosure, having parallel encoding and decoding paths.

[0021] Figure 15 An example bitmap diagram is illustrated for a 16QAM implementation having 24 codewords and 32-bit DM words, according to some embodiments of the present disclosure. Detailed Implementation Overview

[0022] As artificial intelligence (AI) applications continue to evolve, they require unprecedented data processing speeds and bandwidth capabilities to support their complex algorithms and massive datasets. Digital signal processors (DSPs), such as optical DSPs and coherent DSPs, enable high-bandwidth optical interconnects for AI infrastructure. In particular, DSPs enable low-latency, high-performance, and energy-efficient data transmission. These DSPs can provide seamless connectivity across AI, cloud computing, enterprise systems, and 5G infrastructure.

[0023] Forward error correction (FEC) is a coding technique that adds redundant data (called parity bits) to the signal at the transmitter. The receiver can use this redundant data to detect and correct errors introduced during transmission. FEC improves reliability over noisy channels, enabling longer transmission distances and / or higher speeds with lower bit rate errors. FEC is often used in conjunction with complex modulation schemes such as Quadrature Amplitude Modulation (QAM), which encodes data in multiple aspects of the signal, particularly amplitude and phase. Using FEC ensures correct data recovery even for complex, high-data-rate signals.

[0024] In standard QAM implementations, data points have an equal probability of occupying any available amplitude. To reduce the overall signal energy, probabilistic constellation shaping (PCS) reduces the probability of high-amplitude signals, thus making low-amplitude (and low-energy) signals more likely to be transmitted than high-amplitude (and high-energy) signals. Using PCS improves spectral efficiency and transmission capacity, enabling optical channels to approach or reach Shannon channel capacity.

[0025] The PCS stage can be performed before or after FEC encoding. In the implementation of the reverse concatenation scheme (RCS), the splitter divides the input data stream into two data sequences, one intended for symbol data and the other for amplitude data. The distributed matching (DM) encoder performs PCS on the amplitude data to reduce the probability of (multiple) high amplitudes. The FEC encoder calculates parity bits based on the symbol data and the PCS-adjusted amplitude data and inserts the parity bits into the symbol data. The mapper forms a QAM signal based on the amplitude and symbol data streams.

[0026] Many FEC implementations also include interleavers to assist in handling burst errors and error correlations. The interleaver implements deterministic and reversible permutations of the input bit sequence, allowing the FEC decoder at the receiver to reverse the interleaving operation from the encoder on the transmit side. The interleaver can mix bits from different codewords and / or distribute the bits of a given codeword in time. Therefore, the DM word generated by the DM encoder can be interleaved and distributed in time. In some implementations, the transmit side includes a first interleaver after DM encoding and before FEC encoding, and a second interleaver follows the FEC encoder. The receiver side includes two corresponding deinterleavers to reverse the interleaving process on the transmit side. The overall interleaving scheme ensures that the DM word generated by the DM encoder is correctly mapped to the appropriate mapper input channel (e.g., to the amplitude channel).

[0027] The aforementioned DM process reduces the energy of the DM codeword. When an interleaving step is included, bits from multiple DM codewords are mixed and distributed across the transmission sequence, resulting in a temporary energy distribution with a larger variance than a single DM codeword. Although the average signal energy remains constant, this increased variance exacerbates the effects of optical channel nonlinearity and degrades overall system performance.

[0028] As described herein, an FEC encoder with a PCS stage may also include a nonlinear mitigation (NLM) interleaver to address the increased amplitude variance introduced by conventional interleaving schemes in a reverse-cascaded architecture. On the transmitter side, the NLM interleaver may be included as an additional interleaver, following DM coding and FEC coding, as well as earlier interleaving steps. The encoder may include the aforementioned first and second interleavers, along with a third NLM interleaver. The NLM interleaver buffers the amplitude signal output by the second interleaver (or more generally, post-FEC interleaving operation). The NLM interleaver permutes the buffered data to reassemble amplitude bit groups, such as DM codewords. This targeted permutation reduces the temporary energy variance otherwise caused by scattering bits from multiple DM codewords, thereby mitigating the adverse effects of optical channel nonlinearity. The NLM interleaver can be configured to operate in various modes, including single-polarization, dual-polarization, and channel shift sequences, to uniformly distribute amplitude bits across the mapper input channels.

[0029] In some embodiments, the FEC encoder may be a step encoder or a semi-infinite codeword encoder, and the system may include additional components such as payload and parity error decorrelation units to support the FEC encoder. The architecture supports flexible interleaving strategies, including interleaving across multiple codewords and polarization modes, to optimize energy distribution and system robustness.

[0030] On the receiver side, corresponding deinterleaving and decoding devices are provided. These include a demapper, an NLM deinterleaver configured to reverse the NLM interleaving operation, an FEC decoder, and a DM decoder. The NLM deinterleaver ensures that amplitude bits are correctly reassembled before FEC and DM decoding, thus preserving the benefit of reduced nonlinear distortion throughout the transmission chain. The receiver includes an additional deinterleaver to reverse the interleaving operation at the transmitter.

[0031] Overall, the encoding and decoding architecture described in this paper achieves high spectral efficiency and improved transmission performance in optical communication systems by combining PCS, advanced FEC, and an interleaved architecture that addresses the challenges posed by nonlinear channel effects. Example RCS architecture

[0032] Figure 1The diagram illustrates a block diagram pair for encoding and decoding a signal using FEC, distributed matching, and RCS arrangement. Transmitter section 100 receives input data signal 105, which is provided to splitter 110. Splitter 110 splits the input data stream into two sequences: a first sequence is directed to DM encoder 120, while a second sequence is directly provided to FEC encoder 130. The first sequence consists of bits that determine the symbols (i.e., positive or negative polarity) of the in-phase (I) and quadrature (Q) components of a QAM symbol. These are commonly referred to as "symbol bits" or "symbol data." The second sequence consists of bits that determine the amplitude levels of the I and Q components. This sequence is referred to as "amplitude data" or "amplitude bits."

[0033] The DM encoder 120 applies probabilistic constellation shaping to the amplitude data to generate DM coded bits with a controlled probability distribution, thereby reducing the likelihood of high-amplitude symbols and thus reducing the average signal energy.

[0034] The output of DM encoder 120 and the first sequence from splitter 110 are provided to FEC encoder 130. FEC encoder 130 generates parity bits based on the two input sequences (the first sequence from splitter 110 and the second DM-encoded sequence from DM encoder 120). FEC encoder 130 inserts the parity bits into the data stream, specifically into the symbol data. The parity bits add redundancy to the data stream, thereby enabling error detection and correction at the receiver.

[0035] The output of the FEC encoder 130 is provided to the mapper 140, which assigns the encoded bits to specified symbols and amplitude components for QAM transmission. The mapped signal is then forwarded to the transmitter-side digital signal processor (TX-DSP) for further processing and transmission over the optical channel.

[0036] Receiver section 150 processes the signal received from the optical channel (e.g., from a receiver-side DSP (RX-DSP)) to generate a recovered signal 195. The received signal is first provided to a soft demapper 160, which extracts soft information for the symbol and amplitude bits from the received QAM symbols. The soft information is then decoded by a soft decision FEC (SD-FEC) decoder 170, which uses redundancy added at the transmitter to correct errors introduced during transmission.

[0037] The output of SD-FEC decoder 170 is provided to DM decoder 180, which inverts the probability shaping applied at the transmitter and reconstructs the original amplitude data. Finally, combiner 190 combines the outputs of DM decoder 180 and SD-FEC decoder 170 to recover the original data stream, thereby producing the recovered signal 195.

[0038] Example RCS architecture with interleaving

[0039] Figure 2 The diagram illustrates a block diagram pair for encoding and decoding a signal using FEC, distributed matching, and additional interleaving and deinterleaving steps. Transmitter section 200 receives input data signal 205, which is provided to splitter 210. Splitter 210 splits the input data stream into two sequences, similar to the two sequences output by splitter 110 described above. Figure 1 In this process, a second sequence is provided to DM encoder 220, which is similar to DM encoder 120.

[0040] The first sequence from splitter 210 and the output of DM encoder 220 (the second sequence encoded in DM) are provided to FEC pre-interleaver 225. FEC pre-interleaver 225 performs deterministic and reversible permutations on one or both of the received sequences, distributing bits within a given sequence across time or codewords to mitigate error bursts and correlations. For example, FEC pre-interleaver 225 permutates DM-encoded bits from DM encoder 220, and in some cases, may also permutate bits (symbol bits) of the first sequence. The interleaved data is provided to FEC encoder 230, which adds redundancy for error correction, as described with respect to FEC encoder 130.

[0041] The output of FEC encoder 230 is further processed by FEC interleaver 235. FEC interleaver 235 permutates the encoded bits (including parity bits inserted into the first data sequence) to further disperse potential error patterns and enhance the effectiveness of the FEC decoder at the receiver. FEC interleaver 235 outputs two sequences to mapper 240, one sequence corresponding to symbols and the other to amplitudes. Mapper 240 outputs a QAM signal, as described with respect to mapper 140.

[0042] Receiver section 250 includes a software demapper 260, an SD-FEC decoder 270, a DM decoder 280, and a combiner 290, which can be similar to those described above. Figure 1The described components include a soft demapper 160, an SD-FEC decoder 170, a DM decoder 180, and a combiner 190. The receiver section 250 also includes an FEC deinterleaving unit 265 and an FEC pre-deinterleaving unit 275. The FEC deinterleaving unit 265, located between the soft demapper 260 and the SD-FEC decoder 270, reverses the interleaving performed by the FEC interleaving unit 235, thereby restoring the original order of the FEC-coded bits. The FEC pre-deinterleaving unit 275, located between the SD-FEC decoder 270 and the DM decoder 280, reverses the interleaving performed by the FEC pre-deinterleaving unit 225, reconstructing the original order of the DM-coded bits before DM decoding.

[0043] In some cases, FEC interleaving is implemented as a two-stage process. After FEC encoding at FEC encoder 230, the encoded data is first processed by a post-DM FEC interleaver, which buffers and permutes amplitude and symbol bits to further distribute the matching codewords. The output of the post-DM FEC interleaver is then provided to a subsequent FEC interleaver, which performs additional permutations across multiple codewords and parity bits. This two-stage interleaving method enhances the dispersion of error patterns and ensures that amplitude bits are correctly aligned for subsequent mapping and transmission. A corresponding deinterleaving stage is implemented in the receiver path to reverse these permutations and restore the original data order before decoding.

[0044] Example RCS architecture with NLM interleaving

[0045] Figure 3 The diagram illustrates block diagram pairs illustrating the encoding and decoding of signals using FEC and distributed matching along with NLM interleavers and NLM deinterleavers according to some embodiments of the present disclosure. More specifically, Figure 3 This is an example of RCS used for encoding and decoding QAM signals, except... Figure 2 In addition to the interleaving and deinterleaving stages, it also incorporates an NLM interleaver and a corresponding NLM deinterleaver.

[0046] In the transmitter section 300, the input signal 305 is provided to the splitter 310, which splits the data stream into a first sequence (e.g., a symbol sequence) and a second sequence (e.g., an amplitude sequence). The amplitude sequence is processed by the DM encoder 320, which generates distributed matching codewords for probabilistic constellation shaping.

[0047] The output of the DM encoder 320 is provided to the FEC pre-interleaver 325. The FEC pre-interleaver 325 applies deterministic and reversible permutations to the DM encoded bits, thereby distributing them across time or codewords. The interleaved data is then encoded by the FEC encoder 330, which generates parity bits based on the interleaved symbol and amplitude data. The output of the FEC encoder 330 is further processed by the FEC interleaver 335, which permutates the encoded bits (including the parity bits) to further disperse potential error patterns. The splitter 310, DM encoder 320, FEC pre-interleaver 325, FEC encoder 330, and FEC interleaver 335 are similar to those described above. Figure 2 The splitter 210, DM encoder 220, FEC pre-interleaver 225, FEC encoder 230 and FEC interleaver 235.

[0048] The output of FEC interleaver 335 is provided to and processed by NLM interleaver 345. NLM interleaver 345 buffers the amplitude signal output from the FEC interleaver and permutes the buffered amplitude bits to reduce the energy variance in the coded QAM signal. In some embodiments, NLM interleaver 345 may reassemble distributed matching codewords or allocate consecutive bits to amplitude channels according to a channel shift sequence.

[0049] The permuted symbol and amplitude bits from NLM interleaver 345 are provided to mapper 340, which assigns the bits to the appropriate I / Q components for QAM symbol generation and transmission, as described with respect to mapper 240.

[0050] In receiver section 350, the received signal is first processed by soft demapper 360, which extracts soft information for the symbol and amplitude bits from the received QAM symbols, as described with respect to soft demappers 160 and 260. The output of soft demapper 360 is provided to and processed by NLM deinterleaving unit 355. NLM deinterleaving unit 355 buffers the amplitude bits and reverses the permutations applied at the transmitter by NLM deinterleaving unit 345, thereby restoring the order of the amplitude bits.

[0051] The output of NLM interleaver 345 is processed by FEC deinterleaver 365, which inverts the permutations applied by FEC interleaver 335. SD-FEC decoder 370 performs error correction using the recovered bit sequence. FEC pre-interleaver 375 inverts the permutations applied by FEC pre-interleaver 325, reconstructing the original order of DM-coded bits. DM decoder 380 recovers the original amplitude data, and combiner 390 combines the recovered amplitude and symbol data to generate the recovered signal 395. FEC deinterleaver 365, SD-FEC decoder 370, FEC pre-interleaver 375, DM decoder 380, and combiner 390 can be similar to those described above. Figure 2 The FEC deinterleaver 265, SD-FEC decoder 270, FEC pre-deinterleaver 275, DM decoder 280 and merger 290.

[0052] Figure 3 The architecture shown includes three interleaving operations in the transmitter path, called FEC pre-interleaving, FEC interleaving, and nonlinearity-mitigated interleaving, and a corresponding deinterleaving operation in the receiver path. The NLM interleaver and NLM deinterleaver reduce the energy variance in the amplitude signal, thereby mitigating nonlinear effects in the coded QAM signal. (See also: ...) Figure 2 In some implementations, the FEC interleaver 335 and the FEC deinterleaver 365 can each be implemented as two separate interleaver / deinterleaver stages; in such an implementation, there are four interleaver operations and four corresponding deinterleaver operations.

[0053] Example interleaving scheme

[0054] Figure 4 The illustration shows example interleaved codewords before and after FEC encoding according to some embodiments of the present disclosure. Figure 4This is an example result of a QAM16 signal after FEC pre-interleaving at FEC pre-interleaver 325 and FEC encoding at FEC encoder 330. In this example, the FEC code is a system fixed-word-length code with a codeword length of (N = 10x1024) bits and a dimension of (K = 8x1024), resulting in a 25% FEC overhead. This system code passes the input bits to the output codeword without modification or permutation and adds a parity bit at the end. The codeword can be labeled as CW[i] = (CW[i].b[0], CW[i].b[1], CW[i].b[2], ..., CW[i].b

[10239] ), where (i) refers to the codeword transmitted in (i), CW[i].b[0] refers to the first bit of the codeword, CW[i].b[1] refers to the second bit of the codeword, and so on. Different shadings represent different codewords. Solid lines represent DM words (corresponding to amplitude data), and dashed lines represent random words (corresponding to symbol data, where "random" refers to a random distribution, as opposed to the PCS distribution of amplitude data). Each CW includes a set of DM words and random words; for example, CW[0] includes DMW[0][0], DMW[0][1], etc., and RW[0][0], RW[0][1], etc. Each DMW and RW includes a set of marked bits; for example, DMW[0][0] includes bits D0.0 b0, D0.0 b1, ..., D0.0 b63.

[0055] More specifically, the DM encoder 320 operates in 64-bit output word mode. Each DM word is represented as (D[i][j] = (D[i][j].b[0], D[i][j].b[1], D[i][j].b[2], …, D[i][j].b

[63] ) ), where (i) indicates the FEC codeword to which the DM block belongs, and (j) represents the (j)th DM word within the FEC codeword. The bits within each DM word are sequentially labeled, where (D[i].[j].b[0]) is the first bit, (D[i].[j].b[1]) is the second bit, and so on. Note that parentheses are removed from the diagram within individual bits.

[0056] For the FEC codeword bits mapped to the symbol bits, the symbol bit portion is divided into 64-bit words of consecutive bits, labeled as (R[i][j]). This can be represented as (R[i][j] = (R[i][j].b[0], R[i][j].b[1], R[i][j].b[2], …, R[i][j].b

[63] ), which corresponds to (CW[i].b[5120 + j⋅64 + 0], CW[i].b[5120 + j⋅64 + 1], CW[i].b[5120 + j⋅64 + 2], …, CW[i].b[5120 + j⋅64 + 63]).

[0057] The FEC pre-interleaver 325 organizes the data so that the first half of the FEC codeword contains all amplitude bits, arranged as consecutive 64-bit DM words. Therefore, at the output of the FEC encoder, the codeword can be represented as follows:

[0058] [ CW[i] = (CW[i].b[0], CW[i].b[1], CW[i].b[2], …, CW[i].b

[10239] ) =D[i][0] ⌢ D[i][1] ⌢ D[i][2] ⌢ … ⌢ D[i]

[79] ⌢ R[i][0] ⌢ R[i][1] ⌢ R[i][2] ⌢ … ⌢R[i]

[79] ]

[0059] (⌢) represents the concatenation of sequences.

[0060] Figure 5 The illustration shows the result after further interlacing at FEC interlacer 335 according to some embodiments of the present disclosure. Figure 4Examples of interleaved and FEC-encoded codewords. The FEC interleaver 335 buffers the entire FEC codeword (10,240 bits in length), splits the codeword into two halves (the first half contains amplitude bits, and the second half contains sign bits), and then delivers bit pairs using a polling interleaving method between the amplitude and sign bits. If the input word of the FEC interleaver 335 is represented as CW[i] = D[i][0]⌢ D[i][1]⌢ D[i][2]⌢…⌢ D[i]

[79] ⌢R[i][0]⌢ R[i][1]⌢ R[i][2] ... R[i].

[79] , then its output word can be represented as: CW'[i]= ( D[i][0].b[0], R[i][0].b[0], D[i][0].b[1], R[i][0].b[1],… D[i][0].b

[63] , R[i][0].b

[63] , D[i][1].b[0], R[i][1].b[0], D [i][1].b[1], R [i][1].b[1],… D[i][1].b

[63] , R[i][1].b

[63] , …, D[i]

[79] .b

[63] , R[i]

[79] .b

[63] ).

[0061] Figure 6 Examples of codewords following a further interleaving step are illustrated according to some embodiments of this disclosure. (See also: Regarding...) Figure 2 and Figure 3 In some implementations, the FEC interleaver 235 or 335 represents two sequential interleaving processes (which can be implemented as two separate interleavers), and the output of the second interleaver is... Figure 6As shown in the diagram, this interleaver operates by mixing the bits of four different codewords in a polling manner. If the input sequence (FEC_int.inseq) of the FEC interleaver is FEC_int.inseq = (CW[0], CW[1], CW[2], CW[3], CW[4], CW[5], CW[6], CW[7],…), then the output sequence (FEC_int.outseq) is FEC_int.outseq = (CW[0].b[0], CW[1].b[0], CW[2].b[0], CW[3].b[0], CW[0].b[1], CW[1].b[1], CW[2].b[1], CW[3].b[1], CW[0].b[2],… CW[3].b

[10239] , CW[4].b[0], CW[5].b[0],…). The output bit sequence of the FEC interleaver 335 is divided into 10x1024 bit blocks to match the length of the input FEC codeword. These 10x1024 consecutive bit blocks are called the FEC interleaver output codewords and are labeled CW”[i], where i refers to the i-th output codeword. That is, FEC_int.outseq = (CW”[1], CW”[2], CW”[3], CW”[4]…); where CW”[0] is the first 10-bit codeword output by the FEC interleaver 335. A sequence of 1024 consecutive bits, CW”[1] is the second 10 from the output of the FEC interleaver 335. A sequence of 1024 consecutive bits, CW”[2] is the third 10 output of the FEC interleaver 335. A 1024-bit sequence, and so on.

[0062] like Figure 3 As shown, the NLM interleaver 345 is located at the output of the FEC interleaver 335 (e.g., the output of the second interleaver represented by the FEC interleaver 335). In this example, the NLM interleaver 345 buffers 2,048-bit blocks, organized as (64x2x4x4) bits. Due to the combined operation of the pre-FEC interleaver 325, the FEC interleaver, and the post-DM FEC interleaver, each 2,048-bit block contains 16 blocks of 64-bit DM words and 16 blocks of 64-bit random data words. Each of the four codewords contributes one-quarter of the DM word and one-quarter of the random word.

[0063] The contents of the buffer are labeled NLMI.inW (NLM interleaver input word), and can be represented as NLMI.inW[k] = (CW”[i].b[2048 k: 2048 k+2047]) = (CW”[i].b[2048 k+0], CW”[i].b[2048 k+1], CW”[i].b[2048 k+2], …, CW”[i].b[2048 k+2047]) = (D[i].[k 16+0].b[0], R[i].[k 16+0].b[0], D[i].[k 16+0].b[1], R[i].[k 16+0].b[1],…, D[i].[k 16+15].b

[63] , R[i].[k 16+15].b

[63] ), where k is an index (0 ≤ k ≤ 5) used to number the 2048 consecutive bit blocks within a 10240-bit FEC codeword.

[0064] Figure 7 The contents of an NLM interleaver buffer (e.g., the buffer of NLM interleaver 345) according to some embodiments of this disclosure are illustrated. In this example, the bits of each DM word and the bits of the random word are grouped and plotted together because the permutation does not change the buffer operation.

[0065] The NLM interleaver 345 generates 8 sets of bits, corresponding to the four amplitude channels (AL[0], AL[1], … AL[3]) and four symbol channels (SL[0], SL[1], … SL[3]) of the QAM16 dual polarization mapper. The NLM interleaver 345 then mixes the data according to a predetermined permutation. For example, the NLM interleaver 345 can mix the data according to a procedure for single-channel mode, single-polarization mode, or dual-polarization mode.

[0066] Figure 8 and Figure 9 The diagram illustrates an example channel mapping for single-channel mode. In single-channel mode, for the amplitude channel, the NLM interleaver 345 sends bits to the (n+m)th FEC codeword in a sequential manner, belonging to the m-th DM word of each n-th FEC codeword. (4-1)%4 Amplitude Channel. That is, the NLM interleaver 345 sends the first DM word of the first FEC codeword to the first amplitude channel, the first DM word of the second FEC codeword to the second amplitude channel, the first DM word of the third FEC codeword to the third amplitude channel, and the first DM word of the fourth FEC codeword to the fourth amplitude channel. Next, the NLM interleaver 345 sends the second DM word of the first FEC codeword to the second amplitude channel, the second DM word of the second FEC codeword to the third amplitude channel, and so on, until all DM words of the buffer block have been sent. A similar operation can be implemented using (n+m)%4 as an equation, which is converted into an inverse channel shift operation.

[0067] Figure 8 The illustration shows a first example amplitude channel mapping in single-channel mode. The amplitude mapping can also be represented as follows:

[0068] AL[0] = D[i+0][k 4+0]⌢D[i+1][k 4+1]⌢D[i+2][k 4+2]⌢D[i+3][k 4+3]

[0069] AL[1] = D[i+1][k 4+0]⌢D[i+2][k 4+1]⌢D[i+3][k 4+2]⌢D[i+0][k 4+3]

[0070] AL[2] = D[i+2][k 4+0]⌢D[i+3][k 4+1]⌢D[i+0][k 4+2]⌢D[i+1][k 4+3]

[0071] AL[3] = D[i+3][k 4+0]⌢D[i+0][k 4+1]⌢D[i+1][k 4+2]⌢D[i+2][k 4+3]

[0072] in:

[0073] AL[0] = HI amplitude channel

[0074] AL[1] = HQ amplitude channel

[0075] AL[2] = VI amplitude channel

[0076] AL[3] = VQ amplitude channel

[0077] Figure 9 An example symbol channel mapping of an NLM interleaver 345 in single-channel mode is illustrated according to some embodiments of the present disclosure.

[0078] Typically, symbol channels can be optimally interleaved according to a default FEC interleaver (e.g., FEC interleaver 335). For example, take a block of (n) bits (one bit per codeword in the interleaver; 4 in this case) and assign those bits to symbol channels of one polarization. For the next block of (n) bits, perform a similar distribution, but shift the symbol channel index by 1. Repeat this process for each symbol channel in each polarization using a different incremental index shift. Then, take the next set of (k x n) bits (where (k) is the number of symbol channels per polarization; typically, (k = 2)) and repeat the process for symbol channels of another polarization. Continue this process until all symbol bits in the NLMI buffer block are used.

[0079] Symbolic channel mapping can also be represented as follows:

[0080] SL[0] = (R[i+0][k 4+0].b[0], R[i+2][k 4+0].b[0], R[i+1][k 4+0].b[1],R[i+3][k 4+0].b[1], …

[0081] SL[1] = (R[i+1][k 4+0].b[0], R[i+3][k 4+0].b[0], R[i+0][k 4+0].b[1],R[i+2][k 4+0].b[1], …

[0082] SL[2] = (R[i+0][k 4+0].b[2], R[i+2][k 4+0].b[2], R[i+1][k 4+0].b[3],R[i+3][k 4+0].b[3], …

[0083] SL[3] = (R[i+1][k 4+0].b[2], R[i+3][k 4+0].b[2], R[i+0][k 4+0].b[3],R[i+2][k 4+0].b[3], …

[0084] As an alternative to single-channel mode, the NLM interleaver 345 can operate in single-polarization mode, which assigns the even and odd bits of each distributed match word to in-phase and quadrature amplitude channels with the same polarization. In single-polarization mode, for amplitude channels, the NLM interleaver 345 splits each DM word into even and odd bits and sends consecutive even or odd bits of that DM word to a specific amplitude channel. Figure 10 The diagram illustrates the second amplitude channel mapping for an NLM interleaver based on a single polarization mode.

[0085] The following is an example process for allocating the even and odd bits of a DM word to each amplitude channel. The NLM interleaver 345 forms groups of (n) DM words, each belonging to a different FEC codeword, where (n) is the number of different codewords in each interleaver block. These groups can be called subgroups. The NLM interleaver 345 then forms groups of four subgroups, which are called blocks.

[0086] For the first sub-packet of each group, the NLM interleaver 345 sends the DM word from the even-numbered codeword to the amplitude channel of polarization H (one polarization), and sends the DM word from the odd-numbered codeword to the amplitude channel of polarization V (another polarization). Additionally, for these first sub-packets, the NLM interleaver 345 sends the even-numbered bits of each DM word to the I component of the corresponding polarization, and sends the odd-numbered bits to the Q component.

[0087] For the second sub-group of each packet, the NLM interleaver 345 sends the DM word from the odd-numbered codeword to the amplitude channel of polarization H, and sends the DM word from the even-numbered codeword to the amplitude channel of polarization V. Similarly, for these second sub-groups, the NLM interleaver 345 sends the even-numbered bits of each DM word to the I component of the corresponding polarization, and sends the odd-numbered bits to the Q component.

[0088] For the third sub-packet of each group, the NLM interleaver 345 sends the DM word from the even-numbered codeword to the amplitude channel of polarization H, and sends the DM word from the odd-numbered codeword to the amplitude channel of polarization V. For these third sub-packets, the NLM interleaver 345 sends the odd-numbered bits of each DM word to the I component of the corresponding polarization, and sends the even-numbered bits to the Q component.

[0089] For the fourth sub-packet of each group, the NLM interleaver 345 sends the DM word from the odd-numbered codeword to the amplitude channel of polarization H, and sends the DM word from the even-numbered codeword to the amplitude channel of polarization V. For these fourth sub-packets, the NLM interleaver 345 sends the odd bits of each DM word to the I component of the corresponding polarization, and sends the even bits to the Q component.

[0090] The amplitude mapping for a single polarization mode can be represented as follows:

[0091] AL[0] = D[i+0][k 4+0].even⌢D[i+2][k 4+0].even⌢D[i+1][k 4+1].even⌢D[i+3][k 4+1].even⌢

[0092] D[i+0][k 4+2].odd ⌢D[i+2][k 4+2].odd ⌢D[i+1][k 4+3].odd ⌢D[i+3][k 4+3].odd…

[0093] AL[1] = D[i+0][k 4+0].odd ⌢D[i+2][k 4+0].odd ⌢D[i+1][k 4+1].odd ⌢D[i+3][k 4+1].odd ⌢

[0094] D[i+0][k 4+2].even⌢D[i+2][k 4+2].even⌢D[i+1][k 4+3].even⌢D[i+3][k 4+3].even…

[0095] AL[2] = D[i+1][k 4+0].even⌢D[i+3][k 4+0].even⌢D[i+0][k 4+1].even⌢D[i+2][k 4+1].even⌢

[0096] D[i+1][k 4+2].odd ⌢D[i+3][k 4+2].odd ⌢D[i+0][k 4+3].odd ⌢D[i+2][k 4+3].odd…

[0097] AL[3] = D[i+1][k 4+0].odd ⌢D[i+3][k 4+0].odd ⌢D[i+0][k 4+1].odd ⌢D[i+2][k 4+1].odd ⌢

[0098] D[i+1][k 4+2].even⌢D[i+3][k 4+2].even⌢D[i+0][k 4+3].even⌢D[i+2][k 4+3].even…

[0099] in:

[0100] DMW[i][j].even = (D[i][j].b[0], D[i][j].b[2], D[i][j].b[4],…, D[i][j].b

[62] )

[0101] DMW[i][j].odd = (D[i][j].b[1], D[i][j].b[3], D[i][j].b[5],…, D[i][j].b

[63] )

[0102] Similar to the single-channel mode, in the single-polarization mode, the symbol channels are interleaved according to the FEC interleaver (e.g., NLM interleaver 345). For example, above Figure 9 The symbol mapping illustrated and described in the figure can also be used for single polarization modes.

[0103] As another example, the NLM interleaver 345 can operate in a dual-polarization mode, which distributes groups of bits from multiple distributed matching words across amplitude channels with different polarizations according to the channel shift sequence. In dual-polarization mode, for each amplitude channel, the NLM interleaver 345 divides each DM word into four groups of bits: bits with a base index of a multiple of 4 (referred to as (g[0])), a multiple of 4 plus 1 (referred to as (g[1])), a multiple of 4 plus 2 (referred to as (g[2])), and a multiple of 4 plus 3 (referred to as (g[3])). The NLM interleaver 345 sends these groups of consecutive bits to a specific amplitude channel. The process for allocating the (g[0]), (g[1]), (g[2]), and (g[3]) bits of each DM word to the amplitude channel is as follows.

[0104] The NLM interleaver 345 forms groups of (n) DM words, each DM word belonging to a different FEC codeword, where (n) is the number of different codewords in each interleaver block. These groups can be called DM subgroups. Then, the NLM interleaver 345 forms groups of 4 DM subgroups, which are called blocks.

[0105] For the (m)th subgroup, send group (g[x]) (where (x) is in {0, 1, 2, 3}) to the (AL[(x+m) %4]) amplitude channel. In other words:

[0106] For the first sub-group of each group, the NLM interleaver 345 sends the (g[0]) bit of the DM word to the (AL[0]) channel (H polarization I amplitude channel), the (g[1]) bit to the (AL[1]) channel (H polarization Q amplitude channel), the (g[2]) bit to the (AL[2]) channel (V polarization I amplitude channel), and the (g[3]) bit to the (AL[3]) channel (V polarization Q amplitude channel).

[0107] For the second sub-packet of each packet, the NLM interleaver 345 sends the (g[0]) bit of the DM word to the (AL[1]) channel, sends the (g[1]) bit to the (AL[2]) channel, sends the (g[2]) bit to the (AL[3]) channel, and sends the (g[3]) bit to the (AL[0]) channel.

[0108] For the third sub-packet of each packet, the NLM interleaver 345 sends the (g[0]) bit of the DM word to the (AL[2]) channel, sends the (g[1]) bit to the (AL[3]) channel, sends the (g[2]) bit to the (AL[0]) channel, and sends the (g[3]) bit to the (AL[1]) channel.

[0109] For the fourth sub-packet of each packet, the NLM interleaver 345 sends the (g[0]) bit of the DM word to the (AL[3]) channel, the (g[1]) bit to the (AL[0]) channel, the (g[2]) bit to the (AL[1]) channel, and the (g[3]) bit to the (AL[2]) channel.

[0110] The amplitude mapping of the dual polarization mode can be represented as follows:

[0111] AL[0] = D[i+0][k 4+0].g0⌢D[i+1][k 4+0].g0⌢…⌢D[i+3][k 4+0].g0⌢D[i+0][k 4+1].g1⌢…

[0112] AL[1] = D[i+0][k 4+0].g1⌢D[i+1][k 4+0].g1⌢…⌢D[i+3][k 4+0].g1⌢D[i+0][k 4+1].g2⌢…

[0113] AL[2] = D[i+0][k 4+0].g2⌢D[i+1][k 4+0].g2⌢…⌢D[i+3][k 4+0].g2⌢D[i+0][k 4+1].g3⌢…

[0114] AL[3] = D[i+0][k 4+0].g3⌢D[i+1][k 4+0].g3⌢…⌢D[i+3][k 4+0].g3⌢D[i+0][k 4+1].g0⌢…

[0115] in:

[0116] D[i][j].g[0] = (D[i][j].b[0], D[i][j].b[4], D[i][j].b[8],…, D[i][j].b

[60] )

[0117] D[i][j].g[1] = (D[i][j].b[1], D[i][j].b[5], D[i][j].b[9],…, D[i][j].b

[61] )

[0118] D[i][j].g[2] = (D[i][j].b[2], D[i][j].b[6], D[i][j].b

[10] ,…, D[i][j].b

[62] )

[0119] D[i][j].g[3] = (D[i][j].b[3], D[i][j].b[7], D[i][j].b

[11] ,…, D[i][j].b

[63] )

[0120] Similar to single-channel and single-polarization modes, in dual-polarization mode, the symbol channels are interleaved according to an FEC interleaver (e.g., an NLM interleaver 345). For example, above... Figure 9 The symbol mapping illustrated and described in the figure can also be used for dual polarization modes.

[0121] Example RCS architecture with NLM interleaving, payload error decorrelation, and parity check interleaving

[0122] Figure 11 The illustration shows a pair of block diagrams illustrating encoding and decoding signals using FEC and distributed matching along with nonlinearity mitigation interleavers and deinterleavers, as well as payload error decorcorrelation and parity check interleavers, according to some embodiments of the present disclosure. Similar to the previous block diagrams, Figure 11 This includes a transmitter section 1100 and a corresponding receiver section 1150. In this example, the FEC encoder 1130 may be a step encoder, which can be combined with a payload error decorrelator that operates on the codeword payload and a parity interleaver for interleaving parity bits.

[0123] In transmitter section 1100, input signal 1105 is provided to splitter 1110, which splits the data stream into a first sequence (such as a symbol sequence) and a second sequence (such as an amplitude sequence). The amplitude sequence is processed by DM encoder 1120, which generates distributed matching codewords for probabilistic constellation shaping. The output of DM encoder 1120 is provided to FEC pre-interleaver 1125, which applies deterministic and reversible permutations to the DM encoded bits, distributing them across time or codewords to enhance error recovery capability. Splitter 1110, DM encoder 1120, and FEC pre-interleaver 1125 can be similar to splitter 310, DM encoder 320, and FEC pre-interleaver 325.

[0124] Following pre-interleaving (FEC), the data is processed by the payload error decorrelator 1127. The payload error decorrelator modifies the input of the FEC encoder 1130 to decorrelate the error pattern of the payload portion of the codeword. In some embodiments, the payload error decorrelator 1127 is configured to modify the encoder input without interleaving the payload bits. The FEC encoder 1130 generates codewords with a payload portion and a parity portion, wherein parity bits are added based on both sign and amplitude data. In some embodiments, the FEC encoder may include a ladder encoder configured to generate codewords with different payload and parity portions.

[0125] The output of the FEC encoder 1130 is provided to a parity interleaver 1133, which permutes the parity bits to further disperse error patterns and enhance error correction performance. The parity interleaver can buffer multiple DM words generated from the amplitude sequence and multiple random words generated from the symbol sequence, where the random words are further derived from the parity section. The output of the parity interleaver 1133 is then processed by an NLM interleaver 1145, which buffers the amplitude signal and permutes the buffered amplitude bits to reduce the energy variance in the encoded QAM signal. The NLM interleaver 1145 can reassemble distributed matching codewords or allocate consecutive bits to the amplitude channels according to the channel shift sequence, and can operate in single-polarization or dual-polarization mode. The permuted symbol and amplitude bits from the NLM interleaver 1145 are provided to a mapper 1140, which allocates the bits to the appropriate I / Q components for QAM symbol generation and transmission.

[0126] In receiver section 1150, the received signal is first processed by soft demapper 1160, which extracts soft information for the symbol and amplitude bits from the received QAM symbols. The output of soft demapper 1160 is provided to NLM deinterleaving unit 1155, which buffers the amplitude bits and reverses the permutations applied by NLM deinterleaving unit 1145 at the transmitter, thereby restoring the order of the amplitude bits. The output of NLM deinterleaving unit 1155 is processed by parity deinterleaving unit 1162, which reverses the permutations applied by parity deinterleaving unit 1133. Error decorrelation unit 1163 further processes the data to recover the original error characteristics before FEC decoding. The output is then processed by SD-FEC decoder 1170, which performs error correction using the recovered bit sequence. Inverse error decorrelation unit 1173 and pre-FEC deinterleaving unit 1175 further process the data to reconstruct the original order of DM-coded bits. The DM decoder 1180 recovers the original amplitude data, and the combiner 1190 combines the recovered amplitude and symbol data to generate the recovered signal 1195.

[0127] Figure 11 The architecture shown includes multiple interleaving and deinterleaving operations, as well as decorrelation operations, including pre-FEC interleaving, payload error decorrelation, parity check interleaving, and NLM interleaving, with corresponding deinterleaving and decorrelation stages in the receiver path. The payload error decorrelator and parity check interleaver provide enhanced error dispersion and support advanced FEC schemes such as ladder codes.

[0128] Figure 12 The illustrations depict some embodiments of the present disclosure. Figure 11 Example FEC encoder output of the encoder. Figure 13 The illustrations depict some embodiments of the present disclosure. Figure 11 Example output codewords of the encoder.

[0129] As mentioned above, the FEC encoder 1130 can be a ladder encoder with a codeword length of N = 512x512 bits and a dimension of K = 512x480, resulting in an FEC overhead of 6.67%. Figure 12 In the codeword, the codeword is marked as CW[i] = (CW[i].b[0], CW[i].b[1], CW[i].b[2], ... , CW[i].b[262143]), where i refers to the i-th transmitted codeword, CW[i].b[0] refers to the first bit of the codeword, CW[i].b[1] refers to the second transmitted bit, and so on.

[0130] The FEC encoder 1130 works in conjunction with a payload error decorrelation unit 1127 for the codeword payload (512x480 data bits) and a parity error decorrelation unit (512x32 parity bits) (e.g., a parity interleaver 1133). The payload error decorrelation unit modifies the encoder input and affects the generation of the resulting parity bits. However, the payload bits are transmitted without being interleaved. Therefore, the FEC pre-interleaver 1125 operates as follows: the first 512x480 bits consist of a sequence of a DM word (DM[i][j]: a 32-bit word in this example) and a random word (RW[i][j]), each 32 bits in length. The final 512x32 FEC encoder payload bits consist of the DM word. After the FEC encoder 1130 generates the parity bits, the amplitude and the number of symbol bits are equal. These final 512x32 payload bits, consisting entirely of 32-bit DM words, are buffered so that when 512x32 FEC parity bits are available, they can be interleaved into DM words and 32-bit random words (from the parity bits) pairs.

[0131] In this case, the NLM interleaver 1145 buffers 16 consecutive DM words and 16 consecutive 32-bit random words, and performs any of the above modes (single-channel, single-polarization, dual-polarization) with a simplification of data from only a single codeword.

[0132] Example RCS architecture with NLM interleaving and parallel paths

[0133] In other examples, the FEC encoder can have codewords of semi-infinite length, such as braided codes. In such embodiments, the transmitter and receiver sections can each include two parallel encoding paths (in the transmitter) and two parallel decoding paths (in the receiver), as... Figure 14 As shown.

[0134] Figure 14 The illustration shows a block diagram of a transmitter section 1400 and a receiver section 1450 for encoding and decoding signals in an optical communication system according to an embodiment of the present disclosure. Figure 14 The architecture shown supports advanced FEC schemes that utilize semi-infinite codewords, block payloads, parity check structures, and joint interleaving operations.

[0135] exist Figure 14 In the example, the FEC encoder 1430 can employ a semi-infinite codeword composed of FEC blocks, where each block comprises 16x256 bits (4096 bits per block). Each block contains 14x256 bits of payload and 2x256 bits of parity, resulting in an FEC overhead of 14.29%. The FEC blocks are further divided into 16x16 bit sub-blocks (256-bit sub-blocks), referred to as blocks. There are two parallel DM encoding and FEC encoding paths on the transmit path, and two parallel DM decoding and FEC decoding paths on the receive path. Specifically, each encoding path includes a DM encoder 1420A or 1420B, an FEC pre-interleaver 1425A or 1425B, an FEC encoder 1430A or 1430B, and an FEC interleaver 1435A or 1435B, with "A" components along one path and "B" components on parallel paths. The outputs of FEC interleavers 1435A and 1435B are provided to joint FEC interleaver 1437, which performs interleaving operations on signals from both paths. The decoding side includes joint FEC deinterleaver 1463 (which reverses the operation of joint FEC interleaver 1437), FEC deinterleavers 1465A and 1465B, SD-FEC decoders 1470A and 1470B, FEC pre-deinterleavers 1475A and 1475B, and DM decoders 1480A and 1480B, with "A" components along one path and "B" components on parallel paths.

[0136] In the example, the DM word length can be chosen to be 256 bits. The codeword can be organized as a block array with 2 rows and 8 columns, corresponding to 32 rows of bits and 128 columns of bits. Block columns 0 to 6 contain payload bits, while block column 7 contains parity bits.

[0137] In each transmit path, FEC pre-interleavers 1425A and 1425B distribute DM words within blocks. In this example, each DM word is 256 bits long. FEC pre-interleavers 1425A and 1425B can assemble DM words such that each word is contained within a single FEC block. Additionally, even-numbered block columns contain blocks with DM words, while odd-numbered block columns contain blocks with 256-bit random words. Parity blocks (block column 7) are also considered to have random content. In this context, a random word refers to bits that come directly from the input and are not encoded by the distribution-matched encoder, as described in the previous example.

[0138] FEC interleavers 1435A and 1435B mix DM words with random words. The outputs of the DM FEC interleavers 1435A and 1435B are arranged in a 2x8 block matrix, similar to the output blocks of the FEC encoders 1430A and 1430B. Output blocks can be created by polling and interleaving 16-bit rows of even and odd blocks. For example, output block 0 row 0 corresponds to input block 0 row 0; output block 0 row 1 corresponds to input block 1 row 0; output block 0 row 2 corresponds to input block 0 row 1; output block 0 row 3 corresponds to input block 1 row 1, and so on. This arrangement ensures that after the interleaving steps at the FEC interleavers 1435A and 1435B and the joint FEC interleaver 1440, the NLM buffer used by the NLM interleaver 1445 is smaller than the memory required by the joint FEC interleaver 1440 alone.

[0139] The joint FEC interleaver 1440 can buffer a 32x8 block matrix, where even-numbered blocks come from FEC encoder 1430A and odd-numbered blocks come from FEC encoder 1430B. The block array can be divided into two subarrays by middle rows: rows 0 to 15 are assigned to the first subarray, and rows 16 to 31 are assigned to the second subarray. The output sequence for the joint FEC interleaver 1440 is generated as follows: 8 bits are read from the even-numbered block column of subarray 0, then 8 bits are read from the odd-numbered block column of subarray 0, then 8 bits are read from the even-numbered block column of subarray 1, and finally 8 bits are read from the odd-numbered block column of subarray 1. This process is repeated until all bits in the first column are read. The same process is then applied to subsequent columns until all bits are read.

[0140] Using a combination of FEC pre-interleavers 1425A and 1425B, DM FEC interleavers 1435A and 1435B, and joint FEC interleaver 1440, NLM interleaver 1445 is designed to buffer 256x2x32 bits (16,384 bits) of the output of joint FEC interleaver 1440. The resulting buffer content can contain 32 pairs of DM words and random words, evenly divided between FEC encoders 1430A and 1430B. The buffer data can be divided into four subgroups, each containing four pairs of DM words plus random words from FEC encoder 1430A and four pairs of DM words plus random words from FEC encoder 1430B. The aforementioned interleaving process (e.g., single-channel mode, single-polarization mode, or dual-polarization mode) can then be applied to each subgroup, thereby reducing the number of codewords from 4 to 2 and the length of the DM words and random words from 64 bits to 256 bits.

[0141] Example bitmap for interleaver

[0142] Figure 15 An example bitmap diagram is illustrated for a 16QAM implementation with 24 codewords and a 32-bit DM word, according to some embodiments of this disclosure. In this example, each codeword is assigned a unique numeric identifier C0-C23. Bits from each codeword are distributed across multiple amplitude channels according to a predetermined channel shift sequence.

[0143] The output patterns are arranged in four blocks, each containing two rows. Within each block, the top row corresponds to the amplitude bits for HI (top row of the topmost block), HQ (top row of the second block), VI (top row of the third block), and VQ (top row of the bottom block). The bottom row of each block corresponds to the symbol bits for HI, HQ, VI, or VQ. Within each block, each column corresponds to the bit position within the transmitted sequence. Bits are marked using their respective codeword numbers (between C0 and C23). Amplitude bits (i.e., DM-controlled bits) are further marked using DM blocks (e.g., c0, c1). Symbol bits include unnumbered letters (a, b, c, d) indicating how the 24 codewords are assembled into four groups, which are then divided into four symbol bits. Each 24-bit random bit packet (used for symbols) is mapped to symbol bits, with the mapping shifted from block to block. The mapping is performed such that consecutive bits from each codeword are not concentrated within a single amplitude channel, but are interleaved across several channels. This arrangement ensures that bits from different codewords are evenly distributed throughout the transmission (e.g., across amplitude channels), thereby minimizing the possibility of energy concentration in any single channel or time interval.

[0144] Figure 15The interleaving operations described herein can be implemented by an NLM interleaver (e.g., any of the NLM interleavers described above). The NLM interleaver buffers the output of the encoding stage and, according to... Figure 15 The channel shift sequence shown permutes bits. In some embodiments, the mapping can be extended to support dual-polarization transmission, where groups of bits are assigned to amplitude channels associated with different polarizations. For example, an NLM interleaver can operate in dual-polarization mode, distributing groups of bits from each distribution match word across amplitude channels of different polarizations, or in relation to... Figure 10 The single-polarization mode operation is described. This mapping strategy supports robust error correction and mitigates the effects of optical channel nonlinearity by reducing the energy variance in the transmitted signal. Figure 15 An example is illustrated; more generally, an NLM interleaver can interleave bits from other numbers of codewords, for example, at least 24 different codewords. Select Example

[0145] Example 1 provides a method for reducing nonlinear effects in coded quadrature amplitude modulation (QAM) signals, the method comprising: splitting a bit sequence into a first sequence and a second sequence; encoding the second sequence using a distributed matched encoder; performing a first interleaving operation on the first sequence and the encoded second sequence; encoding the output of the first interleaving operation using a forward error correction (FEC) encoder; performing a second interleaving operation based on the signal output by the FEC encoder; and performing a third interleaving operation based on the signal output by the second interleaving operation, wherein the second interleaving operation outputs an amplitude signal and a symbol signal, and the third interleaving operation reduces the energy variance in the amplitude signal.

[0146] Example 2 provides the method of Example 1, wherein encoding the output of the first interleaving operation using an FEC encoder includes: generating a parity bit based on the first interleaving signal and the second interleaving signal; and adding the parity bit to the first interleaving signal.

[0147] Example 3 provides the method of Example 1 or 2, in which the encoded QAM signal is output through an optical channel.

[0148] Example 4 provides a method for any of Examples 1 to 3, wherein the third interleaving operation further includes: buffering the amplitude signal output by the second interleaving operation; and replacing the buffered amplitude signal to reduce energy variance.

[0149] Example 5 provides the method of Example 4, in which a second sequence is encoded using a distribution-matching encoder to generate multiple distribution-matching codewords, and the amplitude signal of the permutation buffer is used to reduce energy variance by recombining the distribution-matching codewords.

[0150] Example 6 provides the method of Example 5, in which the FEC encoder interleaves bits of different distribution-matching codewords in multiple distribution-matching codewords.

[0151] Example 7 provides a method of any one of Examples 1 to 6, wherein the FEC encoder includes a step encoder configured to generate codewords having a payload portion and a parity portion, and a third interleaving operation buffers a plurality of distributed matching words generated from a second sequence and a plurality of random words generated from a first sequence, wherein the random words are further derived from the parity portion.

[0152] Example 8 provides the method of Example 7, in which the step encoder operates in conjunction with a payload error decorrelation unit and a parity interleaving unit, and in which the payload error decorrelation unit modifies the input of the step encoder without interleaving the payload bits.

[0153] Example 9 provides a method for any of Examples 1-6, wherein the FEC encoder includes a semi-infinite codeword encoder configured to generate multiple FEC blocks, each block including a payload portion and a parity portion arranged in blocks.

[0154] Example 10 provides the method of Example 9, wherein the third interleaving operation includes: buffering a set of distributed matching words and random words corresponding to multiple blocks from different FEC blocks, and interleaving words across amplitude channels.

[0155] Example 11 provides a method of any of Examples 1 to 6, wherein the FEC encoder generates multiple codewords, and a second interleaving operation interleaves bits from at least twenty-four different codewords.

[0156] Example 12 provides the method of Example 11, wherein the third interleaving operation includes: allocating consecutive bits of each distributed matching word to the amplitude channel according to the channel shift sequence, the channel shift sequence being uniformly distributed across the amplitude channel.

[0157] Example 13 provides the method of Example 12, wherein the third interleaving operation is configured to operate in a dual polarization mode, which distributes the bit groups from each distributed matching word across amplitude channels of different polarizations.

[0158] Example 14 provides an encoding apparatus for reducing nonlinear effects in coded quadrature amplitude modulation (QAM) signals. The encoding apparatus includes: a forward error correction (FEC) encoder; a distributed matching encoder, wherein the FEC encoder and the distributed matching encoder are arranged in a reverse cascaded scheme, wherein the distributed matching encoder is configured to operate on the input data stream before the FEC encoder; a first interleaver, following the FEC encoder, wherein the first interleaver interleaves the distributed matching amplitude bits; and a nonlinear mitigation (NLM) interleaver, following the FEC encoder, wherein the NLM interleaver is configured to: buffer the amplitude bits output by the first interleaver; and permutate the buffered amplitude bits to reduce the energy variance in the coded QAM signal.

[0159] Example 15 provides the encoding device of Example 14, and also includes a second interleaver between the distributed matching encoder and the FEC encoder, the second interleaver being configured to interleave the codewords output by the distributed matching encoder.

[0160] Example 16 provides an encoding device similar to that of Example 14 or 15, wherein a distributed matching encoder is configured to generate multiple distributed matching codewords, and an NLM interleaver is configured to reassemble the distributed matching codewords before mapping them to amplitude channels.

[0161] Example 17 provides an encoding device for any of Examples 14 through 16, wherein the NLM interleaver is configured to operate in a single polarization mode, which assigns the even and odd bits of each distributed matching word to a single polarization in-phase and quadrature amplitude channel.

[0162] Example 18 provides an encoding device for any of Examples 14 through 17, wherein the NLM interleaver is configured to operate in a dual polarization mode, which distributes groups of bits from multiple distributed matching words across amplitude channels of different polarizations according to a channel shift sequence.

[0163] Example 19 provides an encoding device of Example 14 or 15, wherein the FEC encoder is configured to process multiple codewords, and the first interleaver is configured to interleave bits from at least twenty-four different codewords.

[0164] Example 20 provides the encoding device of Example 19, wherein an NLM interleaver is configured to assign consecutive bits of each distributed matching word to an amplitude channel according to a channel shift sequence, the channel shift sequence being uniformly distributed across the amplitude channels.

[0165] Example 21 provides the encoding device of Example 19 or 20, in which the NLM interleaver is configured to operate in a dual polarization mode, which distributes the bit groups from each distributed matching word across amplitude channels of different polarizations.

[0166] Example 22 provides the encoding device of Example 14 or 15, and also includes a payload error decorrelation between the distributed matching encoder and the FEC encoder, the payload error decorrelation being configured to modify the input to the FEC encoder before generating the parity bit.

[0167] Example 23 provides the encoding device of Example 22, and also includes a parity error interleaver between the FEC encoder and the NLM interleaver, the parity error interleaver being configured to interleave parity bits generated by the FEC encoder.

[0168] Example 24 provides the encoding device of Example 22 or 23, where the FEC encoder is a step encoder.

[0169] Example 25 provides an encoding device of Example 14 or 15, wherein an FEC encoder and a distribution matching encoder are arranged along a first path, and the device further includes a second FEC encoder and a second distribution matching encoder arranged along a second path parallel to the first path.

[0170] Example 26 provides the encoding device of Example 25, wherein a first path includes a first FEC post-interleaver following an FEC encoder, a second path includes a second FEC post-interleaver following a second FEC encoder, and the first interleaver receives the outputs of the first and second FEC post-interleavers.

[0171] Example 27 provides a decoding apparatus for decoding a coded quadrature amplitude modulation (QAM) signal with reduced nonlinear effects. The apparatus includes: a demapper configured to output symbol bits and amplitude bits from a received QAM signal; a nonlinear mitigation (NLM) deinterleaving unit following the demapper, configured to: buffer the amplitude bits output by the demapper; and replace the buffered amplitude bits based on interleaving performed at the encoding device to reduce nonlinear effects; a forward error correction (FEC) decoder following the NLM deinterleaving unit; and a distributed matching decoder following the FEC decoder.

[0172] Example 28 provides the decoding device of Example 27, and also includes an FEC deinterleaver between the NLM deinterleaver and the FEC decoder. Variations and other annotations

[0173] Detailed implementations, such as the “Selection Examples” section, provide various examples of the embodiments disclosed herein.

[0174] As used herein, the term “coupled to” or “coupled with” refers to a relationship between electronic components or circuit elements, wherein the components communicate electrically with each other and are able to transmit and / or receive electrical signals between them. The term “coupled to” does not require a direct physical or electrical connection between the coupled components. Rather, “coupled to” can encompass an arrangement in which components are connected via one or more intermediate elements, components, circuits, or transmission paths. For example, a first component may be “coupled to” a second component via an intermediate component (such as a resistor, capacitor, inductor, transistor, logic gate, bus, transformer, or other electronic component) or via an intermediate transmission path, while still maintaining the ability to communicate electrically between the first and second components.

[0175] The foregoing description of implementations of this disclosure, including the description in the abstract, is not intended to be exhaustive or to limit this disclosure to the precise form disclosed. While specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications may be made to this disclosure in light of the above specific embodiments.

[0176] For illustrative purposes, specific figures, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementation. However, it will be apparent to those skilled in the art that this disclosure may be practiced without specific details and / or may be practiced using only some of the aspects described. In other instances, well-known features have been omitted or simplified to avoid obscuring the illustrative implementation.

[0177] Furthermore, reference has been made to the accompanying drawings, which form a part of this document, illustrating possible embodiments. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the above specific embodiments should not be considered limiting.

[0178] Various operations can be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the disclosed subject matter. However, the order of description should not be construed as implying that these operations are necessarily sequentially related. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from that described in the embodiments. Various additional operations may be performed in additional embodiments, or the described operations may be omitted.

[0179] For the purposes of this disclosure, the phrase "A or B" or the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, or C" or the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used as a reference measurement range, includes the endpoints of the measurement range.

[0180] This specification uses the phrase "in embodiments" or "in multiple embodiments," each of which can refer to one or more embodiments of the same or different embodiments. The terms "comprising," "including," "having," etc., as used with respect to embodiments of this disclosure, are synonymous. This disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side" to explain various features of the drawings, but these terms are for ease of discussion only and do not imply a desired or required orientation. The drawings are not necessarily drawn to scale. Unless otherwise specified, ordinal adjectives such as "first," "second," "third," etc., are used to describe common objects, indicating only different instances of the same object and not intended to imply that the objects so described must be in a given sequence, whether temporally, spatially, rankly, or in any other way.

[0181] In the above specific embodiments, the various aspects of the illustrative implementation will be described using terminology commonly used by those skilled in the art, in order to convey the substance of its work to other those skilled in the art.

[0182] The terms “substantially,” “near,” “approximately,” “near,” and “about” generally refer to within + / - 20% of the target value, as described herein or known in the art. Similarly, terms indicating various element orientations, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements, generally refer to within + / - 5% to 20% of the target value, as described herein or known in the art.

[0183] Furthermore, the terms “comprise / comprising / include / including,” “have / having,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a method, process, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such a method, process, or apparatus. Additionally, the term “or” refers to an inclusive “or,” not an exclusive “or.”

[0184] The systems, methods, and apparatuses disclosed herein each have several innovative aspects, none of which are solely responsible for all the desired properties disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the description and accompanying drawings.

Claims

1. A method for reducing nonlinear effects in coded quadrature amplitude modulation (QAM) signals, the method comprising: Divide the bit sequence into a first sequence and a second sequence; The second sequence is encoded using a distribution matching encoder; Perform a first interleaving operation on the first sequence and the encoded second sequence; The output of the first interleaving operation is encoded using a forward error correction (FEC) encoder; A second interleaving operation is performed based on the signal output by the FEC encoder; as well as A third interleaving operation is performed based on the signal output by the second interleaving operation, wherein the second interleaving operation outputs an amplitude signal and a symbol signal, and the third interleaving operation reduces the energy variance in the amplitude signal.

2. The method of claim 1, wherein encoding the output of the first interleaving operation using the FEC encoder comprises: Parity check bits are generated based on the first and second interleaved signals; as well as Add the parity bit to the first interleaved signal.

3. The method according to claim 1, wherein the encoded QAM signal is output through an optical channel.

4. The method of claim 1, wherein the third interleaving operation further comprises: Buffer the amplitude signal output by the second interleaving operation; as well as The amplitude signal of the buffer is replaced to reduce the energy variance.

5. The method of claim 4, wherein encoding the second sequence using the distribution matching encoder to generate a plurality of distribution matching codewords, and permuting the buffered amplitude signal to reduce the energy variance includes recombining the distribution matching codewords.

6. The method of claim 5, wherein the FEC encoder interleaves bits of different distribution-matching codewords among the plurality of distribution-matching codewords.

7. The method of claim 1, wherein the FEC encoder comprises a step encoder configured to generate codewords having a payload portion and a parity portion, and the third interleaving operation buffers a plurality of distributed matching words generated from the second sequence and a plurality of random words generated from the first sequence, wherein the random words are further derived from the parity portion.

8. The method of claim 7, wherein the step encoder operates in conjunction with a payload error decorrelation unit and a parity check interleaver, and wherein the payload error decorrelation unit modifies the input of the step encoder without interleaving payload bits.

9. The method of claim 1, wherein the FEC encoder comprises a semi-infinite codeword encoder configured to generate a plurality of FEC blocks, each block comprising a payload portion and a parity portion arranged in blocks.

10. The method of claim 9, wherein the third interleaving operation comprises: The buffer corresponds to a set of distributed matching words and random words from multiple blocks from different FEC blocks, as well as the words of the cross-amplitude channel interleaving buffer.

11. The method of claim 1, wherein the FEC encoder generates a plurality of codewords, and the second interleaving operation interleaves bits from at least twenty-four different codewords.

12. The method of claim 11, wherein the third interleaving operation comprises: Each consecutive bit of a distributed matching word is assigned to an amplitude channel according to a channel shift sequence, the channel shift sequence being uniformly distributed across the amplitude channel.

13. The method of claim 12, wherein the third interleaving operation is configured to operate in a dual polarization mode, the dual polarization mode distributing the bit groups from each distributed matching word across amplitude channels of different polarizations.

14. An encoding device for reducing nonlinear effects in coded quadrature amplitude modulation (QAM) signals, the encoding device comprising: Forward error correction (FEC) encoder; A distributed matching encoder, wherein the FEC encoder and the distributed matching encoder are arranged in a reverse cascaded scheme, wherein the distributed matching encoder is configured to operate on the input data stream before the FEC encoder; A first interleaver, which follows the FEC encoder, wherein the first interleaver interleaves distributed amplitude bits; and A nonlinear mitigation NLM interleaver, which follows the FEC encoder, is configured to: Buffer the amplitude bits output by the first interleaver; and The amplitude bits of the buffer are replaced to reduce the energy variance in the encoded QAM signal.

15. The encoding apparatus of claim 14, further comprising a second interleaver between the distributed matching encoder and the FEC encoder, the second interleaver being configured to interleave codewords output by the distributed matching encoder.

16. The encoding apparatus of claim 14, wherein the distribution-matching encoder is configured to generate a plurality of distribution-matching codewords, and the NLM interleaver is configured to reassemble the distribution-matching codewords before mapping them to an amplitude channel.

17. The encoding apparatus of claim 14, wherein the FEC encoder is configured to process a plurality of codewords, and the first interleaver is configured to interleave bits from at least twenty-four different codewords.

18. The encoding apparatus of claim 17, wherein the NLM interleaver is configured to allocate consecutive bits of each distributed matching word to an amplitude channel according to a channel shift sequence, the channel shift sequence uniformly distributing bits across the amplitude channel.

19. A decoding apparatus for decoding coded quadrature amplitude modulation (QAM) signals with reduced nonlinear effects, the apparatus comprising: A demapping unit configured to output symbol bits and amplitude bits from a received QAM signal; A nonlinear mitigation NLM deinterleaver, which follows the demapping mechanism, is configured to: Buffer the amplitude bits output by the demapper; and The amplitude bits of the buffer are replaced based on interleaving performed at the encoding device to reduce nonlinear effects; A forward error correction (FEC) decoder, which follows the NLM interleaver; as well as A distributed matching decoder that follows the FEC decoder.

20. The decoding apparatus of claim 19, further comprising an FEC deinterleaver between the NLM deinterleaver and the FEC decoder.

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